Instruction cache method and compilation tool chain

Abstract

The embodiment of the application provides an instruction cache method and a compiling tool chain, the method comprises the following steps: running a compiling program and an assembling program to compile and assemble original code to obtain first machine instructions; if the assembling program determines that the first machine instructions satisfy a cross cache line cache condition according to a starting write address of the first machine instructions and the length of the first machine instructions, then the first cache line where the starting write address is located is written full of empty operation instructions; the first machine instructions are written from the starting boundary of the second cache line, and the second cache line is the next cache line of the first cache line. The technical scheme provided by the embodiment of the application can improve the efficiency of program execution.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an instruction caching method and a compiler toolchain. Background Technology

[0002] Network processors use mixed-length machine instructions to process data packets, which can speed up packet processing. However, when these mixed-length machine instructions are compiled together, machine instructions can cross cache lines. When this happens, the network processor performs internal alignment operations on the machine instructions, which can cause pipeline stalls and reduce program execution efficiency. Summary of the Invention

[0003] The purpose of this application is to provide an instruction caching method and a compilation toolchain to improve program execution efficiency. The specific technical solution is as follows:

[0004] In a first aspect, embodiments of this application provide an instruction caching method, the method comprising:

[0005] Run the compiler and assembler to compile and assemble the original code to obtain the first machine instructions;

[0006] If the assembler determines that the first machine instruction satisfies the cross-cache line caching condition based on the starting write address and the length of the first machine instruction, then it uses a no-operation instruction to fill the first cache line where the starting write address is located.

[0007] The first machine instruction is written starting from the beginning boundary of the second cache line, where the second cache line is the next cache line after the first cache line.

[0008] In some embodiments, the method further includes:

[0009] During the execution of the assembler, if it is detected that the assembler contains preset running parameters, the global variables are set to preset values;

[0010] When the global variable is the preset value, it is determined whether the first machine instruction meets the cross-cache line caching condition based on the starting write address of the first machine instruction and the length of the first machine instruction.

[0011] In some embodiments, the step of determining whether the first machine instruction satisfies the cross-cache line caching condition based on the starting write address and the length of the first machine instruction includes:

[0012] Determine the target offset length of the starting write address of the first machine instruction relative to the starting boundary of the first cache line;

[0013] Detect whether the sum of the target offset length and the length of the first machine instruction is greater than the length of the cache line;

[0014] If it is greater than the length of the cache line, then the first machine instruction is determined to satisfy the cross-cache line caching condition;

[0015] If the length of the cache line is less than or equal to the length of the cache line, then the first machine instruction does not meet the cross-cache line caching condition.

[0016] In some embodiments, the step of determining the target offset length of the starting write address of the first machine instruction relative to the starting boundary of the first cache line includes:

[0017] The target offset length of the starting write address relative to the starting boundary of the first cache line is obtained by taking the remainder of the starting write address of the first machine instruction with respect to the length of the cache line.

[0018] In some embodiments, the first machine instruction corresponds to a first structure, and the starting write address of the first structure is the starting write address of the first machine instruction; the method further includes:

[0019] When the global variable is the preset value, a preset identifier is added to the first structure;

[0020] When the first structure carries the preset identifier and the first machine instruction satisfies the cross-cache line caching condition, the length of the first structure is updated to the sum of the target length and the length of the first machine instruction, where the target length is the length from the starting write address to the end boundary of the first cache line.

[0021] The step of filling the first cache line containing the starting write address with a no-operation instruction includes:

[0022] Based on the length of the first structure, starting from the starting write address, write no-operation instructions of the target length into the first structure;

[0023] The step of writing the first machine instruction starting from the beginning boundary of the second cache line includes:

[0024] Based on the length of the first structure, the first machine instruction is written into the first structure starting from the end address of the no-operation instruction in the first structure.

[0025] In some embodiments, the machine description file of the original code includes extended lengths of multiple machine instructions, the extended length of each machine instruction being the sum of its original length and a preset length; if the multiple machine instructions include a first jump instruction, then the method further includes:

[0026] During the execution of the compiler, the extended length of each machine instruction is used to estimate the jump destination address corresponding to the first jump instruction;

[0027] If the jump destination address exceeds the jump range of the first jump instruction, then the first jump instruction is replaced with a second jump instruction, wherein the jump destination address is within the jump range of the second jump instruction;

[0028] The steps of running the compiler and assembler to compile and assemble the source code to obtain the first machine instructions include:

[0029] Run the compiler and assembler to compile and assemble the original code corresponding to the second jump instruction, thereby obtaining the first machine instruction corresponding to the second jump instruction.

[0030] Secondly, embodiments of this application provide a compiler toolchain, the compiler toolchain comprising:

[0031] A compiler is used to run a compiler program to compile the original code into assembly code;

[0032] An assembler is used to run an assembler to assemble the assembly code to obtain a first machine instruction. If the first machine instruction satisfies the cross-cache line caching condition based on the starting write address and the length of the first machine instruction, a no-operation instruction is used to fill the first cache line where the starting write address is located. Starting from the starting boundary of a second cache line, the first machine instruction is written, and the second cache line is the next cache line of the first cache line.

[0033] In some embodiments, the assembler is further configured to:

[0034] During the execution of the assembler, if it is detected that the assembler contains preset running parameters, the global variables are set to preset values;

[0035] When the global variable is the preset value, it is determined whether the first machine instruction meets the cross-cache line caching condition based on the starting write address of the first machine instruction and the length of the first machine instruction.

[0036] In some embodiments, the assembler is specifically used for:

[0037] Determine the target offset length of the starting write address of the first machine instruction relative to the starting boundary of the first cache line;

[0038] Detect whether the sum of the target offset length and the length of the first machine instruction is greater than the length of the cache line;

[0039] If it is greater than the length of the cache line, then the first machine instruction is determined to satisfy the cross-cache line caching condition;

[0040] If the length of the cache line is less than or equal to the length of the cache line, then the first machine instruction does not meet the cross-cache line caching condition.

[0041] In some embodiments, the assembler is specifically used for:

[0042] The target offset length of the starting write address relative to the starting boundary of the first cache line is obtained by taking the remainder of the starting write address of the first machine instruction with respect to the length of the cache line.

[0043] In some embodiments, the first machine instruction corresponds to the first structure, and the starting write address of the first structure is the starting write address of the first machine instruction.

[0044] The assembler is further configured to: add a preset identifier to the first structure when the global variable is the preset value; and update the length of the first structure to the sum of the target length and the length of the first machine instruction when the first structure has the preset identifier and the first machine instruction satisfies the cross-cache line caching condition, wherein the target length is the length from the start write address to the end boundary of the first cache line.

[0045] The assembler is specifically configured to write no-operation instructions of the target length into the first structure, starting from the starting write address, based on the length of the first structure; and to write the first machine instructions into the first structure, starting from the end address of the no-operation instructions in the first structure, based on the length of the first structure.

[0046] In some embodiments, the machine description file of the original code includes extended lengths of multiple machine instructions, the extended length of each machine instruction being the sum of its original length and a preset length; if the multiple machine instructions include a first jump instruction, then the compiler is further configured to:

[0047] During the execution of the compiler, the jump destination address corresponding to the first jump instruction is estimated by utilizing the extended length of each machine instruction; if the jump destination address exceeds the jump range of the first jump instruction, the first jump instruction is replaced with a second jump instruction, and the jump destination address is within the jump range of the second jump instruction.

[0048] The compiler is specifically used to run a compiler to compile the original code corresponding to the second jump instruction, thereby obtaining the assembly code corresponding to the second jump instruction;

[0049] The assembler is specifically used to run an assembler to assemble the assembly code corresponding to the second jump instruction, thereby obtaining the first machine instruction corresponding to the second jump instruction.

[0050] Beneficial effects of the embodiments in this application:

[0051] In the technical solution provided in this application embodiment, after obtaining the compiled and assembled source code and the machine instructions, the machine instructions are not directly written into the cache line. Instead, it is checked whether the machine instruction meets the cross-cache line caching condition. If the cross-cache line caching condition is met, a no-operation instruction is used to fill the cache line of the current write instruction. Thus, the obtained machine instructions can be written starting from the beginning boundary of the next cache line, achieving boundary alignment of machine instructions. The network processor does not need to perform alignment operations on machine instructions, which will not cause pipeline operation to stop and improve the efficiency of program execution.

[0052] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0054] Figure 1 This is a schematic diagram of machine instructions being cached across cache lines in related technologies;

[0055] Figure 2 This is a schematic diagram of a first type of instruction caching method provided in an embodiment of this application;

[0056] Figure 3 This is a second flowchart illustrating the instruction caching method provided in an embodiment of this application.

[0057] Figure 4This is a third flowchart illustrating the instruction caching method provided in the embodiments of this application;

[0058] Figure 5 This is a schematic diagram of a compiler toolchain provided in an embodiment of this application. Detailed Implementation

[0059] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0060] A compiler toolchain is a collection of tools, primarily consisting of a preprocessor, compiler, assembler, and linker. The preprocessor performs tasks such as header file expansion and macro substitution; the compiler compiles high-level language code into assembly language code; the assembler assembles the assembly language code into machine instructions and writes these instructions into object files; and the linker combines multiple object files to generate the final executable file. The GNU compiler toolchain releases the preprocessor and compiler code in a single `gcc` package, and the assembler and linker in a separate `binutils` package.

[0061] Reduced Instruction Set Computer (RISC) architecture computers typically use fixed-length machine instructions to simplify design. However, to run on embedded systems with limited memory, RISC architecture computers using a 32-bit RISC instruction set also employ a separate 16-bit RISC instruction set. These two RISC instruction sets can be parsed and executed simultaneously. The RISC instruction set includes multiple machine instructions. For network processors with many-core architectures, which typically have thousands of hardware threads, using a RISC architecture greatly helps reduce chip area. However, in addition to the two RISC instruction sets mentioned above, network processors also extend the instruction set with 32-bit immediate values ​​to accelerate network packet processing. In this case, the machine instruction length can be 16, 32, 48, or 64 bits. These inconsistently long machine instructions are compiled together, resulting in a single machine instruction spanning multiple cache lines, as shown below. Figure 1 The machine instructions shown are cached across cache lines. Figure 1 In this context, a single rectangle represents a cache line, a rectangle with an ellipsis indicates that multiple rectangles have been omitted, and a single rectangle represents 2 bytes (16 bits) of space. Figure 1In the diagram, the shaded rectangles at the end of each cache line and the beginning of the corresponding next cache line represent the same machine instruction, and that machine instruction is an instruction cached across cache lines.

[0062] Longer machine instructions help increase code density, but they also bring another problem to computers with 4-byte RISC architectures. If the starting address of a machine instruction is not aligned to the 4-byte boundary (i.e., the starting address of the machine instruction is not 0 when modulo 4), the network processor will perform alignment operations internally, which will cause pipeline operations to stall, thereby reducing the efficiency of program execution.

[0063] In related technologies, to improve program execution efficiency, 2 bytes of machine instructions are trimmed. However, if 2 bytes of machine instructions are trimmed, the length of the machine instructions is only 4 bytes or 8 bytes. This allows for alignment at 4-byte address boundaries, and the pipeline will not stall due to alignment. But this leads to code bloat, such as 2-byte machine instructions bloating into 4-byte machine instructions, and 6-byte machine instructions bloating into 8-byte machine instructions. This reduces the hit rate of the instruction cache and also affects the program's execution efficiency.

[0064] To improve program execution efficiency, this application provides an instruction caching method. This method can be applied to network processors or compiler toolchains, such as the GNU compiler toolchain mentioned above. For ease of description, the following description uses the compiler toolchain as the execution entity and is not intended to limit the scope. In the above instruction caching method, after obtaining the compiled and assembled source code and obtaining the machine instructions, the compiler toolchain does not directly write the machine instructions into the cache line. Instead, it checks whether the machine instruction meets the cross-cache line caching condition. If the cross-cache line caching condition is met, a no-operation instruction is used to fill the cache line of the currently written instruction. Thus, the obtained machine instructions can be written starting from the beginning boundary of the next cache line, achieving boundary alignment of machine instructions. The network processor does not need to perform alignment operations on machine instructions internally, thus preventing pipeline stalls and improving program execution efficiency.

[0065] In addition, in the instruction caching method provided in this application embodiment, the compilation toolchain will only insert no-operation instructions when the machine instructions meet the cross-cache line caching conditions. Compared with cutting off 2 bytes of machine instructions, the code bloat provided in this application embodiment is smaller, which improves the hit rate of instruction cache and further improves the efficiency of program execution.

[0066] The instruction caching method provided in this application will be described in detail below through specific embodiments.

[0067] See Figure 2 , Figure 2 This is a first flowchart illustrating an instruction caching method provided in an embodiment of this application. The method includes the following steps:

[0068] Step S21: Run the compiler and assembler to compile and assemble the original code to obtain the first machine instructions.

[0069] In this embodiment, the original code is high-level language code. The compilation toolchain runs the compiler to compile the high-level language original code into assembly language code (i.e., assembly code); and runs the assembler to assemble the assembly language code into machine instructions, i.e., the first machine instructions.

[0070] In some embodiments, the machine description file of the source code may include extended lengths of multiple machine instructions, the extended length of each machine instruction being the sum of the original length of the machine instruction and a preset length.

[0071] For example, the machine description file in the gcc source tree includes the length attribute of the relevant machine instructions. The compiler toolchain can modify the length attribute of the relevant machine instructions in the machine description file so that the length value of the length attribute is the sum of the original length value of the machine instruction and the preset length.

[0072] For example, if the default length is 2 bytes and machine instruction 1 is 4 bytes, then the compiler toolchain modifies the length attribute of machine instruction 1 to 4 + 2 = 6 bytes.

[0073] The machine description file based on the above original code includes extended lengths of multiple machine instructions. When the machine instructions that need to be compiled and assembled include jump instructions (such as the first jump instruction), the compilation toolchain estimates the jump destination address corresponding to the first jump instruction by utilizing the extended length of each machine instruction during the process of running the compiler.

[0074] If the destination address exceeds the jump range of the first jump instruction, the compiler toolchain replaces the first jump instruction with a second jump instruction, whose destination address is within the jump range of the second jump instruction. The second jump instruction can be a jump instruction with a jump range greater than the first jump instruction, and can also consist of multiple jump instructions; there are no restrictions on this. In this case, step S21 can be: running the compiler and assembler to compile and assemble the source code corresponding to the second jump instruction, obtaining the first machine instruction corresponding to the second jump instruction.

[0075] If the jump destination address is within the jump range of the first jump instruction, the compiler toolchain will not perform any other operations on the first jump instruction. In this case, step S21 above can be: running the compiler and assembler to compile and assemble the original code corresponding to the first jump instruction to obtain the first machine instruction corresponding to the first jump instruction.

[0076] The machine description file includes the length attribute of the relevant machine instructions, used during the compilation phase to estimate whether the jump destination address is within the jump range of the jump instruction (a type of machine instruction). During compilation, if the compiler toolchain estimates the jump destination address to be outside the jump range, it will select an instruction with a larger jump range, or multiple jump instructions, to jump to the destination address through multiple jumps; otherwise, it will select an instruction with a shorter jump range. During assembly, if the compiler toolchain calculates the destination address of an instruction to be outside the jump range of a jump instruction with a shorter jump range, it cannot jump to the destination address, resulting in an error. In this embodiment, the compiler toolchain adds a preset length to the length attribute of the relevant machine instructions in the machine description file. This ensures that during compilation, the compiler toolchain estimates a larger jump destination address, thus selecting an instruction with a larger jump range, or multiple jump instructions, reducing the probability of subsequent code bloat causing the actually calculated destination address to exceed the jump range of the jump instruction.

[0077] The aforementioned preset length represents the predicted length of the machine instruction expansion. The size of the preset length can be set according to actual needs. In one example, the preset length can be the length of a minimum-length machine instruction. In this embodiment, the compiler toolchain uses the insertion of no-operation instructions (such as nop instructions) to achieve machine instruction boundary alignment. The length of the minimum-length machine instruction is the same as the length of the no-operation instruction; therefore, the aforementioned preset length can also be understood as the length of a no-operation instruction. The expanded length of each machine instruction included in the machine description file is: the original length of the machine instruction plus the length of a no-operation instruction.

[0078] For example, if the length of a no-operation instruction is 2 bytes, then the above-mentioned preset length is 2 bytes. If the original length of a machine instruction is 4 bytes, then the extended length of the machine instruction included in the machine description file is 4 + 2 = 6 bytes.

[0079] In this embodiment of the application, the compiler toolchain can also solve the problem that the destination address of the actually calculated instruction exceeds the jump range of the jump instruction due to code bloat in other ways. For example, the compiler toolchain can write a preset length as a running parameter into the compiler, run the modified compiler, and add the preset length in the compiler to the length of each machine instruction in the machine description file, thereby completing the determination of whether the estimated jump destination address is within the jump range of the jump instruction.

[0080] Step S22: If the assembler determines that the first machine instruction satisfies the cross-cache line caching condition based on the starting write address and the length of the first machine instruction, then a no-operation instruction is used to fill the first cache line where the starting write address is located.

[0081] In this embodiment, the cross-cache-line caching condition indicates that a machine instruction requires at least two cache lines to complete caching. A cache line is a cache line in memory, and memory includes multiple cache lines. The starting write address can be the starting address of memory or the end address after the last write instruction. For example, when no instructions are cached in memory, the starting write address is the starting address of memory; when instructions are cached in memory, the starting write address is the end address after the last write instruction.

[0082] After obtaining the first machine instruction, the compiler toolchain can temporarily hold off on writing it into memory and continue running the assembler. Based on the starting write address and length of the first machine instruction, it can determine whether the first machine instruction meets the cross-cache line caching condition. If the first machine instruction does not meet the cross-cache line caching condition, the compiler toolchain can then write the first machine instruction starting from the starting write address.

[0083] For ease of description, the cache line containing the starting write address will be referred to as the first cache line, and the length of the space from the starting write address to the end of the first cache line will be referred to as the target length. If the first machine instruction satisfies the cross-cache line caching condition, the compiler toolchain can obtain a no-operation instruction of the target length and write the obtained no-operation instruction starting from the starting write address. This achieves the goal of filling the first cache line containing the starting write address with no-operation instructions.

[0084] Step S23: Starting from the beginning boundary of the second cache line, write the first machine instruction. The second cache line is the next cache line after the first cache line.

[0085] After the write-no-operation instruction is completed, the starting write address is updated to the starting boundary of the second cache line. After the write-no-operation instruction is completed, the compiler toolchain continues writing the first machine instructions, that is, starting from the starting boundary of the second cache line.

[0086] For example, the no-operation instruction is 2 bytes of 0xFFFF, and the first machine instruction is 4 bytes of 0x12345678. If it's determined that the first machine instruction does not meet the cross-cache line cache condition, the compiler toolchain writes 0x12345678 starting from the start write address. If it's determined that the first machine instruction meets the cross-cache line cache condition, such as when the target length is 2 bytes, then 0xFFFF is written first starting from the start write address, followed by 0x12345678. In this case, the start write address of 0x12345678 is the starting boundary of a cache line.

[0087] After the machine instructions are written into memory, the compilation toolchain writes the machine instructions into the object file, thereby generating the final executable file.

[0088] In the instruction caching method provided in this application embodiment, after obtaining the compiled and assembled source code and the machine instructions, the compilation toolchain does not directly write the machine instructions into the cache line. Instead, it checks whether the machine instruction meets the cross-cache line caching condition. If the cross-cache line caching condition is met, a no-operation instruction is used to fill the cache line of the currently written instruction. Thus, the obtained machine instructions can be written starting from the beginning boundary of the next cache line, achieving boundary alignment of machine instructions. The network processor does not need to perform alignment operations on machine instructions, which will not cause pipeline operation to stall and improve the efficiency of program execution.

[0089] In addition, in the instruction caching method provided in this application embodiment, the compilation toolchain will only insert no-operation instructions when the machine instructions meet the cross-cache line caching conditions. Compared with cutting off 2 bytes of machine instructions, the code bloat provided in this application embodiment is smaller, which improves the hit rate of instruction cache and further improves the efficiency of program execution.

[0090] In some embodiments, an instruction caching method is also provided, such as Figure 3 As shown, steps S31-S35 are included, wherein steps S31 and S34-S35 are similar to steps S21-S23 above, and will not be described again here.

[0091] Step S32: During the execution of the assembler, if it is detected that the assembler contains preset running parameters, the global variables are set to preset values.

[0092] In this embodiment, the preset running parameter is a parameter indicating whether to perform cross-cache line cache detection. This preset running parameter can be written into the assembler. The content of the preset running parameter can be set according to actual needs; for example, the preset running parameter can be represented by "-madjc1". A global variable is used to indicate whether to perform cross-cache line detection on machine instructions. The content of the global variable can be set according to actual needs; for example, the global variable can be represented by "adjc1". A global variable with a preset value indicates that cross-cache line detection on machine instructions is performed; a global variable with other values ​​indicates that cross-cache line detection on machine instructions is rejected. The preset value can be set according to actual needs; for example, the preset value can be 1 or 0.

[0093] In one example, the assembler is stored in the binutils source tree. The compiler toolchain can modify files in the binutils source tree to add preset runtime parameters to the assembler.

[0094] In this embodiment of the application, if the compiler toolchain runs an assembler that contains preset running parameters during the process of converting the original code into first machine instructions, then the global variables are set to preset values.

[0095] Step S33: When the global variable is a preset value, determine whether the first machine instruction meets the cross-cache line cache condition based on the starting write address of the first machine instruction and the length of the first machine instruction.

[0096] After obtaining the first machine instruction, if the compilation toolchain detects that the global variable is a preset value, it means that a no-operation instruction may be inserted before the first machine instruction. The first machine instruction is not written to memory for the time being. The machine instruction is then checked across cache lines. That is, based on the starting write address of the first machine instruction and the length of the first machine instruction, it is determined whether the first machine instruction meets the cache conditions across cache lines.

[0097] When it is determined that the first machine instruction meets the cross-cache line caching condition, steps S34-S35 are executed to complete instruction caching.

[0098] In the technical solution provided in this application embodiment, the compilation toolchain fine-tunes the assembler program and adds preset running parameters to the assembler program to selectively enable cross-cache line detection, thereby improving the flexibility of cross-cache line detection.

[0099] In some embodiments, an instruction caching method is also provided, such as Figure 4 As shown, steps S41-S47 are included, wherein steps S41-S42 and S45-S46 are the same as steps S31-S32 and S34-S35 above, and will not be repeated here.

[0100] Step S43: When the global variable is a preset value, determine the target offset length of the starting write address of the first machine instruction relative to the starting boundary of the first cache line.

[0101] The compiler toolchain determines the length between the starting write address and the starting boundary of the first cache line, which is the target offset length of the starting write address relative to the starting boundary of the first cache line.

[0102] In some embodiments, to improve the accuracy of the determined starting write address, step S43 may be: taking the remainder of the starting write address of the first machine instruction with respect to the length of the cache line to obtain the target offset length of the starting write address relative to the starting boundary of the first cache line.

[0103] For example, if a cache line is 32 bytes long and the starting write address of the first machine instruction is 78 bytes, then 78%32 is 14 bytes. Therefore, the compiler toolchain determines the target offset length to be 14 bytes.

[0104] In this embodiment, the compiler toolchain can also update the target offset length after each machine instruction is written to a cache line; when caching machine instructions again, the target offset length is directly obtained, cross-cache line detection is performed based on the target offset length, and after writing to memory, the target offset length is updated. For example, the sum of the target offset length and the length of the machine instruction is calculated. If the sum is less than the length of the cache line, the sum is updated to the target offset length; if the sum is greater than or equal to the length of the cache line, the difference between the sum and the length of the cache line is updated to the target offset length; when caching machine instructions again subsequently, the target offset length is directly obtained, and this process is repeated.

[0105] For example, when writing machine instructions to memory for the first time, the target offset length is 0 bytes, the starting write address is 0 bytes, and the cache line length is 8 bytes. After the compiler toolchain writes 4 bytes of machine instructions to the cache line, it updates the target offset length to 0 + 4 = 4 bytes. Subsequently, when caching other 6 bytes of machine instructions, it performs a cross-cache line check based on the target offset length of 4 bytes and writes the 6 bytes of other machine instructions to memory. Then, it calculates 4 + 6 = 10 > 8, and updates the target offset length to 10 - 8 = 2 bytes. In subsequent caches of other machine instructions, it performs a cross-cache line check based on the target offset length of 2 bytes.

[0106] In this embodiment of the application, the compiler toolchain may also use other methods to determine the target offset length, and there is no limitation on this.

[0107] Step S44: Check if the sum of the target offset length and the length of the first machine instruction is greater than the length of the cache line. If yes, proceed to step S45. If no, proceed to step S47.

[0108] The compiler toolchain calculates the sum of the target offset length and the length of the first machine instruction, and checks whether this sum is greater than the length of the cache line. If so, that is, the sum of the target offset length and the length of the first machine instruction is greater than the length of the cache line, the compiler toolchain determines that the first machine instruction satisfies the cross-cache line caching condition, executes steps S45-S46, uses a no-operation instruction to fill the first cache line where the starting write address is located, and writes the first machine instruction starting from the beginning boundary of the second cache line.

[0109] If not, that is, if the sum of the target offset length and the length of the first machine instruction is less than or equal to the length of the cache line, then the compiler toolchain determines that the first machine instruction does not meet the cross-cache line caching condition, and there is no need to insert a no-operation instruction. Then, step S47 is executed to write the first machine instruction to the first cache line starting from the start write address.

[0110] Step S47: Starting from the initial write address, write the first machine instruction to the first cache line.

[0111] In the technical solution provided in this application embodiment, the compilation toolchain can accurately and quickly determine whether the first machine instruction crosses a cache line based on the target offset and the length of the first machine instruction, thereby achieving boundary alignment of machine instructions and improving the efficiency of program execution.

[0112] In some embodiments, machine instructions are stored in memory in the form of structures (such as frags). Writing machine instructions to a cache line is equivalent to writing machine instructions to a structure. For example, if a first machine instruction corresponds to a first structure, writing the first machine instruction to a first cache line is equivalent to writing the first machine instruction to the first structure. The starting write address of the first structure is the starting write address of the first machine instruction.

[0113] When a global variable has a default value, it indicates that cross-cache line checking of machine instructions is required, and the compiler toolchain adds a default flag to the first structure. The default flag indicates that the structure's length is indeterminate. The content of the default flag can be set according to actual needs. For example, the default flag can be represented as `rs_machine_dependent`.

[0114] When the first structure has a preset identifier and the first machine instruction satisfies the cross-cache line caching condition, the compilation toolchain updates the length of the first structure to the sum of the target length and the length of the first machine instruction. The target length is the length from the start write address to the end boundary of the first cache line.

[0115] In this scenario, the compiler toolchain's step of filling the first cache line containing the starting write address with no-operation instructions can be as follows: Based on the length of the first structure, starting from the starting write address of the first structure, write no-operation instructions of the target length into the first structure. After writing the target length of no-operation instructions into the first structure, the first cache line is filled.

[0116] Correspondingly, the step of the compiler toolchain writing the first machine instruction starting from the beginning boundary of the second cache line can be: based on the length of the first structure, starting from the end address of the empty operation instruction in the first structure, write the first machine instruction into the first structure.

[0117] After writing a no-operation instruction of the target length to the first structure, the first cache line is full. In this case, the compiler toolchain continues to write the first machine instruction to the first structure, and the starting address of the first machine instruction is the starting boundary of the second cache line.

[0118] As can be seen, in the technical solution provided by the embodiments of this application, the compiler toolchain uses preset identifiers to mark the corresponding structures in order to control the execution of the assembly process, thereby improving the accuracy of assembly, which in turn improves the accuracy of machine instruction boundary alignment and improves the efficiency of program execution.

[0119] In this embodiment of the application, for machine instructions that cannot be inserted with no-operation instructions, such as delay branch slots, the compiler toolchain can use other forms to control the execution of the assembly process, such as inserting a structure that only includes no-operation instructions and has a length of the target length, as long as the boundary alignment of the machine instructions is achieved, without specific limitations.

[0120] In this embodiment, the compiler toolchain can automatically detect instances of machine instructions crossing cache lines and, by inserting appropriately long no-operation instructions, align these cross-cache lines to the next cache line. This aligns machine instructions to specific boundaries without significantly increasing program size, reducing pipeline stalls caused by instruction alignment within the network processor and thus improving overall program execution efficiency. Experimental results show that modifying the compiler toolchain using the technical solution provided in this embodiment improves the packet forwarding performance of the network processor by 3%–5%.

[0121] Corresponding to the instruction caching method described above, this application provides a compiler toolchain, such as... Figure 5 As shown, the compiler toolchain includes:

[0122] Compiler 51 is used to run a compiler to compile the source code into assembly code;

[0123] Assembler 52 is used to run the assembler to assemble the above assembly code to obtain the first machine instruction. If the first machine instruction satisfies the cross-cache line caching condition based on the starting write address and the length of the first machine instruction, then the first cache line where the starting write address is located is filled with a no-operation instruction. Starting from the starting boundary of the second cache line, the first machine instruction is written, and the second cache line is the next cache line of the first cache line.

[0124] In some embodiments, the assembler 52 can also be used for:

[0125] During the execution of the assembler, if the assembler is found to contain preset execution parameters, the global variables are set to their preset values.

[0126] When the global variable is a preset value, the system determines whether the first machine instruction meets the cross-cache line caching condition based on the starting write address of the first machine instruction and the length of the first machine instruction.

[0127] In some embodiments, the assembler 52 may specifically be used for:

[0128] Determine the target offset length of the starting write address of the first machine instruction relative to the starting boundary of the first cache line;

[0129] Check whether the sum of the target offset length and the length of the first machine instruction is greater than the length of the cache line;

[0130] If it is greater than the length of the cache line, then the first machine instruction is determined to satisfy the cross-cache line caching condition;

[0131] If the length of the cache line is less than or equal to the length of the cache line, then the first machine instruction does not meet the cross-cache line caching condition.

[0132] In some embodiments, the assembler 52 may specifically be used for:

[0133] The target offset length of the starting write address relative to the starting boundary of the first cache line is obtained by taking the remainder of the starting write address of the first machine instruction with respect to the length of the cache line.

[0134] In some embodiments, the first machine instruction corresponds to the first structure, and the starting write address of the first structure is the starting write address of the first machine instruction;

[0135] The assembler 52 can also be used to: add a preset identifier to the first structure when the global variable is a preset value; when the first structure has a preset identifier and the first machine instruction meets the cross-cache line caching condition, update the length of the first structure to the sum of the target length and the length of the first machine instruction, where the target length is the length from the start write address to the end boundary of the first cache line.

[0136] The assembler 52 can be used to write no-operation instructions of a target length into the first structure, starting from the start write address, based on the length of the first structure; and to write first machine instructions into the first structure, starting from the end address of the no-operation instructions in the first structure, based on the length of the first structure.

[0137] In some embodiments, the machine description file of the source code includes extended lengths of multiple machine instructions, the extended length of each machine instruction being the sum of its original length and a preset length; if the multiple machine instructions include a first jump instruction, then compiler 51 can also be used for:

[0138] During the compilation process, the extended length of each machine instruction is used to estimate the jump destination address corresponding to the first jump instruction; if the jump destination address exceeds the jump range of the first jump instruction, the first jump instruction is replaced with a second jump instruction, and the jump destination address is within the jump range of the second jump instruction.

[0139] In this case, compiler 51 can be used to run the compiler to compile the original code corresponding to the second jump instruction, and obtain the assembly code corresponding to the second jump instruction;

[0140] The assembler 52 can be used to run an assembler to assemble the assembly code corresponding to the second jump instruction, thereby obtaining the first machine instruction corresponding to the second jump instruction.

[0141] In the technical solution provided in this application embodiment, after obtaining the compiled and assembled source code and the machine instructions, the machine instructions are not directly written into the cache line. Instead, it is checked whether the machine instruction meets the cross-cache line caching condition. If the cross-cache line caching condition is met, a no-operation instruction is used to fill the cache line of the current write instruction. Thus, the obtained machine instructions can be written starting from the beginning boundary of the next cache line, achieving boundary alignment of machine instructions. The network processor does not need to perform alignment operations on machine instructions, which will not cause pipeline operation to stop and improve the efficiency of program execution.

[0142] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0143] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0144] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the compiler toolchain embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0145] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. An instruction caching method, characterized in that, The method includes: Run the compiler and assembler to compile and assemble the original code to obtain the first machine instructions; If the assembler determines that the first machine instruction satisfies the cross-cache line caching condition based on the starting write address and the length of the first machine instruction, then it uses a no-operation instruction to fill the first cache line where the starting write address is located. The first machine instruction is written starting from the beginning boundary of the second cache line, where the second cache line is the next cache line after the first cache line. The step of determining that the first machine instruction satisfies the cross-cache line caching condition based on the starting write address of the first machine instruction and the length of the first machine instruction includes: determining the target offset length of the starting write address of the first machine instruction relative to the starting boundary of the first cache line; detecting whether the sum of the target offset length and the length of the first machine instruction is greater than the length of the cache line; if it is greater than the length of the cache line, then determining that the first machine instruction satisfies the cross-cache line caching condition.

2. The method according to claim 1, characterized in that, The method further includes: During the execution of the assembler, if it is detected that the assembler contains preset running parameters, the global variables are set to preset values; When the global variable is the preset value, it is determined whether the first machine instruction meets the cross-cache line caching condition based on the starting write address of the first machine instruction and the length of the first machine instruction.

3. The method according to claim 1, characterized in that, The step of determining the target offset length of the starting write address of the first machine instruction relative to the starting boundary of the first cache line includes: The target offset length of the starting write address relative to the starting boundary of the first cache line is obtained by taking the remainder of the starting write address of the first machine instruction with respect to the length of the cache line.

4. The method according to claim 2, characterized in that, The first machine instruction corresponds to a first structure, and the starting write address of the first structure is the starting write address of the first machine instruction; the method further includes: When the global variable is the preset value, a preset identifier is added to the first structure; When the first structure carries the preset identifier and the first machine instruction satisfies the cross-cache line caching condition, the length of the first structure is updated to the sum of the target length and the length of the first machine instruction, where the target length is the length from the starting write address to the end boundary of the first cache line. The step of filling the first cache line containing the starting write address with a no-operation instruction includes: Based on the length of the first structure, starting from the starting write address, write no-operation instructions of the target length into the first structure; The step of writing the first machine instruction starting from the beginning boundary of the second cache line includes: Based on the length of the first structure, the first machine instruction is written into the first structure starting from the end address of the no-operation instruction in the first structure.

5. The method according to any one of claims 1-3, characterized in that, The machine description file of the original code includes extended lengths of multiple machine instructions, where the extended length of each machine instruction is the sum of its original length and a preset length; if the multiple machine instructions include a first jump instruction, then the method further includes: During the execution of the compiler, the extended length of each machine instruction is used to estimate the jump destination address corresponding to the first jump instruction; If the jump destination address exceeds the jump range of the first jump instruction, then the first jump instruction is replaced with a second jump instruction, wherein the jump destination address is within the jump range of the second jump instruction; The steps of running the compiler and assembler to compile and assemble the source code to obtain the first machine instructions include: Run the compiler and assembler to compile and assemble the original code corresponding to the second jump instruction, thereby obtaining the first machine instruction corresponding to the second jump instruction.

6. A compiler toolchain, characterized in that, The compiler toolchain includes: A compiler is used to run a compiler program to compile the original code into assembly code; An assembler is used to run an assembler to assemble the assembly code to obtain a first machine instruction; if the first machine instruction satisfies the cross-cache line caching condition based on the starting write address and the length of the first machine instruction, then a no-operation instruction is used to fill the first cache line where the starting write address is located; starting from the starting boundary of a second cache line, the first machine instruction is written, and the second cache line is the next cache line of the first cache line; The assembler is specifically configured to: determine the target offset length of the starting write address of the first machine instruction relative to the starting boundary of the first cache line; detect whether the sum of the target offset length and the length of the first machine instruction is greater than the length of the cache line; if it is greater than the length of the cache line, determine that the first machine instruction satisfies the cross-cache line caching condition; if it is less than or equal to the length of the cache line, determine that the first machine instruction does not satisfy the cross-cache line caching condition.

7. The compiler toolchain according to claim 6, characterized in that, The assembler is also used for: During the execution of the assembler, if it is detected that the assembler contains preset running parameters, the global variables are set to preset values; When the global variable is the preset value, it is determined whether the first machine instruction meets the cross-cache line caching condition based on the starting write address of the first machine instruction and the length of the first machine instruction.

8. The compiler toolchain according to claim 6, characterized in that, The assembler is specifically used for: The target offset length of the starting write address relative to the starting boundary of the first cache line is obtained by taking the remainder of the starting write address of the first machine instruction with respect to the length of the cache line.

9. The compiler toolchain according to claim 7, characterized in that, The first machine instruction corresponds to the first structure, and the starting write address of the first structure is the starting write address of the first machine instruction. The assembler is further configured to: add a preset identifier to the first structure when the global variable is the preset value; and update the length of the first structure to the sum of the target length and the length of the first machine instruction when the first structure has the preset identifier and the first machine instruction satisfies the cross-cache line caching condition, wherein the target length is the length from the start write address to the end boundary of the first cache line. The assembler is specifically configured to write no-operation instructions of the target length into the first structure, starting from the starting write address, based on the length of the first structure; and to write the first machine instructions into the first structure, starting from the end address of the no-operation instructions in the first structure, based on the length of the first structure.

10. The compiler toolchain according to any one of claims 6-8, characterized in that, The machine description file of the original code includes extended lengths of multiple machine instructions, where the extended length of each machine instruction is the sum of its original length and a preset length; if the multiple machine instructions include a first jump instruction, then the compiler is further configured to: During the execution of the compiler, the extended length of each machine instruction is used to estimate the jump destination address corresponding to the first jump instruction; If the jump destination address exceeds the jump range of the first jump instruction, then the first jump instruction is replaced with a second jump instruction, wherein the jump destination address is within the jump range of the second jump instruction; The compiler is specifically used to run a compiler to compile the original code corresponding to the second jump instruction, thereby obtaining the assembly code corresponding to the second jump instruction; The assembler is specifically used to run an assembler to assemble the assembly code corresponding to the second jump instruction, thereby obtaining the first machine instruction corresponding to the second jump instruction.

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