Defect root cause determination method, apparatus, and storage medium

Abstract

The application relates to a defect root cause determination method, device and storage medium. The method comprises: obtaining a layout of a chip and diagnosis information of a defect in the chip; determining first feature information according to the layout and the diagnosis information, the first feature information comprising feature information corresponding to manufacturing defects and design defects respectively; and determining, based on the first feature information, a defect as a root cause from among the manufacturing defects and the design defects by using a neural network model. According to the embodiments of the application, the design defects and the manufacturing defects of the chip can be considered simultaneously, the inference of the root cause is more comprehensive, the interaction relationship between complex root causes can be considered, the inferred defect root cause is more accurate, and therefore the subsequent improvement of chip-related design or manufacturing process can be better assisted to reduce the cost increase caused by low yield.

Description

Technical Field

[0001] This application relates to the field of artificial intelligence technology, and in particular to a method, apparatus and storage medium for determining the root cause of defects. Background Technology

[0002] With the development of electronic product functions and the expansion of application areas, chips, as the core components of electronic products, have become an indispensable part of people's lives. Chip production is mainly divided into two parts: layout design and manufacturing. Layout design typically includes multi-layered circuit functional design, while manufacturing includes processes such as production, packaging, and testing. When the same chip design is used with different manufacturing processes, some circuit structures that are normal under the original process may have defects, leading to a lower-than-expected chip yield. These circuit structures that are prone to defects due to process changes are called design defects. In the same chip manufacturing process, manufacturing stages that frequently cause chip failure under different layout designs are called manufacturing defects.

[0003] Design and manufacturing defects increase the likelihood of integrated circuit malfunctions. Chips with malfunctioning circuitry cannot be used properly, leading to a decrease in chip yield. Decreased yield increases production costs and can even cause products to miss their sales window. Therefore, given the increasingly shorter chip time-to-market, identifying the root causes of declining chip yields in a timely manner to maintain stable, high yields and reduce chip production costs has become a critical issue that needs to be addressed. Summary of the Invention

[0004] In view of this, a method, apparatus and storage medium for determining the root cause of defects are proposed.

[0005] In a first aspect, embodiments of this application provide a method for determining the root cause of a defect. The method includes:

[0006] Obtain the chip layout and diagnostic information on defects within the chip;

[0007] Based on the layout and diagnostic information, the first feature information is determined, which includes feature information corresponding to manufacturing defects and design defects, respectively.

[0008] Based on the first feature information, the defects that are the root causes of manufacturing defects and design defects are identified through a neural network model.

[0009] According to embodiments of this application, by acquiring the chip layout and diagnostic information, feature information corresponding to manufacturing defects and design defects respectively is determined. This allows for the simultaneous consideration of both chip design and manufacturing defects, resulting in a more comprehensive inference of root causes. By utilizing neural network models to deduce the root causes of defects leading to decreased chip yield, the interaction relationships between complex root causes can be taken into account, making the inferred root causes more accurate. This, in turn, better assists in subsequent improvements to chip-related designs or manufacturing processes, thereby reducing the cost increases caused by low yield.

[0010] According to the first aspect, in a first possible implementation of the defect root cause determination method, based on first feature information, defects that are the root causes of manufacturing defects and design defects are determined through a neural network model, including:

[0011] Based on the first feature information, the probability distribution of manufacturing defects and design defects is determined through a neural network model;

[0012] Based on the probability distribution of manufacturing defects and design defects, identify the defects that are the root causes among manufacturing defects and design defects.

[0013] According to the embodiments of this application, the probability distribution of manufacturing defects and design defects is determined by a neural network model, and the root cause of the defects is determined accordingly, which can make the inferred root cause of the defects more accurate.

[0014] According to the first aspect or the first possible implementation of the first aspect, in the second possible implementation of the defect root cause determination method, based on the first feature information, the defect that is the root cause among manufacturing defects and design defects is determined by a neural network model, which may include:

[0015] The neural network model determines second feature information based on the first feature information, which is used to indicate the probability distribution of manufacturing defects and design defects;

[0016] The neural network model uses second feature information to identify defects that are the root cause of manufacturing and design defects.

[0017] According to the embodiments of this application, by using a neural network model to determine the second feature information, the manufacturing defects and design defects indicated by the second feature information can be used to efficiently and accurately determine the root cause of the defects. In this process, the complex interactions between different defects can be taken into account to determine the root cause of the decline in chip yield.

[0018] According to the second possible implementation of the first aspect, in the third possible implementation of the defect root cause determination method, the second feature information is used to indicate the probability distribution of manufacturing defects and design defects in the chip, and the neural network model, based on the second feature information, determines the defects that are the root causes among the manufacturing defects and design defects, including:

[0019] The neural network model determines the probability distribution of manufacturing defects and design defects in all chips in the current batch based on the second feature information.

[0020] Based on the probability distribution of manufacturing defects and design defects in all chips of the current batch, identify the root causes of manufacturing defects and design defects.

[0021] According to the embodiments of this application, by utilizing the probability distribution of manufacturing defects and design defects in each chip, the probability distribution of manufacturing defects and design defects in all chips can be determined. This allows for the identification of the overall root causes of failure in the current batch of chips due to manufacturing defects and design defects, thereby better assisting in subsequent improvements to chip-related designs or manufacturing processes to reduce the cost increase caused by low yield.

[0022] According to the second or third possible implementation of the first aspect, in the fourth possible implementation of the defect root cause determination method, the second feature information is optimized second feature information, the neural network model can be a latent variable model, and the neural network model determines the second feature information based on the first feature information, which may include:

[0023] The first feature information is input into the encoder of the latent variable model to determine the initial second feature information;

[0024] The initial second feature information is input into the decoder of the latent variable model to determine the third feature information;

[0025] The first loss function value corresponding to the encoder is calculated based on the initial second feature information;

[0026] Calculate the second loss function value corresponding to the decoder based on the third feature information;

[0027] The latent variable model is optimized based on the first and second loss function values ​​to determine the optimized latent variable model.

[0028] Based on the optimized latent variable model, the optimized second feature information is determined.

[0029] According to the embodiments of this application, by using the encoder to determine the initial second feature information, the global correlation of each defect in the batch of failed chips can be taken into account. By using the decoder to obtain the third feature information, the local correlation of each defect in the same chip can be taken into account. Thus, the encoder and decoder of the latent variable model are co-optimized, so that the complex interaction between design defects and manufacturing defects can be comprehensively taken into account, and the root cause of defects that lead to a decrease in chip yield can be determined more accurately.

[0030] According to the fourth possible implementation of the first aspect, in the fifth possible implementation of the defect root cause determination method, the third feature information is the reconstructed second feature information, used to indicate the correlation between different defects on the same chip.

[0031] According to the embodiments of this application, by reconstructing the second feature information to obtain the third feature information, the third feature information can be used to constrain the second feature information, thereby utilizing the correlation between different defects on the same chip indicated by the third feature information to better learn the local correlation of each defect in the same chip.

[0032] According to the fourth or fifth possible implementation of the first aspect, in the sixth possible implementation of the defect root cause determination method, the feature value in the third feature information can be 0 or 1.

[0033] According to the embodiments of this application, by making the feature value in the third feature information a binary value, the decoder can better learn the local correlation between design defects and manufacturing defects in each failed chip, so as to more accurately determine the root cause of the defect that leads to the decline in chip yield.

[0034] According to the fourth, fifth, or sixth possible implementation of the first aspect, in the seventh possible implementation of the defect root cause determination method, the encoder can be used to construct a multivariate Gaussian distribution or a multivariate t-distribution.

[0035] According to the embodiments of this application, by constructing a multivariate distribution in the encoder, each candidate defect root cause can be modeled as a real defect root cause multivariate distribution as each observed variable. In this process, the global correlation between design defects and manufacturing defects in a batch of failed chips can be taken into account, making the root cause inference results more accurate.

[0036] According to the fourth, fifth, sixth, or seventh possible implementation of the first aspect, in the eighth possible implementation of the defect root cause determination method, the decoder structure can be any of the following: multilayer perceptron, graph convolutional neural network, graph attention network.

[0037] According to the embodiments of this application, the true root cause distribution of defects in the latent variable space can be remapped to the observed variables through a graph network structure in the decoder to constrain the root cause distribution in the latent variable space and avoid overfitting. In this process, the local correlation between design defects and manufacturing defects in each failed chip can be taken into account, making the root cause inference results more accurate.

[0038] According to the first aspect or any of the first, second, third, fourth, fifth, sixth, seventh, or eighth possible implementations of the first aspect, in a ninth possible implementation of the defect root cause determination method, the diagnostic information may include first diagnostic information corresponding to the design defect. Based on the layout and the diagnostic information, first characteristic information is determined, which may include:

[0039] Based on the layout and diagnostic information, identify the layout image segments in the layout, and each layout image segment corresponds to the location of the design defect;

[0040] Cluster the equivalent image segments in the image segments to determine the equivalence classes;

[0041] Based on the first diagnostic information corresponding to the equivalence class, determine the feature information corresponding to the design defect in the first feature information.

[0042] According to the embodiments of this application, by clustering equivalent image segments within the layout and determining equivalence classes, the first diagnostic information can be integrated to remove redundant diagnostic information of design defects, making the feature information corresponding to design defects in the determined first feature information more concise, and subsequently able to more accurately and efficiently determine the root cause of defects from design defects and manufacturing defects.

[0043] According to the ninth possible implementation of the first aspect, in the tenth possible implementation of the defect root cause determination method, the equivalence may include at least one of rotational equivalence, mirror equivalence, and translation equivalence between image segments.

[0044] According to the embodiments of this application, by clustering the image segments that are rotationally equivalent, mirror-equivalent, and translationally equivalent, redundant information in the first diagnostic information can be more comprehensively identified, making the identified first feature information more concise and improving the efficiency and accuracy of subsequent root cause inference.

[0045] According to the first aspect or any of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, or tenth possible implementations of the first aspect, in the eleventh possible implementation of the defect root cause determination method, the diagnostic information may include second diagnostic information corresponding to a manufacturing defect. Based on the layout and the diagnostic information, the first characteristic information is determined, which may include:

[0046] Based on the second diagnostic information, the feature information corresponding to the manufacturing defect in the first feature information is determined.

[0047] According to the embodiments of this application, by utilizing the diagnostic information corresponding to the manufacturing defect to determine the corresponding feature information of the manufacturing defect, more targeted inferences can be made when determining the root cause in the subsequent process.

[0048] Secondly, embodiments of this application provide a defect root cause determination apparatus. The apparatus includes:

[0049] The acquisition module is used to acquire the chip layout and diagnostic information on defects in the chip;

[0050] The first determining module is used to determine the first feature information based on the layout and diagnostic information. The first feature information includes feature information corresponding to manufacturing defects and design defects, respectively.

[0051] The second determination module is used to determine the root cause defects in manufacturing and design defects through a neural network model based on the first feature information.

[0052] According to the second aspect, in a first possible implementation of the defect root cause determination device, the second determination module can be used to:

[0053] Based on the first feature information, the probability distribution of manufacturing defects and design defects is determined through a neural network model;

[0054] Based on the probability distribution of manufacturing defects and design defects, identify the defects that are the root causes among manufacturing defects and design defects.

[0055] According to the second aspect or the first possible implementation of the second aspect, in the second possible implementation of the defect root cause determination device, the second determination module can be used for:

[0056] The neural network model determines second feature information based on the first feature information, which is used to indicate the probability distribution of manufacturing defects and design defects;

[0057] The neural network model uses second feature information to identify defects that are the root cause of manufacturing and design defects.

[0058] According to the second possible implementation of the second aspect, in the third possible implementation of the defect root cause determination device, the second feature information is used to indicate the probability distribution of manufacturing defects and design defects in the chip, and the neural network model, based on the second feature information, determines the defects that are the root causes among the manufacturing defects and design defects, including:

[0059] The neural network model determines the probability distribution of manufacturing defects and design defects in all chips in the current batch based on the second feature information.

[0060] Based on the probability distribution of manufacturing defects and design defects in all chips of the current batch, identify the root causes of manufacturing defects and design defects.

[0061] According to the second or third possible implementation of the second aspect, in the fourth possible implementation of the defect root cause determination device, the second feature information is optimized second feature information, the neural network model can be a latent variable model, and the neural network model determines the second feature information based on the first feature information, which may include:

[0062] The first feature information is input into the encoder of the latent variable model to determine the initial second feature information;

[0063] The initial second feature information is input into the decoder of the latent variable model to determine the third feature information;

[0064] The first loss function value corresponding to the encoder is calculated based on the initial second feature information;

[0065] Calculate the second loss function value corresponding to the decoder based on the third feature information;

[0066] The latent variable model is optimized based on the first and second loss function values ​​to determine the optimized latent variable model.

[0067] Based on the optimized latent variable model, the optimized second feature information is determined.

[0068] According to the fourth possible implementation of the second aspect, in the fifth possible implementation of the defect root cause determination device, the third feature information is the reconstructed second feature information, used to indicate the correlation between different defects on the same chip.

[0069] According to the fourth or fifth possible implementation of the second aspect, in the sixth possible implementation of the defect root cause determination device, the feature value in the third feature information can be 0 or 1.

[0070] According to the fourth, fifth, or sixth possible implementation of the second aspect, in the seventh possible implementation of the defect root cause determination device, the encoder can be used to construct a multivariate Gaussian distribution or a multivariate t-distribution.

[0071] According to the fourth, fifth, sixth, or seventh possible implementation of the second aspect, in the eighth possible implementation of the defect root cause determination device, the decoder structure can be any of the following: multilayer perceptron, graph convolutional neural network, graph attention network.

[0072] According to the second aspect or any of the first, second, third, fourth, fifth, sixth, seventh, or eighth possible implementations of the second aspect, in a ninth possible implementation of the defect root cause determination device, the diagnostic information may include first diagnostic information corresponding to a design defect, and the first determination module may be used for:

[0073] Based on the layout and diagnostic information, identify the layout image segments in the layout, and each layout image segment corresponds to the location of the design defect;

[0074] Cluster the equivalent image segments in the image segments to determine the equivalence classes;

[0075] Based on the first diagnostic information corresponding to the equivalence class, determine the feature information corresponding to the design defect in the first feature information.

[0076] According to the ninth possible implementation of the second aspect, in the tenth possible implementation of the defect root cause determination device, the equivalence may include at least one of rotational equivalence, mirror equivalence, and translational equivalence between image segments.

[0077] According to the second aspect or any of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, or tenth possible implementations of the second aspect, in the eleventh possible implementation of the defect root cause determination device, the diagnostic information may include second diagnostic information corresponding to a manufacturing defect, and the first determination module may be used for:

[0078] Based on the second diagnostic information, the feature information corresponding to the manufacturing defect in the first feature information is determined.

[0079] Thirdly, embodiments of this application provide a defect root cause determination apparatus, the apparatus comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to execute instructions to implement one or more of the defect root cause determination methods described in the first aspect or in various possible implementations of the first aspect.

[0080] Fourthly, embodiments of this application provide a non-volatile computer-readable storage medium storing computer program instructions thereon, which, when executed by a processor, implement one or more of the defect root cause determination methods described in the first aspect or various possible implementations of the first aspect.

[0081] Fifthly, embodiments of this application provide a terminal device that can execute one or more of the defect root cause determination methods described in the first aspect or various possible implementations of the first aspect.

[0082] In a sixth aspect, embodiments of this application provide a computer program product including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in an electronic device, a processor in the electronic device executes one or more of the defect root cause determination methods described in the first aspect or various possible implementations of the first aspect.

[0083] These and other aspects of this application will become more apparent in the description of the following embodiments(s). Attached Figure Description

[0084] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this application together with the specification and serve to explain the principles of this application.

[0085] Figure 1 A schematic diagram illustrating an application scenario according to an embodiment of this application is shown.

[0086] Figure 2 A flowchart illustrating a defect root cause determination method according to an embodiment of this application is shown.

[0087] Figure 3 A flowchart illustrating a defect root cause determination method according to an embodiment of this application is shown.

[0088] Figure 4 A schematic diagram showing a section of images according to an embodiment of this application.

[0089] Figure 5 This diagram illustrates the clustering of image segments according to an embodiment of the present application.

[0090] Figure 6 A flowchart illustrating a defect root cause determination method according to an embodiment of this application is shown.

[0091] Figure 7 A schematic diagram of the architecture of a latent variable model according to an embodiment of this application is shown.

[0092] Figure 8 A structural diagram of a defect root cause determination apparatus according to an embodiment of this application is shown.

[0093] Figure 9 A structural diagram of an electronic device 900 according to an embodiment of this application is shown. Detailed Implementation

[0094] Various exemplary embodiments, features, and aspects of this application will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0095] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0096] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0097] With the development of electronic product functions and the expansion of application areas, chips, as the core components of electronic products, have become an indispensable part of people's lives. Chip production is mainly divided into two parts: layout design and manufacturing. Layout design typically includes multi-layered circuit functional design, while manufacturing includes processes such as production, packaging, and testing. When the same chip design is used with different manufacturing processes, some circuit structures that are normal under the original process may have defects, leading to a lower-than-expected chip yield. These circuit structures that are prone to defects due to process changes are called design defects. In the same chip manufacturing process, manufacturing stages that frequently cause chip failure under different layout designs are called manufacturing defects.

[0098] Design and manufacturing defects increase the likelihood of integrated circuit (IC) malfunctions. Chips with malfunctioning circuitry cannot be used properly, leading to a decrease in chip yield. Chip yield refers to the ratio of the number of chips that pass all process steps to the number of usable chips on the entire wafer. A decrease in yield increases production costs and may even cause related products to miss their sales window. Therefore, given the increasingly shorter chip time-to-market, a key issue to address is how to promptly identify the root causes of declining chip yields from a large number of defects, thereby maintaining a stable high chip yield and reducing chip production costs.

[0099] In view of this, this application proposes a defect root cause determination method. This method can obtain the chip layout and fault diagnosis report, analyze the relevant information of chip design defects and manufacturing defects, and use a neural network model to deduce the defect root causes that lead to a decrease in chip yield. This can help to improve the chip-related design or manufacturing process in the future, so as to reduce the cost increase caused by low yield.

[0100] Figure 1 A schematic diagram illustrating an application scenario according to an embodiment of this application is shown. For example... Figure 1As shown, the defect root cause determination system 100 of this application embodiment can be integrated as a software system into the software used by users for chip design and yield analysis. This software can be deployed in terminal devices or servers.

[0101] In one application scenario, when a predetermined number of chips in a batch have a yield rate lower than a predetermined threshold, the defect root cause determination system of this application embodiment can be used to determine the root cause of the low chip yield for the chips in the batch with a yield rate lower than the threshold (which can be referred to as failed chips). Figure 1 As shown, the system can input the layout of the batch of chips and the batch fault diagnosis reports of each failed chip. Each fault diagnosis report can include relevant information on the candidate root causes of defects in the corresponding failed chip. The defect root cause determination system of this application embodiment can determine the true root causes of chip yield decline by analyzing the relevant information on chip design defects and manufacturing defects in the layout and batch fault diagnosis reports. Specifically, the probability distribution of each candidate defect root cause (including design defects and / or manufacturing defects) can be determined, i.e., the probability that each defect is the true root cause (e.g., ...). Figure 1 The horizontal bar chart shows the probability of each defect, and this probability distribution helps determine the true root cause of the chip yield reduction. This can assist in subsequent improvements to the chip's design or manufacturing process. For example, if the root cause of the chip yield reduction is determined to be a manufacturing defect, such as a short circuit in the manufacturing process, improvements can be made to the corresponding manufacturing process to target the specific short circuit location. Similarly, if the root cause is determined to be a design defect, such as an open circuit in the chip's layout design, improvements can be made to the corresponding design process.

[0102] The terminal device involved in this application can refer to a device with wireless connection capability, which means that it can connect to other terminal devices or servers through wireless connection methods such as Wi-Fi and Bluetooth. The terminal device of this application can also have wired connection communication capability. The terminal device of this application can be touch screen, non-touch screen, or screenless. Touch screen devices can be controlled by clicking, swiping, etc. on the display screen with fingers, styluses, etc. Non-touch screen devices can be connected to input devices such as mice, keyboards, touch panels, etc., to control the terminal device through input devices. Screenless devices can be, for example, Bluetooth speakers without screens. For example, the terminal device of this application can be a smartphone, netbook, tablet computer, laptop computer, wearable electronic device (such as smart bracelet, smartwatch, etc.), TV, virtual reality device, speaker, e-ink, etc. For example, the defect root cause determination system 100 of this application can be deployed on the terminal device. Users can input data (layout and batch fault diagnosis report) into the terminal device to use the defect root cause determination system 100 of this application to determine the defects that are the root causes of manufacturing defects and design defects.

[0103] The server involved in this application can be located in the cloud or locally, and can be a physical device or a virtual device, such as a virtual machine or container, with wireless communication capabilities. These wireless communication capabilities can be configured in the server's chip (system) or other components. It can refer to a device with wireless connectivity, meaning it can connect to other servers or terminal devices via wireless connection methods such as Wi-Fi or Bluetooth. The server in this application can also have wired communication capabilities. For example, the server in this application can be located in the cloud, communicate with terminal devices, receive data (layout and batch fault diagnosis reports) sent by the terminal devices, and use a defect root cause determination system 100 deployed on the server to determine the defects that are the root causes of manufacturing and design defects, and return the inference results to the terminal devices.

[0104] It should be noted that the defect root cause determination method of this application embodiment can also be applied to other application scenarios besides those described above, and this application does not impose any restrictions on it.

[0105] The following is passed Figures 2-7 The method for determining the root cause of defects according to the embodiments of this application will be described in detail.

[0106] Figure 2 A flowchart illustrating a defect root cause determination method according to an embodiment of this application is shown. This method can be used in terminal devices or servers, such as in the defect root cause determination system 100 described above. Figure 2 As shown, the method includes:

[0107] Step S201: Obtain the chip layout and diagnostic information on defects in the chip.

[0108] For example, when the yield of a predetermined number of chips in a batch falls below a predetermined threshold, the layout and diagnostic information of that batch of chips can be obtained. The chip layout can be a planar geometric description of the physical state of the integrated circuit, corresponding to the chips in that batch, which can be manufactured based on the same layout. For each defective chip in the batch, a corresponding fault diagnosis report can be generated. Each defective chip (also known as a failure) can correspond to a separate fault diagnosis report. Each fault diagnosis report can include relevant statistical information about the defects present in the corresponding chip, such as the location of the defect in the layout, the defect type, and the frequency of the defect occurrence. These defects can include design defects and manufacturing defects, corresponding to various candidate root causes. Diagnostic information can be obtained from the fault diagnosis reports corresponding to that batch of chips and can represent statistical information about the candidate root causes of defects.

[0109] Optionally, the diagnostic information may include first diagnostic information corresponding to the design defect. When the candidate defect root cause is a design defect, the first diagnostic information obtained can be found in Table 1, which shows an example of the first diagnostic information obtained from the fault diagnosis report.

[0110] Table 1

[0111] 138238 1 780 90％ M1 OPEN <float> < / float>

[0112] The identifier can be the number corresponding to the design defect (e.g., 138238); the current occurrence count can indicate the number of times the design defect appears in the current fault diagnosis report (e.g., 1 time); the total occurrence count can indicate the number of times the design defect appears in all fault diagnosis reports of this batch (e.g., 780 times); the defect root cause probability can indicate the probability that the design defect is the root cause among all defects appearing in the current fault diagnosis report (e.g., 90%); the layer can indicate which layer of the chip the design defect is located on (e.g., M1 layer); the defect type can indicate the type of the design defect (e.g., 'OPEN' indicates that the design defect has an open circuit structure, and 'SHORT' indicates that the design defect has a short circuit structure); and the coordinate position can indicate the coordinates of the design defect in its layer, which can be two-dimensional floating-point coordinates. The diagnostic information corresponding to the design defect may also include a portion of the statistical information shown in Table 1, or more information than shown in Table 1.

[0113] Optionally, the diagnostic information may further include second diagnostic information corresponding to the manufacturing defect. When the candidate defect root cause is a manufacturing defect, the acquired second diagnostic information may include: the identifier of the manufacturing defect, such as the number or name of the manufacturing defect; the area of ​​the manufacturing defect in a critical region, which may represent the area in the corresponding chip where the defect exists; the probability that the manufacturing defect is the root cause among the defects in the critical region; and the yield analysis constant of the manufacturing defect, which may indicate the prevalence of the manufacturing defect in this type of chip, etc.

[0114] The first and second diagnostic information can be obtained based on relevant technologies. After acquiring the layout and diagnostic information, the design and manufacturing characteristics of the chip can be comprehensively considered based on the layout and diagnostic information to determine the characteristic information corresponding to manufacturing defects and design defects, respectively, in order to analyze the root causes of defects. See below.

[0115] Step S202: Determine the first feature information based on the layout and diagnostic information.

[0116] The first feature information may include feature information corresponding to manufacturing defects and design defects, respectively.

[0117] For example, feature vectors corresponding to each manufacturing defect and design defect can be determined first. These feature vectors may include one (e.g., a one-dimensional vector) or multiple (e.g., a multi-dimensional vector) feature values. These one or more feature values ​​indicate the likelihood of the defect being the root cause in the current fault diagnosis report. For instance, when the feature vector is a multi-dimensional vector, each feature value in the multi-dimensional vector can indicate the likelihood of the defect being the root cause in the current fault diagnosis report from different dimensions. For example, for a given defect, the feature values ​​in the multi-dimensional vector corresponding to that defect can be determined separately using information from different dimensions in the diagnostic information. Alternatively, the weighted average of the feature values ​​in the vector can also indicate the likelihood of the defect being the root cause in the current fault diagnosis report. The following explanation uses the example of a one-dimensional feature vector corresponding to each defect, i.e., one feature value per defect, to illustrate step S202.

[0118] For example, for each fault diagnosis report, the corresponding vector r can be determined first. m :

[0119]

[0120] Where m can represent the fault diagnosis report number, and d can represent the total number of defects in the m-th fault diagnosis report. It can represent the characteristic value corresponding to the i-th defect in the m-th fault diagnosis report. This characteristic value can be a positive real number. The larger the characteristic value, the greater the probability that the defect is the root cause defect. It can represent the characteristic value corresponding to a design defect or the characteristic value corresponding to a manufacturing defect.

[0121] The characteristic value r corresponding to a manufacturing defect can be determined based on the second diagnostic information mentioned above. For example, it can be determined based on the area of ​​the manufacturing defect in the critical region and the probability that the manufacturing defect is the root cause among all defects in the critical region. The larger the area of ​​the manufacturing defect in the critical region and the higher the probability that it is the root cause among all defects in the critical region, the larger the determined characteristic value r can be. If each manufacturing defect corresponds to a multi-dimensional vector, for example, a two-dimensional vector, in one possible implementation, the two characteristic values ​​in the two-dimensional vector can be determined respectively by the area of ​​the manufacturing defect in the critical region and the probability that the manufacturing defect is the root cause among all defects in the critical region.

[0122] The characteristic value *r* corresponding to the design defect can be determined based on the aforementioned first diagnostic information. For example, it can be determined based on statistical information such as the number of times the design defect appears in the current fault diagnosis report, the total number of occurrences, and the probability of the defect being a root cause. The greater the number of times the design defect appears in the current fault diagnosis report, the greater the total number of occurrences, and the higher the statistical probability of it being a root cause, the larger the determined characteristic value *r* can be. If each design defect corresponds to a multi-dimensional vector, for example, a two-dimensional vector, one possible implementation is to determine one characteristic value in the two-dimensional vector based on the number of times the design defect appears in the current fault diagnosis report, and to determine another characteristic value in the two-dimensional vector based on the total number of occurrences and the probability of the defect being a root cause.

[0123] After determining the characteristic value r corresponding to each defect, the characteristic information corresponding to each manufacturing defect and each design defect in the first characteristic information can be determined based on the characteristic value.

[0124] For manufacturing defects, the characteristic value r corresponding to the manufacturing defect can be determined based on the second diagnostic information (see above), and the characteristic value r can be directly used as the characteristic information corresponding to the manufacturing defect in the first characteristic information, as shown below:

[0125] Optionally, when determining the feature information corresponding to each manufacturing defect in the first feature information, step S202 may include:

[0126] Based on the second diagnostic information, the feature information corresponding to the manufacturing defect in the first feature information is determined.

[0127] The feature information in the first feature information corresponding to the manufacturing defect may include the feature value r corresponding to the manufacturing defect.

[0128] According to the embodiments of this application, by utilizing the diagnostic information corresponding to the manufacturing defect to determine the corresponding feature information of the manufacturing defect, more targeted inferences can be made when determining the root cause in the subsequent process.

[0129] Regarding design defects, since there may be equivalent duplicate image segments in the layout, there may be redundant design defect diagnosis information in the fault diagnosis report. The repetition of design defects may lead to a dispersed probability distribution of root causes when inferring root causes, reducing the accuracy of the inference. Therefore, when determining the feature information corresponding to each design defect in the first feature information, we can first use the equivalent image segments identified in the layout to remove duplicate information from the first diagnosis information corresponding to each fault diagnosis report, as shown below:

[0130] Figure 3 A flowchart illustrating a defect root cause determination method according to an embodiment of this application is shown. Figure 3 As shown, step S202 may include:

[0131] Step S2021: Based on the layout and diagnostic information, determine the layout image segment in the layout.

[0132] The number of layout image segments can be one or more, each corresponding to a location of a design defect. For example, based on the layer and coordinates of the design defect in the first diagnostic information, the location of the corresponding design defect can be located in the layout, and a layout image segment of a predetermined area corresponding to the location of the design defect can be obtained. This application does not limit the method or size of determining the layout image segments, as long as they can contain the location of the design defect.

[0133] See Figure 4 The image shows a schematic diagram of a section of a page according to an embodiment of this application. Figure 4 In the illustrated example of image segments, there are equivalent image segments. This equivalence can include at least one of rotational equivalence, mirror equivalence, and translational equivalence between image segments. For example, image segments (1) and (4) are rotationally (or mirrorally) equivalent; image segments (2), (3), and (5) are equivalent, wherein image segments (2) and (3) are translationally equivalent, and image segments (2) and (5) are mirrorally equivalent. The method for determining equivalent image segments is described below.

[0134] Step S2022: Cluster the equivalent image segments in the image segments to determine the equivalence classes.

[0135] For example, a convolutional neural network (CNN) model can be used as an encoder to extract feature vectors of image segments in the feature space (i.e., input the image segments into the CNN encoder and output the feature vectors corresponding to each image segment), and then cluster the extracted feature vectors to determine the equivalence classes between image segments.

[0136] The CNN model can employ feature extraction networks such as Residual Networks (ResNET), Xception, and Inception to extract features from image segments. The CNN model can be trained using a self-supervised strategy of contrastive learning. During training, loss functions suitable for contrastive learning can be used for optimization, such as triplet loss or normalized temperature-scaled cross entropy loss (NT-Xent). Training data for the CNN model can be generated by rotating, mirroring, or translating image segments.

[0137] The method for clustering the extracted feature vectors can be to use clustering algorithms such as k-means, k-medoids, Gaussian mixture model, and density-based spatial clustering of applications with noise (DBSCAN) to obtain the image segments and their corresponding equivalence class labels, thereby determining the equivalence classes that exist between the image segments.

[0138] See Figure 5 This diagram illustrates clustering of image segments according to an embodiment of this application. Figure 5 As shown, after clustering, the image segments from each version can be classified into different equivalence classes.

[0139] For example, image segments (1) and (4) are clustered into the first equivalence class (equivalence class 1 in the figure); image segments (2), (3), and (5) are clustered into the second equivalence class (equivalence class 2 in the figure). Each equivalence class corresponds to a design defect.

[0140] Therefore, redundant first diagnostic information in the fault diagnosis report can be identified.

[0141] Step S2023: Based on the first diagnostic information corresponding to the equivalence class, determine the feature information corresponding to the design defect in the first feature information.

[0142] For example, for the feature vector r corresponding to each fault diagnosis report m Based on the equivalence class labels of the image segments, for the same equivalence class, in r m The system retains a predetermined number (e.g., one) of the feature values ​​*r* from one or more design defects corresponding to the equivalence class, removing other redundant feature values. If the feature values ​​of multiple design defects corresponding to the equivalence class are different, a predetermined number of feature values ​​can be determined according to preset conditions or randomly as the retained feature values. This is equivalent to removing redundant first diagnostic information from the corresponding fault diagnosis report. The feature value *r* corresponding to the design defect remaining after removing redundant values ​​can be used as the feature information corresponding to the design defect in the first feature information.

[0143] It should be noted that, based on the equivalence class labels of the image segments, for the same equivalence class, first retain the diagnostic information of a predetermined number (e.g., 1) of the corresponding design defects in the first diagnostic information, remove other redundant diagnostic information, and then determine the feature information (the feature value corresponding to the design defect) in the first feature information based on the remaining first diagnostic information.

[0144] According to the embodiments of this application, by clustering equivalent image segments within the layout and determining equivalence classes, the first diagnostic information can be integrated to remove redundant diagnostic information of design defects, making the feature information corresponding to design defects in the determined first feature information more concise, and subsequently able to more accurately and efficiently determine the root cause of defects from design defects and manufacturing defects.

[0145] See back Figure 2 After determining the first feature information, the root cause of the defect can be inferred using a neural network model based on the first feature information, as described below.

[0146] Step S203: Based on the first feature information, determine the root cause of manufacturing defects and design defects through a neural network model.

[0147] In the inference process using a neural network model, by inputting the first feature information, different candidate root causes of defects can be modeled as different variables rather than the same variable and input into the neural network model. This allows for consideration of the complex interactions between root causes, thus more accurately identifying the defects that are the root causes in manufacturing and design defects. The first feature information determined through the above steps can be represented as the following vector x. n :

[0148]

[0149] 'n' can represent the corresponding fault diagnosis report number, and the value of 'n' can range from 1 to N, where N is the total number of fault diagnosis reports (or the total number of failed chips). 'j' can represent the corresponding defect number, and 'k' can represent the total number of manufacturing defects and design defects corresponding to fault diagnosis report 'n'. It can represent the feature vector corresponding to the j-th defect in the fault diagnosis report n (as mentioned above, it can be a one-dimensional or multi-dimensional vector), and can correspond to one candidate root cause of the defect.

[0150] According to embodiments of this application, by acquiring the chip layout and diagnostic information, feature information corresponding to manufacturing defects and design defects respectively is determined. This allows for the simultaneous consideration of both chip design and manufacturing defects, resulting in a more comprehensive inference of root causes. By utilizing neural network models to deduce the root causes of defects leading to decreased chip yield, the interaction relationships between complex root causes can be taken into account, making the inferred root causes more accurate. This, in turn, better assists in subsequent improvements to chip-related designs or manufacturing processes, thereby reducing the cost increases caused by low yield.

[0151] Optionally, step S203 may also include:

[0152] Based on the first feature information, the probability distribution of manufacturing defects and design defects is determined through a neural network model.

[0153] In other words, the output of the neural network model can be either the root cause of manufacturing defects or design defects, or the probability distribution of manufacturing defects and design defects. After determining the probability distribution of manufacturing defects and design defects, the root cause of manufacturing defects and design defects can be determined based on the probability distribution.

[0154] Optionally, the neural network model can be a latent variable model. The process of determining the root cause of manufacturing defects and design defects through the latent variable model based on the first feature information is described below.

[0155] Figure 6 A flowchart illustrating a defect root cause determination method according to an embodiment of this application is shown. Figure 6 As shown, step S203 may include:

[0156] Step S2031: The neural network model determines the second feature information based on the first feature information.

[0157] The first feature information may include the aforementioned vector x. n (These can be referred to as observed variables), and for each fault diagnosis report, a corresponding feature vector x can be determined. nThe first feature information may include N feature vectors (N being the total number of fault diagnosis reports). Each feature vector x n Each feature vector included in the fault diagnosis report can correspond to a defect indicated in the report; that is, each defect can be used as a variable input into the neural network model.

[0158] The second feature information can be the input x. n The corresponding feature representation (i.e., the latent variable feature vector in the latent variable model) can be used to indicate the probability distribution of manufacturing defects and design defects, thereby inferring the true root causes of chip defects in manufacturing and design defects based on the probability distribution. N first feature information can determine N second feature information.

[0159] By constructing different defects as different variables and inputting the corresponding first feature information into a neural network model, the root cause of manufacturing and design defects can be identified. This allows for consideration of the complex interrelationships between different defects, thus enabling more accurate inference of the root cause of defects.

[0160] The aforementioned second feature information can be optimized second feature information. The method for determining the optimized second feature information is described below. Step S2031 may include:

[0161] The first feature information is input into the encoder of the latent variable model to determine the initial second feature information.

[0162] Among them, see Figure 7 The diagram shows a schematic representation of the architecture of a latent variable model according to an embodiment of this application.

[0163] The first feature information can be seen in the figure as x, which corresponds to the vector x mentioned above. n The second feature information can be seen in the figure as z, which corresponds to the latent variable feature vector z. n , z n Each eigenvector in the model can be related to the observed variable x. n Corresponding (e.g., one-to-one correspondence), where z n Each eigenvector in the model can represent the probability that the corresponding defect in the fault diagnosis report n (i.e. the nth failed chip) determined by the latent variable model is the root cause among all defects.

[0164] The encoder for the latent variable model can be found in [reference needed]. Figure 7 The encoder can be used to consider the global correlation between design defects and manufacturing defects in all defects of a batch of failed chips, thereby establishing a mapping relationship between observed variables and latent variables. Optionally, the encoder can be used to construct a multivariate Gaussian distribution or a multivariate t-distribution.

[0165] For example, see Figure 7 As shown, an encoder can be used to establish the following multivariate Gaussian distribution to learn the global correlation between design defects and manufacturing defects:

[0166] z~N(μ z ,∈ z ) Formula (3)

[0167] Where, μ z and ∈ z This can represent the parameters of a multivariate Gaussian distribution. ∈ z It can follow the following Gaussian distribution:

[0168]

[0169] It can represent the covariance matrix of the observed variable x, and can be calculated in advance.

[0170] After determining the latent variables (i.e. the initial second feature information), they can be input into the decoder of the latent variable model for feature reconstruction to constrain the root cause distribution in the latent variable space, avoid overfitting, and determine the third feature information.

[0171] The decoder can be found here. Figure 7 In the Decoder, the third feature information can represent the reconstructed second feature information, as shown in s in the figure. The feature vector in the third feature information s can correspond to the latent variable z (e.g., one-to-one correspondence).

[0172] Alternatively, the decoder can be structured as any of the following: multilayer perceptron, graph convolutional network (GCN), or graph attention network (GAT).

[0173] Therefore, the local correlation between design defects and manufacturing defects in each failed chip can be considered, thereby establishing a mapping relationship between hidden variables and s (see the example of the mapping between z1, z2, z3, z4 and s1, s2, s3, s4 in the figure).

[0174] To better guide the model in learning the local correlations between different defects, the feature value in the third feature information can optionally be 0 or 1.

[0175] In other words, the eigenvalues ​​in s can be represented in a binary format, where s nWhen the characteristic value of the corresponding defect is 1, it means that the defect appears in the defect corresponding to the observed variable for the fault diagnosis report n; when the characteristic value of the corresponding defect is 0, it means that the defect does not appear in the defect corresponding to the observed variable for the fault diagnosis report n.

[0176] In the process of optimizing the latent variable model, the encoder and decoder of the latent variable model can be optimized together, as shown below:

[0177] The first loss function value corresponding to the encoder can be calculated based on the initial second feature information, and the second loss function value corresponding to the decoder can be calculated based on the third feature information.

[0178] The overall optimization objective corresponding to the latent variable model can be determined based on the first loss function and the second loss function (which can be called the reconstruction loss function), and can be expressed as:

[0179] min L1+λL2 formula (5)

[0180] Here, L1 can represent the first loss function corresponding to the encoder, L2 can represent the reconstruction loss function corresponding to the decoder, and λ can represent the hyperparameter used to balance likelihood and reconstruction. The value of λ can be preset (e.g., 1). The two loss functions can be minimized simultaneously to perform co-optimization of the model.

[0181] The value of the first loss function L1 can be calculated, for example, using log-likelihood loss, and the value of the second loss function L2 can be calculated, for example, using binary crossentropy loss.

[0182] Therefore, the latent variable model can be optimized based on the first and second loss function values ​​to determine the parameters of the encoder and decoder of the optimized latent variable model, thus defining the optimized latent variable model. Based on the optimized latent variable model, the optimized second feature information can be determined.

[0183] Since optimizing the model allows us to determine the optimized decoder, we can then use the optimized decoder to determine the optimized second feature information based on the first feature information.

[0184] According to the embodiments of this application, by using the encoder to determine the initial second feature information, the global correlation of each defect in the batch of failed chips can be taken into account. By using the decoder to reconstruct the first feature information to obtain the third feature information, the local correlation of each defect in the same chip can be taken into account. Thus, the encoder and decoder of the latent variable model are co-optimized, so that the complex interaction between design defects and manufacturing defects can be comprehensively taken into account, and the root cause of the defect that leads to the decline in chip yield can be determined more accurately.

[0185] See back Figure 6 In step S2032, the neural network model determines the root cause of each manufacturing defect and design defect based on the second feature information.

[0186] This second feature information can be used to indicate the probability distribution of manufacturing defects and design defects in the chip. For example, a neural network model can first analyze N fault diagnosis reports based on z... n By using the softmax function for normalization, N probability distributions corresponding to N fault diagnosis reports are obtained, which can then be used to determine the probability distributions corresponding to manufacturing defects and design defects on each failed chip.

[0187] Wherein, in the eigenvector z n When the eigenvectors corresponding to manufacturing defects and design defects are multi-dimensional vectors, they can be first converted into one-dimensional vectors respectively (for example, using the average of the eigenvalues ​​in the multi-dimensional vector as the eigenvalues ​​in the one-dimensional vector), and then the converted z... n Perform normalization. Alternatively, you can first normalize the eigenvector z. n After normalization, we obtain N probability distributions corresponding to the N normalized fault diagnosis reports. Then, for each of the N probability distributions The multidimensional vectors corresponding to each defect are converted into one-dimensional vectors (for example, the sum of the probability values ​​in the multidimensional vector is used as the probability value in the one-dimensional vector).

[0188] Based on the probability distribution corresponding to each failed chip, the probability distribution corresponding to all defects in the batch can be determined (for example, see [link to relevant documentation]). Figure 1 (See the horizontal bar chart). The average of the probability distributions for the failed chips in the current batch can be used as the probability distribution for all defects in that batch:

[0189]

[0190] Wherein, p(c k This can be used to indicate the probability distribution of all defects in a batch. It can represent the normalized eigenvector zn If z n When the feature vectors corresponding to each defect are multi-dimensional vectors, this This can represent the transformed probability distribution, where the vector corresponding to each defect is a one-dimensional vector. If a fault diagnosis report does not contain a feature vector z... n If such a defect does not exist, then the second characteristic information z corresponding to the fault diagnosis report... n In formula (6), we take the value 0. In this probability distribution, if the probability value corresponding to a certain defect is 0.5, it can be said that 50% of the N failed chips in this batch are due to this defect. The more chips that fail due to the defect, the greater the probability that the corresponding defect is the true root cause.

[0191] Based on the probability distribution of manufacturing defects and design defects among all failed chips in the current batch, the root cause of manufacturing defects and design defects can be identified.

[0192] In the case of a single root cause, the defect with the highest probability value can be taken as the root cause; in the case of multiple root causes (e.g., k root causes), each defect corresponding to the k highest probability values ​​can be taken as the root cause.

[0193] Table 2 shows the accuracy of true defect root cause inference in the embodiments of this application under the condition of single root cause and no noise-annotated data:

[0194] Table 2

[0195]

[0196] As shown in Table 2, taking two different layout designs as examples, existing commercial tools achieve an accuracy rate of 77% in inferring the root causes of manufacturing defects and 84.62% in inferring the root causes of design defects for the first layout design (Layout Design 1); and an accuracy rate of 88.36% in inferring the root causes of manufacturing defects and 92.52% in inferring the root causes of design defects for the second layout design (Layout Design 2). In contrast, this application achieves an accuracy rate of 85.00% in inferring the root causes of manufacturing defects and 94.87% in inferring the root causes of design defects for the first layout design (Layout Design 1); and an accuracy rate of 97.88% in inferring the root causes of manufacturing defects and 94.30% in inferring the root causes of design defects for the second layout design (Layout Design 2).

[0197] Table 3 shows the accuracy of true defect root cause inference in the embodiments of this application under the case of a single root cause and noisy, mislabeled data:

[0198] Table 3

[0199]

[0200] As shown in Table 3, taking two different layout designs as examples, existing commercial tools achieve an accuracy rate of 41.35% in inferring the root causes of manufacturing defects and 57.55% in inferring the root causes of design defects for the first layout design (Layout Design 1); and an accuracy rate of 74.57% in inferring the root causes of manufacturing defects and 82.62% in inferring the root causes of design defects for the second layout design (Layout Design 2). In contrast, this application achieves an accuracy rate of 66.35% in inferring the root causes of manufacturing defects and 71.13% in inferring the root causes of design defects for the first layout design (Layout Design 1); and an accuracy rate of 87.50% in inferring the root causes of manufacturing defects and 83.49% in inferring the root causes of design defects for the second layout design (Layout Design 2).

[0201] As can be seen from Tables 2 and 3, in the case of a single root cause, the accuracy of this application in inferring the root cause of design defects in two different layout designs is comparable to and higher than that of existing commercial tools. The accuracy of inferring the root cause of manufacturing defects is significantly improved compared to existing commercial tools, and the improvement exceeds 5% in different layout designs.

[0202] Table 4 shows the accuracy and average error of true defect root cause inference in the embodiments of this application under the condition of multiple root causes and noisy, mislabeled data:

[0203] Table 4

[0204]

[0205] As shown in Table 4, hit1, hit2, and hit3 represent the accuracy rates when hitting 1, 2, and 3 defect root causes, respectively, in the case of multiple root causes. WAME represents the weighted mean absolute error (WAME) of hit1, hit2, and hit3. Taking two different layout designs as examples, the existing commercial tools have the following accuracy rates for the first layout design (layout design 1): hit1 accuracy is 80.63%, hit2 accuracy is 24.56%, hit3 accuracy is 1.14%, and WAME is 0.2689; for the second layout design (layout design 2), hit1 accuracy is 97.89%, hit2 accuracy is 83.02%, hit3 accuracy is 37.97%, and WAME is 0.1918. In comparison, the accuracy of hit1 for the first layout design (layout design 1) is 99.10%, the accuracy of hit2 is 83.76%, the accuracy of hit3 is 30.82%, and the wame is 0.1259; for the second layout design (layout design 2), the accuracy of hit1 is 99.48%, the accuracy of hit2 is 94.32%, the accuracy of hit3 is 62.45%, and the wame is 0.0830.

[0206] As can be seen from Table 4, in the case of multiple root causes, the accuracy of defect root cause inference in this application exceeds that of existing commercial tools in both different layout designs, and WAME has also achieved an optimization of more than 20% compared with existing commercial tools. It can be seen that the probability distribution inference results of each defect as a root cause in this application are more accurate.

[0207] Figure 8 This diagram illustrates a structural diagram of a defect root cause determination apparatus according to an embodiment of the present application. This apparatus can be used in the aforementioned terminal device or server, such as in the aforementioned defect root cause determination system 100. Figure 8 As shown, the device includes:

[0208] The acquisition module 801 is used to acquire the chip layout and diagnostic information on defects in the chip;

[0209] The first determining module 802 is used to determine first feature information based on the layout and diagnostic information. The first feature information includes feature information corresponding to manufacturing defects and design defects, respectively.

[0210] The second determining module 803 is used to determine the defects that are the root causes of manufacturing defects and design defects through a neural network model based on the first feature information.

[0211] According to embodiments of this application, by acquiring the chip layout and diagnostic information, feature information corresponding to manufacturing defects and design defects respectively is determined. This allows for the simultaneous consideration of both chip design and manufacturing defects, resulting in a more comprehensive inference of root causes. By utilizing neural network models to deduce the root causes of defects leading to decreased chip yield, the interaction relationships between complex root causes can be taken into account, making the inferred root causes more accurate. This, in turn, better assists in subsequent improvements to chip-related designs or manufacturing processes, thereby reducing the cost increases caused by low yield.

[0212] Optionally, the diagnostic information may include first diagnostic information corresponding to the design defect. The first determining module 802 can be used for:

[0213] Based on the layout and diagnostic information, identify the layout image segments in the layout, and each layout image segment corresponds to the location of the design defect;

[0214] Cluster the equivalent image segments in the image segments to determine the equivalence classes;

[0215] Based on the first diagnostic information corresponding to the equivalence class, determine the feature information corresponding to the design defect in the first feature information.

[0216] According to the embodiments of this application, by clustering equivalent image segments within the layout and determining equivalence classes, the first diagnostic information can be integrated, redundant diagnostic information of design defects can be removed, and the feature information corresponding to design defects in the determined first feature information can be more concise, so that the root cause of defects can be determined more accurately and efficiently from design defects and manufacturing defects in the future.

[0217] Optionally, the equivalence may include at least one of rotational equivalence, mirror equivalence, and translation equivalence between image segments.

[0218] According to the embodiments of this application, by clustering the image segments that are rotationally equivalent, mirror-equivalent, and translationally equivalent, redundant information in the first diagnostic information can be more comprehensively identified, making the identified first feature information more concise and improving the efficiency and accuracy of subsequent root cause inference.

[0219] Optionally, the diagnostic information may include second diagnostic information corresponding to manufacturing defects. The first determining module 802 can be used for:

[0220] Based on the second diagnostic information, the feature information corresponding to the manufacturing defect in the first feature information is determined.

[0221] According to the embodiments of this application, by utilizing the diagnostic information corresponding to the manufacturing defect to determine the corresponding feature information of the manufacturing defect, more targeted inferences can be made when determining the root cause in the subsequent process.

[0222] Optionally, the second determining module 803 can be used for:

[0223] Based on the first feature information, the probability distribution of manufacturing defects and design defects is determined through a neural network model;

[0224] Based on the probability distribution of manufacturing defects and design defects, identify the defects that are the root causes among manufacturing defects and design defects.

[0225] According to the embodiments of this application, the probability distribution of manufacturing defects and design defects is determined by a neural network model, and the root cause of the defects is determined accordingly, which can make the inferred root cause of the defects more accurate.

[0226] Optionally, the second determining module 803 can be used for:

[0227] The neural network model determines second feature information based on the first feature information, which is used to indicate the probability distribution of manufacturing defects and design defects;

[0228] The neural network model uses second feature information to identify defects that are the root cause of manufacturing and design defects.

[0229] According to the embodiments of this application, by using a neural network model to determine the second feature information, the manufacturing defects and design defects indicated by the second feature information can be used to efficiently and accurately determine the defects that are the root causes. In this process, the complex interactions between different defects can be taken into account to determine the root causes of defects that lead to a decrease in chip yield.

[0230] Optionally, the second feature information is used to indicate the probability distribution of manufacturing defects and design defects in the chip. Based on the second feature information, the neural network model determines the defects that are the root causes of manufacturing defects and design defects, including:

[0231] The neural network model determines the probability distribution of manufacturing defects and design defects in all chips in the current batch based on the second feature information.

[0232] Based on the probability distribution of manufacturing defects and design defects in all chips of the current batch, identify the root causes of manufacturing defects and design defects.

[0233] According to the embodiments of this application, by utilizing the probability distribution of manufacturing defects and design defects in each chip, the probability distribution of manufacturing defects and design defects in all chips can be determined. This allows for the identification of the overall root causes of failure in the current batch of chips due to manufacturing defects and design defects, thereby better assisting in subsequent improvements to chip-related designs or manufacturing processes to reduce the cost increase caused by low yield.

[0234] Optionally, the second feature information is optimized second feature information, and the neural network model can be a latent variable model. The neural network model determines the second feature information based on the first feature information, and may include:

[0235] The first feature information is input into the encoder of the latent variable model to determine the initial second feature information;

[0236] The initial second feature information is input into the decoder of the latent variable model to determine the third feature information;

[0237] The first loss function value corresponding to the encoder is calculated based on the initial second feature information;

[0238] Calculate the second loss function value corresponding to the decoder based on the third feature information;

[0239] The latent variable model is optimized based on the first and second loss function values ​​to determine the optimized latent variable model.

[0240] Based on the optimized latent variable model, the optimized second feature information is determined.

[0241] According to the embodiments of this application, by using the encoder to determine the initial second feature information, the global correlation of each defect in the batch of failed chips can be taken into account. By using the decoder to obtain the third feature information, the local correlation of each defect in the same chip can be taken into account. Thus, the encoder and decoder of the latent variable model are co-optimized, so that the complex interaction between design defects and manufacturing defects can be comprehensively taken into account, and the root cause of defects that lead to a decrease in chip yield can be determined more accurately.

[0242] Optionally, the third feature information is the reconstructed second feature information, used to indicate the correlation between different defects on the same chip.

[0243] According to the embodiments of this application, by reconstructing the second feature information to obtain the third feature information, the third feature information can be used to constrain the second feature information, thereby utilizing the correlation between different defects on the same chip indicated by the third feature information to better learn the local correlation of each defect in the same chip.

[0244] Optionally, the feature value in the third feature information can be 0 or 1.

[0245] According to the embodiments of this application, by making each feature value in the third feature information a binary value, the decoder can better learn the local correlation between design defects and manufacturing defects in each failed chip, so as to more accurately determine the root cause of defects that lead to a decrease in chip yield.

[0246] Optionally, the encoder can be used to construct a multivariate Gaussian distribution or a multivariate t-distribution.

[0247] According to the embodiments of this application, by constructing a multivariate distribution in the encoder, each candidate defect root cause can be modeled as a real defect root cause multivariate distribution as each observed variable. In this process, the global correlation between design defects and manufacturing defects in a batch of failed chips can be taken into account, making the root cause inference results more accurate.

[0248] Alternatively, the decoder can be structured as any of the following: multilayer perceptron, graph convolutional neural network, or graph attention network.

[0249] According to the embodiments of this application, the distribution of real defect root causes in the latent variable space can be remapped to the observed variables through a graph network structure in the decoder to constrain the root cause distribution in the latent variable space and avoid overfitting. In this process, the local correlation between design defects and manufacturing defects in each failed chip can be taken into account, making the root cause inference results more accurate.

[0250] Embodiments of this application provide a defect root cause determination apparatus, including: a processor and a memory for storing processor-executable instructions; wherein the processor is configured to implement the above method when executing the instructions.

[0251] An embodiment of this application provides a terminal device that can perform the above-described defect root cause determination method.

[0252] Embodiments of this application provide a non-volatile computer-readable storage medium storing computer program instructions thereon, which, when executed by a processor, implement the above-described method.

[0253] Embodiments of this application provide a computer program product including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the above-described method.

[0254] Figure 9 A structural diagram of an electronic device 900 according to an embodiment of this application is shown. Figure 9 As shown, the electronic device 900 can be either the aforementioned server or the aforementioned terminal device, performing the aforementioned... Figures 2-7 The function of the server or terminal device in any of the defect root cause determination methods shown can also be the aforementioned defect root cause determination system 100. The electronic device 900 includes at least one processor 1801, at least one memory 1802, and at least one communication interface 1803. Furthermore, the electronic device may also include general components such as antennas, which will not be detailed here.

[0255] The following is combined with Figure 9 A detailed introduction to each component of the electronic device 900 is provided.

[0256] Processor 1801 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of programs in the above scheme. Processor 1801 may include one or more processing units, such as: processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors.

[0257] The communication interface 1803 is used to communicate with other electronic devices or communication networks, such as Ethernet, Radio Access Network (RAN), core network, Wireless Local Area Networks (WLAN), etc.

[0258] The memory 1802 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed discs, laser discs, optical discs, digital universal discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. The memory may exist independently and be connected to the processor via a bus. The memory may also be integrated with the processor.

[0259] The memory 1802 stores the application code for executing the above scheme, and its execution is controlled by the processor 1801. The processor 1801 executes the application code stored in the memory 1802.

[0260] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0261] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), electrically programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital video disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing.

[0262] The computer-readable program instructions or code described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0263] The computer program instructions used to perform the operations of this application may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuits, such as programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), are personalized by utilizing state information from computer-readable program instructions. These electronic circuits can execute computer-readable program instructions to implement various aspects of this application.

[0264] Various aspects of this application are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0265] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0266] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0267] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved.

[0268] It should also be noted that each block in the block diagram and / or flowchart, as well as combinations of blocks in the block diagram and / or flowchart, can be implemented using hardware (such as circuits or ASICs (Application Specific Integrated Circuits)) that performs the corresponding function or action, or using a combination of hardware and software, such as firmware.

[0269] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0270] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for determining the root cause of a defect, characterized in that, The method includes: The layout of the chip and diagnostic information of defects in the chip are obtained from the chip's fault diagnosis report; Based on the layout and the diagnostic information, first feature information is determined. The first feature information includes feature information corresponding to manufacturing defects and design defects, respectively. Each feature vector included in the first feature information corresponds to a defect indicated in the fault diagnosis report. By constructing different manufacturing defects and design defects as different variables, and inputting the corresponding first feature information into a neural network model, the root cause defect among the manufacturing defects and design defects is determined.

2. The method according to claim 1, characterized in that, The method involves constructing different manufacturing defects and design defects as different variables, inputting the corresponding first feature information into a neural network model, and determining the defects that serve as root causes among the manufacturing defects and design defects, including: The neural network model determines second feature information based on the first feature information, and the second feature information is used to indicate the probability distribution of the manufacturing defects and design defects; The neural network model determines the root cause of the manufacturing and design defects based on the second feature information.

3. The method according to claim 2, characterized in that, The neural network model is a latent variable model, and the second feature information is the optimized second feature information. The neural network model determines the second feature information based on the first feature information, including: The first feature information is input into the encoder of the latent variable model to determine the initial second feature information; The initial second feature information is input into the decoder of the latent variable model to determine the third feature information; The first loss function value corresponding to the encoder is calculated based on the initial second feature information; Calculate the second loss function value corresponding to the decoder based on the third feature information; The latent variable model is optimized based on the first loss function value and the second loss function value to determine the optimized latent variable model. Based on the optimized latent variable model, the optimized second feature information is determined.

4. The method according to claim 3, characterized in that, The feature value in the third feature information is 0 or 1.

5. The method according to claim 3 or 4, characterized in that, The encoder is used to construct a multivariate Gaussian distribution or a multivariate t-distribution.

6. The method according to any one of claims 3-5, characterized in that, The decoder can be structured in any of the following ways: multilayer perceptron, graph convolutional neural network, or graph attention network.

7. The method according to any one of claims 1-6, characterized in that, The diagnostic information includes first diagnostic information corresponding to the design defect, and the step of determining the first feature information based on the layout and the diagnostic information includes: Based on the layout and the diagnostic information, the layout image segments in the layout are determined, and each layout image segment corresponds to the location of the design defect; Cluster the equivalent image segments in the image segments to determine the equivalence classes; Based on the first diagnostic information corresponding to the equivalence class, determine the feature information in the first feature information that corresponds to the design defect.

8. The method according to claim 7, characterized in that, The equivalence includes at least one of rotational equivalence, mirror equivalence, and translation equivalence between image segments.

9. The method according to any one of claims 1-8, characterized in that, The diagnostic information includes second diagnostic information corresponding to the manufacturing defect, and the step of determining the first feature information based on the layout and the diagnostic information includes: Based on the second diagnostic information, the feature information corresponding to the manufacturing defect in the first feature information is determined.

10. A defect root cause determination device, characterized in that, The device includes: An acquisition module is used to acquire the chip layout and diagnostic information of defects in the chip, wherein the diagnostic information is obtained from the chip's fault diagnosis report; The first determining module is used to determine first feature information based on the layout and the diagnostic information. The first feature information includes feature information corresponding to manufacturing defects and design defects, respectively. Each feature vector included in the first feature information corresponds to a defect indicated in the fault diagnosis report. The second determining module is used to determine the root cause of the manufacturing defects and design defects by constructing different manufacturing defects and design defects as different variables, inputting the corresponding first feature information into a neural network model.

11. The apparatus according to claim 10, characterized in that, The second determining module is used for: The neural network model determines second feature information based on the first feature information, and the second feature information is used to indicate the probability distribution of the manufacturing defects and design defects; The neural network model determines the root cause of the manufacturing and design defects based on the second feature information.

12. The apparatus according to claim 11, characterized in that, The neural network model is a latent variable model, and the second feature information is the optimized second feature information. The neural network model determines the second feature information based on the first feature information, including: The first feature information is input into the encoder of the latent variable model to determine the initial second feature information; The initial second feature information is input into the decoder of the latent variable model to determine the third feature information; The first loss function value corresponding to the encoder is calculated based on the initial second feature information; Calculate the second loss function value corresponding to the decoder based on the third feature information; The latent variable model is optimized based on the first loss function value and the second loss function value to determine the optimized latent variable model. Based on the optimized latent variable model, the optimized second feature information is determined.

13. The apparatus according to claim 12, characterized in that, The feature value in the third feature information is 0 or 1.

14. A defect root cause determination device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to implement the method according to any one of claims 1-9 when executing the instructions.

15. A non-volatile computer-readable storage medium storing computer program instructions thereon, characterized in that, When the computer program instructions are executed by the processor, they implement the method described in any one of claims 1-9.

16. A computer program product comprising computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code, wherein when the computer-readable code is executed in an electronic device, a processor in the electronic device performs the method of any one of claims 1-9.

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