A system and method for a crossbar design of a peripheral bus based on an FPGA

Abstract

The application provides a crossbar design system and method based on an FPGA peripheral bus, and the method comprises the following steps: S1, starting, an APB slave interface receives upstream device transmission, apb-slave protocol is converted into cmd format, whether the same downstream device transmission is triggered at the same time is judged through cmd-vld, if yes, step S2 is executed, if not, step S4 is executed; S2, fixed priority arbitration is performed, and whether the buffer is full is judged, if not, step S3 is directly executed; if yes, the priority is replaced into this high, and step S3 is executed; S3, according to the selected downstream device channel of the priority, cmd to apb-master protocol conversion is completed, and step S5 is executed; S4, according to the trigger sequence, channel selection is executed, cmd to apb-master protocol conversion is completed, and step S5 is executed; S5, the apb-master interface sends transmission to the downstream device, and the method is ended. The application effectively avoids the bus jamming condition, and compared with the traditional bus routing, the arbitration time is shorter, the waiting time is effectively reduced, and the bus utilization rate is high.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a general data flow control design for data communication interfaces during data transmission within a chip, specifically a crossbar design system and method based on an FPGA peripheral bus. Background Technology

[0002] FPGAs (Field-Programmable Gate Arrays) are essential for hardware logic verification and design due to their advantages such as high speed, high efficiency, flexibility, stability, and high integration. Crossbars (also known as CrossPoints), or crossbar switching matrices, are commonly used in internet applications and are based on switch chip designs.

[0003] However, current general data flow control designs for data communication interfaces during data transmission within chips mostly use crossbar structures based on the Internet or switches, lacking crossbars for on-chip buses; for peripheral devices on the APB bus, there is no dedicated crossbar for the APB bus in cases of multiple master and slave devices accessing each other. Summary of the Invention

[0004] In view of this, and addressing the issues of the lack of an on-chip bus and the absence of a dedicated crossbar for the AMBA bus, this invention focuses on improving hardware reusability. The purpose of this invention is to propose a crossbar design system and method based on the FPGA peripheral bus (APB). It is based on the AMBA bus (APB) design, incorporates APB master-slave interface logic, employs a cache design for internal logic, and includes a dedicated address translation configuration module and cache interface to handle potential congestion conditions during use. Fixed-priority hardware logic is used to reduce transmission rate loss. Channel selection utilizes an alternating priority design for better timing.

[0005] To achieve the above objectives, in one aspect, the present invention provides a crossbar design system based on an FPGA peripheral bus, wherein the system includes an APB_SLAVE0 interface, an Interface2cmd_queue0, a buffer, a Fixed-priority module, a Cmd2apb_m0, and an APB_master0 interface: The APB_SLAVE0 interface is used to process the input APB master bus signals, receive data, address, read / write valid, and enable signals, and convert the signal timing of the slave end and send it to the Interface2cmd_queue0 module. The Interface2cmd_queue0 is used to package the received slave timing data, address, read / write enable signal, and enable signal into cmd format according to the amount of data transmitted; The Buffer is used to cache data from the upstream device master1 that has not obtained channel priority, and before the Buffer is full, it feeds back the command queue queue0 of the upstream device master0, so that the Buffer feeds back busy to the upstream device 0. The Fixed-priority module is configured by default to give priority to the interface of upstream device 0. When upstream devices access downstream device 0 at the same time, channel 0 will be connected to the interface of upstream device 0 first. If they are not valid at the same time, the upstream device that occupies the cmd message first will be valid and the channel will be occupied first. The Cmd2apb_m0 is used to convert cmd messages into APB master bus signals and convert the signal timings into APB master signal timings. The APB_master0 interface is used to send data to downstream devices according to the APB master bus timing sequence.

[0006] As a further aspect of the present invention, the interface protocol of the APB_SLAVE0 interface conforms to the AMBA APB bus protocol, and receives data, address, read / write valid, and enable signals in accordance with the APB slave bus protocol.

[0007] As a further embodiment of the present invention, the Interface2cmd_queue0 is also used to pack data into 66-bit parallel messages according to the order of read / write validity, enable signal, address, and data, and write them into the FIFO. Each time the enable signal is valid, a valid FIFO write is performed.

[0008] As a further aspect of the present invention, if the Cmd queue of the Fixed-priority module does not receive a valid request simultaneously, and the two upstream devices occupy different channels, arbitration will not occur.

[0009] As a further embodiment of the present invention, the FPGA-based peripheral bus crossbar design system is based on the AMBA bus (APB) design. The FPGA-based peripheral bus crossbar design system also includes APB master-slave interface logic, adopts a cache design for the internal logic, and has a dedicated address translation configuration module and cache interface.

[0010] As a further embodiment of the present invention, the FPGA-based crossbar design system adopts fixed-priority hardware logic, and the channel selection adopts an alternating priority design. It uses the Apb master / slave bus protocol and includes an address translation module, a cache module, and a state machine for channel selection.

[0011] In view of the above objectives, and in a second aspect, the present invention provides a crossbar design method based on an FPGA peripheral bus, applicable to read / write access between two upstream devices and two downstream devices, wherein the method includes the following steps: Step S1: Start. The APB slave interface receives transmissions from the upstream device. The APB-slave protocol is converted to cmd format. The Cmd queue is used to determine whether the same downstream device transmissions are triggered simultaneously. If yes, proceed to step S2; otherwise, proceed to step S4. Step S2: Perform fixed priority arbitration and determine whether the buffer is full. If it is not full, proceed directly to step S3. If it is full, perform channel priority alternation and proceed to step S3. Step S3: According to the downstream device channel selected by priority, complete the protocol conversion from cmd to apb master, and then proceed to step S5; Step S4: Select the channel according to the trigger sequence, complete the conversion from cmd to apb master protocol, and then proceed to step S5. Step S5: The apb master interface sends the data to the downstream device, and the process ends.

[0012] In another aspect, the present invention provides a computer-readable storage medium storing computer program instructions that, when executed, implement any of the above-described FPGA-based crossbar design methods according to the present invention.

[0013] In another aspect, the present invention provides a computer device including a memory and a processor, the memory storing a computer program which, when executed by the processor, performs any of the above-described FPGA-based crossbar design methods according to the present invention.

[0014] In another aspect, the present invention provides an Avatar chip for reading and writing according to the crossbar design method based on the FPGA peripheral bus according to any one of the above-mentioned inventions, wherein the chip architecture includes a CPU reset vector register, a CPU release control pin, a CPU release control register, and a debug interface, wherein... The CPU reset vector register is used to control the address of the instructions read and executed after the CPU is released; The CPU release control register is used to control the CPU release when the chip is powered on. The CPU release control pin is used to control the validity of the CPU release control register; The debug interface is used to read and write on-chip RAM and registers to perform chip read and write operations.

[0015] The present invention has at least the following beneficial technical effects: This invention proposes a crossbar design system and method based on an FPGA peripheral bus. It utilizes the AMBA bus (APB) design, incorporating APB master-slave interface logic and employing a cached design for internal logic. A dedicated address translation configuration module and cache interface are included to handle potential congestion conditions during use. Fixed-priority hardware logic is used to reduce transmission rate loss. Channel selection employs an alternating priority design for improved timing. This design presents a crossbar design method based on an FPGA peripheral bus, using the APB master / slave bus protocol and incorporating an address translation module, a cache module, and a state machine for channel selection. Based on the logical principles, the hardware implementation principles are presented, and the data flow control logic is implemented using Verilog hardware description language, verifying the feasibility of the scheme.

[0016] This invention employs FPGA logic to implement the APB bus master-slave hardware logic, fixed arbitration logic, and an address translation module to achieve master-slave switching on 2x2 ports. To prevent congestion, a dual-port buffer design is used, and the logic for obtaining channel usage rights adopts an alternating mechanism. This effectively avoids bus congestion and, compared to traditional bus routing, results in shorter arbitration time, significantly reduced waiting time, and higher bus utilization. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0018] In the diagram: Figure 1 A schematic diagram of the implementation principle of the crossbar design system based on the FPGA peripheral bus according to the present invention is shown. Figure 2 The figure shows an application scenario of the crossbar design system based on the FPGA peripheral bus according to the present invention; Figure 3 A flowchart illustrating the implementation of the FPGA-based crossbar design method according to the present invention is shown. Figure 4 A schematic diagram of an embodiment of a computer-readable storage medium for implementing a crossbar design method for an FPGA-based peripheral bus according to the present invention is shown; Figure 5 A schematic diagram of the hardware structure of a computer device implementing a crossbar design method based on an FPGA peripheral bus according to the present invention is shown. Figure 6 A schematic diagram of the framework of an embodiment of the chip according to the present invention is shown. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0020] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two different entities or different parameters with the same name. Therefore, "first" and "second" are merely for convenience of expression and should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as other steps or units inherent in a process, method, system, product, or device that includes a series of steps or units.

[0021] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0024] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0025] Currently, the general data flow control design for data communication interfaces during data transmission within chips is mostly based on the crossbar structure of the Internet or switches, lacking crossbars for on-chip buses; for peripheral devices on the APB bus, there is no crossbar specifically for the APB bus in cases where multiple masters and slaves access each other.

[0026] In view of this, and addressing the issues of the lack of an on-chip bus and the absence of a dedicated crossbar for the AMBA bus, this invention focuses on improving hardware reusability. The purpose of this invention is to propose a crossbar design system and method based on the FPGA peripheral bus (APB). It is based on the AMBA bus (APB) design, incorporates APB master-slave interface logic, employs a cache design for internal logic, and includes a dedicated address translation configuration module and cache interface to handle potential congestion conditions during use. Fixed-priority hardware logic is used to reduce transmission rate loss. Channel selection utilizes an alternating priority design for better timing.

[0027] This invention primarily implements a crossbar design method based on FPGA peripheral bus, applied to the Avatar chip project. The design framework diagram is shown below. Figure 1 Application scenarios reference Figure 2 Workflow diagram reference Figure 3 .

[0028] For this reason, see Figure 1 and Figure 2As shown, in a first aspect, the present invention provides a crossbar design system based on an FPGA peripheral bus, the system including an APB_SLAVE0 interface, an Interface2cmd_queue0, a buffer, a Fixed-priority module, a Cmd2apb_m0, and an APB_master0 interface.

[0029] The APB_SLAVE0 interface is used to process the input APB master bus signals, receive data, address, read / write valid, and enable signals, and convert the signal timing of the slave end before sending it to the Interface2cmd_queue0 module.

[0030] In some embodiments, the interface protocol of the APB_SLAVE0 interface conforms to the AMBA APB bus protocol and receives data, address, read / write valid, and enable signals in accordance with the APB slave bus protocol.

[0031] The Interface2cmd_queue0 is used to package the received slave timing data, address, read / write enable signals, and enable signals into cmd format according to the amount of data transmitted.

[0032] In some embodiments, the Interface2cmd_queue0 is also used to pack data into 66-bit parallel messages according to the order of read / write validity, enable signal, address, and data, and write them into the FIFO. Each time the enable signal is valid, a valid FIFO write is performed.

[0033] The Buffer is used to cache data from the upstream device master1 that has not obtained channel priority, and before the Buffer is full, it feeds back the command queue queue0 of the upstream device master0, so that the Buffer feeds back busy to the upstream device 0. The Fixed-priority module is configured by default to give priority to the interface of upstream device 0. When upstream devices access downstream device 0 at the same time, channel 0 will be connected to the interface of upstream device 0 first. If they are not valid at the same time, the upstream device that occupies the cmd message first will be valid and the channel will be occupied first.

[0034] In some embodiments, if the Cmd queue of the Fixed-priority module does not receive a valid request simultaneously, arbitration will not occur if the two upstream devices occupy different channels.

[0035] The Cmd2apb_m0 is used to convert cmd messages into APB master bus signals and convert the signal timings into APB master signal timings. The APB_master0 interface is used to send data to downstream devices according to the APB master bus timing sequence.

[0036] In some embodiments, the FPGA-based peripheral bus crossbar design system is based on the AMBA bus (APB) design. The FPGA-based peripheral bus crossbar design system also includes APB master-slave interface logic, adopts a cache design for internal logic, and has a dedicated address translation configuration module and cache interface.

[0037] In some embodiments, the FPGA-based crossbar design system uses fixed-priority hardware logic, and the channel selection adopts an alternating priority design. It uses the Apb master / slave bus protocol and includes an address translation module, a cache module, and a state machine for channel selection.

[0038] This invention is based on the AMBA bus APB design, incorporating APB master-slave interface logic. The internal logic employs a cache design, including a dedicated address translation configuration module and cache interface to handle potential congestion during use. Fixed-priority hardware logic is used to reduce transmission rate loss. Channel selection utilizes an alternating priority design for superior timing. This invention proposes a crossbar design system based on an FPGA peripheral bus, employing the APB master / slave bus protocol and incorporating an address translation module, a cache module, and a state machine for channel selection. Based on the logical principles, this invention presents the hardware implementation principles and implements the data flow control logic using Verilog hardware description language, verifying the feasibility of the scheme.

[0039] It should be noted that although several modules or units of the device for performing actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of the present invention, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0040] A second aspect of the present invention provides a crossbar design method based on an FPGA peripheral bus, applied when two upstream devices perform read / write access to two downstream devices, wherein the method includes the following steps: Step S1: Start. The APB slave interface receives transmissions from the upstream device. The APB slave protocol is converted to cmd format. The Cmd queue is used to determine whether the same downstream device transmissions are triggered simultaneously. If yes, proceed to step S2; otherwise, proceed to step S4. Step S2: Perform fixed priority arbitration and determine whether the buffer is full. If it is not full, proceed directly to step S3. If it is full, perform channel priority alternation and proceed to step S3. Step S3: According to the downstream device channel selected by priority, complete the protocol conversion from cmd to apb master, and then proceed to step S5; Step S4: Select the channel according to the trigger sequence, complete the conversion from cmd to apb master protocol, and then proceed to step S5. Step S5: The apb master interface sends the data to the downstream device, and the process ends.

[0041] This invention proposes a crossbar design system and method based on an FPGA peripheral bus. It utilizes the AMBA bus (APB) design, incorporating APB master-slave interface logic and employing a cached design for internal logic. A dedicated address translation configuration module and cache interface are included to handle potential congestion conditions during use. Fixed-priority hardware logic is used to reduce transmission rate loss. Channel selection employs an alternating priority design for improved timing. This design presents a crossbar design method based on an FPGA peripheral bus, using the APB master / slave bus protocol and incorporating an address translation module, a cache module, and a state machine for channel selection. Based on the logical principles, the hardware implementation principles are presented, and the data flow control logic is implemented using Verilog hardware description language, verifying the feasibility of the scheme.

[0042] It should be understood that although the above description follows a certain order, these steps are not necessarily executed in that order. Unless otherwise expressly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, some steps in this embodiment may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least a portion of the steps or stages in other steps.

[0043] A third aspect of the present invention also provides a computer-readable storage medium. Figure 4 A schematic diagram of a computer-readable storage medium illustrating a crossbar design method for an FPGA-based peripheral bus according to an embodiment of the present invention is shown. Figure 4 As shown, the computer-readable storage medium 300 stores computer program instructions 310, which can be executed by a processor. When the computer program instructions 310 are executed, they implement the FPGA-based crossbar design method for peripheral buses according to any of the above embodiments, including the following steps: Step S1: Start. The APB slave interface receives transmissions from the upstream device. The APB slave protocol is converted to cmd format. The Cmd queue is used to determine whether the same downstream device transmissions are triggered simultaneously. If yes, proceed to step S2; otherwise, proceed to step S4. Step S2: Perform fixed priority arbitration and determine whether the buffer is full. If it is not full, proceed directly to step S3; if it is full, change the priority to the higher one and proceed to step S3. Step S3: According to the downstream device channel selected by priority, complete the protocol conversion from cmd to apb master, and then proceed to step S5; Step S4: Select the channel according to the trigger sequence, complete the conversion from cmd to apb master protocol, and then proceed to step S5. Step S5: The apb master interface sends the data to the downstream device, and the process ends.

[0044] It should be understood that, where there is no conflict, all the embodiments, features and advantages described above for the FPGA-based peripheral bus crossbar design method according to the present invention are equally applicable to the FPGA-based peripheral bus crossbar design system and storage medium according to the present invention.

[0045] A fourth aspect of the present invention also provides a computer device 400, including a memory 420 and a processor 410. The memory stores a computer program, which, when executed by the processor, implements the FPGA-based crossbar design method for peripheral buses according to any of the above embodiments, including the following steps: Step S1: Start. The APB slave interface receives transmissions from the upstream device. The APB slave protocol is converted to cmd format. The Cmd queue is used to determine whether the same downstream device transmissions are triggered simultaneously. If yes, proceed to step S2; otherwise, proceed to step S4. Step S2: Perform fixed priority arbitration and determine whether the buffer is full. If it is not full, proceed directly to step S3. If it is full, perform channel priority alternation and proceed to step S3. Step S3: According to the downstream device channel selected by priority, complete the protocol conversion from cmd to apb master, and then proceed to step S5; Step S4: Select the channel according to the trigger sequence, complete the conversion from cmd to apb master protocol, and then proceed to step S5. Step S5: The apb master interface sends the data to the downstream device, and the process ends.

[0046] like Figure 5 The diagram shown is a hardware structure schematic of an embodiment of a computer device that executes a crossbar design method based on an FPGA peripheral bus, as provided by the present invention. Figure 5 Taking the computer device 400 shown as an example, this computer device includes a processor 410 and a memory 420, and may also include an input device 430 and an output device 440. The processor 410, memory 420, input device 430, and output device 440 can be connected via a bus or other means. Figure 5 Taking a bus connection as an example, input device 430 can receive input digital or character information and generate signal inputs related to the FPGA-based peripheral bus crossbar design. Output device 440 may include display devices such as a display screen.

[0047] Memory 420, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the resource monitoring method in this embodiment. Memory 420 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created by the use of the resource monitoring method, etc. In addition, memory 420 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 420 may optionally include memory remotely located relative to processor 410, and these remote memories can be connected to the local module via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0048] The processor 410 executes various server functions and data processing by running non-volatile software programs, instructions, and modules stored in the memory 420, thereby implementing the resource monitoring method of the above method embodiment.

[0049] A fifth aspect of the present invention also provides an Avatar chip 500 for reading and writing according to any of the above-mentioned FPGA-based peripheral bus crossbar design methods. Figure 6 A schematic diagram of the frame of the chip 500 according to the present invention is shown. (As shown) Figure 6 As shown, in this embodiment, the chip 500 architecture includes a CPU reset vector register 510, a CPU release control pin 520, a CPU release control register 530, and a debug interface 540, wherein... The CPU reset vector register 510 is used to control the address of the instructions read and executed after the CPU is released; The CPU release control register 530 is used to control the CPU release when the chip 500 is powered on. The CPU release control pin 520 is used to control the validity of the CPU release control register 530; The debug interface 540 is used to read and write on-chip RAM and registers to perform chip read and write operations.

[0050] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.

[0051] Finally, it should be noted that the computer-readable storage medium (e.g., memory) described herein can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. By way of example, and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM), which can act as external cache memory. By way of example, and not limitation, RAM can be obtained in various forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The storage devices disclosed herein are intended to include, but are not limited to, these and other suitable types of memory.

[0052] The various exemplary logic blocks, modules, and circuits described herein can be implemented or performed using the following components designed to perform the functions herein: general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP, and / or any other such configuration.

[0053] This invention employs FPGA logic to implement the APB bus master-slave hardware logic, fixed arbitration logic, and an address translation module to achieve master-slave switching on 2x2 ports. To prevent congestion, a dual-port buffer design is used, and the logic for obtaining channel usage rights adopts an alternating mechanism. This effectively avoids bus congestion and, compared to traditional bus routing, results in shorter arbitration time, significantly reduced waiting time, and higher bus utilization.

[0054] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the claims in the FPGA-based peripheral bus crossbar design method according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0055] It should be understood that, as used herein, the singular form "a" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the associatedly listed items. The embodiment numbers disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0056] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A crossbar design system based on an FPGA peripheral bus, characterized in that, The system includes the APB_SLAVE0 interface, Interface2cmd_queue0, Buffer, Fixed-priority module, Cmd2apb_m0, and APB_master0 interface; The APB_SLAVE0 interface is used to process the input APB master bus signals, receive data, address, read / write valid, and enable signals, and convert the signal timing of the slave end and send it to the Interface2cmd_queue0 module. The Interface2cmd_queue0 is used to package the received slave timing data, address, read / write enable signal, and enable signal into cmd format according to the amount of data transmitted; The Buffer is used to cache data from the upstream device master1 that has not obtained channel priority, and before the Buffer is full, it feeds back the command queue queue0 of the upstream device master0, so that the Buffer feeds back busy to the upstream device 0. The Fixed-priority module is configured by default to give priority to the interface of upstream device 0. When upstream devices access downstream device 0 at the same time, channel 0 will be connected to the interface of upstream device 0 first. If they are not valid at the same time, the upstream device that occupies the cmd message first will be valid and the channel will be occupied first. The Cmd2apb_m0 is used to convert cmd messages into app master bus signals and convert the signal timings into app master signal timings. The APB_master0 interface is used to send data to downstream devices according to the APB master bus timing sequence.

2. The crossbar design system based on FPGA peripheral bus according to claim 1, characterized in that, The APB_SLAVE0 interface conforms to the AMBA APB bus protocol and receives data, address, read / write valid, and enable signals according to the APB slave bus protocol.

3. The FPGA-based crossbar design system for peripheral buses according to claim 2, characterized in that, The Interface2cmd_queue0 is also used to pack data into 66-bit parallel messages according to the order of read / write validity, enable signal, address, and data, and write them into the FIFO. Each time the enable signal is valid, a valid FIFO write is performed.

4. The FPGA-based crossbar design system for peripheral buses according to claim 3, characterized in that, If the Cmd queue of the Fixed-priority module does not receive a valid request simultaneously, arbitration will not occur if the two upstream devices occupy different channels.

5. The FPGA-based crossbar design system for peripheral buses according to claim 4, characterized in that, The FPGA-based peripheral bus crossbar design system is based on the AMBA bus APB design.

6. The FPGA-based crossbar design system for peripheral buses according to claim 4, characterized in that, The FPGA-based crossbar design system also includes APB master-slave interface logic, employs a cache design for its internal logic, and features a dedicated address translation configuration module and cache interface.

7. The FPGA-based crossbar design system for peripheral buses according to claim 5, characterized in that, The FPGA-based crossbar design system uses fixed-priority hardware logic, while channel selection employs an alternating priority design. It adopts the Apb master / slave bus protocol and includes an address translation module, a cache module, and a state machine for channel selection.

8. A crossbar design method based on FPGA peripheral bus, characterized in that, Based on the FPGA-based peripheral bus crossbar design system as described in any one of claims 1-6, when two upstream devices perform read / write access to two downstream devices, the method includes the following steps: Step S1: Start. The APB slave interface receives transmissions from the upstream device. The APB-slave protocol is converted to cmd format. The Cmd queue is used to determine whether the same downstream device transmissions are triggered simultaneously. If yes, proceed to step S2; otherwise, proceed to step S4. Step S2: Perform fixed priority arbitration and determine whether the buffer is full. If it is not full, proceed directly to step S3. If it is full, perform channel priority alternation and proceed to step S3. Step S3: According to the downstream device channel selected by priority, complete the protocol conversion from cmd to apb master, and then proceed to step S5; Step S4: Select the channel according to the trigger sequence, complete the conversion from cmd to apb master protocol, and then proceed to step S5. Step S5: The apb master interface sends the data to the downstream device, and the process ends.

9. A computer-readable storage medium, characterized in that, It stores computer program instructions, which, when executed, implement the FPGA-based crossbar design method for peripheral buses as described in claim 8.

10. A computer device, comprising a memory and a processor, characterized in that, The memory stores a computer program, which, when executed by the processor, performs the crossbar design method based on the FPGA peripheral bus as described in claim 8.

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