An isolated SONOS pFLASH switching cell structure

Abstract

The application discloses an isolated SONOS pFLASH switch unit structure and belongs to the microelectronic field, comprising a SONOS pFLASH programming / erasing tube T11 and T12, a pMOS type selection tube T21, a pMOS type isolation tube T22 and a pMOS type signal transmission tube T3; the source end of T11, the source end of T21 and the drain end of T22 are interconnected; the drain end of T21 is connected with the source end of T12; the source end of T22 is connected with the gate end of T3; T11, T12, T21 and T22 are located in the same n well. The application adopts an indirect coupling type structure, the SONOS pFLASH programming / erasing tube adopts a band tunnel programming mode and a Fowler-Nordheim erasing mode to respectively realize potential transmission and potential blocking functions, can reduce damage of a tunnel oxide layer, avoids abnormal phenomena that over-erasing leads to device failure, and is beneficial to improving durability.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, and in particular to an isolated SONOS pFLASH switch unit structure. Background Technology

[0002] With major projects in aerospace, electronic warfare, and communications requiring electronic systems to develop towards multi-functionality, high speed, miniaturization, and low power consumption, the demand for highly reliable and radiation-resistant programmable logic devices is becoming increasingly prominent.

[0003] FLASH switching units are the basic building blocks for reconfigurable FLASH programmable logic devices and their cores. Compared to SRAM and antifuse switching units, FLASH switching units offer advantages such as power-on operation, strong single-event immunity, and reconfigurability. FLASH switching units include floating-gate (FG) FLASH switching units and charge-trapping (CP) FLASH switching units. Floating-gate FLASH switching units store charge through a floating gate, resulting in poor charge retention. Furthermore, the feature size of floating-gate devices is difficult to shrink, limiting their development towards process nodes below 65nm. Summary of the Invention

[0004] The purpose of this invention is to provide an isolated SONOS pFLASH switch unit structure to solve the problems in the background art.

[0005] To solve the above-mentioned technical problems, the present invention provides an isolated SONOS pFLASH switch unit structure, including a SONOS pFLASH programming / erasing transistor T11, a SONOS pFLASH programming / erasing transistor T12, a pMOS type select transistor T21, a pMOS type isolation transistor T22, and a pMOS type signal transmission transistor T3, wherein,

[0006] The source terminal of the SONOS pFLASH programming / erasing transistor T11, the source terminal of the pMOS selection transistor T21, and the drain terminal of the pMOS isolation transistor T22 are interconnected; the drain terminal of the pMOS selection transistor T21 is connected to the source terminal of the SONOS pFLASH programming / erasing transistor T12; the source terminal of the pMOS isolation transistor T22 is connected to the gate terminal of the pMOS signal transmission transistor T3.

[0007] The SONOS pFLASH programming / erasing transistor T11, the SONOS pFLASH programming / erasing transistor T12, the pMOS type select transistor T21, and the pMOS type isolation transistor T22 are located in the same n-well.

[0008] In one embodiment, the SONOS pFLASH programming / erasing transistor T11 and the SONOS pFLASH programming / erasing transistor T12 share a common control gate CG, and the SONOS pFLASH programming / erasing transistors T11 and T12 use a band-to-band tunneling programming method and a Fowler-Nordheim erasing method to achieve their potential transfer and potential blocking functions.

[0009] In one embodiment, when the SONOS pFLASH programming / erasing transistor T11 is programmed, a potential is applied to the gate terminal of the pMOS type select transistor T21 to turn it off, a potential is applied to the gate terminal of the pMOS type isolation transistor T22 to turn it off, a negative potential is applied to the drain terminal of the SONOS pFLASH programming / erasing transistor T11, and a positive potential is applied to the gate terminal of the SONOS pFLASH programming / erasing transistor T11. This band-to-band tunneling programming method allows electrons to enter the nitride trapping layer of the SONOS pFLASH programming / erasing transistor T11.

[0010] In one embodiment, when the SONOS pFLASH programming / erasing transistor T12 is programmed, a potential is applied to the gate terminal of the pMOS type select transistor T21 to turn the pMOS type select transistor T21 off, a negative potential is applied to the drain terminal of the SONOS pFLASH programming / erasing transistor T12, and a positive potential is applied to the gate terminal of the SONOS pFLASH programming / erasing transistor T12. The band-to-band tunneling programming method is used to allow electrons to enter the nitride trapping layer of the SONOS pFLASH programming / erasing transistor T12.

[0011] In one embodiment, when the SONOS pFLASH programming / erasing transistors T11 and T12 perform an erasure operation, a potential is applied to the gate terminal of the pMOS isolation transistor T22 to turn it off. A positive potential is applied to the drain terminal of the SONOS pFLASH programming / erasing transistor T11, the n-well containing the SONOS pFLASH programming / erasing transistors T11 and T12, and the drain terminal of the SONOS pFLASH programming / erasing transistor T12. At the same time, a negative potential is applied to the gate terminals of the SONOS pFLASH programming / erasing transistors T11 and T12. The Fowler-Nordheim erasure method is used to allow electrons to flow out of the nitride trapping layer of the SONOS pFLASH programming / erasing transistors T11 and T12.

[0012] In one embodiment, the first operation method steps for putting the pMOS signal transmission transistor T3 in the on state are as follows: (1) performing an erase operation on the SONOS pFLASH programming / erasing transistors T11 and T12; (2) performing a programming operation on the SONOS pFLASH programming / erasing transistor T11; (3) connecting the drain terminal of the SONOS pFLASH programming / erasing transistor T12, the gate terminal of the SONOS pFLASH programming / erasing transistor T12, and the gate terminal of the SONOS pFLASH programming / erasing transistor T11 to the GND potential, and connecting the drain terminal of the SONOS pFLASH programming / erasing transistor T11, the gate terminal of the pMOS type select transistor T21, and the gate terminal of the pMOS type isolation transistor T22 to the -Vcc potential, so that the -Vcc potential is transmitted to the gate terminal of the pMOS type signal transmission transistor T3 through the SONOS pFLASH programming / erasing transistor T11 and the pMOS type isolation transistor T22, thereby realizing the on state of the pMOS type signal transmission transistor T3.

[0013] In one embodiment, the second operation method for putting the pMOS signal transmission transistor T3 in the on state includes the following steps: (1) performing an erase operation on the SONOS pFLASH programming / erasing transistors T11 and T12; (2) performing a programming operation on the SONOS pFLASH programming / erasing transistor T12; (3) connecting the drain of the SONOS pFLASH programming / erasing transistor T11, the gate of the SONOS pFLASH programming / erasing transistor T12, and the gate of the SONOS pFLASH programming / erasing transistor T11 to the GND potential, and connecting the drain of the SONOS pFLASH programming / erasing transistor T12, the gate of the pMOS type select transistor T21, and the gate of the pMOS type isolation transistor T22 to the -Vcc potential, so that the -Vcc potential passes through the SONOS The pFLASH programming / erasing transistor T12, the pMOS selection transistor T21, and the pMOS isolation transistor T22 transmit the signal to the gate of the pMOS signal transmission transistor T3, thereby enabling the pMOS signal transmission transistor T3 to be in the on state.

[0014] In one embodiment, the first operation method for putting the pMOS signal transmission transistor T3 in the off state includes the following steps: (1) performing an erase operation on the SONOS pFLASH programming / erasing transistors T11 and T12; (2) performing a programming operation on the SONOS pFLASH programming / erasing transistor T11; (3) connecting the drain of the SONOS pFLASH programming / erasing transistor T12, the gate of the pMOS selection transistor T21, and the gate of the pMOS isolation transistor T22 to a -Vcc potential, and connecting the drain of the SONOS pFLASH programming / erasing transistor T11, the gate of the SONOS pFLASH programming / erasing transistor T12, and the gate of the SONOS pFLASH programming / erasing transistor T11 to a GND potential, so that the GND potential is transmitted to the gate of the pMOS signal transmission transistor T3 through the SONOS pFLASH programming / erasing transistor T11 and the pMOS isolation transistor T22, thereby realizing the off state of the pMOS signal transmission transistor T3.

[0015] In one embodiment, the second operation method for putting the pMOS signal transmission transistor T3 in the off state includes the following steps: (1) performing an erase operation on the SONOS pFLASH programming / erasing transistors T11 and T12; (2) performing a programming operation on the SONOS pFLASH programming / erasing transistor T12; (3) connecting the drain of the SONOS pFLASH programming / erasing transistor T11, the gate of the pMOS selection transistor T21, and the gate of the pMOS isolation transistor T22 to a -Vcc potential, and connecting the drain of the SONOS pFLASH programming / erasing transistor T12, the gate of the SONOS pFLASH programming / erasing transistor T12, and the gate of the SONOS pFLASH programming / erasing transistor T11 to a GND potential, so that the GND potential passes through the SONOS The pFLASH programming / erasing transistor T12, the pMOS selection transistor T21, and the pMOS isolation transistor T22 transmit the signal to the gate of the pMOS signal transmission transistor T3, thereby realizing the off state of the pMOS signal transmission transistor T3.

[0016] This invention provides an isolated SONOS pFLASH switch unit structure, employing an indirect coupling structure. The SONOS pFLASH programming / erasing transistor uses a band-to-band tunneling programming method and a Fowler-Nordheim erasing method to achieve its potential transfer and potential blocking functions, respectively. This reduces tunnel oxide layer damage, avoids abnormal phenomena such as device failure due to over-erasure, and improves its durability. The isolated SONOS pFLASH switch unit structure of this invention transfers potential to the gate terminal of the signal transmission transistor through the SONOS pFLASH programming / erasing transistor, controlling the on / off state of the signal transmission transistor. Simultaneously, the isolation transistor effectively isolates the signal transmission transistor from the SONOS pFLASH programming / erasing transistor, enhancing its anti-interference capability. The SONOS pFLASH transistor, as the programming / erasing transistor, has a long charge retention life, further enhancing the reliability of the switch unit. Furthermore, its signal transmission transistor can be a low-voltage MOSFET, effectively improving its driving capability and increasing the speed of control signal transmission. The feature size of SONOS pFLASH switch units can be further reduced, thereby enabling the fabrication of low-power, high-speed, high-reliability, and highly integrated FLASH programmable logic devices. Attached Figure Description

[0017] Figure 1 This invention provides a schematic diagram of an isolated SONOS pFLASH switch unit structure.

[0018] Figure 2 This is a schematic diagram of the first signal transmission path in which the pMOS type signal transmission transistor T3 is in the on state in this invention;

[0019] Figure 3 This is a schematic diagram of the second signal transmission path in which the pMOS type signal transmission transistor T3 is in the on state in this invention;

[0020] Figure 4 This is a schematic diagram of the first signal transmission path in which the pMOS signal transmission transistor T3 is in the off state in this invention;

[0021] Figure 5 This is a schematic diagram of the second signal transmission path in which the pMOS signal transmission transistor T3 is in the off state in this invention. Detailed Implementation

[0022] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the isolated SONOS pFLASH switch unit structure proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0023] This invention provides an isolated SONOS pFLASH switch unit structure, such as... Figure 1 As shown, it includes SONOS pFLASH programming / erasing transistors T11 and T12, pMOS type select transistor T21, pMOS type isolation transistor T22 and pMOS type signal transmission transistor T3.

[0024] Please continue reading. Figure 1 The source terminal of the SONOS pFLASH programming / erasing transistor T11, the source terminal of the pMOS type select transistor T21, and the drain terminal of the pMOS type isolation transistor T22 are interconnected; the drain terminal of the pMOS type select transistor T21 is connected to the source terminal of the SONOS pFLASH programming / erasing transistor T12; and the source terminal of the pMOS type isolation transistor T22 is connected to the gate terminal of the pMOS type signal transmission transistor T3. The SONOS pFLASH programming / erasing transistor T11, the SONOS pFLASH programming / erasing transistor T12, the pMOS type select transistor T21, and the pMOS type isolation transistor T22 are located in the same n-well B1. The gate terminals of the SONOS pFLASH programming / erasing transistor T11 and the SONOS pFLASH programming / erasing transistor T12 are both CG, i.e., common control gate terminals. The SONOS pFLASH programming / erasing transistors T11 and T12 both use the band-to-band tunneling programming method and the Fowler-Nordheim erasing method to realize their potential transfer and potential blocking functions, respectively.

[0025] When the SONOS pFLASH programming / erasing transistor T11 is programmed, a potential is applied to the gate terminal SG1 of the pMOS type select transistor T21 to turn it off, a potential is applied to the gate terminal SG2 of the pMOS type isolation transistor T22 to turn it off, a negative potential is applied to the drain terminal D1 of the SONOS pFLASH programming / erasing transistor T11, and a positive potential is applied to the gate terminal CG of the SONOS pFLASH programming / erasing transistor T11. The band-to-band tunneling programming method is used to allow electrons to enter the nitride trapping layer of the SONOS pFLASH programming / erasing transistor T11.

[0026] When the SONOS pFLASH programming / erasing transistor T12 is programmed, a potential is applied to the gate terminal SG1 of the pMOS type select transistor T21 to turn the pMOS type select transistor T21 off. A negative potential is applied to the drain terminal D2 of the SONOS pFLASH programming / erasing transistor T12, and a positive potential is applied to the gate terminal CG of the SONOS pFLASH programming / erasing transistor T12. The band-to-band tunneling programming method is used to allow electrons to enter the nitride trapping layer of the SONOS pFLASH programming / erasing transistor T12.

[0027] When the SONOS pFLASH programming / erasing transistors T11 and T12 are simultaneously erased, a potential is applied to the gate terminal SG2 of the pMOS isolation transistor T22 to turn it off. A positive potential is applied to the drain terminal D1 and n-well B1 of the SONOS pFLASH programming / erasing transistor T11 and the drain terminal D2 of the SONOS pFLASH programming / erasing transistor T12. At the same time, a negative potential is applied to the common control gate terminal CG of the SONOS pFLASH programming / erasing transistors T11 and T12. The Fowler-Nordheim erasing method is used to allow electrons to flow out of the nitride trapping layer of the SONOS pFLASH programming / erasing transistors T11 and T12.

[0028] like Figure 2 As shown, the first operation method for the pMOS signal transmission transistor T3 to be in the on state includes the following steps: (1) performing an erase operation on the SONOS pFLASH programming / erasing transistors T11 and T12; (2) performing a programming operation on the SONOS pFLASH programming / erasing transistor T11; (3) connecting the drain terminal D2 of the SONOS pFLASH programming / erasing transistor T12, the gate terminal CG of the SONOS pFLASH programming / erasing transistor T12, and the gate terminal CG of the SONOS pFLASH programming / erasing transistor T11 to the GND potential, and connecting the drain terminal D1 of the SONOS pFLASH programming / erasing transistor T11, the gate terminal SG1 of the pMOS type selection transistor T21, and the gate terminal SG2 of the pMOS type isolation transistor T22 to the -Vcc potential, so that the -Vcc potential passes through the SONOS The pFLASH programming / erasing transistor T11 and the pMOS isolation transistor T22 transmit the signal to the gate of the pMOS signal transmission transistor T3, thereby enabling the pMOS signal transmission transistor T3 to be in the on state.

[0029] like Figure 3As shown, the second operation method for the pMOS signal transmission transistor T3 to be in the on state includes the following steps: (1) performing an erase operation on the SONOS pFLASH programming / erasing transistors T11 and T12; (2) performing a programming operation on the SONOS pFLASH programming / erasing transistor T12; (3) connecting the drain terminal D1 of the SONOS pFLASH programming / erasing transistor T11, the gate terminal CG of the SONOS pFLASH programming / erasing transistor T12, and the gate terminal CG of the SONOS pFLASH programming / erasing transistor T11 to the GND potential, and connecting the drain terminal D2 of the SONOS pFLASH programming / erasing transistor T12, the gate terminal SG1 of the pMOS type select transistor T21, and the gate terminal SG2 of the pMOS type isolation transistor T22 to the -Vcc potential, so that the -Vcc potential passes through the SONOS The pFLASH programming / erasing transistor T12, the pMOS selection transistor T21, and the pMOS isolation transistor T22 transmit the signal to the gate of the pMOS signal transmission transistor T3, thereby realizing the on state of the pMOS signal transmission transistor T3.

[0030] like Figure 4 As shown, the first operation method for the pMOS signal transmission transistor T3 to be in the off state includes the following steps: (1) Erasing the SONOS pFLASH programming / erasing transistors T11 and T12; (2) Programming the SONOS pFLASH programming / erasing transistor T11; (3) Connecting the drain terminal D2 of the SONOS pFLASH programming / erasing transistor T12, the gate terminal SG1 of the pMOS selection transistor T21, and the gate terminal SG2 of the pMOS isolation transistor T22 to -Vcc potential, and connecting the drain terminal D1 of the SONOS pFLASH programming / erasing transistor T11, the gate terminal CG of the SONOS pFLASH programming / erasing transistor T12, and the gate terminal CG of the SONOS pFLASH programming / erasing transistor T11 to GND potential, so that the GND potential passes through the SONOS The pFLASH programming / erasing transistor T11 and the pMOS isolation transistor T22 transmit the signal to the gate of the pMOS signal transmission transistor T3, thereby realizing the off state of the pMOS signal transmission transistor T3.

[0031] like Figure 5As shown, the second operation method for the pMOS signal transmission transistor T3 to be in the off state includes the following steps: (1) performing an erase operation on the SONOS pFLASH programming / erasing transistors T11 and T12; (2) performing a programming operation on the SONOS pFLASH programming / erasing transistor T12; (3) connecting the drain terminal D1 of the SONOS pFLASH programming / erasing transistor T11, the gate terminal SG1 of the pMOS selection transistor T21, and the gate terminal SG2 of the pMOS isolation transistor T22 to a -Vcc potential, and connecting the drain terminal D2 of the SONOS pFLASH programming / erasing transistor T12, the gate terminal CG of the SONOS pFLASH programming / erasing transistor T12, and the gate terminal CG of the SONOS pFLASH programming / erasing transistor T11 to a GND potential, so that the GND potential passes through the SONOS The pFLASH programming / erasing transistor T12, the pMOS selection transistor T21, and the pMOS isolation transistor T22 transmit the signal to the gate of the pMOS signal transmission transistor T3, thereby realizing the off state of the pMOS signal transmission transistor T3.

[0032] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. An isolated SONOS pFLASH switch unit structure, characterized in that, This includes SONOS pFLASH programming / erasing transistor T11, SONOS pFLASH programming / erasing transistor T12, pMOS select transistor T21, pMOS isolation transistor T22, and pMOS signal transmission transistor T3, among which... The source terminal of the SONOS pFLASH programming / erasing transistor T11, the source terminal of the pMOS selection transistor T21, and the drain terminal of the pMOS isolation transistor T22 are interconnected; the drain terminal of the pMOS selection transistor T21 is connected to the source terminal of the SONOS pFLASH programming / erasing transistor T12; the source terminal of the pMOS isolation transistor T22 is connected to the gate terminal of the pMOS signal transmission transistor T3. The SONOS pFLASH programming / erasing transistor T11, the SONOS pFLASH programming / erasing transistor T12, the pMOS type select transistor T21, and the pMOS type isolation transistor T22 are located in the same n-well; When the SONOS pFLASH programming / erasing transistor T11 is programmed, a potential is applied to the gate terminal of the pMOS type select transistor T21 to turn off the pMOS type select transistor T21, a potential is applied to the gate terminal of the pMOS type isolation transistor T22 to turn off the pMOS type isolation transistor T22, a negative potential is applied to the drain terminal of the SONOS pFLASH programming / erasing transistor T11, and a positive potential is applied to the gate terminal of the SONOS pFLASH programming / erasing transistor T11. The band-to-band tunneling programming method is used to allow electrons to enter the nitride trapping layer of the SONOS pFLASH programming / erasing transistor T11. When the SONOS pFLASH programming / erasing transistor T12 is programmed, a potential is applied to the gate terminal of the pMOS type select transistor T21 to turn the pMOS type select transistor T21 off. A negative potential is applied to the drain terminal of the SONOS pFLASH programming / erasing transistor T12, and a positive potential is applied to the gate terminal of the SONOS pFLASH programming / erasing transistor T12. The band-to-band tunneling programming method is used to allow electrons to enter the nitride trapping layer of the SONOS pFLASH programming / erasing transistor T12.

2. The isolated SONOS pFLASH switch unit structure as described in claim 1, characterized in that, The SONOSpFLASH programming / erasing transistor T11 and the SONOS pFLASH programming / erasing transistor T12 share a common control gate CG. The SONOSpFLASH programming / erasing transistors T11 and T12 use a band-to-band tunneling programming method and a Fowler-Nordheim erasing method to achieve their potential transfer and potential blocking functions.

3. The isolated SONOS pFLASH switch unit structure as described in claim 2, characterized in that, When the SONOS pFLASH programming / erasing transistors T11 and T12 are simultaneously erased, a potential is applied to the gate terminal of the pMOS isolation transistor T22 to turn it off. A positive potential is applied to the drain terminal of the SONOS pFLASH programming / erasing transistor T11, the n-well containing the SONOS pFLASH programming / erasing transistors T11 and T12, and the drain terminal of the SONOS pFLASH programming / erasing transistor T12. At the same time, a negative potential is applied to the gate terminals of the SONOS pFLASH programming / erasing transistors T11 and T12. The Fowler-Nordheim erasing method is used to allow electrons to flow out of the nitride trapping layer of the SONOS pFLASH programming / erasing transistors T11 and T12.

4. The isolated SONOS pFLASH switch unit structure as described in claim 3, characterized in that, The first operation method for putting the pMOS signal transmission transistor T3 in the on state is as follows: (1) Erasing the SONOS pFLASH programming / erasing transistors T11 and T12; (2) Programming the SONOS pFLASH programming / erasing transistor T11; (3) Connecting the drain of the SONOS pFLASH programming / erasing transistor T12, the gate of the SONOS pFLASH programming / erasing transistor T12, and the gate of the SONOS pFLASH programming / erasing transistor T11 to the GND potential, and connecting the drain of the SONOS pFLASH programming / erasing transistor T11, the gate of the pMOS type selection transistor T21, and the gate of the pMOS type isolation transistor T22 to the -Vcc potential, so that the -Vcc potential is transmitted to the gate of the pMOS type signal transmission transistor T3 through the SONOS pFLASH programming / erasing transistor T11 and the pMOS type isolation transistor T22, thereby realizing the on state of the pMOS type signal transmission transistor T3.

5. The isolated SONOS pFLASH switch unit structure as described in claim 4, characterized in that, The second operation method for the pMOS signal transmission transistor T3 to be in the on state includes the following steps: (1) performing an erase operation on the SONOS pFLASH programming / erasing transistors T11 and T12; (2) performing a programming operation on the SONOS pFLASH programming / erasing transistor T12; (3) connecting the drain of the SONOS pFLASH programming / erasing transistor T11, the gate of the SONOS pFLASH programming / erasing transistor T12, and the gate of the SONOS pFLASH programming / erasing transistor T11 to the GND potential, and connecting the drain of the SONOS pFLASH programming / erasing transistor T12, the gate of the pMOS type select transistor T21, and the gate of the pMOS type isolation transistor T22 to the -Vcc potential, so that the -Vcc potential passes through the SONOS The pFLASH programming / erasing transistor T12, the pMOS selection transistor T21, and the pMOS isolation transistor T22 transmit the signal to the gate of the pMOS signal transmission transistor T3, thereby enabling the pMOS signal transmission transistor T3 to be in the on state.

6. The isolated SONOS pFLASH switch unit structure as described in claim 5, characterized in that, The first operation method for putting the pMOS signal transmission transistor T3 in the off state includes the following steps: (1) performing an erase operation on the SONOS pFLASH programming / erasing transistors T11 and T12; (2) performing a programming operation on the SONOS pFLASH programming / erasing transistor T11; (3) connecting the drain of the SONOS pFLASH programming / erasing transistor T12, the gate of the pMOS selection transistor T21, and the gate of the pMOS isolation transistor T22 to a -Vcc potential, and connecting the drain of the SONOS pFLASH programming / erasing transistor T11, the gate of the SONOS pFLASH programming / erasing transistor T12, and the gate of the SONOS pFLASH programming / erasing transistor T11 to a GND potential, so that the GND potential is transmitted to the gate of the pMOS signal transmission transistor T3 through the SONOS pFLASH programming / erasing transistor T11 and the pMOS isolation transistor T22, thereby realizing the off state of the pMOS signal transmission transistor T3.

7. The isolated SONOS pFLASH switch unit structure as described in claim 6, characterized in that, The second operation method for the pMOS signal transmission transistor T3 to be in the off state includes the following steps: (1) performing an erase operation on the SONOS pFLASH programming / erasing transistors T11 and T12; (2) performing a programming operation on the SONOS pFLASH programming / erasing transistor T12; (3) connecting the drain of the SONOS pFLASH programming / erasing transistor T11, the gate of the pMOS selection transistor T21, and the gate of the pMOS isolation transistor T22 to a -Vcc potential, and connecting the drain of the SONOS pFLASH programming / erasing transistor T12, the gate of the SONOS pFLASH programming / erasing transistor T12, and the gate of the SONOS pFLASH programming / erasing transistor T11 to a GND potential, so that the GND potential passes through the SONOS The pFLASH programming / erasing transistor T12, the pMOS selection transistor T21, and the pMOS isolation transistor T22 transmit the signal to the gate of the pMOS signal transmission transistor T3, thereby realizing the off state of the pMOS signal transmission transistor T3.

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