Memory, method of performing read setup burst operation, and memory operation method

Abstract

A memory includes an array of memory cells and a plurality of control circuits. The array of memory cells includes a plurality of blocks. The plurality of control circuits includes logic to decode a read set burst command to identify an address of a first read set block in a set of read set blocks and a number of read set blocks that are candidates for a read set operation and perform a read set burst operation at the plurality of read set blocks of the set of read set blocks in response to the decoding of the read set burst command.

Description

Technical Field

[0001] This disclosure relates to an integrated circuit memory, including a non-volatile NAND flash memory and its operation, and more particularly to a technique for performing a read-set operation in a NAND flash memory by implementing a read-set burst command to reduce the deviation of voltage threshold distribution over time. Background Technology

[0002] A problem with NAND flash memory is that the threshold voltage of a cell will deviate over time, eventually unintentionally altering the cell's logic state. For example, this threshold voltage deviation can occur in a specific column of cells due to data being read from another column. Although error-correcting codes (ECCs) can be used to correct read errors caused by unintentional changes in the cell's logic state, the ability to correct these errors remains limited.

[0003] Therefore, it is necessary to prevent deviations in the threshold voltage of memory cells in NAND flash memory.

[0004] Public content

[0005] One aspect of this disclosure is a memory including a memory cell array and a plurality of control circuits. The memory cell array comprises a plurality of blocks. The plurality of control circuits include logic to perform the following operations: decoding a read-setup burst command to identify an address of a first read-setup block in a set of read-setup blocks and a number of read-setup blocks as candidates for a read-setup operation; and, in response to the decoding of the read-setup burst command, performing a read-setup burst operation in the plurality of read-setup blocks in the set of read-setup blocks.

[0006] Another aspect of this disclosure is a method for executing a read-setup burst operation, applicable to a memory, wherein the memory includes a memory cell array comprising a plurality of blocks, the method comprising: decoding a read-setup burst command to identify an address of a first read-setup block in a set of read-setup blocks and a number of read-setup blocks as candidates for a read-setup operation; and, in response to the decoding of the read-setup burst command, performing a read-setup burst operation in the plurality of read-setup blocks in the set of read-setup blocks.

[0007] Another aspect of this disclosure is a memory operation method, comprising: identifying a set of read setting blocks of a memory as candidates for a read setting operation; generating a read setting burst command to identify an address of a first read setting block in the set of read setting blocks and a number of read setting blocks as candidates for the read setting operation; and sending the generated read setting burst command to the memory to initiate the execution of a read setting burst operation on a plurality of read setting blocks in the set of read setting blocks.

[0008] To make other aspects and advantages of the present invention more apparent and understandable, the following drawings and detailed description are provided for illustration. Attached Figure Description

[0009] Figure 1 It is a perspective view of a three-dimensional vertical NAND structure with block and sub-block architecture.

[0010] Figure 2 It can be used Figure 1 The diagram shows a circuit diagram of a block of NAND cache memory cells implemented using the structure shown.

[0011] Figure 3 A simplified diagram is shown of a sense amplifier and bit line bias circuit that can be used in the apparatus described in this disclosure.

[0012] Figure 4 This is a block diagram illustrating the segmentation of a memory plane according to embodiments described in this disclosure.

[0013] Figure 5 This is a block diagram illustrating a segmented storage cell array comprising multiple planes, according to embodiments described in this disclosure.

[0014] Figure 6 This is a schematic diagram illustrating, according to an embodiment of the disclosed technology, the use of first and second queues for identifying read setting candidate blocks of flash memory.

[0015] Figure 7 This is a schematic diagram illustrating, according to an embodiment of the disclosed technology, the use of first and second queues for identifying read setting candidate blocks of flash memory.

[0016] Figure 8 This is a flowchart illustrating an embodiment of the disclosed technology, which describes identifying read candidate blocks of flash memory and performing read setting operations on the identified read candidate blocks.

[0017] Figure 9A flowchart illustrating an embodiment of the disclosed technology describes scanning a second queue to identify read setting candidate blocks of flash memory and performing read setting operations on the identified read setting candidate blocks.

[0018] Figure 10 This is a flowchart illustrating an embodiment of the disclosed technology, which describes scanning a second queue to identify read setting candidate blocks of flash memory and performing read setting operations on the identified read setting candidate blocks.

[0019] Figure 11 This is a schematic diagram illustrating the use of a read setting table to perform a read setting operation according to an embodiment of the disclosed technology.

[0020] Figure 12 This is a flowchart illustrating an embodiment of the disclosed technology, which describes the use of error correction code (ECC) to identify read setting candidate blocks.

[0021] Figure 13 This is a flowchart illustrating an embodiment of the disclosed technology, which describes the use of a read setting permission table to identify read candidate blocks and to perform read setting operations on the identified read candidate blocks.

[0022] Figure 14 This is a simplified diagram illustrating a controller for sending a read / set burst command to a flash memory, according to an embodiment of the disclosed technology.

[0023] Figure 15 This is a flowchart illustrating an embodiment of the disclosed technology, which describes the generation of a read setting burst command, the sending of the read setting burst command to the memory, and the memory performing a read setting operation according to the read setting burst command.

[0024] Figure 16 This is a block diagram of a memory system according to an embodiment of the present disclosure.

[0025] Explanation of reference numerals in the attached figures

[0026] 10:Substrate

[0027] 11: Wordline Layer

[0028] 12: Serial select line

[0029] 13: Low selection line

[0030] 15: column

[0031] 18: Common source conductor

[0032] 20: Global Bitline Conductor

[0033] 21: First line overlapping

[0034] 22: Second line overlapping

[0035] 201: Dashed line

[0036] 202: Sub-block string selection line

[0037] 203: Bit Line

[0038] 318: Bit Line Select Transistor

[0039] 319, 322: Lines

[0040] 320: Global Bitline

[0041] 321: Bit-line clamping transistor

[0042] 323: Connecting Nodes

[0043] 327, 336: Transistors

[0044] 332: Sensing Node

[0045] 335: Channel Transistor

[0046] 337: Capacitor

[0047] 338: Sensing signal node / sensing pulse node

[0048] 339: Sensing Transistor

[0049] 400: Plane

[0050] 405: A combination of a sensing amplifier and a bit line bias circuit.

[0051] 410, 411, 413, 414: Serial select line / word line driver

[0052] 412, MBL0, MBLi, MBLn: Global bit lines

[0053] 500: Memory

[0054] 1300: First Queue

[0055] 1302: Second Queue

[0056] 1500, 1600, 1700, 1900, 2000, 2200: Flowchart

[0057] 1502, 1504, 1506, 1508, 1510, 1512, 1514, 1516, 1602, 1604, 1606, 1608, 1701, 1702, 1704, 1706, 1708, 1902, 1904, 1906, 2002, 2202, 2204, 2206, 2208, 2210, 2212, 2214, 2216, 2218: Operation

[0058] 1800: Read the settings table

[0059] 2100: Flash memory

[0060] 2102: Controller

[0061] 2104: Sequentially read the number of blocks set

[0062] 2106: First read the address of the setting block

[0063] 2302: Host side

[0064] 2308: Memory

[0065] 2314, 2316, 2344: Links

[0066] 2318: Input / Output Circuit

[0067] 2326: Bus System

[0068] 2328: Cache circuit

[0069] 2334: Command Decoding / Control Circuit

[0070] 2335: State Buffer

[0071] 2338: Page Buffer Circuit

[0072] 2345, 2346, 2365: Arrows

[0073] 2348: Bit line drive circuit

[0074] 2364: Square

[0075] 2366: Bitline

[0076] 2376A: Word Line Decoder

[0077] 2376B: Word line driver circuit

[0078] 2377: Word Line

[0079] 2378: Memory Cell Array

[0080] 2378A: Serial Select / Ground Select Decoder

[0081] 2378B: Series Select / Ground Select Driver Circuit

[0082] 2379: Serial Select Line / Ground Select Line

[0083] 2380: Read the settings and license table

[0084] 2382: Error Correction Code

[0085] 2384: Candidate Table Buffer

[0086] BLS, BLC1, BLC2, BLC3, BLC4: Control signals

[0087] CSL1: Common Source Pole

[0088] DWLG: Low Virtual Word Line

[0089] DWLS: High Virtual Word Line Layer

[0090] GSL: Low-select gate layer

[0091] SSL0, SSl1, SSLn: Serial select lines

[0092] VGW1, VGW2: Bias voltage

[0093] WL0, WL1, WL30, WL31, WLn-3, WLn-2, ​​WLn-1, WLn, WLn+k: word lines Detailed Implementation

[0094] Please see Figures 1-16 It provides a detailed description of embodiments of the present invention.

[0095] Figure 1 A perspective view of a three-dimensional semiconductor device is shown, wherein the three-dimensional semiconductor device includes multiple blocks and sub-blocks of multiple memory cells in multiple vertical NAND strings. The three-dimensional semiconductor device 1 includes a multi-level stacked word line layer 11, a first word line stack 21 and a second word line stack 22 respectively configured to be parallel to a substrate 10; and in the Z direction (e.g., ... Figure 1Multiple pillars 15, orthogonally oriented to the substrate 10 and extending through the corresponding word line stacks, are shown. Each pillar 15 includes a semiconductor body providing multiple channels for multiple serially connected memory cells. These channels can be thin-film channels with a thickness of less than 10 nanometers, where the serially connected memory cells are located at the intersections of multiple pillars and multiple word lines in the NAND string configuration. Multiple string select lines (SSLs) 12 are aligned with the substrate in the Y direction (e.g., ...). Figure 1 As shown, the first and second memory cell blocks are oriented parallel to and located above word line layer 11. In this example, the first and second memory cell blocks are formed on the first word line stack 21 and the second word line stack 22, respectively, wherein the first word line stack 21 and the second word line stack 22 are coupled to different groups of NAND strings. Each string select line intersects at a subset (e.g., one or more columns) of a set of multiple pillars in a corresponding block, wherein each sub-memory cell block in the corresponding block is formed on a subset of pillars coupled to the corresponding string select line.

[0096] This structure also includes multiple parallel global bit line conductors 20, located in the X direction (e.g., ...). Figure 1 A layer extending on and parallel to the substrate (as shown), and above multiple string select lines. Each global bit line conductor is superimposed on a corresponding row of pillars in an array spanning multiple blocks, and each row contains a pillar of a subset of the pillars of each string select line.

[0097] Each intersection of a post and a select line defines the post's select gate, which is used to connect to the corresponding bit line. Each post is located below one of the multiple bit line conductors and is coupled to one of the multiple bit line conductors through the post's select gate.

[0098] Multiple low-select lines (lower select gates) 13 are formed below the word line layer 11 to couple multiple pillars to one or more source lines, such as common-source conductors 18. The common-source conductors can be connected to the bias circuitry system via multiple vertical connections between multiple blocks or otherwise.

[0099] Figure 1 The structure is an example of a memory that includes multiple memory cell blocks and multiple bit lines. Each block contains a set of word lines (i.e., Figure 1 (A stack of layers). A NAND string set has multiple string select gates for coupling to multiple corresponding bit lines among multiple bit lines. Each NAND string in a block of NAND string sets is connected to a set of word lines. Figure 1This structure is also an example of a memory where each block of multiple memory cell blocks contains multiple sub-blocks. Each sub-block contains different subsets of a set of NAND strings in a block. In this example, the different subsets of NAND strings in each sub-block are operatively connected to corresponding sub-block string select lines, wherein multiple gate voltages can be applied to multiple string select gates of multiple NAND strings in the different subsets of the sub-block via the sub-block string select lines.

[0100] At Figure 1 In the illustrated structure, the effect of the resistivity of multiple channel semiconductor materials changing over time can be limited through an operation. For example, in some memory structures, when writing to multiple memory cells, the channel polysilicon is subjected to voltage stress, such that the write threshold is based on the resistivity under voltage stress. To address this issue, a stress read bias can be used to apply voltage stress to multiple memory cells for reading. After the stress read, the channel can remain under voltage stress for a period of time, for example, about 10 minutes. In this way, memory cells can be read during this period without requiring another stress read bias.

[0101] Figure 2 A schematic diagram of a memory cell block in a 3D NAND device is shown. The 3D NAND device may include multiple blocks, and each block may include multiple sub-blocks. In this schematic diagram, multiple global bit lines MBL0~MBLn cover an array of NAND strings arranged in multiple columns and rows. Each NAND string contains a series of multiple memory cells (e.g., multiple dielectric charge trapping memory cells) connected in series between a corresponding bit line and a reference line (e.g., a common source line CSL). In some embodiments, the common source line of a block may serve as one or more reference lines and may be coupled to a bias circuit system, wherein multiple operating voltages can be applied to various operations of the memory through the bias circuit system.

[0102] For example, in a 3D NAND configuration, Figure 2 The set of multiple NAND strings in the block shown corresponds to Figure 1Multiple pillars. In this example, multiple NAND strings are coupled to corresponding stacks of multiple word lines WL0~WLn+k, where each word line is coupled to multiple memory cells in all NAND strings of the block in its layer. At word line WLn, the planar structure of each word line layer is indicated by dashed line 201. Therefore, all memory cells in a layer of a given word line (e.g., WLn) in the block are coupled to that given word line, such that these memory cells can be activated by a voltage applied to that given word line.

[0103] In addition, each NAND string contains a corresponding sub-block string selection line (e.g., 202) to connect the NAND string to a specific bit line among a plurality of bit lines (e.g., 203).

[0104] Multiple subblock string select lines SSL0~SSLn are operatively coupled to the string select gates of multiple different NAND string subsets to apply multiple gate voltages to the multiple subblock string select gates, wherein each NAND string subset contains a subblock of a memory cell block.

[0105] In addition, each NAND string includes a corresponding lower select gate for connecting the NAND string to a common-source line or one or more reference lines to implement the common-source line. In this example, a lower select gate layer (GSL) is coupled to all the lower select gates of multiple NAND strings in the block. In another example, the block may include multiple lower select gate lines for connecting to multiple lower select gates.

[0106] In this example, a lower dummy word line (DWLG) is located between the lower select gate layer (GSL) and the bottommost word line layer (WL0), and an upper dummy word layer (DWLS) is located between the string select lines (SSL0~SSLn) and the topmost word line layer (WLn+k).

[0107] exist Figure 2In the circuitry, to select a specific memory cell within a block, a sub-block string select line activates a sub-block, where the sub-block string select line connects each NAND string in the selected sub-block to a corresponding bit line among multiple bit lines. Additionally, a word line layer is selected to select a memory cell located on that layer of the selected word line within each NAND string of the selected sub-block. The selected memory cell is activated by selecting a bit line corresponding to the NAND string containing the selected memory cell. This configuration, through its corresponding bit lines and word line layers, enables the activation of multiple parallel memory cells, each of which resides in a corresponding NAND string within the multiple NAND strings of the selected sub-block.

[0108] As used in this disclosure, "activate" means applying a specific bias voltage to activate a plurality of connected cells or switches. This bias voltage can be high or low depending on the operation or memory design. For illustrative purposes, the term "charging" can refer to driving a node to a higher voltage or driving a node to a lower voltage. In some embodiments, the lower voltage includes a ground voltage or a negative voltage.

[0109] The NAND block described in this disclosure can be implemented using three-dimensional NAND memory technology or using two-dimensional NAND technology, wherein the NAND block is logically formed by spanning multiple two-dimensional NAND memory cell arrays.

[0110] Figure 3 The diagram illustrates the structure of a sense amplifier and a bit line bias circuit, wherein the bit line bias circuit can be used to apply a bias voltage to each of a plurality of bit lines. A page buffer may include a sense amplifier and a bit line bias circuit, and each bit line is coupled to a selected block in an array.

[0111] Figure 3The circuitry is connected to global bit line 320. A bit line select transistor 318 has a first source / drain terminal and a second source / drain terminal connected to global bit line 320. The gate of bit line select transistor 318 is connected to control signal BLS on line 319. A bit line clamp transistor 321 has a first source / drain terminal connected to the second source / drain terminal of transistor 318 and a second source / drain terminal connected to connection node 323. The gate of bit line clamp transistor 321 is connected to line 322 (receiving control signal BLC1), wherein a circuit (not shown) applies a bias voltage to line 322 to control the voltage level of global bit line MBL during precharge operation or other operations. A transistor 327 connects node 323 to control signal BLC2, wherein a circuit (not shown) applies a bias voltage to the line receiving control signal BLC2. A channel transistor 335 is connected between connection node 323 and a sensing node 332.

[0112] Channel transistor 335 is controlled by a control signal BLC3 to control whether connection node 323 is connected to sensing node 332. A transistor 336 is connected between sensing node 332 and a bias voltage VGW2, and is controlled by a control signal BLC4. A capacitor 337 (capacitance value) is coupled from sensing node 332 to a sensing signal node 338. A sensing transistor 339 has a gate connected to sensing node 332, a first current-carrying terminal connected to sensing pulse node 338, and a second current-carrying terminal providing the output of a sensing amplifier, and can be connected to multiple latches of a page buffer.

[0113] In read operations or other operations, operable transistors 318, 327, and 321 set a bias voltage level on selected bit lines to satisfy a specific operation.

[0114] Figure 4 and Figure 5 This illustration, based on an example of the application of the techniques described herein, depicts a portion of a memory cell array in a memory device at the plane, block, and sub-block levels. The techniques include the application of readsetup operations, which involve simultaneously applying bias voltages to multiple memory cells to adjust the multiple memory cells for subsequent read operations and to prevent voltage threshold deviations in the multiple memory cells. The aforementioned adjustment actions can adjust the memory cells so that the threshold voltage matches or approaches the threshold voltage established during the aforementioned write operation.

[0115] Figure 4The diagram illustrates the configuration of a single plane 400 in a memory cell array. Plane 400 contains multiple blocks 0 to b. Each block contains multiple sub-blocks. Thus, block 0 contains multiple sub-blocks 00 to 0n, block 1 contains multiple sub-blocks 10 to 1n, block (b-1) contains multiple sub-blocks (b-1)0 to (b-1)n, and block b contains multiple sub-blocks b0 to bn.

[0116] All blocks in the overlapping plane of multiple global bit lines (MBLs) 412, and shared by all blocks in the plane. A collection 405 of sense amplifiers and bit line bias circuitry (e.g., Figure 3 This can be part of the page buffer circuitry and coupled to multiple global bit lines 412, thereby allowing bias voltages to be applied to the global bit lines 412 to support read / set operations. The collection 405 of sense amplifiers and bit line bias circuitry is shared by all blocks in the plane. Each block contains corresponding SSL / WL drivers 410, 411, 413, and 414, thereby allowing bias voltages to be applied to support read / set operations. Additionally, a common-source driver can be applied to each block.

[0117] In some embodiments, a read setting operation can be applied to only one block at a time in a given plane. In other embodiments, a read setting operation can be applied to multiple blocks simultaneously in a given plane. In other embodiments, a read setting operation applicable to a block having n sub-blocks can be applied simultaneously to more than 1 and fewer than n sub-blocks. In other embodiments, a read setting operation can be applied simultaneously to one or more sub-blocks of one block in the plane or one or more sub-blocks of another block.

[0118] Figure 5 The diagram illustrates a memory chip 500 with multiple planes, in this example, plane 0, plane 1, plane 2, and plane 3. Each plane contains different page buffer circuitry, such as page buffer 0, page buffer 1, page buffer 2, and page buffer 3. Multiple page buffers are coupled to an input / output circuitry system (not shown) to support high-volume memory operations across the multiple planes. As shown, each plane contains multiple blocks. Plane 0 contains blocks 00, 01, 02, 03, etc.; plane 1 contains blocks 10, 11, 12, 13, etc.; plane 2 contains blocks 20, 21, 22, 23, etc.; and plane 3 contains blocks 30, 31, 32, 33, etc.

[0119] See also Figure 5 The discussion outlines how read setup operations can be applied to one or more blocks in a single plane to prevent voltage threshold deviations in memory cells, thereby matching or approaching the threshold voltage established during the aforementioned write operation. In some embodiments, read setup operations can also be applied simultaneously to one or more blocks in one plane and one or more blocks in another plane. Read setup operations can also be applied simultaneously to one or more sub-blocks in one block of one plane and one or more sub-blocks in one block of another plane. Furthermore, read setup operations can be applied to read setup units other than sub-blocks, blocks, and plane cells to meet specific memory configurations.

[0120] Figures 6 to 11 Alternative embodiments of read setup bias arrangements applied simultaneously to multiple parallel memory cells in the read setup operations described herein are illustrated. The bias arrangements applied to the read setup operations can be determined based on the memory architecture of the cell array through trial and error or simulation. Generally, the bias arrangements applied to the read setup operations should be configured to prevent the charge stored in the memory cells from being disturbed by an amount that could lead to data loss. Typically, such bias arrangements have a voltage magnitude approximately equal to that applied during normal read operations.

[0121] Figures 6 to 16 Examples and flowcharts of operations that can be used to perform the read setup procedure described in this disclosure, which applies bias arrangements in parallel or simultaneously to multiple memory cells. For example, to multiple memory cells coupled to a single bit line, to all memory cells in a sub-block, to all memory cells in a block, to all memory cells in multiple sub-blocks, or to all memory cells in multiple blocks.

[0122] also, Figures 6 to 16These are examples and flowcharts illustrating the logic executed by a memory controller or a memory device. The logic can be implemented by a processor programmed with a computer program, wherein the computer program is stored in memory accessible to the computer system, and the computer program can be executed by the processor, by dedicated logic hardware containing field-programmable integrated circuits, or by a combination of dedicated logic hardware and a computer program. It is understood that many steps in all the flowcharts herein can be combined, executed in parallel, or executed in different orders without affecting the implemented functionality. It is also understood that in some cases, only by making certain necessary modifications can the rearranged steps achieve the same result. Furthermore, it is understood that the flowcharts herein only show steps relevant to understanding the disclosed technology. It is understood that multiple additional steps to accomplish other functions can be performed before, after, and between the steps shown.

[0123] Figure 6 This is a schematic diagram illustrating the use of a first and second queue for identifying multiple read setting candidate blocks of a 3D flash memory, according to an embodiment of the disclosed technology.

[0124] Specifically, Figure 6 The diagram illustrates a first queue 1300, which can be a first-in-first-out (FIFO) queue; and a second queue 1302, which can be a least recently used (LRU) queue. The first and second queues 1300 and 1302 can also be other types of queues, such as circular queues, priority queues, or double-ended queues. The first and second queues 1300 and 1302 can be implemented using a linked list and multiple linked list pointers to indicate positions within the list.

[0125] As shown in the figure, the first and second queues 1300 and 1302 contain multiple positions, including a front (frontmost) position, multiple middle positions, and a back (rearmost) position. Figure 6The illustration shows that the second queue 1302 has more positions than the first queue 1300 (e.g., the "size" of the second queue 1302 is larger than that of the first queue 1300). However, this is only an example. The first queue 1300 may have the same number of positions as the second queue 1302 (e.g., the "size" of the first and second queues 1300 and 1302 is the same), or it may have more positions than the second queue 1302 (e.g., the "size" of the first queue 1300 is larger than that of the second queue 1302).

[0126] The positions in the first queue 1300 are used to identify the accessed (e.g., read operation) flash memory blocks. As a new flash memory block is accessed, its identifier (e.g., block #12) is added to a later position in the first queue 1300 (see [link to queue 1300]). Figure 6 (Item 1). To make room for the new identifier, other identifiers will be shifted forward of the first queue 1300. In this example, because block #12 is accessed, the identifier for block #12 is newly added to the end of the first queue 1300, causing other identifiers to be shifted forward of the first queue 1300. If the first queue 1300 is full, an identifier for a memory block will be eliminated with the shift (for example, the identifier for block #45 will be eliminated from the first queue 1300; see [link to project 1]). Figure 6 (Project 2). In an alternative to the aforementioned example, the first queue 1300 can be implemented as a linked list and multiple updatable linked list pointers to achieve the same result.

[0127] Before adding an identifier for a flash memory block to the first queue 1300, the disclosed technology checks whether the first queue 1300 or the second queue 1302 already contains an identifier for a flash memory block. If neither the first queue 1300 nor the second queue 1302 contains an identifier for a specific block of flash memory, then the identifier for that specific block (e.g., block #12) can be added to the end of the first queue 1300.

[0128] If a specific block of the flash memory being accessed (e.g., block #63) has been identified in the first queue 1300 (and has not yet been identified in the second queue 1302), then the identifier of the specific block (e.g., block #63) can be added to the end of the second queue 1302 (see [link to relevant documentation]). Figure 6 (Item 3). As discussed above regarding the first queue 1300, to make room for the new identifier to be added to the second queue 1302, the identifiers of other blocks in the second queue 1302 will be shifted forward of the second queue 1302. If the second queue 1302 is already full, one identifier of the memory block will be eliminated during the shift (see Item 3). Figure 6Project 4). For example, such as Figure 6 As shown, the shifting and adding of the identifier for block #63 causes block #27 to be removed from the second queue 1302. The identifier of the accessed block is newly added to the second queue 1302, thus allowing it to be removed from the first queue 1300. For example, as Figure 6 As shown, the identifier for block #63 can be removed from the first queue 1300 to make room for a new block identifier and prevent the same block from being identified multiple times in the first and second queues 1300 and 1302. In this example, the removal of block #63 causes multiple blocks #12, #00, #11, #60, #31, and #28 to be shifted to the front of the first queue 1300. In an alternative to the aforementioned example, the first and / or second queues 1300 and 1302 can be implemented as a linked list and multiple updatable linked list pointers to achieve the same result.

[0129] Figure 7 This is a schematic diagram illustrating the use of a first and second queue for identifying multiple read setting candidate blocks of a flash memory, according to an embodiment of the disclosed technology.

[0130] Figure 7 Similar to Figure 6 The difference lies in that it provides an example of an identifier for an access block of flash memory that is not included in the first queue 1300 but is already included in the second queue 1302. Therefore, if the identifier in the second queue 1302 is not yet at the end of the second queue 1302, the identifier can be moved to the end position (see [link to relevant documentation]). Figure 7 Project 5). For example, such as Figure 7 As shown, if block #42 is accessed and not identified in the first queue 1300, but has been identified in the second queue 1302 at a non-last position, then the identifier of block #42 is moved to the last position in the second queue 1302. In this example, as the identifier of block #42 is moved to the end of the second queue 1302, multiple blocks #63, #01, and #21 will be shifted to the front of the second queue 1302. In an alternative to the aforementioned example, the first and / or second queues 1300, 1302 can be implemented as a linked list and multiple updatable linked list pointers to achieve the same result.

[0131] Figure 8 This is a flowchart illustrating, according to an embodiment of the disclosed technology, the identification of read candidate blocks of a flash memory and the execution of read setting operations on the identified read candidate blocks.

[0132] Specifically, Figure 8A flowchart 1500 illustrates an operation method of a NAND flash memory comprising multiple blocks consisting of multiple memory cells arranged in multiple NAND strings, wherein each block contains a different set of NAND strings. As previously described, each block may contain multiple sub-blocks, and each sub-block contains a different subset of NAND strings.

[0133] exist Figure 8 Operation 1502 identifies a flash memory block to be accessed. In response to access to the memory block (e.g., an access operation is identified), operation 1504 checks whether the memory block to be accessed exists in the first queue 1300 or the second queue 1302. (See above.) Figures 6-7 If the discussion proceeds and no memory block is found to be accessed in the first or second queue 1300, 1302, then operation 1506 is performed to update the first queue 1300 to identify the accessed block.

[0134] If a memory block to be accessed is identified in the first or second queue 1300, 1302 (i.e., "Yes" in operation 1504), then operation 1508 is executed to check whether there is a flash memory block to be accessed in the first queue 1300. If an access block is identified in the first queue 1300 (i.e., "Yes" in operation 1508), then operation 1510 is executed to update the second queue 1302 to identify the access block. See above. Figures 6-7 The discussion proceeds as the identifier of the access block is added to the second queue 1302, and the identifier of the access block can be removed from the first queue 1300. Furthermore, as mentioned earlier, when an identifier is added to a queue in operations 1506 and 1510, an identifier already existing in the queue can be shifted to the front of the queue.

[0135] If no access block is identified in the first queue 1300 during operation 1508, then operation 1512 is executed to determine that the access block should already be included in the second queue 1302, and then the position of the access block identifier in the second queue 1302 is updated, as described above. Figures 6-7 The discussion that took place (e.g., the position of the identifier was moved to the back of the second queue 1302, and other identifiers could be moved to the front of the second queue 1302).

[0136] Next, operation 1514 is performed to scan the second queue 1302 to identify any access block eligible as a read setup candidate block (also called a candidate read setup block). If a block is identified as having existed in the second queue 1302 for a period exceeding (or equal to) a preset threshold, the block is identified as a read setup candidate block. To determine whether a block has existed in the second queue 1302 for a period exceeding (or equal to) the preset threshold, a timestamp or timecounter associated with the block in the second queue 1302 can be used. If the timestamp or timecounter indicates a time lapse exceeding (or equal to) the preset threshold, it means that the block has existed in the second queue 1302 for a period exceeding (or equal to) the preset threshold. The preset threshold used to identify read setup candidate blocks can be set to reflect any amount of time. In one example, the preset threshold can be set to 9 minutes. Therefore, if an access block is identified as being in the second queue 1302 for more than 9 minutes, the access block will be identified as a read setup candidate block. When a block is first identified in the second queue 1302 or when it is moved to the end of the second queue 1302, the timestamp or time counter of the identified and accessed block can be set to 0 (as discussed below, the timestamp or time counter can be updated each time a scan is executed). The timestamp or time counter can be set relative to a point in time when the block is accessed and / or identified in the first and / or second queues 1300, 1302. For example, the timestamp or time counter of the identified and accessed block can be set to reflect a point in time when the access block was identified in the first queue 1300 (e.g., system clock time). Alternatively, it can be set to reflect a point in time when the access block was first identified in the second queue 1302 (e.g., when the identifier of the access block is moved from the first queue 1300 to the second queue 1302) (e.g., system clock time). As discussed in operation 1512, the timestamp or time counter for accessing the block can also be set to reflect a point in time when the position of the access block identifier is moved to the end of the second queue 1302. Other techniques for setting and / or changing the timestamp or time counter can also be implemented, such as those described below. Figures 10-11 The technology described in the figure. As an alternative to the position of the identifier of the moving block in the first and / or second queues 1300, 1302, and as an alternative to updating the linked list pointer as described above, a timestamp or time counter may be updated in the first and / or second queues 1300, 1302 in response to the use or access of a particular block.

[0137] Once a candidate block for setting is identified, operation 1516 is performed, whereby a read setting operation is performed on the identified candidate block. The read setting operation can be performed according to any of the techniques disclosed herein. In one embodiment, other conditions for performing a read setting operation on a block may be considered, and the read setting operation may not be performed on all candidate blocks. In one embodiment, the read setting operation is performed only on a subset of blocks, such as a specific page of a block. The page of a block can be identified using the aforementioned techniques, or the page of a block can be identified in the block's identifier when the block is identified in the first and second queues 1300, 1302. Accordingly, the read setting operation can be performed on a page-by-page basis. Therefore, the read setting operation performed on an identified block can be included in performing read setting operations on one page, multiple pages, or all pages of the block. These techniques for performing read operations on a subset of blocks (e.g., one page of a block) can be implemented using all other read setting operation techniques disclosed herein.

[0138] Figure 9 This is a flowchart illustrating, according to an embodiment of the disclosed technology, scanning a second queue to identify read setting candidate blocks of flash memory and performing read setting operations on the identified read candidate blocks.

[0139] Specifically, Figure 9 The illustration describes it in more detail. Figure 8 The flowchart 1600 describes the scanning operation 1514. The second queue 1302 can be scanned periodically according to a preset time interval. The preset time interval can be set to any time. In one example, the preset time interval can be 1 minute. The scanning of the second queue 1302 can start from the first position and end at the last position, or the second queue 1302 can be scanned in any order. Each time a scan is performed, all positions in the second queue 1302 can be scanned.

[0140] In operation 1602, during scanning, it is determined whether the duration of a specific block identified in the second queue 1302 is greater than (or equal to) a preset threshold (e.g., a specific block identified as existing in the second queue 1302 for a duration greater than the preset threshold). If the duration of the specific block is greater than (or equal to) the preset threshold, operation 1604 is executed to add the identifier of the specific block to the read setting table. Next, operation 1606 is executed to determine whether all positions in the second queue 1302 have been scanned. If not (i.e., operation 1606 is "No"), operation 1602 is executed to check the duration of another block identified in the second queue 1302.

[0141] On the other hand, if the time length determined in operation 1602 does not exceed (or equal to) a preset threshold, the identifier of the specific block will not be added to the read setting table, and operation 1606 will be executed to check whether all positions of the second queue 1302 have been scanned. As shown in the figure, once all positions of the second queue 1302 have been scanned (i.e., operation 1606 is "yes"), operation 1608 will be executed, sending a read setting command to the memory, and performing the read setting operation through the memory block in the read setting table. For example, in operation 1608, a read setting command is sent from a host (e.g., a memory controller) to the memory 2308, causing the command decoding / control circuit 2334 of the memory 2308 to receive the read setting command, which is then scheduled by a state machine of the memory 2308 and executed on the memory 2308. After the read setting operation is initialized and / or completed, the read setting table can be cleared so that it can be repopulated when the second queue 1302 is scanned again (e.g., once the preset time increment expires and it is time to perform the scan operation again).

[0142] Figure 10 This is a flowchart illustrating, according to an embodiment of the disclosed technology, scanning a second queue to identify read setup candidate blocks of flash memory and performing read setup operations on the identified read candidate blocks.

[0143] Specifically, Figure 10 Flowchart 1700 is shown, and it is related to... Figure 9 The flowchart is similar to 1600, but provides further details about the scan order and the addition of the timestamps.

[0144] In operation 1701, the scan begins at position n of the second queue 1302. As previously mentioned, the scan can begin from the very beginning, the very end, or any other arbitrary position of the second queue 1302. In this example, in operation 1701, the scan will begin from the very beginning of the second queue 1302, where n represents the number of positions in the second queue 1302. For example, if the second queue 1302 contains 12 positions for identifying different memory blocks, then n could initially be 11 in operation 1701. This can also be done in reverse order, where if there are 12 positions in the second queue 1302, n can increase from 0 to 11.

[0145] In operation 1701, it is determined whether the time length of the block identified at position n (e.g., position 12, where n equals 11) is greater than (or equal to) a preset threshold.

[0146] In one embodiment, if the time length is not greater than (or equal to) a preset threshold, operation 1708 is performed to increment the timestamp or time counter associated with the block identifier. In this particular embodiment, when the block identifier is added to the second queue 1302, the timestamp or time counter associated with the block is initially set to, for example, 0. Then, when operation 1708 is performed, the timestamp or time counter is incremented at the same time the scan is set to be repeated. For example, if the scan is set to repeat every minute, the timestamp or time counter will increment by 1 minute each time a scan is performed and the identified block is still below the preset threshold. Eventually, the timestamp or time counter associated with a particular block will be sufficiently incremented to be equal to or greater than the preset threshold.

[0147] In another embodiment, operation 1708 can be omitted when the timestamp or time counter associated with a specific block is based on the system clock time when the identifier of the specific block is added to, for example, the second queue 1302 (or the time when the identifier is added to, for example, the first queue 1300, or the time when the identifier is moved from one position to the front in the second queue 1302). In this embodiment, because the timestamp or time counter associated with the specific block can be compared with the current system clock time to determine whether enough time has elapsed to reach or exceed a preset threshold, operation 1708 is not required. In this embodiment, operation 1708 is omitted. Accordingly, if the result of operation 1701 is "no", then operation 1704 is executed to determine whether the last position of the second queue 1302 has been scanned. In one embodiment, as described above, the second queue 1302 is scanned starting from the first position and ending at the last position. Therefore, if the last position has been scanned, it means that all positions have been scanned. In another embodiment, the scan may start from the last position and proceed towards the first position. In this case, operation 1704 will determine whether the first position has been scanned. Alternatively, in another embodiment, operation 1704 may simply determine whether all positions in the second queue 1302 have been scanned.

[0148] Returning to the description of operation 1701, if the time length is greater than (or equal to) a preset threshold, then operation 1702 is executed to add the identifier of the specific block at position n in the second queue 1302 to the read setting table. Once the identifier is added to the read setting table, operation 1704 is executed to determine whether the last position of the second queue 1302 has been scanned (i.e., whether all positions have been scanned).

[0149] If the last position has not yet been scanned, operation 1706 is executed, decrementing the value of n by 1, and then operation 1701 is executed in the next block of the second queue 1302. Note that in another embodiment, in one case, for example, if n starts from 0, the value of n can be increased in operation 1706. This cycle continues until all positions have been scanned.

[0150] Once all locations have been scanned (i.e., operation 1704 is "Yes"), operation 1608 is performed to execute a read setup operation by reading the blocks identified in the read setup table. After executing the read setup operation, the read setup table can be cleared so that it is empty when the next scan is performed at a preset time.

[0151] Figure 11 This is a schematic diagram illustrating the use of a read settings table for performing read settings operations, according to an embodiment of the disclosed technology.

[0152] Specifically, Figure 11 The diagram illustrates how the read setup table 1800 is filled from the second queue 1302. As shown, the second queue 1302 contains, for example, 12 locations for identifying specific blocks. See the previous section. Figure 10 The discussion proceeds that the scanning of the second queue 1302 can begin at the very front position (e.g., n=11) and end at the very back position (e.g., n=0), such that each time n decreases, the next position closer to the very back of the second queue 1302 will be scanned. Once the very back position is reached, the specific scanning operation is complete, and the scanning will restart after a preset time increment (e.g., 1 minute).

[0153] In addition, such as Figure 11 As shown, each position in the second queue 1302 contains an identifier for a specific block (e.g., block #06) and a corresponding timestamp or time counter (e.g., timestamp (Y)). As previously mentioned, the timestamp can be used in different ways. For example, the timestamp can start from 0, and the timestamp or time counter can be incremented by a value (e.g., a predetermined time increment used when performing the scan) each time a scan is performed. Alternatively, the timestamp or time counter can be added to the system clock time of the second queue 1302 or the first queue 1300 for the identifier of the specific block. If this alternative is used, operation 1708 is not required, as previously mentioned. Figure 10 The discussions that took place.

[0154] When a scan is performed, if a specific timestamp or time counter (e.g., timestamp (Y)) associated with a specific block (e.g., block #06) is greater than (or equal to) a preset threshold, the identifier of the specific block is added to the read settings table 1800. Figure 11 Two timestamps or time counters that exceed a preset threshold are plotted, so that the identifiers of blocks #06 and #03 are added to the read settings table 1800.

[0155] The read setup table 1800 can have the same number of positions as the second queue 1302, allowing multiple positions in the second queue 1302 to be mapped one-to-one to multiple positions in the read setup table 1800. Other types of read setup tables that cannot be mapped one-to-one to the second queue 1302 can also be used. Once the scan iteration is complete, the read setup operation will be performed on the block identified in the read setup table 1800. See also... Figure 10 As mentioned, the read setup table 1800 can be cleared after the read setup operation is performed, so that it is empty when the next scan operation begins. The read setup operation can start from the beginning or the end of the read setup table 1800, or in any other order or simultaneously.

[0156] Figure 12 This is a schematic diagram illustrating the use of an error correction code (ECC) for identifying and reading candidate blocks, according to an embodiment of the disclosed technology.

[0157] In the early stages of a memory block's lifecycle, because the rate at which the threshold voltage deviates over time is not yet unpredictable, a read-set operation may not be necessary. Therefore, in one embodiment of the disclosed technology, the read-set operation is only performed on blocks that have already been fully used.

[0158] Figure 12 A flowchart 1900 illustrates the use of an error correction code to identify an ECC error count to determine whether a particular block has been fully utilized before various technical implementations of a read-setup operation are performed. In operation 1902, a flash memory block that has been accessed is identified. In operation 1904, for a specific block, the number of detected error counts is determined using the error correction code to be greater than (or equal to) an ECC threshold. A persistent non-volatile table can be used to continuously track the number of errors detected for the memory block, allowing the table's contents to be retained after power loss. Each time an error occurs, the ECC error count for the specific block can be incremented in the table. This table can be used when the number of errors for the block identified in operation 1902 is greater than (or equal to) the error correction code threshold. Alternatively, the number of errors for a specific read operation can be tracked so that if the number of errors detected using the error correction code exceeds the error correction code threshold, the specific block that constitutes the subject of the read operation can be identified in the table.

[0159] If the number of errors (e.g., ECC error count) is greater than (or equal to) the error correction code threshold, operation 1906 is performed to add the identifier of the specific block to a read setup permitted list. Then, operation 1902 is performed to identify another block. If the number of ECC error counts is not greater than (or equal to) the error correction code threshold (i.e., "No" in operation 1904), the identifier of the specific block will not be added to the read setup permitted list, and operation 1902 will be performed to identify another block. Furthermore, if operation 1904 determines that the number of ECC error counts for a specific block is greater than (or equal to) the error correction code threshold, the block can be identified in the first or second queues 1300, 1302, or it can be identified in the read setup table (i.e., identified as a read setup candidate), regardless of whether the specific memory block has been present in the second queue 1302 for more than a preset threshold, or regardless of whether the specific memory block has been identified in either the first or second queues 1300, 1302.

[0160] Using ECC error counting is one way to determine whether a specific memory block is fully utilized to become a read setup candidate. Other usage methods can also be considered, such as the number of program and erase (PE) cycles for a specific block. Similar to the description of ECC error counting above, a table can be used to continuously track the number of PE cycles for each block. If the number of PE cycles is greater than (or equal to) a specific PE threshold for a particular block, the block's identifier is added to the read setup permission table. Other techniques for determining whether a specific memory block is fully utilized can be implemented in conjunction with ECC error counting and / or PE cycle counting, or separately.

[0161] In one embodiment of the disclosed technology, without using the aforementioned technique of using the first and second queues 1300, 1302, the read setting operation can be performed on multiple blocks identified in the read setting permission table. Alternatively, see see Figure 13 As described below, the read settings permission table can be integrated into operations using the first and second queues 1300 and 1302 to determine which blocks are candidate blocks for read settings operations.

[0162] Figure 13 This is a flowchart illustrating an embodiment of the disclosed technology, which describes the use of a read setting permission table to identify read candidate blocks of a flash memory and to perform read setting operations on the identified read candidate blocks.

[0163] Specifically, Figure 13 Drawing similar to Figure 9 Flowchart 1600 is a flowchart of 2000. The descriptions of operations 1701, 1702, 1704, 1706, 1708, and 1608 in flowchart 2000 are as follows: Figure 9 The operation is the same as in [the previous section]. Therefore, its explanation is omitted here.

[0164] exist Figure 13 Operation 2002 determines whether the read settings permission table contains the block identified at location n. Figure 12 Operations 1904 and 1906 describe adding a specific block to the read settings permission table based on block usage. If a block is identified in the read settings permission table, operation 1702 is performed to add the block's identifier to the read settings table. If no block is identified in the read settings permission table, operation 1704 is performed to check if block n is the last position in the second queue. Figure 13 The operation can be performed in Figure 12 Execute after the operation. See also Figure 12 The blocks discussed can be identified in the read settings permission table based on their usage, such as ECC error count, PE count, etc.

[0165] Figure 14 This is a simplified diagram illustrating a controller that sends a read setupburst command to a flash memory, according to an embodiment of the disclosed technology.

[0166] Specifically, Figure 14 A flash memory 2100 and a controller 2102 are illustrated. As shown, the flash memory 2100 contains multiple blocks, starting from block #00 and ending at block #n. As previously mentioned, each block contains multiple pages.

[0167] Controller 2102 can identify or obtain information for identifying the number of sequential read setup blocks 2104 and the address of the first read setup block 2106 in the sequence of sequential read setup blocks. (Sequential or non-sequential) read setup blocks can be identified as candidates for read setup operations, wherein the read setup operations use the techniques described herein, such as using first and second queues 1300, 1302, etc. Alternatively, read setup blocks can also be non-sequential memory blocks. The “number” of sequential read setup blocks represents the actual number of blocks in flash memory 2100 that are candidates for read setup operations and are arranged sequentially. Alternatively, controller 2102 can identify the first and last blocks in the sequence of sequential read setup blocks, or it can identify the addresses of the first and last blocks in the sequence of sequential read setup blocks.

[0168] The controller 2102 generates a read-setup burst command to identify (1) the address of a first block in a set of (sequential or non-sequential) read-setup blocks and (2) the number of candidate read-setup blocks for a read-setup operation, and provides the generated read-setup burst command to the flash memory 2100. The generated read-setup burst command may contain additional information, as described herein. Alternatively, the read-setup burst command may identify the first and last blocks in a sequence of sequential read-setup blocks, or it may identify the addresses of the first and last blocks in a sequence of sequential read-setup blocks.

[0169] like Figure 14 As shown, the identified sequence of sequential read setup blocks may include blocks #01 to #99 of flash memory 2100. In this example, a read setup burst command received by flash memory 2100 may identify the address of block #01, where block #01 is the first read setup block in the sequence of sequential read setup blocks. The read setup burst command may also indicate that there are 99 blocks in the sequence of sequential read setup blocks, or 99 blocks in the set of non-sequential read setup blocks.

[0170] In response to receiving a read setting burst command from controller 2102, or in response to decoding a read setting burst command, flash memory 2100 may then perform read operations on multiple read setting blocks in the read setting block set. Receiving and / or decoding a read setting burst command triggers a read setting burst operation on flash memory 2100, comprising performing read operations on multiple read setting blocks in the read setting block set.

[0171] Controller 2102 may be part of the host unit, as shown in [reference needed]. Figure 16The detailed discussion includes the possibility that the host device may be part of or separate from flash memory 2100. Controller 2102 may also be separate from the host device, and may be part of or separate from flash memory 2100. Controller 2102 may identify or manage the operation of identifying (sequential or non-sequential) read setting blocks by using, for example, first-level second queues 1300, 1302, or it may receive information from another device for identifying (sequential or non-sequential) read setting blocks. Controller 2102 may send a read setting table of candidate read setting blocks as part of or independently of a read setting burst command. Memory 2100 may receive, store, and maintain the read setting table. Furthermore, memory 2100 may utilize the read setting table to perform read setting operations on blocks identified in the read setting table. Furthermore, the blocks identified in the read setting table may include some or all of the blocks contained in any block table described herein, wherein any block table described herein includes read setting table 1800. The memory 2100 may perform read setting operations on the blocks identified in the read setting table.

[0172] Figure 15 This is a flowchart illustrating an embodiment of the disclosed technology, which describes the generation of a read setting burst command and the sending of the read setting burst command to a memory, wherein the memory performs a read setting operation according to the read setting burst command.

[0173] Specifically, Figure 15 A flowchart 2200 is illustrated, which includes various operations performed by the controller 2102 and the flash memory 2100. In one embodiment, at... Figure 15 Operations on the left (e.g., operations 2202, 2204, and 2206) can be executed by controller 2102, and in Figure 15 Operations on the right-hand side (e.g., operations 2208, 2210, 2212, 2214, 2216, and 2218) can be performed by flash memory 2100. However, the present disclosure is not limited to this. Figure 15 The operations described herein. For example. Figure 15 All operations can be performed by components of the memory 2100 itself.

[0174] In operation 2202, controller 2102 can generate and send read setting burst commands to flash memory 2100. See above. Figure 15 The discussion involved reading and setting burst commands to identify an address and a number.

[0175] After sending the read / setup burst command in operation 2202, controller 2102 may send a polling message to flash memory 2100. The polling message may request information about the status of the read / setup burst operation. The polling message may be sent after a preset time elapsed since the read / setup burst command was sent, or it may be sent immediately after the read / setup burst command is sent. Alternatively, the polling message may be sent together with the read / setup burst command.

[0176] In operation 2206, it is determined whether the controller 2102 has received a message from flash memory 2100 indicating that a read-setup burst operation has been completed. If the message has not yet been received, operation 2204 can be executed to send another polling message to flash memory 2100. If the message has been received from flash memory 2100, operation 2202 can be executed to generate and send another read-setup burst command to memory 2100. Operation 2204 can be executed selectively, and the controller 2102 may simply wait until the completion indication is received in operation 2206 before operation 2202 can be executed again. Alternatively, the controller 2102 may wait for a preset time length before operation 2202 can be executed again.

[0177] In response to receiving a read-setup burst command from controller 2102, flash memory 2100 may decode the read-setup burst command in operation 2208 and initiate a read-setup burst operation starting from the address of a first block (or the address of a page of the first block). In one embodiment, in operation 2208, a counter equivalent to the number identified in the read-setup burst command may be set, and a current block number may be set to identify the first read-setup block in the sequence of read-setup blocks. For example, if the read-setup burst command contains an address identifying block #01, then the current block number identifies block #01. If the read-setup burst command identifies 99 blocks in the sequence of read-setup blocks, then the counter is set to 99.

[0178] In optional operation 2210, it is determined whether the current block (identified by the current block number) is a bad block. In the example above, operation 2210 will be performed on block #01, which is identified based on the address in the read-set burst command. In operation 2210, a bad block can be identified from a list or using logic and / or circuitry. A block can be identified as a bad block based on its performance, usage, or other factors. If the current block (identified by the current block number) is not a bad block, operation 2212 is performed, executing a read-set operation on the current block. If the current block (identified by the current block number) is determined to be a bad block, the read-set operation is not performed on the current block (i.e., operation 2212 is skipped), and operation 2214 is performed to move to the next block (e.g., increment the current block number by 1) and adjust the counter (e.g., decrement the counter by 1).

[0179] Following the example above, operation 2210 determines whether block #01 is a corrupted block. If block #01 is not a corrupted block (i.e., it is an intact block), then operation 2212 is executed to perform a read setting operation on block #01.

[0180] In operation 2214, the block number is incremented by 1, thus identifying block #02 as the current block, where block #02 is the next block in the sequence of read and set blocks. In operation 2214, the counter is also decremented by 1, making the counter equal to 98. In operation 2214, if the current block number is identified as the last block in the sequence of read and set blocks, then the current block number does not need to be incremented. One way to determine whether the current block number is the last block in the sequence of read and set blocks is to use the value of the counter. For example, if the counter value in operation 2214 is 1 before decrementing, or if the counter value in operation 2214 is 0 after decrementing, then it can be determined that the current block is the last block in the sequence of read and set blocks, and the current block number does not need to be incremented.

[0181] After decrementing the counter by 1, operation 2216 is executed to determine if the counter equals 0. If the counter does not equal 0, operations 2210 and / or 2212 can be executed on the current block (note that the current block is a different block because the number used to identify the current block has been updated in operation 2214). The counter can also start from a specific number lower than the number identified in the read setting burst command and can be increased up to the number identified in the read setting burst command.

[0182] In the example above, the current block number currently identifies block #02, and the counter equals 98. Therefore, after determining in operation 2216 that the counter is not equal to 0, operation 2210 is executed to determine whether block #02 is a corrupted block. As mentioned above, operation 2210 can be executed selectively. Therefore, if operation 2210 is omitted, determining that the counter is not equal to 0 in operation 2214 could result in performing a read-set operation on block #02, which is currently identified as the current block, in operation 2212.

[0183] Operations 2210, 2212, 2214, and 2216 will continue to loop until the counter equals 0 (i.e., all blocks in the sequence of read-set blocks have been considered). In the example above, assuming no corrupted blocks are identified in operation 2210, these operations will continue until the counter decreases from 99 to 0, resulting in read-set operations being performed on blocks #01 through #99. In response to the counter reaching 0, operation 2218 can be executed, sending a message to controller 2102 indicating that the read-set burst operation has been completed. As mentioned earlier, this "complete" message can be used to allow controller 2102 to execute operation 2202.

[0184] Read setting blocks can be sequential or non-sequential and can be identified using a table, such as first-level second queues 1300, 1302, etc. For example, a read setting table of candidate read setting blocks can be maintained, and the read setting block set can contain candidate read setting blocks from the read setting table. It can be determined whether any candidate read setting blocks are arranged in the order of their addresses in memory. In response to the determination that candidate read setting blocks are arranged in sequence, the sequentially arranged candidate read setting blocks can be identified as multiple read setting blocks in the read setting block set, where read setting burst operations are performed on multiple read setting blocks in the read setting block set. Furthermore, the controller 2102 or the memory 2100 may identify a first set of candidate read setting blocks from the read setting table (wherein the first set contains two or more candidate read setting blocks arranged in the order of addresses in the memory), identify a second set of candidate read setting blocks from the read setting table (wherein the second set contains two or more candidate read setting blocks arranged in the order of addresses in the memory, and the second set contains candidate read setting blocks that are different from the candidate read setting blocks on the read setting table), determine that the second set of candidate read setting blocks contains more candidate read setting blocks than the first set of candidate read setting blocks, and identify the candidate read setting blocks from the second set as multiple read setting blocks of the read setting block set, wherein the read setting burst operation is performed on multiple read setting blocks of the read setting block set.

[0185] Figure 16This is a simplified diagram of a memory system including a flash memory device 2308 implemented on an integrated circuit and a host terminal 2302. The host terminal 2302 includes logic for issuing commands such as read commands and write commands with addresses and data to be written. In some embodiments, the host terminal can issue read-setup commands and read-setup burst commands to initiate read-setup operations on the memory device 2308. The memory device 2308 can be implemented on a single integrated circuit chip, a multichip module, or configured with multiple chips to meet specific needs.

[0186] The memory device 2308 in this example includes a memory cell array 2378 on an integrated circuit substrate. As described above, the memory cell array 2378 includes multiple blocks, and each block includes multiple sub-blocks. The memory cell array 2378 may be a NAND flash memory, implemented using two-dimensional or three-dimensional array technology.

[0187] In various embodiments, the memory device 2308 may have single-level cells (SLC) or multiple-level cells (e.g., multiple-level cells (MLC), triple-level cells (TLC), or (XLC)) storing more than one bit per cell.

[0188] The memory device 2308 includes a memory cell array 2378, which may be a NAND flash memory implemented by three-dimensional array technology and has one or more planes, each plane having multiple blocks, and each block having multiple sub-blocks.

[0189] A word-line decoder 2376A is coupled to multiple word lines 2377 in the memory cell array 2378 via a word-line driver circuit 2376B. A select-line / ground select-line (SSL / GSL) decoder 2378A is coupled to the string select gate in the array near the bit-line side (SSL) and common-source side (GSL) via a string select line / ground select-line (SSL / GSL) driver circuit 2378B and via string select lines and ground select lines 2379. A page buffer circuit 2338 is coupled to bit lines 2366 in the memory cell array 2378 via a bit-line driver circuit 2348. In some embodiments, row decoding circuitry may be included for transferring data from the bit-line driver to selected bit lines. The page buffer circuit 2338 may store multiple data pages for defining a data pattern in a page write operation and may include sensing circuitry for read and verification operations.

[0190] The bit lines of a memory cell array may include global bit lines (GBLs) and local bit lines. Bit lines are typically contained within a higher pattern layer and traverse multiple memory cell blocks within the array. Global bit lines are connected to the NAND string to allow current to flow in and out of the bit lines, and are subsequently connected to the bit line driver circuit 2348 and the page buffer circuit 2338. Similarly, word lines may include global word lines and local word lines, corresponding to the support circuitry in the word line driver 2376B.

[0191] During sensing operations, sensing data from the page buffer circuit 2338 is supplied to the cache circuit 2328 via the second data line in the bus system 2326. The cache circuit 2328 is sequentially coupled to the input / output circuit 2318 via a data path link 2316. In this example, input data is provided to the cache circuit 2328 via link 2316 and to the page buffer circuit 2338 via the bus system 2326 to support write operations. Furthermore, the cache circuit 2328 may include a candidate table buffer 2384 to store and maintain a read setting table of candidate read setting blocks. The read setting table and read setting burst commands can be received from the host terminal 2302. Additionally, the memory 2308 can utilize the read setting table to perform read setting operations on blocks identified in the read setting table.

[0192] Input / output circuitry 2318 is connected via link 2314 (containing input / output pads) and provides a destination for communication paths of data, addresses, and commands, with the destination located external to memory device 2308. In this example, host side 2302 is included. Input / output circuitry 2318 provides a communication path via link 2316 to cache circuitry 2328 for supporting memory operations. Cache circuitry 2328 communicates with page buffer circuitry 2338 (e.g., using bus system 2326) via data flow communication.

[0193] Control circuitry 2334 is connected to input / output circuitry 2318 and includes command decoding logic, an address counter, a state machine, timing circuitry, and other logic circuitry controlling various memory operations, including write, read, and erase operations on memory cell array 2378. Control circuit signals are distributed to circuitry within the memory device, as indicated by arrows 2345 and 2346, to support circuitry operations. Control circuitry 2334 may include address buffers to transfer addresses to memory device 2308 as needed; in this figure, this includes transfers to cache circuitry 2328 and to page buffer circuitry 2338, word line decoder 2376A, and serial select line / ground select line decoder 2378A via link 2344.

[0194] exist Figure 16 In the example, control circuitry 2334 includes control logic circuitry, which includes modules for implementing one or more bias arrangement state machines to control the application of bias voltages generated or provided by one or more voltage sources in block 2364, including read set, read, erase, verify, and write voltages, including precharge voltages, channel voltages, and other bias voltages as described in this disclosure, to word line driver circuitry 2376B and bit line driver circuitry 2348 to perform a set of selectable write, read set, and read operations. Bias voltages, as indicated by arrow 2365, are applied to components of memory device 2308 to support operation as needed.

[0195] Control circuitry 2334 may include modules known in the art, implemented using a dedicated logic circuitry system including a state machine. In another embodiment, control circuitry 2334 may include modules implemented using a general-purpose processor implemented on the same integrated circuit, which executes a computer program to control the operation of memory device 2308. In yet another embodiment, modules in control circuitry 2334 may be implemented using a combination of dedicated logic circuitry systems and general-purpose processors.

[0196] Flash memory cell array 2378 may include a structure that allows each memory cell to store multiple bits of floating gate memory cells or dielectric charge trapping memory cells. This is achieved by constructing multiple write layers, each corresponding to the amount of stored charge at the threshold voltage Vt used to construct the memory cell. This technique can be used in flash memories where one memory cell stores one bit, as well as other memory technologies for storing multiple bits in one memory cell and storing one bit in one memory cell. In other embodiments, the memory cell may include programmable resistive memory cells, phase-change memory cells, and other types of non-volatile and volatile memory cell technologies.

[0197] In the illustrated embodiment, host terminal 2302 is coupled to link 2314 on memory device 2308 and other control terminals (not shown), such as chip select terminals, and can provide commands or instructions to memory device 2308. In some embodiments, host terminal 2302 may use shared address and data lines and is coupled to memory device 2308 using serial bus technology. Host terminal 2302 may include a general-purpose processor, a special-purpose processor, a processor used as a memory controller, or other processors using memory device 2308. All or part of host terminal 2302 may be implemented on the integrated circuit where the memory resides. The memory controller may execute... Figures 6 to 15 Some or all of the operations described above. The host side 2302 (e.g., a memory controller) may further include error correction code (ECC) circuitry 2382. Error correction code circuitry 2382 can be used to perform, for example... Figure 12 The operation described above. Specifically, for example, the error correction code circuit 2382 can be used (e.g., using error correction code information) to identify memory blocks where multiple errors have been detected, wherein the number of multiple errors is greater than (or equal to) an error correction code threshold. Alternatively, the error correction code circuit 2382 can be used to determine whether multiple errors greater than (or equal to) an error correction code threshold have been detected on a memory block.

[0198] The host 2302 can update data stored in memory based on requests from applications. Typically, the host 2302 may include programs that perform memory management functions, which in some embodiments include functions for controlling or supporting the read setting operations described in this disclosure. Other memory management functions may include, for example, managing first and second queues, identifying read setting candidates, managing timestamps, managing read setting tables and read setting permission tables, and managing information and associated operations and read setting burst commands related to determining read setting candidates as described in this disclosure. Additional memory management functions may include wear leveling, bad block recovery, power loss recovery, garbage collection, error correction, etc. The host 2302 may also include applications, file systems, flash translation layer programs, and other components that can generate data state information stored in memory, wherein the state information includes issuing commands for writing data with addresses and data to be written.

[0199] exist Figure 16In the example shown, the memory device includes a set of state buffers 2335 to store multiple parameters for read-setup operations. These parameters may define the voltage level to be applied, whether to turn on or off the string select and ground select gates, and pulse durations, etc. These parameters may also include a starting plane and block address and a range of block addresses (or addresses of other read-setup units) as the body of a particular read-setup operation. These parameters may include multiple indicators to simultaneously activate planes, blocks within planes, and sub-blocks within blocks during a read-setup operation. Some or all of these parameters may be provided by read-setup commands and / or read-setup burst commands and may be stored on-chip as configuration data.

[0200] The host device 2302 (e.g., a memory controller) may also include a first queue 1300, a second queue 1302, a read setting table 1800, and a read setting permission table 2380. The host device 2302 may implement the first queue 1300, the second queue 1302, the read setting table 1800, and the read setting permission table 2380 in various ways as described in this disclosure. Alternatively, the memory device may include some or all of the first queue 1300, the second queue 1302, the read setting table 1800, the read setting permission table 2380, and the control circuitry 2334, and may utilize some or all of the first queue 1300, the second queue 1302, the read setting table 1800, and the read setting permission table 2380, together with the read setting parameter 2335, to perform the read setting operation as described in this disclosure.

[0201] A state machine on the memory device can access read setup parameters and perform read setup operations, including address generation and applying bias voltage to the memory cell array to maintain the read-ready state of the entire memory. This operation can be contained within a block pattern in one or more planes where read setup operations can be performed simultaneously. This operation can be configured to traverse or partially traverse the array as background operation without external control. This operation can be configured to operate in response to read setup commands and / or read setup burst commands. The read setup operation carries read setup parameters and identifies the segment in the array to be operated on. Read setup commands and / or read setup burst commands can be generated by, for example, a memory controller on the host side. The memory controller monitors block status, such as identifying read setup candidate blocks and sending commands for identifying read setup candidate blocks in read setup operations, and identifying cold blocks as stale blocks in wear-averaging operations, and can send commands to identify stale blocks, or can send commands during a time interval when the memory cell array is idle or about to be idle. A state machine can set a ready / busy pin on the memory device to indicate to the control program on the memory controller to coordinate read setting operations.

[0202] The techniques described in this disclosure can perform read-set operations at high speed and more frequently than existing technologies, thereby improving the memory cell operation window by maintaining the memory cell at a threshold set during write operations. These techniques are particularly beneficial for large, high-density memory systems. For example, if a block contains multiple sub-blocks, all sub-blocks in a block can perform read-set operations simultaneously to improve operation speed. Furthermore, if a memory plane contains multiple blocks, multiple blocks can perform read-set operations simultaneously to improve operation speed. Moreover, if a memory device has multiple planes, blocks or sub-blocks in multiple planes can perform read-set operations simultaneously to improve operation speed.

[0203] Although the present disclosure has been described above with reference to embodiments, it is not intended to limit the present disclosure. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the scope of protection of the appended claims.

Claims

1. A memory, comprising: Include: A storage cell array containing multiple blocks; and Multiple control circuits, including logic, to perform the following operations: Decode a read setting burst command to identify the address of a first read setting block in a set of read setting blocks and the number of read setting blocks that are candidates for read setting operations; as well as In response to the decoding of the read setting burst command, a read setting burst operation is performed in multiple read setting blocks of the read setting block set; The read setup burst operation includes applying a bias voltage to the memory cell array to maintain the read-ready state of the memory.

2. The memory of claim 1, wherein, This set of read settings blocks consists of multiple sequential read settings blocks.

3. The memory of claim 2, wherein, This number represents the number of sequential read setup blocks, and the read setup burst operation includes: The read setting operation is performed on the sequential read setting blocks of the set of read setting blocks starting from the first read setting block, wherein the first read setting block is identified by the address in the read setting burst command; as well as The read setup operation is performed continuously in a sequential order of these sequential read setup blocks until the number of sequential read setup blocks for which read setup operations have been performed equals the number identified in the read setup burst command.

4. The memory of claim 3, wherein, This read setup burst operation also includes: Before performing a read setting operation on each of the sequential read setting blocks, determine whether each sequential read setting block is a corrupted block. as well as If the sequential read setting block is determined to be a corrupt block, the read setting operation for that sequential read setting block is skipped, and the read setting burst operation is performed on the next read setting block in the sequence in the order of the sequence.

5. The memory of claim 2, wherein, This number represents the number of sequential read setup blocks, and the read setup burst operation includes: Based on the address in the received read settings burst command, the first read settings block is identified as a current read settings block; Set a counter equal to the number of sequential read setup blocks identified in the read setup burst command, wherein the number of sequential read setup blocks is greater than 1; and Before the counter equals 0, perform the following operations: Determine whether the currently read setting block is a corrupted block; If the current read settings block is not a corrupted block, perform a read settings operation on the current read settings block; If the current read setting block is not the last block in the sequential read setting blocks, the current read setting block is identified as the next block in the sequence of these sequential read setting blocks; as well as Decrease the counter by 1.

6. The memory of claim 1, wherein, This operation also includes: A read setting table that receives multiple candidate read setting blocks; and In a candidate table buffer, the received candidate read setting blocks are stored and maintained in the read setting table, wherein the set of read setting blocks identifies one or more of the candidate read setting blocks in the read setting table.

7. The memory of claim 6, wherein, This operation also includes: Determine whether any of the candidate read configuration blocks is arranged in the sequence order addressed by the memory; and If the candidate read setting blocks are arranged in sequence order, the candidate read setting blocks arranged in sequence order are identified as the read setting blocks of the read setting block set, wherein the read setting burst operation is performed on the read setting blocks of the read setting block set.

8. The memory of claim 6, wherein, This operation also includes: A first set of candidate read setting blocks is identified from the read setting table, wherein the first set contains two or more candidate read setting blocks arranged in the sequence order of memory addressing; A second set of candidate read setting blocks is identified from the read setting table, wherein the second set contains two or more candidate read setting blocks arranged in sequence order of memory addressing, and the candidate read setting blocks in the second set are different from the candidate read setting blocks in the first set; Determine that there are more candidate read setting blocks in the second set than in the first set; as well as The candidate read setting blocks in the second set are identified as the read setting blocks of the read setting block set, wherein the read setting burst operation is performed on the read setting blocks of the read setting block set.

9. The memory of claim 6, wherein, The read settings table is generated from a least recently used (LRU) queue, which identifies the blocks in the memory based on their usage.

10. The memory of claim 9, wherein, The read settings table is generated to identify candidate read settings blocks from the least recently used (LRU) queue, which has not been accessed for a period exceeding a preset threshold.

11. A method for executing a read setup burst operation, suitable for a memory, wherein, The memory includes a storage cell array comprising multiple blocks, characterized in that the method comprises: Decode a read-setup burst command to identify the address of a first read-setup block in a set of read-setup blocks and the number of read-setup blocks that are candidates for the read-setup operation; and In response to the decoding of the read setting burst command, a read setting burst operation is performed in multiple read setting blocks of the read setting block set; The read setup burst operation includes applying a bias voltage to the memory cell array to maintain the read-ready state of the memory.

12. A memory operation method, comprising: The method includes: Identify a set of read setting blocks in a memory as a candidate for a read setting operation; Generate a read setting burst command to identify the address of a first read setting block in the set of read setting blocks and the number of read setting blocks that are candidates for read setting operation; The generated read setting burst command is sent to the memory to initiate the execution of a read setting burst operation on multiple read setting blocks in the read setting block set; The read setup burst operation includes applying a bias voltage to the memory cell array to maintain the read-ready state of the memory.

13. The method of claim 12, wherein, The method also includes: Send a polling message to the memory to request information about the status of the read setup burst operation; and The memory receives a response message indicating that the read setting burst operation has not been completed.

14. The method of claim 12, wherein, The method also includes: Send a polling message to the memory to request information about the status of the read setting burst operation; The memory receives a response message indicating that the read setting burst operation is complete; and If a response is received indicating that the read-setup burst operation is complete, the next read-setup burst command is generated and sent to the memory.

15. The method of claim 12, wherein, The method also includes: Send a polling message to the memory to request information about the status of the read setup burst operation; and If no response is received from the memory within a preset period, it is determined that the read setting burst operation has not been completed.

16. The method of claim 12, wherein, This set of read settings blocks consists of multiple sequential read settings blocks.

17. The method of claim 16, wherein, This number represents the number of sequential read setup blocks, and the read setup burst operation includes: The read setting operation is performed on the sequential read setting blocks starting from the first read setting block, wherein the first read setting block is identified by the address in the read setting burst command; as well as The read setup operation is performed continuously in a sequential order of these sequential read setup blocks until the number of sequential read setup blocks for which read setup operations have been performed equals the number identified in the read setup burst command.

18. The method of claim 17, wherein, This read setup burst operation also includes: Before performing a read setting operation on each of the sequential read setting blocks, determine whether each sequential read setting block is a corrupted block. as well as If the sequential read setting block is determined to be a corrupt block, the read setting operation of the sequential read setting block is skipped, and the read setting burst operation is performed on the next read setting block in the sequence in the order of the sequence.

19. The method of claim 12, wherein, The method also includes: Maintain a read setting table containing multiple candidate read setting blocks in the memory, wherein the set of read setting blocks contains candidate read setting blocks in the read setting table.

20. The method of claim 19, wherein, The method also includes: Determine whether any candidate read setting block is arranged in the sequence order addressed by the memory; and If candidate read setting blocks are arranged in sequence order, the candidate read setting blocks arranged in sequence order are identified as those read setting blocks in the set of read setting blocks, wherein the read setting burst operation is performed on those read setting blocks in the set of read setting blocks.

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