Architecture and method for NAND memory programming

Abstract

In a method of programming a storage device, inhibit information is stored to a first latch and a second latch. A first state program voltage is applied to a data line of a storage element of a memory device, thereby programming the storage element to a first state. A first state verify voltage is applied to the data line of the storage element, thereby performing a first state verify operation on the storage element. The first state verify operation verifies a first state threshold voltage of the storage element based on a first target value, and also generates failure mode data for the first state verify operation. The failure mode data is then stored to the second latch. In addition, a first level adjusted verify voltage is applied to the data line of a portion of the storage elements that failed the first level verify operation, thereby performing a first level adjusted verify operation.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a memory device and its operating method. Background Technology

[0002] Flash memory devices have recently experienced rapid development. They can retain stored data for extended periods without the application of voltage. Furthermore, flash memory devices offer relatively high read speeds and are easy to erase and rewrite. Consequently, they are widely used in microcomputers, automated control systems, and other applications. To improve the bit density and reduce the bit cost of flash memory devices, 3D NAND flash memory devices have been developed.

[0003] As the performance and complexity of electronic systems increase, the demand for additional memory within these systems also rises. However, to continuously reduce system costs, the number of components must be kept to a minimum. This can be achieved by utilizing techniques such as triple-cell (TLC) to increase the storage density of integrated circuits. For example, TLC NAND flash memory is a highly cost-effective non-volatile memory. Triple-cell utilizes the analog properties of traditional flash memory cells by assigning bit patterns to specific threshold voltage (Vt) ranges stored on the cell. This technique allows three bits to be stored per cell, depending on the number of voltage ranges allocated to the cell and the stability of those voltage ranges during the cell's operational lifetime. Summary of the Invention

[0004] In this disclosure, embodiments relate to apparatus and methods for three-layer cell programming of a 3D-NAND storage device based on an algorithm that enables non-destructive mode programming in a page cache with a reduced number of latches.

[0005] According to one aspect of this disclosure, a method for programming a storage device is provided, wherein the storage device may include a cache structure and storage cells. In this method, prohibition information may be stored in a first latch and a second latch of the cache structure. A first state programming voltage may be applied to the data lines of the storage cells to program the storage cells to a first state. A first state verification voltage may be applied to the data lines of the storage cells to perform a first state verification operation on the storage cells. The first state verification operation may verify a first state threshold voltage of the storage cells based on a first target value, and also generates failure mode data for the first state verification operation. The failure mode data may be stored in a second latch and indicates a first portion of storage cells that passed the first state verification operation and a second portion of storage cells that failed the first state verification operation. Furthermore, an adjusted first state verification voltage may be applied to the data lines of the second portion of storage cells that failed the first state verification operation to perform an adjusted first state verification operation on the second portion of storage cells. The adjusted first state verification operation may verify the first state threshold voltage of the second portion of storage cells to which the adjusted first state verification voltage was applied.

[0006] In this method, a first state programming voltage can be applied to the data line of the memory cell based on the fact that the counter value of the verification state counter is less than a first value, thereby programming the memory cell to the first state. The first value of the verification state counter can be eight, and the counter value of the verification state counter can indicate which state of the memory cell is encoded.

[0007] To apply the first-state programming voltage to the bit line of the memory cell, the initial first-state programming voltage can be determined based on the disable information and counter value stored in the first latch. Initial adjusted verification information (or 3BL information) in the first latch can be used instead of the initial information. The first-state programming voltage can be determined based on the initial first-state programming voltage and this initial adjusted verification information. The initial adjusted verification information can indicate which memory cells received the previous adjusted verification voltage in a previous adjusted verification operation prior to the adjusted first-state verification operation.

[0008] In some embodiments, before applying the first state verification voltage, the prohibition information in the first latch can be reversed to form an inverted prohibition information, wherein the inverted prohibition information can indicate the unverified state of the memory cell, including the first state and the remaining states after the first state.

[0009] In some embodiments, when storing prohibition information to the first and second latches of the cache structure, the next page information of the storage unit can be stored to the third latch of the cache structure, the middle page information of the storage unit can be stored to the fourth latch of the cache structure, and the previous page information of the storage unit can be stored to the fifth latch of the cache structure.

[0010] In this method, after the first state verification operation is performed, first state failure verification information can be added to the first latch, wherein the first state failure verification information can indicate the second part of the storage unit that failed the first state verification operation.

[0011] In this method, after performing the adjusted first state verification operation, the prohibition information and the adjusted first state verification information can be stored in the second latch, wherein the adjusted first state verification information indicates which storage cells received the adjusted first state verification voltage.

[0012] In this method, after performing the first state verification operation, the counter value of the verification state counter can be increased in response to the failure rate of the failure mode data being equal to or less than the second value.

[0013] In this method, after performing an adjusted first state verification operation, a second state verification voltage can be applied to the data line of the memory cell, and a second state verification operation can be performed on the memory cell, thereby verifying the second state threshold voltage of the memory cell based on a second target value. Furthermore, the adjusted second state verification voltage can be applied to the data lines of a portion of the memory cells that failed the second state verification operation, thereby enabling the adjusted second state verification operation to be performed on that portion of the memory cells that failed the second state verification operation.

[0014] Furthermore, second-state failure verification information can be added to the first latch. This second-state failure verification information can be obtained from the second-state verification operation and indicates the memory cells that failed the second-state verification operation. Additionally, adjusted second-state verification information can be added to the second latch, wherein the adjusted second-state verification information indicates which memory cells received the adjusted second-state verification voltage.

[0015] Next, the prohibition information, the first state verification information, and the second state verification information are stored in the first latch. The first state verification information is obtained from the first state verification operation and indicates a first portion of the storage units that passed the first state verification operation. The second state verification information indicates a portion of the storage units that passed the second state verification operation. A determination can be made to determine whether the counter value of the verification level counter is greater than or equal to a first value. In response to determining that the counter value of the verification state counter is less than the first value, in one embodiment, the storage units can be programmed and verified for the first state while the counter value of the verification state counter remains unchanged. In another embodiment, the storage units can be programmed and verified for subsequent states of the first state in response to the counter value of the verification state counter increasing by one.

[0016] In this method, to program the memory cell for a subsequent state of the first state, an initial subsequent state programming voltage can be determined based on the prohibition information stored in the first latch. Next, adjusted verification information, including adjusted first state verification information and adjusted second state verification information, is used instead of the prohibition information in the first latch. The subsequent state programming voltage can be determined based on the initial subsequent state programming voltage and the adjusted verification information. The subsequent state programming voltage can then be further applied to the data lines of the memory cell, thereby programming the memory cell in that subsequent state to the first state.

[0017] In this method, to verify the memory cell for subsequent states of the first state, a subsequent state verification voltage can be applied to the data line of the memory cell, thereby performing a subsequent state verification operation on the memory cell. The subsequent state verification operation can verify the subsequent state threshold voltage of the memory cell based on a subsequent target value, and also generates failure mode data for the subsequent state verification operation. The failure mode data can be stored in a second latch, indicating the first portion of memory cells that passed the subsequent state verification operation and the second portion of memory cells that failed the subsequent state verification. Furthermore, a subsequent state adjusted verification voltage can be applied to the data line of the second portion of memory cells that failed the subsequent state verification operation, thereby performing a subsequent state adjusted verification operation on the second portion of memory cells, wherein the subsequent state adjusted verification operation can verify the subsequent state threshold voltage of the second portion of memory cells to which the subsequent state adjusted verification voltage was applied.

[0018] According to another aspect of this disclosure, a storage device is provided. The storage device may include a plurality of storage cells and a cache structure including data line biasing circuitry and page caches. The data line biasing circuitry may be coupled to a data line of the storage cell and configured to apply a bias voltage to the data line. The page cache may include a first latch and a second latch. Each of the data line biasing circuits may be coupled to a corresponding data line, and each of the page caches may include a corresponding first latch and a corresponding second latch. The storage device may further include control circuitry coupled to the data line of the storage cell, the first latch, and the second latch. The control circuitry may be configured to store inhibit information in the first latch and the second latch. The control circuitry may be configured to apply a first state programming voltage to the data line of the storage cell via the data line biasing circuitry, thereby programming the storage cell to a first state.

[0019] The control circuit can also be configured to apply a first state verification voltage to the data line of the memory cell via a data line bias circuit, thereby performing a first state verification operation on the memory cell. The first state verification operation can verify the first state threshold voltage of the memory cell based on a first target value and generate failure mode data for the first state verification operation. This failure mode data can be stored in a second latch and indicates a first portion of memory cells that passed the first state verification operation and a second portion of memory cells that failed the first state verification operation. The control circuit can also be configured to apply an adjusted first state verification voltage to the data line of the second portion of memory cells that failed the first state verification operation via a data line bias circuit, thereby performing an adjusted first state verification operation on the second portion of memory cells. The adjusted first state verification operation can verify the first state threshold voltage of the second portion of memory cells to which the adjusted first state verification voltage was applied.

[0020] In some embodiments, the page cache may further include a third latch configured to store next page information of the storage unit, a fourth latch configured to store middle page information of the storage unit, and a fifth latch configured to store previous page information of the storage unit. Each of the page caches may include a corresponding third latch, a corresponding fourth latch, and a corresponding fifth latch.

[0021] In some embodiments, the control circuitry may include a verification state counter configured to increment its counter value in response to a failure rate of the failure mode data being equal to or less than a second value. The counter value of the verification state counter may indicate which state the memory cell has been programmed into.

[0022] The control circuit can be further configured to apply a first state programming voltage to the data line of the memory cell based on the fact that the counter value of the verification state counter is less than a first value, thereby programming the memory cell to the first state.

[0023] To program a memory cell to a first level, the control circuit determines an initial first-state programming voltage based on a disable message and a counter value stored in a first latch. The control circuit may replace the disable message with initial adjusted verification information from the first latch and determine the first-state programming voltage based on the initial adjusted verification voltage and the initial adjusted verification information. The initial adjusted verification information may indicate which memory cells received a previous adjusted verification voltage in a previous adjusted verification operation prior to the adjusted first-state verification operation. The control circuit may further apply the first-state programming voltage to the data lines of the memory cells via a data line bias circuit, thereby programming the memory cells to the first state.

[0024] In some embodiments, the control circuit can invert the disable information in the first latch, wherein the inverted disable information indicates an unverified state of the memory cell, including a first state and the remaining states after the first state. Therefore, the control circuit can apply a first state verification voltage to the data line of the memory cell via a data line bias circuit to perform a first state verification operation, wherein the first state verification voltage can be determined based on the inverted disable information stored in the first latch.

[0025] The cache structure may further include verification circuitry, wherein each of the verification circuits is coupled to a corresponding data line, a corresponding first latch, and a corresponding second latch. The verification circuitry can be configured to read a memory cell to which a first state verification voltage has been applied to verify whether the first state threshold voltage of the memory cell conforms to a first target value. Furthermore, failure mode data of the first state verification operation can be stored in the second latch via the verification circuitry. Attached Figure Description

[0026] Various aspects of the invention can be understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be increased or decreased.

[0027] Figure 1 This is a schematic diagram of a 3D-NAND storage device according to an exemplary embodiment of the present disclosure.

[0028] Figure 2 This is a cross-sectional view of a 3D-NAND storage device according to an exemplary embodiment of the present disclosure.

[0029] Figure 3 This is a schematic diagram of a NAND memory cell string according to an exemplary embodiment of the present disclosure.

[0030] Figure 4 This is a schematic diagram of data storage in a three-layer cell (TLC) of a 3D-NAND device according to an exemplary embodiment of the present disclosure.

[0031] Figure 5 This is an exemplary block diagram of a 3D-NAND circuit according to an exemplary embodiment of the present disclosure.

[0032] Figure 6 This is a flowchart of a method for memory programming according to an exemplary embodiment of the present disclosure.

[0033] Figure 7-13 This is a schematic diagram of various latching states during memory programming according to exemplary embodiments of the present disclosure.

[0034] Figure 14 This is a block diagram of an electronic system according to exemplary embodiments of the present disclosure. Detailed Implementation

[0035] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to constitute limitation. For example, the description of forming a first feature on or above a second feature in the following description may include embodiments where the first and second features can be in direct contact, and may also include embodiments where an additional feature can be formed between the first and second features so that the first and second features do not need to be in direct contact. Furthermore, numbers and / or letters used as reference numerals may be repeated in various examples in this disclosure. Such repetition is for the purpose of simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0036] Furthermore, for ease of explanation, spatially relative terms such as "below," "below," "under," "above," and "above" may be used to describe the relationship of one element or feature to other elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation other than those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0037] A 3D-NAND device may include multiple planes. Each of these planes may include multiple blocks. Figure 1This is an exemplary embodiment of the 3D-NAND device 100 (or device 100). Figure 1 As shown, device 100 may include planes 102 and 104. Each of planes 102 and 104 may include two corresponding blocks. For example, plane 102 may include two blocks 106 and 108, and plane 104 may include two blocks 110 and 112. Furthermore, each of these blocks may include a plurality of memory cell strings, in which memory cells are sequentially connected in series on the substrate along the height direction of device 100. It should be noted that... Figure 1 For illustrative purposes only, device 100 may include any number of planes, and each of the planes may include any number of blocks depending on the device design. In device 100, each plane may be coupled to a corresponding cache structure, such as a dynamic data cache (DDC) or a static page cache (SPB). For example, block 106 may be coupled to cache structure 114, and block 108 may be coupled to cache structure 116. The cache structure may include a sense amplifier coupled to a bit line and configured to sense signals during operation of the 3D-NAND device 100. The cache structure may include multiple page caches. Each page cache may be coupled to a corresponding bit line and include multiple latches (or latch structures). The page caches are configured to temporarily hold data while the 3D-NAND device 100 is operating. For example, when the memory cells of the 3D-NAND device are three-level cells (TLC), each page cache may include six latches. Device 100 may also include peripheral circuitry 122, which may include a decoder structure, a driver structure, a charging structure, and other operational storage unit structures.

[0038] In device 100, each of the blocks may include a stepped region and an array region formed in a stack of word line layers and insulating layers. Figure 2 This is an exemplary embodiment of block 106 of device 100. Figure 2As shown, block 106 may include array region 200A and stepped regions 200B-200C disposed in dielectric layer 24. Array region 200A may be disposed between stepped regions 200B-200C and formed on substrate 10 within a stack consisting of alternating word line layers 12a-12p and insulating layers 14a-14q. Word line layers 12a-12p may include one or more bottom select gate (BSG) layers, gate layers (or word line layers), and one or more top select gate (TSG) layers disposed sequentially on substrate 10. For example, word line layers 12o-12p may be BSG layers in device 100, and word line layers 12a-12b may be TSG layers in device 100. Array region 200A may include a plurality of channel structures 18. Each of the channel structures 18 may include a corresponding top channel contact 19 and a corresponding bottom channel contact 21. Each of the channel structures 18 can extend through the stack and can be coupled to word line layers 12a-12p to form a corresponding vertical NAND memory cell string. The vertical NAND memory cell string may include one or more bottom select transistors (BSTs), multiple memory cells (MCs), and one or more top select transistors (TSTs) sequentially connected in series on the substrate 10 along the height direction (e.g., the Z direction) of the substrate. The one or more BSTs may be formed by the channel structure and the one or more BSG layers, the MCs may be formed by the channel structure and the word line layers, and the one or more TSTs may be formed by the channel structure and the one or more TSG layers.

[0039] It should be noted that, in order to more clearly illustrate the structural features of device 100, Figure 2 In the process, images from different cross-sections were stitched together. Figure 2 The cross-sectional orientation of the structure in each dashed segment is shown by the coordinate axes in the dashed segment; where the Z-axis represents the stacking direction of word line layers 12a-12p and insulating layers 14a-14q; the X-axis and Y-axis are perpendicular to each other and both perpendicular to the Z-axis.

[0040] In device 100, each memory cell may store one or more logic bits, depending on the device design. For example, a memory cell may be a single-level cell (SLC), a multi-level cell (MLC), or a three-level cell (TLC). Accordingly, each memory cell may store one, two, or three logic bits.

[0041] Still referencing Figure 2Word line layers 12a-12p can be formed in a stepped configuration within stepped regions 200B-200C, and multiple word line contacts 22 coupled to word line layers 12a-12p can be formed along the height direction. Therefore, a gate voltage can be applied to the gate of the memory cell through the word line contacts 22 coupled to word line layers 12a-12p.

[0042] Furthermore, each of the channel structures can be further coupled to a corresponding bit line (or bit line structure). In some embodiments, the bit line can be connected to the top channel contact 19 of the channel structure 18 and configured to apply a bias voltage when operating the channel structure (such as programming, erasing, or reading the channel structure). Device 100 may have multiple slit structures (or gate line slit structures). For example, in Figure 2 It includes two slit structures 20a-20b. Slit structures 20a-20b can be made of conductive material and are located on the array common source (ACS) region 16 to serve as a contact. The ACS region is formed within the substrate 10 to serve as the common source of the device 100.

[0043] Figure 3 This is a schematic diagram of a NAND memory cell string (or string) 300 that can be formed in device 100. For example... Figure 3 As shown, string 300 may include a bottom select transistor (BST) 302, a plurality of memory cells (MC) 304, and a top select transistor (TST) 306 sequentially connected in series on substrate 10 along the height direction (Z direction) of the substrate. String 300 may be coupled to bit line 308 via the drain terminal of TST 306 and to ACS 310 via the source terminal of BST 302. During operation of device 100, appropriate voltages may be applied to bit line 308, to the gate of TST 306 via TSG layer, to the gate of MC 304 via WL layer, to the gate of BST 302 via BSG layer, and to ACS 310 via slit structures (e.g., 20a or 20b).

[0044] As mentioned above, a storage unit can be a single-level unit, a multi-level unit, a three-level unit, or a four-level unit capable of storing a single logical bit, two logical bits, three logical bits, or four logical bits respectively. Figure 4 This is a schematic diagram of data storage in a three-layer cell (TLC) of a 3D-NAND device. For example... Figure 4As shown, a TLC can have eight threshold voltages Vt0-Vt7 (or eight levels LV0-LV7), and each of these eight threshold voltages Vt0-Vt7 can represent three corresponding logic bits. For example, the first threshold voltage (or first level LV0) Vt0 corresponds to logic bit 000, and the second threshold voltage (or second level LV1) Vt1 corresponds to logic bit 100. Therefore, by adjusting the threshold voltages of the TLC to the target value (or target threshold voltage), the TLC can be programmed with (or written with) the corresponding logic bits. When the programming operation of the TLC is completed, the subsequent verification operation can be performed to verify whether the threshold voltages of the TLC meet the target value. The logic bits stored in the TLC can be further divided into three logic pages, namely the next page, the middle page, and the previous page. For example, the logic bit 100 of the second level LV1 of the TLC can be further stored in the next page, the middle page, and the previous page, where logic bit 1 can be stored in the previous page, the first logic bit 0 can be stored in the middle page, and the second logic bit 0 can be stored in the next page. The information in each of these logical pages (e.g., next page information, middle page information, and previous page information) can represent a corresponding entity, such as a song or an image. In some embodiments, the information in each logical page can be temporarily stored in a corresponding latch during programming operations.

[0045] When programming a 3D-NAND device according to the relevant methods, the raw data (or processed data) can be stored using three latches in the page buffer throughout the programming operation. Additionally, a specific latch (also called a disable latch) can be reserved to store disable information, a latch can be used for sensing / programming, and a latch can be applied to store 3BL (3-bit line) information. In this disclosure, a sensing scheme called non-disabled verification is provided for programming operations on 3D-NAND devices. In non-disabled verification, a page buffer including five latches can be applied. Accordingly, the number of latches can be reduced, for example, to six latches used in the relevant methods. Furthermore, in non-disabled verification, fewer page buffer operations can be applied when switching verification states.

[0046] Figure 5 This is an exemplary block diagram of circuit 500 used in programming operations. (Example...) Figure 5As shown, circuit 500 may include page cache 500A. Page cache 500A may include a DS latch (or first latch) 502 configured to store prohibition information and verification information from a verification operation, a DL latch (or second latch) 504 configured to store prohibition information and 3BL information (or adjusted verification information from an adjusted verification operation), a D1 latch (or third latch) 506 configured to store next page information of each memory cell during a programming operation, a D2 latch (or fourth latch) 508 configured to store middle page information of each memory cell, and a DC latch (or fifth latch) 510 configured to store previous page information of each memory cell. The DS latch 502, DL latch 504, D1 latch 506, D2 latch 508 and DC latch 510 may be further coupled to each other and share data. In some embodiments, the latches in the page cache 500A may be formed by cross-coupled logic inverters.

[0047] Circuit 500 may further include a bit line (BL) bias circuit 512 coupled to DS latch 502. BL bias circuit 512 may be further coupled to bit line (BL) 516 and applies a bias voltage to BL 516 according to a disable information stored in DS latch 502. During programming operation, a programming voltage can be applied to BL 516 via BL bias circuit 512. The programming voltage can be further applied to the memory cell via BL 516 to program the memory cell. During verification operation, a verification voltage can be applied to BL 516 via BL bias circuit 512. The verification voltage can be further applied to the memory cell to perform a verification operation. Circuit 500 may further include a verification circuit 514, such as a sense amplifier, coupled to BL 516, DS latch 502, and DL latch 504. Verification circuit 514 may be configured to read the memory cell during verification operation to verify that the threshold voltage of the memory cell meets a target value. If the threshold voltage of the memory cell meets the target value, it indicates that the memory cell has passed the verification operation. If the threshold voltage of the memory cell does not meet the target value, it indicates that the verification operation has failed. When the threshold voltage of the memory cell does not meet the target value, an adjusted verification voltage can be applied to the memory cell to verify whether the threshold voltage of the memory cell meets the adjusted value.

[0048] Verification circuit 514 can further generate failure mode data (also known as a verification failure counter (VFC)) indicating which memory cells in the memory have failed verification operations. Verification circuit 514 can further transmit verification information to DS latch 502 and / or DL ​​latch 504. Circuit 500 may also include a verification level counter (not shown) configured to increment its value in response to the failure rate of the failure mode data being equal to or less than a standard value (e.g., 10%), for example, incrementing the value of the verification level counter by one. The value of the verification level counter can indicate which level the memory cell has been programmed to.

[0049] It should be noted that a 3D-NAND device (e.g., device 100) may include a plurality of circuits 500 arranged in a cache structure (e.g., 114, 116), and each of the circuits 500 may be coupled to a corresponding bit line of the 3D-NAND device and used in programming operations.

[0050] Figure 6 This is a flowchart of a method 600 for memory programming according to an exemplary embodiment of the present disclosure. Figure 6 As shown, method 600 may include a programming pulse operation 600A configured to program memory cells of a 3D NAND device (e.g., device 100) and a programming verification operation 600B configured to verify whether the memory cells have been programmed to a target threshold voltage. Figure 6 As shown, method 600 may begin at step S604, in which preparation may be performed. During preparation, stored data in the memory cell may be erased to receive new data, and prohibition information may be set (or stored) in a first latch (e.g., DS latch 502) and a second latch (e.g., DL latch 504). The prohibition information may be formed by logic 1 and logic 0, wherein logic 1 indicates that the memory cell is not programmed, and logic 0 indicates that the memory cell is programmed.

[0051] Then, method 600 can proceed to step S606, which is the first step of programming pulse operation 600A. In step S606, an initial first state programming voltage can be determined based on the prohibition information set in the first latch (e.g., DS latch 502) and the counter value of the verification state counter. In an exemplary embodiment of method 600, the first state can be the third level LV2 of the memory cell, and thus the counter value of the verification state counter is two. Then, method 600 can proceed to step S608, which is the second step of programming pulse operation 600A. In step S608, the prohibition information in the first latch (e.g., DS latch 502) can be replaced by initial adjusted verification information (3BL information) previously stored in the second latch (e.g., DL latch 504), wherein the initial adjusted verification information indicates which memory cells in the memory cell received the previous adjusted verification voltage in the previous adjusted verification operation from the prior state (e.g., second level LV1) to the first state (e.g., third level LV2). Subsequently, the first state programming voltage can be determined based on the initial first state programming voltage and the initial adjusted verification information, and the first state programming voltage can be applied to the data line (e.g., word line or bit line) of the memory cell to program the memory cell to the first state (e.g., LV2).

[0052] Method 600 can proceed to S610, thereby initiating the programming verification operation 600B. In step S610, a first state verification voltage can be applied to the data line of the memory cell to perform a first state verification (or first state verification operation) on the memory cell. The first state verification can verify the first state threshold voltage of the memory cell based on a first target value and further generate failure mode data (or VFC) for the first state verification. Figure 6 In an exemplary embodiment, the first state is the third level LV2 of the memory cell, and the first state threshold voltage is Vt2 accordingly. Failure mode data can be set to (transmitted to, stored to, or saved to) a second latch (e.g., DL latch 504) and indicate: a first portion of the memory cell that passed the first state verification, and a second portion of the memory cell that failed the first state verification. In some embodiments, before the first state verification, the prohibition information in the first latch can be inverted, and the inverted prohibition information indicates the unverified state of the memory cell, including the first state (e.g., the third level LV2) and the remaining states after the first state (e.g., LV3-LV7). In some embodiments, first state failure verification information can be added to the first latch (e.g., DS latch 502), wherein the first state failure verification information indicates the second portion of the memory cell that failed the first state verification.

[0053] In step S612, the failure mode data can be counted to calculate the failure rate of the failure mode data.

[0054] In step S614, an adjusted first-state verification voltage can be applied to the data line of the second portion of the memory cell that failed the first-state verification, thereby performing an adjusted first-state verification (or an adjusted first-state verification operation) on the second portion of the memory cell. In some embodiments, a prohibition message and adjusted first-state verification information (or 3BL information) can be set to the second latch. The adjusted first-state verification information indicates which memory cells receive the adjusted first-state verification voltage.

[0055] In step S616, a decision can be made based on the failure rate of the failure mode data. In response to a decision that the failure rate of the failure mode data is equal to or less than a standard value (i.e., pass in step S616), method 600 can proceed to S618, where the counter value of the verification status counter can be incremented by one, and then proceed to step S620. In response to a decision that the failure rate of the failure mode data is greater than a standard value (i.e., failure in step S616), method 600 directly proceeds to step S620.

[0056] In step S620, a second state verification voltage can be applied to the data line of the memory cell to perform a second state verification (or second state verification operation) on the memory cell, thereby verifying the second state threshold voltage of the memory cell based on a second target value. Figure 6 In an exemplary embodiment, when the first state is LV2, the second state is therefore LV3, and the second state threshold voltage is Vt3 accordingly. In step S622, an adjusted second state verification voltage can be applied to the data line of a portion of memory cells that failed the second state verification, thereby performing an adjusted second state verification (or an adjusted second state verification operation) on that portion of memory cells that failed the second state verification. As shown in steps S624 and S626, the verification operation and the adjusted verification operation can be repeated for the remaining states of the memory cells (e.g., LV4-LV7) until the verification and adjusted verification for the last state (e.g., LV7) are completed. In some embodiments, failure verification information for the first state (e.g., LV2) and subsequent states (e.g., LV3-LV7) can be set to a first latch (e.g., DS latch 502), and adjusted verification information for the first state and subsequent states can be set to a second latch (e.g., DL latch 504).

[0057] Next, method 600 proceeds to step S628, where a decision can be made as to whether the counter value of the verification state counter is equal to or less than a threshold (e.g., eight). As mentioned above, the counter value of the verification state counter indicates which state of the memory cell will be programmed and verified. When the counter value of the verification state counter is equal to eight (e.g., "Yes" in S628), it indicates that the first state to be programmed and verified is the eighth level LV7 of the memory cell, and the eighth level LV7 has been successfully programmed. Therefore, method 600 proceeds to step S699 because all levels (LV0-LV7) of the memory cell have been successfully programmed. When the counter value of the verification state counter is less than eight (e.g., "No" in S628), it indicates that the first state is not the eighth level LV7 of the memory cell, and method 600 must continue to program and verify the next state indicated by the counter value of the verification state counter. For example, when the counter value of the verification state counter is three, the next state to be programmed and verified is the fourth level LV3 of the memory cell.

[0058] As shown in S628, in response to a counter value less than eight, the memory cell can be programmed and verified for the next state. In one embodiment, in response to the counter value of the verification state counter remaining unchanged, the next state is still the first state. In another embodiment, in response to the counter value of the verification state counter increasing by one in step S618, the next state is a subsequent state of the first state. To program the memory cell for the next state, an initial programming voltage is determined based on a prohibition message set in the first latch. Furthermore, the prohibition message in the first latch can be replaced by adjusted verification information in the first latch. The adjusted verification information indicates which memory cells receive the adjusted first state verification voltage in the adjusted first state verification operation. Therefore, the programming voltage can be determined based on the initial programming voltage and the adjusted verification information, and this programming voltage can be applied to the data lines of the memory cell, thereby programming the memory cell in the subsequent state (e.g., LV3) to the first state (e.g., LV2).

[0059] Table 1 shows the relationship between the verification level and the verification content when programming and verification operations begin at the second level (e.g., LV1) of the memory cell.

[0060] Table 1: Relationship between verification level and verification content

[0061] As shown in Table 1, when the second level (LV1) is the first state being programmed and verified, the verification operation can verify the second level (LV1) through the eighth level (LV7). For the remaining states relative to the first state, the verification operation can again verify the memory cells that failed in the previous state in the previous state of the remaining states, and verify the memory cells from the remaining states to the final state (e.g., the eighth level LV7). For example, when programming and verifying the third level (e.g., LV2), the verification operation can again verify the memory cells that failed in the second level (e.g., LV1 failure) in the second level (e.g., LV1), and verify the memory cells from the third level (e.g., LV2) to the final level (e.g., LV7). For example, when programming and verifying the fourth level (e.g., LV3), the verification operation can again verify the memory cells that failed in the second level (e.g., LV1 failure) in the second level (e.g., LV1 failure), again verify the memory cells that failed in the third level (e.g., LV2 failure) in the third level (e.g., LV2 failure), and verify the memory cells from the fourth level (e.g., LV3) to the eighth level (e.g., LV7).

[0062] Figure 7-13 This is a schematic diagram illustrating the various latch states during programming of a 3D-NAND storage device using the method described above. For example... Figure 6 As mentioned above, in order to program a 3D-NAND device, a preparation operation can first be applied (e.g., Figure 6 (S604 in the example). Next, programming operations can be applied (e.g., Figure 6 (e.g., 600A) to program (write) the memory cells of the 3D-NAND device. Additionally, verification operations (e.g., Figure 6 (600B in the middle) to verify whether the memory cell has been successfully programmed. Figure 7 The latch state of the latch is shown during a preparation operation (e.g., S604). As mentioned above, a 3D-NAND device may include memory cells formed by multiple vertical NAND memory cell strings. Each of the vertical NAND memory cell strings may be coupled to a corresponding bit line, and the bit line may be further coupled to a corresponding page cache including a latch, such as... Figure 5As shown in the diagram. During the preparation operation, the memory cell can be erased to receive the data to be programmed, and prohibition information can be set (stored or saved) in the DS latch (e.g., DS latch 502) and DL latch (e.g., DL latch 504). The prohibition information can be indicated by logic 1 and logic 0. For example, logic 1 indicates that the memory cell will not be programmed, and logic 0 indicates that the memory cell will be programmed. In addition, user data programmed in the memory cell can be stored in the D1 latch, D2 latch, and DC latch. The D1 latch can save the next page information of the memory cell, the D2 latch can save the middle page information of the memory cell, and the DC latch can save the previous page information of the memory cell. During the preparation operation (e.g., Figure 6 When S604 in the memory module completes, a programming pulse (or programming voltage) is applied to the word line of the memory cell, thereby programming the memory cell, which can be done as follows: Figure 6 The programming pulse operation 600A is shown in the diagram. For example, a memory cell can be programmed to a first state. Figure 7 In an exemplary embodiment, the first state is the third level LV2 of the storage cell.

[0063] Figure 8 This illustrates the execution of the first state verification operation (e.g., Figure 6 The latch state of the latch before S610 in the example. Figure 8 As shown, the disable information in the DS latch can be inverted, where the inverted disable information (e.g., ~disable information) can indicate the unverified state of the memory cell. Figure 8 In an exemplary embodiment, the inverted prohibition information indicates that the first state to be verified is the third level LV2 of the memory cell. Furthermore, the inverted prohibition information indicates that the remaining states after the first state are LV3-LV7, and that the first level LV0 and the second level LV1 of the memory cell have passed the verification operation. Therefore, the prohibition information can also be defined as ~(LV0│Lv1) (i.e., not LV0 or not LV1).

[0064] Figure 9 This illustrates the first state verification operation performed on the storage cell (e.g., Figure 6In S610 of the latch, the latch state of the latch is such that a first state verification voltage can be applied to the word line coupled to the memory cell to perform a first state verification operation (or first state verification). When LV2 is in the first state, the first state verification is used to verify whether the first state threshold voltage of the memory cell meets a first target value (e.g., Vt2). The first state verification voltage can be a pulse voltage signal with an intensity close to the first target value. If the memory cell is turned on under the first state verification voltage, it can indicate that the threshold voltage of the memory cell does not meet the first target value, and the first state verification fails. If the memory cell is not turned on under the first state verification voltage, it can indicate that the threshold voltage of the memory cell meets the first target value, and the first state verification passes. In addition, a verification failure counter (VFC) for the first state verification can be generated and set to (saved to, stored in, or provided to) the DL latch (e.g., 504). The verification failure counter can include failure mode data and indicate the first portion of memory cells that passed the first state verification and the second portion of memory cells that failed the first state verification. In addition, first-state failure verification information (e.g., first-state PV pass) can be added to the DS latch. The first-state failure verification information indicates the second part of the memory cell that failed the first-state verification.

[0065] Figure 10 This demonstrates the performance of the adjusted first state verification (e.g.) Figure 6 In S614 of the latch, the latch state of the latch is such that an adjusted first state verification voltage can be applied to the data line of the second portion of the memory cell that failed the first state verification, thereby performing an adjusted first state verification on the second portion of the memory cell. In some embodiments, the strength of the adjusted first state verification voltage can be set to be lower than the first state verification voltage. The adjusted first state verification voltage can be obtained by subtracting a differential voltage from the first state verification voltage. The differential voltage can be less than 1 volt and can be referred to as a 3BL bias voltage. Therefore, the adjusted first state verification can also be referred to as first state 3BL or first state 3BL verification. The adjusted first state verification voltage can verify whether the first state threshold voltage of the second portion of the memory cell can meet a first adjusted target value lower than a first target value. In addition, a prohibition information can be set to the DL latch (e.g., 504) from the adjusted first state verification information (or first state 3BL information) obtained from the adjusted first state verification, wherein the adjusted first state verification information indicates which memory cells received the adjusted first state verification voltage, and the prohibition information indicates the verified state (e.g., first level LV0 and second level LV1).

[0066] It should be pointed out that, such as Figure 6As shown in S616 and S618, when the adjusted first state verification is completed, the counter value of the verification state counter can be incremented, for example, by one, in response to the failure rate of the failure mode data (VFC) being equal to or less than a standard value. When the failure rate of the failure mode data is equal to or less than the standard value, it indicates that the memory cell has been successfully programmed for the first state (e.g., the third level LV2).

[0067] Figure 11 It shows that it can be followed Figure 6 The sequential verification shown in S620-S626 of the diagram verifies the latch state of the latch during the remaining states (e.g., from the fourth level to the eighth level LV3-LV7) after the first state (e.g., LV2). Similar to the first state, each of the remaining states can receive the corresponding verification and the corresponding adjusted verification. Furthermore, the failure verification information for each of the remaining states can be set to the DS latch, and the adjusted verification information for each of the remaining states can be set to the DL latch.

[0068] For example, a second state verification voltage can be applied to the data line of a memory cell, and a second state verification can be performed on the memory cell to verify the second state threshold voltage (e.g., Vt3) of the memory cell based on a second target value. Next, an adjusted second state verification voltage can be applied to the data lines of a subset of memory cells that failed the second state verification, and the adjusted second state verification can be applied to that subset of memory cells. Furthermore, second state failure verification information (e.g., ~second state PV passed) can be added to the DS latch, wherein the second state failure verification information is obtained from the second state verification and indicates the subset of memory cells that failed the second state verification. Additionally, adjusted second state verification information (e.g., second state 3BL) can be added to the DL latch, wherein the adjusted second state verification information indicates which memory cells received the adjusted second state verification voltage.

[0069] like Figure 11 As shown, while sequentially verifying the remaining states (e.g., the fourth to eighth levels LV3-LV7 of the memory cell), an inverted prohibition message and failure verification messages for all verified states (e.g., ~(prohibition message│first│second│...│final state PV passed)) can be set to the DS latch, and an adjusted prohibition message and verification messages for all verified states (e.g., prohibition message│first│second│...│final state 3BL) can be set to the DL latch. After all remaining states have been verified, it indicates that the memory cell has been programmed to the first state (e.g., LV2).

[0070] exist Figure 12In this configuration, the inverted prohibition information and the failure verification information for all verified states (e.g., ~(prohibition information│first│second│...│final state PV passed)) set in the DS latch can be inverted to form prohibition information and pass verification information for all verified states. Accordingly, the prohibition information and the pass verification information for all verified states are set (or stored) in the DS latch. Furthermore, it can be determined whether the counter value of the verification state counter is greater than or equal to a threshold. Figure 12 In an exemplary embodiment, the threshold can be eight, indicating that the memory cell has eight levels (e.g., LV0-LV7). When the counter value of the verification state counter is eight, it indicates that the eighth level (e.g., LV7) of the memory cell has passed the verification operation. In response to determining that the counter value of the verification state counter is less than the threshold, in an embodiment, the memory cell can be programmed and verified again for the first state (e.g., LV2) in response to the counter value of the verification state counter remaining unchanged. The memory cell can be programmed and verified for a subsequent state (e.g., LV3) of the first state in response to the counter value of the verification state counter increasing (e.g., increasing by one).

[0071] Figure 13 The latch state of the latch is shown when encoding the memory cell for the next state based on the counter value of the verification level counter. As mentioned above, when the counter value of the verification state counter remains unchanged after the first state verification, the next state is still the first state (e.g., LV2), and the memory cell is programmed again for the first state. When the counter value of the verification level counter changes after the first state verification, the next state is a subsequent state of the first state (e.g., LV2) (e.g., LV3), and the memory cell is programmed for the next state. To program the next state, the initial programming voltage can be determined based on the prohibition information set in the DS latch. Alternatively, the prohibition information can be replaced by adjusted verification information (e.g., prohibition information │first │second │...│last state 3BL) set (or stored) in the DL latch. The programming voltage can then be determined based on the initial programming voltage and the adjusted verification information. For example, the programming voltage can be determined by subtracting the differential voltage from the initial programming voltage based on the adjusted verification information. Therefore, the programming voltage can be applied to the word line of the memory cell to program the memory cell for the next state (e.g., LV3).

[0072] Figure 14This is a simplified block diagram of a storage device 1001 according to embodiments of the present disclosure, on which embodiments of the present disclosure may be implemented. The storage device 1001 may include a storage array 1004 arranged in rows and columns. The storage array 1004 may include a plurality of channel structures formed within a stack of alternating word line layers and insulating layers. Row decoding circuitry 1008 and column decoding circuitry 1010 are provided to decode address signals provided to the storage device 1001. Address signals are received and decoded to access the storage array 1004. The storage device 1001 may also include input / output (I / O) control circuitry 1012 to manage inputs of commands, addresses, and data to the storage device 1001, and outputs of data and status information from the storage device 1001. An address register 1014 is coupled between the I / O control circuitry 1012 and the row decoding circuitry 1008 and column decoding circuitry 1010 to latch the address signals prior to decoding. Command register 1024 is coupled between I / O control circuit 1012 and control logic (or control circuit) 1016 to latch incoming commands.

[0073] Control logic 1016 can control access to memory array 1004 in response to a command and generate status information for external processor 1030. Control logic 1016 is coupled to row decoding circuitry 1008 and column decoding circuitry 1010 to control row decoding circuitry 1008 and column decoding circuitry 1010 in response to an address. Control logic 1016 can also be coupled to sense amplifier and latch circuitry (also known as cache structure) 1018 to control sense amplifier and latch circuitry 1018 in response to a command and generate status information for external processor 1030. In some embodiments, control logic 1016 may include the verification status counter mentioned above. Sense amplifier and latch circuitry 1018 may be coupled to memory array 1004 and can latch incoming or outgoing data in the form of analog voltage levels. Sense amplifier and latch circuitry 1018 may include the aforementioned connections. Figure 5 The page buffer (e.g., page buffer 500A), the verification circuit (e.g., verification circuit 514), and the BL bias circuit (e.g., BL bias circuit 512) are mentioned.

[0074] Still referencing Figure 14The status register 1022 can be coupled between the I / O control circuit 1012 and the control logic 1016 to latch status information for output to the external processor 1030. The storage device 1001 receives control signals at the control logic 1016 via the control link 1032. These control signals may include chip enable CE#, command latch enable CLE, address latch enable ALE, and write enable WE#. The storage device 1001 can receive commands in the form of command signals, addresses in the form of address signals, and data in the form of data signals from the external processor via the multiplexed input / output (I / O) bus 1034, and can output data to the external processor via the I / O bus 1034.

[0075] The various embodiments described herein offer several advantages over related 3D-NAND devices. For example, in related 3D-NAND devices, a page buffer including six latches is required to program the three-layer cells of the related 3D-NAND device. This disclosure provides a sensing scheme for programming the three-layer cells of a 3D-NAND device, which may be referred to as non-forbidden verification. In non-forbidden verification, a page buffer including five latches can be applied during programming operations. Accordingly, latches can be saved in 3D-NAND compared to related 3D-NAND devices. Furthermore, in non-forbidden verification, fewer page buffer operations can be applied when switching verification levels.

[0076] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will recognize that they can readily use this disclosure as a basis to design or modify other processes or structures to achieve the same purpose and / or realize the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent designs do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of this disclosure.

Claims

1. A storage device, characterized in that, include: A storage unit and a first latch, a second latch, and a third latch coupled to the storage unit; wherein, The first latch is configured to: store verification information during a verification operation; store inverted prohibition information during a verification operation; the inverted prohibition information indicates the unverified state of the storage cell, the unverified state including a first state and the remaining states after the first state; The second latch is configured to store failure mode data during the verification operation; The third latch is configured to store the logical page information of the storage unit.

2. The storage device according to claim 1, characterized in that, The first latch is also configured to store prohibition information during the verification operation; the verification information includes: first state failure verification information; the first state failure verification information indicates a storage unit that failed the first state verification.

3. The storage device according to claim 2, characterized in that, The verification information further includes: second state failure verification information; the second state failure verification information indicates the storage unit that failed the second state verification.

4. The storage device according to claim 1, characterized in that, The storage device further includes: a fourth latch and a fifth latch coupled to the storage cell; wherein, The third latch is configured to store the next page information of the storage unit; the fourth latch is configured to store the middle page information of the storage unit. The fifth latch is configured to store the previous page information of the storage unit.

5. The storage device according to claim 1, characterized in that, The storage failure mode data includes: storage first state verification operation failure mode data, the first state verification operation being configured to verify the first state threshold voltage of the storage cell based on a first target value.

6. The storage device according to claim 1, characterized in that, The second latch is also configured to: The adjusted first state verification information is stored; the adjusted first state verification information indicates which storage cells receive the adjusted first state verification voltage.

7. The storage device according to claim 1, characterized in that, The storage device further includes: control logic; The control logic is coupled to the memory cell, the first latch, and the second latch, and the control logic is configured as follows: The prohibited information is stored in the first latch and the second latch; A first state programming voltage is applied to the memory cell to program the memory cell to a first state; A first state verification voltage is applied to the storage cell to perform a first state verification operation on the storage cell. The first state verification operation verifies the first state threshold voltage of the storage cell based on a first target value and generates failure mode data of the first state verification operation. The failure mode data is stored in a second latch to indicate storage cells that pass the first state verification operation and storage cells that fail the first state verification operation. An adjusted first state verification voltage is applied to the memory cell that fails the first state verification operation to perform an adjusted first state verification operation on the memory cell that fails the first state verification operation, the adjusted first state verification operation being used to verify the first state threshold voltage of the memory cell to which the adjusted first state verification voltage is applied.

8. The storage device according to claim 7, characterized in that, The control logic also includes: a verification status counter; The verification state counter is configured to increment its counter value in response to the failure rate of the failure mode data being less than or equal to a second value. The counter value of the verification state counter can indicate which state the storage unit is programmed into, and the counter value of the verification state counter is stored in a first latch.

9. The storage device according to claim 8, characterized in that, The control logic is further configured as follows: Based on the fact that the counter value of the verification state counter is less than a first value, a first state programming voltage is applied to the memory cell to program the memory cell to the first state.

10. The storage device according to claim 9, characterized in that, The control logic is further configured as follows: The initial first state programming voltage is determined based on the disable information and counter value stored in the first latch; The disabled information in the first latch is replaced with adjusted initial verification information, which indicates which memory cells received the previous adjusted verification voltage in the previous adjusted verification operation from the prior state to the first state. The first-state programming voltage is determined based on the initial first-state programming voltage and the adjusted initial verification information; The first state programming voltage is applied to the memory cell to program the memory cell to the first state.

11. The storage device according to claim 10, characterized in that, The control logic is further configured as follows: The prohibition information in the first latch is reversed; the reversed prohibition information indicates the unverified state of the memory cell, the unverified state including the first state and the remaining states after the first state; A first state verification voltage is applied to the storage cell to perform a first state verification operation, the first state verification voltage being determined based on inverted prohibition information stored in the first latch.

12. The storage device according to claim 11, characterized in that, The storage device further includes multiple verification circuits; each verification circuit is coupled to its respective first latch and its respective second latch; The verification circuit is configured to verify whether the first state threshold voltage of the storage unit meets the first target value, and the failure mode data of the first state verification operation is stored in the second latch through the verification circuit.

13. A storage device, characterized in that, include: Storage array; The memory array includes multiple channel structures within a stack of alternating word line layers and insulating layers, the multiple channel structures forming multiple memory cells; Page cache; The page cache includes a first latch, a second latch, and a third latch; Control logic; The control logic is configured to respond to commands to control access to the storage array and generate status information for external processors; The first latch is configured to: store verification information during the verification operation; store inverted prohibition information; the inverted prohibition information indicates the unverified state of the storage unit, the unverified state including a first state and the remaining states after the first state; The second latch is configured to store failure mode data during the verification operation; The third latch is configured to store the logical page information of the storage unit.

14. The storage device according to claim 13, characterized in that, The page cache further includes: a fourth latch and a fifth latch; wherein, The third latch is configured to store the next page information of the storage unit, and the fourth latch is configured to store the middle page information of the storage unit. The fifth latch is configured to store the previous page information of the storage unit.

15. The storage device according to claim 13, characterized in that, The first latch is configured as follows: Store second-state failure verification information; the second-state failure verification information indicates the storage unit that failed the second-state verification.

16. The storage device according to claim 13, characterized in that, The second latch is configured as follows: The adjusted first state verification information is stored; the adjusted first state verification information indicates which storage cells receive the adjusted first state verification voltage.

17. A method of operating a storage device, characterized in that, include: During the verification operation, information will be prohibited from being stored in the first latch and the second latch; The prohibition information in the first latch is inverted to form inverted prohibition information in the first latch; the inverted prohibition information indicates the unverified state of the storage cell, the unverified state including the first state and the remaining states after the first state; The first state failure verification information is stored in the first latch; the first state failure verification information indicates the storage unit that failed the first state verification. During the verification operation, the failure mode data is stored in the second latch; The failure mode data indicates the storage units that passed the first state verification operation and the storage units that failed the first state verification operation.

18. The method according to claim 17, characterized in that, The method further includes: The adjusted first state verification information is stored in the second latch; the adjusted first state verification information indicates which storage cells receive the adjusted first state verification voltage.

19. The method according to claim 18, characterized in that, The method further includes: The first latch stores second state failure verification information, which indicates the storage cell that failed the second state verification.

Images