simplified carrier removable by a reduced number of cmp processes

Abstract

The present disclosure relates to simplified carriers that are removable by a reduced number of CMP processes. A method includes bonding a first package component on a composite carrier, and performing a first polishing process on the composite carrier to remove a base carrier of the composite carrier. The first polishing process stops on a first layer of the composite carrier. A second polishing process is performed to remove the first layer of the composite carrier. The second polishing process stops on a second layer of the composite carrier. A third polishing process is performed to remove a plurality of layers in the composite carrier. The plurality of layers includes the second layer, and wherein the third polishing process stops on a dielectric layer in the first package component.

Description

Technical Field

[0001] This disclosure relates to simplified carriers that can be removed by reducing the number of CMP processes. Background Technology

[0002] In integrated circuit packaging, a carrier often serves as a support structure on which the device die is placed and molded. Typically, a carrier can comprise multiple layers formed from different materials suitable for different functions. However, due to the varying properties of these materials, multiple CMP processes may be required for removal. A typical carrier may require five CMP processes to remove, each process handling one layer of material. Therefore, manufacturing costs are high. Summary of the Invention

[0003] According to one embodiment of this disclosure, a method for forming a semiconductor structure is provided, comprising: bonding a first packaging component to a first composite carrier; performing a first polishing process on the first composite carrier to remove a substrate carrier of the first composite carrier, wherein the first polishing process stops at a first layer of the first composite carrier; performing a second polishing process to remove the first layer of the first composite carrier, wherein the second polishing process stops at a second layer of the first composite carrier; and performing a third polishing process to remove a plurality of layers in the first composite carrier, wherein the plurality of layers includes the second layer, and wherein the third polishing process stops at a dielectric layer in the first packaging component.

[0004] According to another embodiment of this disclosure, a semiconductor structure is provided, comprising: a composite carrier, including: a silicon substrate carrier; an oxide-based layer on the silicon substrate carrier; a first nitride-based layer on the oxide-based layer; a second nitride-based layer on the first nitride-based layer; and a third nitride-based layer on the second nitride-based layer, wherein a first material of the first nitride-based layer is different from a second material of the second nitride-based layer and a third material of the third nitride-based layer.

[0005] According to another embodiment of this disclosure, a semiconductor structure is provided, comprising: a composite carrier, including: a substrate carrier; a silicon oxide layer disposed on and in contact with the substrate carrier; a silicon nitride layer disposed on and in contact with the silicon oxide layer; a first silicon oxynitride layer disposed on and in contact with the silicon nitride layer; and a second silicon oxynitride layer disposed on and in contact with the first silicon oxynitride layer; and a packaging assembly disposed on and bonded to the composite carrier, wherein the packaging assembly includes: a second silicon oxide layer bonded to the second silicon oxynitride layer. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood by reading in conjunction with the accompanying drawings through the following detailed description. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1-10 , Figure 11A , Figure 11B , Figure 11C and Figure 12-19 Cross-sectional and perspective views of intermediate stages in the formation of a composite carrier and encapsulation according to some embodiments are shown.

[0008] Figure 20 , Figure 21 , Figure 22A , Figure 22B , Figure 22C and Figure 23-27 Cross-sectional and perspective views of intermediate stages in the formation of a composite carrier and encapsulation according to some embodiments are shown.

[0009] Figure 28 , Figure 29A , Figure 29B and Figures 30-33 Cross-sectional and perspective views of intermediate stages in the formation of a composite carrier and encapsulation according to some embodiments are shown.

[0010] Figure 34 The process flow for forming a composite carrier and using the carrier to form an encapsulation is illustrated according to some embodiments. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not, in itself, define a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, spatially related terms (e.g., "below," "under," "lower part," "above," "above," "top," "upper part," etc.) may be used herein to readily describe the relationship between one element or feature as shown in the figure and another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device during use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly.

[0013] A composite carrier and a method for forming the same are provided. A method for forming a package using the composite carrier is also shown. According to some embodiments of this disclosure, the composite carrier includes a silicon wafer, a first layer over the carrier, and a plurality of second layers over the first layer. The plurality of second layers are formed of similar materials. Alignment marks may be formed in the plurality of second layers. A plurality of package components may be bonded to the carrier, and a package including the plurality of package components may be formed. After the package is formed, three chemical mechanical polishing (CMP) processes are performed, wherein a first CMP process, a second CMP process, and a third CMP process are respectively used to remove the silicon carrier, the first layer, and the plurality of second layers. By forming the plurality of second layers having similar materials, the plurality of second layers can be removed in the same CMP process, thereby reducing manufacturing costs. The embodiments discussed herein are intended to provide examples to enable making or using the subject matter of this disclosure, and modifications that may be made while remaining within the intended scope of the different embodiments will be readily understood by those skilled in the art. Similar reference numerals are used to identify similar elements in the various views and illustrative embodiments. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0014] Figure 1-10 , Figure 11A , Figure 11B , Figure 11C and Figure 12-19 Cross-sectional and perspective views are shown of intermediate stages in forming a composite carrier and using the composite carrier to form an encapsulation according to some embodiments of the present disclosure. The corresponding processes are also schematically illustrated in… Figure 34 The process flow shown is as follows.

[0015] Figures 1 to 7 A cross-sectional view is shown of an intermediate stage in the formation of a composite carrier according to some embodiments of the present disclosure. (See reference...) Figure 1 A substrate carrier 20 is provided. The substrate carrier 20 may be a wafer, which may have a circular top-view shape, such as... Figure 11B As shown in the diagram. The substrate carrier 20 can be made of substrate 42 in the overlay encapsulation assembly 40 ( Figure 8The substrate 20 is formed from the same material, thereby reducing warpage caused by coefficient of thermal expansion (CTE) mismatch during subsequent packaging. According to some embodiments, the substrate 20 may be formed of or contain silicon, but other materials such as laminates, ceramics, glass, and silicate glass may also be used. According to some embodiments, the entire substrate 20 is formed of a homogeneous material, in which no other material differs from the homogeneous material is present. For example, the entire substrate 20 may be formed of silicon (doped or undoped) and may not contain metal regions, dielectric regions, etc.

[0016] refer to Figure 2 Layer 22 is deposited on the substrate 20. For example... Figure 34 As shown, the corresponding process is illustrated as process 202 in process flow 200. Layer 22 is formed of a material different from that of the substrate 20, so that layer 22 can be used as a CMP stop layer in subsequent CMP processes. According to some embodiments, layer 22 is formed of or contains a dielectric material, which can be an oxide-based material (or silicon oxide-based material), such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), etc. Layer 22 can be formed using spin coating, flowable chemical vapor deposition (FCVD), etc. According to an alternative embodiment of the present disclosure, layer 22 is formed by oxidizing the substrate 20 to form a thermal oxide layer. According to still some alternative embodiments of the present disclosure, layer 22 is formed using deposition methods such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), etc. According to some embodiments, the entire layer 22 is formed of a homogeneous material, in which there are no other materials different from the homogeneous material.

[0017] After deposition, layer 22 can be planarized, for example, by a CMP process or a mechanical polishing process. The resulting layer 22 can have a thickness T1 of approximately to approximately It can be within the range of [specific thicknesses], but different thicknesses can be used.

[0018] refer to Figure 3 Layer 24 is deposited on layer 22. For example... Figure 34As shown, the corresponding process is represented as process 204 in process flow 200. Layer 24 is formed of a material different from that of layer 22, so layer 24 can be a CMP stop layer in the subsequent removal process of layer 22. Furthermore, since layer 24 is formed of a material different from that of layer 22, non-uniformity in the removal process of layer 22 can be compensated. The material of layer 24 can also be different from the material of substrate 20, so that in subsequent CMP processes of substrate 20 (which is thicker), layer 24 can also be used as a CMP stop layer for CMP processes that failed to stop in layer 22. Furthermore, the material of layer 24 is also different from that of surface dielectric bonding layer 58 (…). Figure 15 and 16 The material, thus in subsequent CMP processes of layers 24, 26, and 32, such as Figure 16 As shown, the surface dielectric bonding layer 58 is not removed. Furthermore, layer 24 can serve as layer 22 and subsequently formed layer 26. Figure 4 The adhesive layer between the layers. According to some embodiments, the entire layer 24 is formed of a homogeneous material, in which there is no other material different from the homogeneous material.

[0019] Layer 24 can be formed of or contain a dielectric material, which can be a nitride-based material, such as silicon nitride, but layer 24 can also be formed of or contain other materials, such as silicon oxynitride (SiON). According to some embodiments of this disclosure, layer 24 is formed using PECVD, CVD, LPCVD, ALD, etc. The thickness T2 of layer 24 can be approximately... to approximately It can be within the range of [specific thicknesses], but different thicknesses can be used.

[0020] refer to Figure 4 Layer 26 is deposited on layer 24. For example... Figure 34 As shown, the corresponding process is represented as process 206 in process flow 200. Layer 26 is formed of a material similar to that of layer 24, so that layer 26 can be removed in the same CMP process as layer 24 in subsequent CMP processes. On the other hand, the material of layer 26 may also be slightly different from that of layer 24, so that if opening 28 penetrates layer 24 when forming alignment marks, layer 24 can be used as an etch stop layer in the process of forming opening 28. Furthermore, the material of layer 26 may also be different from that of surface dielectric bonding layer 58 ( Figure 15 and 16 ) materials, thus in such Figure 16 In the subsequent CMP process shown, the surface dielectric bonding layer 58 will not be removed.

[0021] According to some embodiments, layer 26 is formed of or contains a dielectric material. The dielectric material can be an oxide-based material, such as silicon oxynitride (SiON), but layer 26 can also be formed of or contain other materials, such as silicon oxycarbide (SiOC), silicon carbonitride (SiCN), etc. According to some embodiments of this disclosure, layer 26 is formed using PECVD, CVD, LPCVD, ALD, etc. The thickness T3 of layer 26 can be approximately... to approximately The thickness can vary between these layers. According to some embodiments, the entire layer 26 is formed of a homogeneous material, in which there is no other material different from the homogeneous material.

[0022] refer to Figure 5 An opening 28 is formed in layer 26. For example... Figure 34 As shown, the corresponding process is represented as process 208 in process flow 200. According to some embodiments, the formation of opening 28 is performed by photolithography and etching, wherein a photoresist (not shown) may be applied and subsequently patterned, and layer 26 is etched using the patterned photoresist as an etching mask. Opening 28 is used to form alignment marks, and the pattern, size, shape, and position are designed according to the requirements of the alignment marks. For example, opening 28 is arranged to have a distinguishable pattern for alignment. According to some embodiments, opening 28 is formed to partially extend into layer 26. According to an alternative embodiment, opening 28 is formed to penetrate layer 26, and thus, expose the top surface of layer 24. Dashed line 29 indicates the corresponding edge of the bottom portion of opening 28 when opening 28 penetrates layer 26.

[0023] Figure 6 The formation of alignment mark 30 is shown. Alignment mark 30 can be formed of, or contain metals, metal alloys, metal compounds, etc., to increase the contrast of alignment mark 30 relative to the surrounding material. For example... Figure 34 As shown, the corresponding process is illustrated as process 210 in process flow 200. According to some embodiments, alignment marks 30 include a metal region formed of or containing copper, copper alloys, tungsten, nickel, etc. An adhesive layer may be formed below and lining the metal region, or it may not be formed. The adhesive layer may be formed of titanium, titanium nitride, tantalum, tantalum nitride, etc., or may contain titanium, titanium nitride, tantalum, tantalum nitride, etc. The formation process may include, for example, depositing the adhesive layer (if formed) as a conformal layer using physical vapor deposition (PVD), depositing metal material over the adhesive region, and then performing a CMP process to remove excess portions of the adhesive layer and metal material, thereby leaving alignment marks 30 in layer 26.

[0024] According to some embodiments, alignment marks 30 are formed in layer 26, such as Figure 5 As shown in the diagram. According to an alternative embodiment, alignment marks 30 may be formed in other layers, such as in layers 24, 22, or base layer 20, or in the subsequently formed bonding layer 32, as illustrated. Figure 7 As shown in the image.

[0025] refer to Figure 7 A bonding layer 32 is deposited on layer 24. For example... Figure 34 As shown, the corresponding process is illustrated as process 212 in process flow 200. Bonding layer 32 is formed of a material similar to that of layers 24 and 26, allowing it to be removed in the same CMP process as layers 24 and 26 in subsequent CMP processes. According to some embodiments, the materials of layers 32 and 26 are identical. Therefore, a distinguishable interface may or may not exist between layers 32 and 26. According to other embodiments, the materials of layers 32 and 26 are different from each other. Furthermore, the material of bonding layer 32 is also different from that of surface dielectric bonding layer 58 (…). Figure 15 and 16 ) materials, thus in such Figure 16 In the subsequent CMP process shown, the surface dielectric bonding layer 58 is not removed. According to some embodiments, the bonding layer 32 is formed of or contains a dielectric material, which can be an oxide-based material, such as silicon oxynitride (SiON). According to some embodiments, layer 26 and bonding layer 32 are formed of the same material having the same composition, for example, both are formed of SiON having the same percentages of Si, O, and N atoms. According to alternative embodiments, layer 26 and bonding layer 32 are formed of similar materials having the same elements (e.g., Si, O, and N), but with different percentages of each element. For example, bonding layer 32 may have a larger percentage of oxygen atoms (and possibly a lower percentage of nitrogen atoms) than layer 26, thereby improving the bonding with the dielectric bonding layer 58. Figure 8 The bonding strength is reduced, and layer 26 and bonding layer 32 can still be removed in the same CMP process.

[0026] According to some embodiments of this disclosure, bonding layer 32 is formed using PECVD, CVD, LPCVD, ALD, etc. The thickness T4 of bonding layer 32 can be approximately... To date The thickness can be within the range specified, but different thicknesses can be used. According to some embodiments, the entire bonding layer 32 is formed of a homogeneous material, without any other material different from the homogeneous material. The bonding layer serves to prevent oxidation of the alignment marks 30.

[0027] According to some embodiments, layers 22, 24, 26 and bonding layer 32 have distinguishable interfaces, regardless of their materials. According to an alternative embodiment, layers 26 and 32 do not have distinguishable interfaces, but distinguishable interfaces are formed between all other adjacent layers.

[0028] As will be discussed in later paragraphs, layers 24 and 26, as well as bonding layer 32, will be removed using the same slurry in the same CMP process. This can be achieved by selecting appropriate similar materials for layers 24 and 26, and bonding layer 32, and also by selecting appropriate slurries, so that layers 24, 26, and 32 can be removed in the same CMP process regardless of whether layers 24 and 26, and bonding layer 32 are formed of the same or different materials, and the CMP can stop at dielectric bonding layer 58 ( Figure 16 For example, when layer 24 is formed of SiN and layers 26 and 32 are formed of SiON, the percentage of oxygen atoms in layers 26 and 32 can be less than about 20%, or less than about 10% or about 5%. According to some embodiments, the percentage of oxygen atoms in layers 26 and 32 is in the range of about 10% to about 15%. On the other hand, adding some oxygen to the bonding layer 32 can improve the bonding effect between the bonding layer 32 and the dielectric bonding layer 58. Figure 8 The bond strength between layers 24, 26, and 32. The percentage of nitrogen atoms in layers 24, 26, and 32 can be greater than about 70%, and can be in the range of about 50% to about 80%.

[0029] Throughout the description, the substrate carrier 20 and the overlying layers 22, 24, 26 and 32 are collectively referred to as the composite carrier 34, which can be used to support the encapsulated components during the encapsulation process.

[0030] refer to Figure 8 The first-tier (tier-1) encapsulation component 40 is bonded to the composite carrier 34 via fusion bonding. For example... Figure 34 As shown, the corresponding process is illustrated as process 214 in process flow 200. Although one package component 40 is shown, there may be multiple package components 40 that are identical to each other, such as... Figure 11B As shown in the diagram. Multiple package components 40 can be physically separate discrete package components, and as... Figure 8 The bonding process shown is chip-to-wafer bonding. Alternatively, the package assembly 40 can be located within an uncut wafer, and as... Figure 8 The bonding process shown is wafer-to-wafer bonding.

[0031] According to some embodiments, package component 40 is a device die, a package containing a device die, a system-on-a-chip (SoC) die including multiple integrated circuits (or device dies) integrated into a system, etc. The device die in package component 40 may be or may include logic dies, memory dies, input / output dies, integrated passive devices (IPDs), etc., or combinations thereof. For example, the logic device die in package component 40 may be a central processing unit (CPU) die, a graphics processing unit (GPU) die, a mobile application die, a microcontroller unit (MCU) die, a baseband (BB) die, an application processor (AP) die, etc. The memory die in package component 40 may include static random access memory (SRAM) dies, dynamic random access memory (DRAM) dies, etc. The device die in package component 40 may include a semiconductor substrate and interconnect structures.

[0032] According to some embodiments, the package assembly 40 may include a substrate 42, an integrated circuit device 44 located on the surface of the substrate 42, and a substrate via 46 penetrating the substrate 42. The substrate 42 may be a semiconductor substrate, such as a silicon substrate. The integrated circuit device 44 may include active devices, passive devices, etc. An interconnect structure 48 is located on the front side of the package assembly 40 and includes metal lines 52 and vias 54 electrically connected to the via 46 and the integrated circuit device 44. A metal pad 56 may be under-bump metallurgies (UBM) and is electrically connected to the via 46 and the integrated circuit device 44. The top portion of the via 46 may protrude beyond the rear surface of the substrate 42 (the top surface shown in the figure) and is located in a dielectric layer 59. A bonding pad 62 is electrically connected to the via 46 and is located in a dielectric layer 60.

[0033] A dielectric bonding layer 58 is located at the bottom of the encapsulation assembly 40. The dielectric bonding layer 58 is formed of or contains materials different from those of layers 24, 26, and 32 in the composite carrier 34. According to some embodiments, the material of the dielectric bonding layer 58 may include O-Si-O bonds, Si-OH bonds, N-Si-O bonds, and may include SiO2, SiON, etc. It will be appreciated that the materials of bonding layer 32 and dielectric bonding layer 58 can be interchanged. Bonding layer 32 and dielectric bonding layer 58 may include oxygen and OH bonds on their surfaces, wherein the OH bonds are bonded to silicon atoms.

[0034] According to some embodiments, the dielectric bonding layer 58 is a monolayer formed of a homogeneous material. According to alternative embodiments, the dielectric bonding layer 58 is a composite layer comprising a lower layer 58A and an upper layer 58B. According to these embodiments, the lower layer 58A may be formed of a material similar to or the same as that of layers 24, 26, and 32, which has a higher bonding strength with the bonding layer 32 than with the upper layer 58B. The upper layer 58B is formed of a different material than the lower layer 58A and can be used to stop the CMP (Continuous Motion Processing) of the bonding layers 32 and the lower layer 58A. For example, the lower layer 58A may be formed of SiN or SiON, while the upper layer 58B may be formed of SiO2.

[0035] According to some embodiments, bonding of the encapsulation assembly 40 to the composite carrier 34 includes: pretreating the bonding layers 32 and 58 in a process gas containing oxygen (O2) and / or nitrogen (N2), performing a pre-bonding process to connect the bonding layers 32 and 58 together, and performing an annealing process after the pre-bonding process. According to some embodiments, during the pre-bonding process, the encapsulation assembly 40 is contacted with the composite carrier 34, and pressure is applied to press the encapsulation assembly 40 firmly against the composite carrier 34. Pre-bonding can be performed at room temperature (about 20°C to about 25°C) or at higher temperatures.

[0036] After pre-bonding, an annealing process is performed. Si-O-Si bonds can be formed between bonding layers 32 and 58, allowing them to be bonded together with high bond strength. According to some embodiments, the annealing process is performed at a temperature between about 200°C and about 350°C. The annealing duration can range from about 30 minutes to about 60 minutes.

[0037] Figure 9 The deposition of gap-filling material (region) 64 is shown for sealing encapsulation assembly 40. (See diagram.) Figure 34 As shown, the corresponding process is illustrated as process 216 in process flow 200. According to some embodiments where the package assembly 40 is located in an uncut wafer, the gap-filling process may be skipped. According to some embodiments, the gap-filling region 64 is formed of or contains an inorganic material. For example, the formation of the gap-filling region 64 may include depositing a dielectric liner (which is also an etch stop layer) and depositing a dielectric material on the dielectric liner. The dielectric liner may be a conformal layer extending to the top surface and sidewalls of the package assembly 40. The etch stop layer is formed of a dielectric material having good adhesion to the sidewalls of the package assembly 40. According to some embodiments of this disclosure, the etch stop layer is formed of a nitride-containing material (e.g., silicon nitride). The deposition of the etch stop layer may include a conformal deposition process, such as ALD or CVD. The dielectric material deposited on the etch stop layer may be formed of or contain silicon oxide. According to alternative embodiments, the gap-filling region 64 is formed of a molding compound, epoxy resin, resin, and / or the like.

[0038] refer to Figure 10 A planarization process, such as CMP or mechanical polishing, is performed to make the rear surface of the package assembly 40 (the top surface shown) flush with the top surface of the gap-filling region 64. Figure 34 As shown, the corresponding process is illustrated as process 218 in process flow 200. The planarization process is stopped after the bonding pads 62 and dielectric layer 60 are exposed. Throughout the description, the package assembly 40 and the gap fill region 64 are collectively referred to as the reconstructed wafer 66. When viewed in a top view of the reconstructed wafer 66, the gap fill region 64 surrounds the corresponding package assembly 40.

[0039] Figure 11A , Figure 11B , Figure 11C and Figure 12 Cross-sectional and perspective views are shown of an intermediate stage in bonding the second-layer packaging component 68 to the reconstructed wafer 66. Figure 34 As shown, the corresponding process is illustrated as process 220 in process flow 200. Although a set of package components 68 comprising two package components 68 is shown as an example, multiple sets of package components 68 can be individually bonded to one package component 40 of the reconstructed wafer 66. The bonding of the package components 68 to the reconstructed wafer 66 can be achieved through hybrid bonding, wherein metal-to-metal direct bonding (between bonding pads 62 and 74) and dielectric-to-dielectric bonding (e.g., Si-O-Si bonding between surface dielectric layers 76 and 60) are formed. Furthermore, single or multiple package components 68 can be bonded to the same package component 40. Multiple package components 68 bonded to the same package component 40 can be identical or different from each other.

[0040] According to some embodiments, package assembly 68 includes a device die therein and may include other package components such as internal components, packages, die stacks, etc. According to some embodiments, package assembly 68 includes logic dies, memory dies, isolated passive devices (IPDs), etc. According to some embodiments, package assembly 68 includes a semiconductor substrate 70, an integrated circuit device 72, pads 74, and a dielectric layer 76.

[0041] Figure 11B A perspective view of the illustrated composite carrier 34, multiple tier-1 encapsulation components 40, and multiple tier-2 encapsulation components 68 is shown. Figure 11C An enlarged view of a first-layer encapsulation component 40 and a corresponding second-layer encapsulation component 68 bonded thereto is shown.

[0042] Figure 12 The gap filling of the encapsulation component 68 in the gap filling region 78 is shown. (As shown) Figure 34As shown, the corresponding process is illustrated as process 222 in process flow 200. The gap-filling region 78 may be formed of or comprise (one or more) dielectric materials selected from the same group of candidate materials for forming the gap-filling region 64. For example, the gap-filling region 78 may include a dielectric liner (e.g., a SiN liner) and a dielectric region (e.g., a SiO2 region) situated above the dielectric liner. Alternatively, the gap-filling region 78 may include molding compounds, epoxy resins, resins, etc. A planarization process is performed to make the top surface of the gap-filling region 78 flush with the rear surface of the package assembly 68.

[0043] Refer again Figure 12 A bonding layer 80 is deposited on top of the gap-filling regions 78 and the package assembly 68. According to some embodiments, the bonding layer 80 is formed of a silicon-containing dielectric material, which may be selected from SiO2, SiON, SiN, SiOCN, SiCN, SiOC, SiC, etc. Throughout the description, the structure including the package assemblies 40 and 68, the gap-filling regions 64 and 78, and the bonding layer 80 is collectively referred to as the reconstructed wafer 82.

[0044] refer to Figure 13 The composite carrier 34' is bonded to the reconstructed wafer 82 via fusion bonding. For example... Figure 34 As shown, the corresponding process is illustrated as process 224 in process flow 200. According to some embodiments, the composite carrier 34' has a structure similar to (or identical to) the composite carrier 34 and includes a substrate carrier 20', layer 22', layer 24', layer 26', and bonding layer 32'. The materials of the substrate carrier 20', layer 22', layer 24', layer 26', and bonding layer 32' can be selected from the candidate material group of carrier 20, layer 22, layer 24, layer 26, and bonding layer 32, respectively. Therefore, layer 24', layer 26', and bonding layer 32' can be formed of or contain similar materials. The materials of the substrate carrier 20', layer 22', layer 24', layer 26', and bonding layer 32' can also be the same as the materials of carrier 20, layer 22, layer 24, layer 26, and bonding layer 32, respectively.

[0045] According to an alternative embodiment, the composite carrier 34' has a different structure from the composite carrier 34. For example, the materials of the substrate carrier 20', layer 22', layer 24', and layer 26', and bonding layer 32' can be selected from a different group of candidate materials than the respective substrate carrier 20, layer 22, layer 24, and layer 26, and bonding layer 32. According to some embodiments, layer 26' is formed of a material different from the materials of layer 24' and bonding layer 32'. For example, layers 24', 26', and 32' can be formed of SiN, SiO2, and SiON, respectively. Although this means that if the composite carrier 34' requires five CMP processes to remove, with each of the substrate carrier 20', layer 22', layer 24', and layer 26', and bonding layer 32' requiring one CMP process, this does not result in an increase in manufacturing costs when the composite carrier 34' is not removed.

[0046] Figure 14 , Figure 15 and Figure 16 Three CMP processes for removing composite carrier 34 are shown. (Reference) Figure 14 Perform the first CMP process 84 to remove the substrate carrier 20. For example... Figure 34 As shown, the corresponding process is represented as process 226 in process flow 200. Layer 22 is formed of a material different from that of the substrate 20. Furthermore, a suitable slurry is selected so that the CMP rate for removing the substrate 20 is significantly greater than the CMP rate for removing layer 22. Therefore, the first CMP process 84 stops at layer 22. Next, refer to... Figure 15 Then, perform the second CMP process 86 to remove layer 22. For example... Figure 34 As shown, the corresponding process is represented as process 228 in process flow 200. Layer 24 is formed of a material different from that of layer 22. Furthermore, a suitable slurry is selected so that the CMP rate for removing layer 22 is significantly greater than the CMP rate for removing layer 24. Therefore, the second CMP process 86 stops at layer 24.

[0047] refer to Figure 16 The third CMP process 88 is performed to remove layers 24 and 26, bonding layer 32, and alignment mark 30. (As...) Figure 34 As shown, the corresponding process is represented as process 230 in process flow 200. Layers 24 and 26, as well as bonding layer 32, are formed of similar materials, which differ from the material of bonding layer 58. Furthermore, a suitable slurry is selected such that the CMP rate for removing layers 24 and 26, and bonding layer 32, is significantly greater than the CMP rate for removing dielectric bonding layer 58, such that the third CMP process 88 terminates on dielectric bonding layer 58. The slurries used in the first, second, and third CMP processes can be different from each other.

[0048] According to some embodiments of this disclosure, since layers 24 and 26, as well as bonding layer 32, are formed of similar materials, three CMP processes are used to remove the composite carrier 34. This differs from the removal of a conventional composite carrier, in which layer 26 is formed of a different material than layers 24 and bonding layer 32. Therefore, in the removal of a conventional composite carrier, each of layers 24, 26, and 32 requires a separate CMP process, and a total of five CMP processes are required.

[0049] In the exemplary embodiments discussed above, the dielectric bonding layer 58 may be a monolayer formed of a homogeneous material, which remains unremoved during the third CMP process. According to an alternative embodiment, the dielectric bonding layer 58 includes a lower layer 58A serving as the bonding layer and an upper layer 58B for stopping the third CMP process. The lower layer 58B is formed of a material similar to that of the bonding layer 32. The upper layer 58B is formed of a material different from that of the lower layer 58A and layers 24, 26, and 32. Therefore, in the third CMP process, the lower layer 58A is also removed to expose the upper layer 58B. The resulting structure is also similar to... Figure 16 The structure shown.

[0050] Figure 17 The pad opening process is illustrated, wherein an opening 90 is formed in the dielectric bonding layer 58 to expose the bonding pad 56. (See diagram) Figure 34 As shown, the corresponding process is illustrated as process 232 in process flow 200. According to some embodiments, the opening 90 is formed by a photolithography process, and the dielectric bonding layer 58 is etched to form the opening 90, wherein the metal pads 56 are exposed to the opening 90.

[0051] Figure 18 The formation of the electrical connector 92 is shown. (As shown) Figure 34 As shown, the corresponding process is illustrated as process 234 in process flow 200. According to some embodiments, the electrical connector 92 includes a solder region that can be formed by placing solder balls in an opening 90 and then reflowing the solder balls as the solder region. According to an alternative embodiment, the electrical connector 92 includes metal pillars that can be formed by electroplating.

[0052] Figure 18 The structure shown is referred to as reconstructed wafer 94. A separation process can be performed to saw the reconstructed wafer 94 along scribing line 96 and form discrete packages 94' that are identical to each other. Figure 34As shown, the corresponding process is illustrated as process 236 in process flow 200. Each discrete package 94' includes a portion of a composite carrier 34'. According to an alternative embodiment, the composite carrier 34' is removed prior to the separation process. Removal can be performed by three CMP processes. The substrate carrier 20' and layer 22' can be removed in the first CMP process and the second CMP process, respectively. Layers 24', 26', and 32' can be removed in the third CMP process. The bonding layer 80 can be removed by the third CMP process, or the bonding layer 80 may not be removed.

[0053] Figure 19 The bonding of package 94' to package component 98 is shown to form package 100. (See diagram) Figure 34 As shown, the corresponding process is illustrated as process 238 in process flow 200. The packaging assembly 98 may be a packaging substrate, an internal component, a package, etc. Bottom filler 102 is distributed between package 94' and packaging assembly 98. According to some embodiments, package 100 includes a composite carrier 34'. According to packaging assembly 40 ( Figure 18 This is one embodiment of an uncut wafer portion in which the resulting package 100 lacks gap fill region 64, and the edge of package assembly 40 is a portion of the edge of package 100. It will be appreciated that this composite carrier 34' may not include alignment marks 30, as the alignment marks 30 may have been removed during the separation process. According to an alternative embodiment where the composite carrier 34' has been removed, the top surface of substrate 70 may be exposed.

[0054] Figure 20 , Figure 21 , Figure 22A , Figure 22B , Figure 22C and Figure 23-27 A cross-sectional view of an intermediate stage in forming a package according to an alternative embodiment of the present disclosure is shown. These embodiments are similar to those shown in the preceding process, except that in each package, two second-layer package components 68 are bonded to two first-layer package components 40, instead of two second-layer package components 68 being bonded to the same first-layer package component 40. Unless otherwise specified, the materials, structure, and formation process of the components in these embodiments are substantially the same as those of similar components indicated by the same reference numerals in the preceding embodiments. Therefore, regarding Figure 20 , Figure 21 , Figure 22A , Figure 22B , Figure 22C and Figure 23-27 (and the subsequent discussion) Figure 28 , Figure 29A , Figure 29B and Figures 30-33The details of the formation process, structure, and materials of the components shown can be found in the discussion of the preceding embodiments.

[0055] The initial steps of these embodiments are basically the same as Figures 1 to 7 The same as shown, wherein a composite carrier 34 is formed. Next, as... Figure 20 As shown, multiple first-layer encapsulation components 40 are bonded to the composite carrier 34 via fusion bonding. The structure of the encapsulation components 40 is substantially the same as that in the reference design. Figure 8 The discussion is the same and will not be repeated here. Next, as... Figure 21 As shown, a gap-filling region 64 is formed. This forms a reconstructed wafer 66.

[0056] Figure 22A The bonding between the second-layer package assembly 68 and the lower first-layer package assembly 40 is shown. A gap-filling region 78 is then formed, followed by the bonding layer 80. This forms the reconstructed wafer 82. Figure 22B The illustration shows a perspective view of a composite carrier 34, a plurality of first-layer encapsulation components 40, and a plurality of encapsulation components 68, each of which is bonded to a lower-layer encapsulation component 40. Figure 22C An enlarged view of a set of first-layer encapsulation components 40 and corresponding second-layer encapsulation components 68 bonded thereto is shown.

[0057] Figures 23 to 27 The remaining processes for forming package 100 according to some embodiments are illustrated. Reference Figure 13-19 The processes shown can be found in detail for these processes and their corresponding components, and these details will not be repeated in this article. Figure 23 The bonding between the composite carrier 34' and the reconstructed wafer 82 is shown. Figure 24 , Figure 25 and Figure 26 Three CMP processes, 84, 86 and 88, are shown for removing the composite carrier 34. Figure 27 The resulting package 100 is shown.

[0058] Figure 28 , Figure 29A , Figure 29B and Figures 30-33 Cross-sectional and perspective views of intermediate stages in the formation of a package according to some embodiments of the present disclosure are shown. These embodiments are similar to those shown in the preceding process, except that the first and second layer package components are wafer-level package components, and no composite carrier is bonded to the second layer package component.

[0059] The initial steps of these embodiments are basically the same as Figures 1 to 7 The same as shown, wherein a composite carrier 34 is formed. Next, as... Figure 28As shown, wafer 40' is bonded to composite carrier 34 by wafer-to-wafer bonding (also by fusion bonding). Wafer 40' includes a plurality of packaging components 40, which are identical to each other, and the packaging components 40 may be device dies according to some embodiments. Figure 28 One of the packaging components 40 representing wafer 40' is shown. According to some embodiments, there is no gap fill region around wafer 40. According to an alternative embodiment, a gap fill region 64 is formed to surround wafer 40'. Therefore, the gap fill region 64 is shown as a dashed line to indicate that it may or may not be formed.

[0060] Figure 29A The bonding of wafer 68' to wafer 40' is shown. According to some embodiments, bonding is performed using hybrid bonding. Wafer 68' may be an unsaved device wafer or a reconstructed wafer having discrete device dies packaged therein. Wafer 68' includes a plurality of identical package assemblies 68. Figure 29B A perspective view showing the composite carrier 34, wafer 40', and wafer 68' is shown.

[0061] Figures 30 to 33 The remaining processes for forming package 100 according to some embodiments are shown. Details of these processes and corresponding components can be found in processes 13-19, and will not be repeated herein. Figure 30 , Figure 31 and Figure 32 Three CMP processes 84, 86, and 88 are shown for removing the composite carrier 34. Details of CMP processes 84, 86, and 88 have been discussed in the previously discussed embodiments and will not be repeated herein. Figure 33 The resulting package 100 is shown.

[0062] In the embodiments shown above, some processes and features for forming a three-dimensional (3D) package are discussed according to some embodiments of this disclosure. Other features and processes may also be included. For example, test structures may be included to aid in the verification testing of the 3D package or 3D IC device. Test structures may include, for example, test pads formed in a redistribution layer or on a substrate, which allow testing of the 3D package or 3D IC using probes and / or probe cards, etc. Verification tests can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be used in conjunction with test methods that include intermediate verification of known good dies to increase yield and reduce costs.

[0063] The embodiments of this disclosure have several advantageous features. Some layers of the composite carrier are formed using similar materials that differ from the bonding layer materials in another packaging assembly bonded to the reconstructed wafer. Therefore, these layers of the composite carrier can be removed in the same CMP process, thereby reducing manufacturing costs. While the materials of these layers are similar, they may also differ slightly from each other to meet different requirements, such as improving CMP stopping capability and increasing bond strength.

[0064] According to some embodiments of this disclosure, a method includes: bonding a first encapsulation assembly to a first composite carrier; performing a first polishing process on the first composite carrier to remove a substrate carrier of the first composite carrier, wherein the first polishing process stops at a first layer of the first composite carrier; performing a second polishing process to remove the first layer of the first composite carrier, wherein the second polishing process stops at a second layer of the first composite carrier; and performing a third polishing process to remove a plurality of layers in the first composite carrier, wherein the plurality of layers includes the second layer, and wherein the third polishing process stops at a dielectric layer in the first encapsulation assembly. In one embodiment, the plurality of layers removed by the third polishing process includes three layers. In one embodiment, the third polishing process includes: removing the second layer; removing the third layer and alignment marks in the third layer; and removing a fourth layer physically bonded to the first encapsulation assembly. In one embodiment, the third layer and the fourth layer are formed of the same material different from the material of the second layer, and the third polishing process is performed using the same slurry to remove the second layer, the third layer, and the fourth layer. In one embodiment, each of the first polishing process, the second polishing process, and the third polishing process includes a chemical mechanical polishing process. In one embodiment, the method further includes: sealing the first packaging assembly in a first seal, wherein the first seal contacts a sidewall of the dielectric layer in the first packaging assembly, and wherein the third polishing process exposes the first seal. In one embodiment, the method further includes: bonding a second packaging assembly to the first packaging assembly; bonding a second composite carrier to the second packaging assembly; and sawing the second composite carrier to form a package, wherein the package includes the first packaging assembly, the second packaging assembly, and a piece of the second composite carrier. In one embodiment, the second composite carrier is identical to the first composite carrier. In one embodiment, the second composite carrier and the first composite carrier have different structures. In one embodiment, the method further includes: bonding a device wafer to the first packaging assembly; and after the third polishing process, sawing the device wafer to form a package, wherein the package includes the first packaging assembly and a device die in the device wafer.

[0065] According to some embodiments of this disclosure, a structure includes a composite carrier comprising: a silicon substrate carrier; an oxide-based layer disposed on the silicon substrate carrier; a first nitride-based layer disposed on the oxide-based layer; a second nitride-based layer disposed on the first nitride-based layer; and a third nitride-based layer disposed on the second nitride-based layer, wherein a first material of the first nitride-based layer is different from a second material of the second nitride-based layer and a third material of the third nitride-based layer. In one embodiment, each of the silicon substrate carrier, the oxide-based layer, the first nitride-based layer, and the third nitride-based layer is a homogeneous layer. In one embodiment, the structure further includes alignment marks in the second nitride-based layer. In one embodiment, the alignment marks extend from the top surface of the second nitride-based layer to an intermediate level between the top and bottom surfaces of the second nitride-based layer. In one embodiment, the alignment marks penetrate the second nitride-based layer. In one embodiment, there are distinguishable interfaces between the first nitride-based layer, the second nitride-based layer, and the third nitride-based layer. In one embodiment, the structure further includes an encapsulation component comprising: a surface dielectric layer bonded to the third nitride-based layer, wherein the surface dielectric layer and the oxide-based layer are formed of the same dielectric material.

[0066] According to some embodiments of this disclosure, a structure includes a composite carrier comprising: a substrate carrier; a silicon oxide layer disposed on and in contact with the substrate carrier; a silicon nitride layer disposed on and in contact with the silicon oxide layer; a first silicon oxynitride layer disposed on and in contact with the silicon nitride layer; and a second silicon oxynitride layer disposed on and in contact with the first silicon oxynitride layer. The structure further includes an encapsulation assembly disposed on and bonded to the composite carrier, wherein the encapsulation assembly includes the second silicon oxide layer and is bonded to the second silicon oxynitride layer. In one embodiment, the encapsulation assembly further includes a semiconductor substrate spaced apart from the silicon oxide layer. In one embodiment, the encapsulation assembly further includes a semiconductor substrate in solid contact with the silicon oxide layer.

[0067] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0068] Example 1 is a method of forming a semiconductor structure, comprising: bonding a first packaging component to a first composite carrier; performing a first polishing process on the first composite carrier to remove a substrate carrier of the first composite carrier, wherein the first polishing process stops at a first layer of the first composite carrier; performing a second polishing process to remove the first layer of the first composite carrier, wherein the second polishing process stops at a second layer of the first composite carrier; and performing a third polishing process to remove a plurality of layers in the first composite carrier, wherein the plurality of layers includes the second layer, and wherein the third polishing process stops at a dielectric layer in the first packaging component.

[0069] Example 2 is the method described in Example 1, wherein the plurality of layers removed by the third polishing process comprises three layers.

[0070] Example 3 is the method described in Example 2, wherein the third polishing process includes: removing the second layer; removing the third layer and alignment marks in the third layer; and removing the fourth layer that is physically bonded to the first encapsulation component.

[0071] Example 4 is the method described in Example 3, wherein the third layer and the fourth layer are formed of the same material, different from the material of the second layer, and the same slurry is used to perform the third polishing process to remove the second layer, the third layer, and the fourth layer.

[0072] Example 5 is the method described in Example 1, wherein each of the first polishing process, the second polishing process, and the third polishing process includes a chemical mechanical polishing process.

[0073] Example 6 is the method of Example 1, further comprising: sealing the first encapsulation assembly in a first seal, wherein the first seal contacts a sidewall of the dielectric layer in the first encapsulation assembly, and wherein the third polishing process exposes the first seal.

[0074] Example 7 is the method of Example 1, further comprising: bonding a second encapsulation component to the first encapsulation component; bonding a second composite carrier to the second encapsulation component; and sawing the second composite carrier to form an encapsulation, wherein the encapsulation includes the first encapsulation component, the second encapsulation component, and a piece of the second composite carrier.

[0075] Example 8 is the method described in Example 7, wherein the second composite carrier is the same as the first composite carrier.

[0076] Example 9 is the method described in Example 7, wherein the second composite carrier and the first composite carrier have different structures.

[0077] Example 10 is the method of Example 1, further comprising: bonding a device wafer to the first packaging assembly; and, after the third polishing process, sawing the device wafer to form a package, wherein the package includes the first packaging assembly and a device die in the device wafer.

[0078] Example 11 is a semiconductor structure comprising: a composite carrier including: a silicon substrate carrier; an oxide-based layer on the silicon substrate carrier; a first nitride-based layer on the oxide-based layer; a second nitride-based layer on the first nitride-based layer; and a third nitride-based layer on the second nitride-based layer, wherein a first material of the first nitride-based layer is different from a second material of the second nitride-based layer and a third material of the third nitride-based layer.

[0079] Example 12 is the structure described in Example 11, wherein each of the silicon substrate carrier, the oxide-based layer, the first nitride-based layer, and the third nitride-based layer is a homogeneous layer.

[0080] Example 13 is the structure described in Example 11, and further includes: alignment marks located in the second nitride-based layer.

[0081] Example 14 is the structure described in Example 13, wherein the alignment mark extends from the top surface of the second nitride-based layer to an intermediate level between the top and bottom surfaces of the second nitride-based layer.

[0082] Example 15 is the structure described in Example 13, wherein the alignment mark penetrates the second nitride-based layer.

[0083] Example 16 is the structure described in Example 11, wherein there is a distinguishable interface between the first nitride-based layer, the second nitride-based layer and the third nitride-based layer.

[0084] Example 17 is the structure described in Example 11, and further includes an encapsulation component comprising: a surface dielectric layer bonded to the third nitride-based layer, wherein the surface dielectric layer and the oxide-based layer are formed of the same dielectric material.

[0085] Example 18 is a semiconductor structure comprising: a composite carrier including: a substrate carrier; a silicon oxide layer disposed on and in contact with the substrate carrier; a silicon nitride layer disposed on and in contact with the silicon oxide layer; a first silicon oxynitride layer disposed on and in contact with the silicon nitride layer; and a second silicon oxynitride layer disposed on and in contact with the first silicon oxynitride layer; and a packaging assembly disposed on and bonded to the composite carrier, wherein the packaging assembly includes: a second silicon oxide layer bonded to the second silicon oxynitride layer.

[0086] Example 19 is the structure described in Example 18, wherein the packaging assembly further includes a semiconductor substrate spaced apart from the silicon oxide layer.

[0087] Example 20 is the structure described in Example 18, wherein the packaging assembly further includes a semiconductor substrate in contact with the silicon oxide layer entity.

Claims

1. A method for forming a semiconductor structure, comprising: The first encapsulation component is bonded to the first composite carrier; A first polishing process is performed on the first composite carrier to remove the substrate carrier of the first composite carrier, wherein the first polishing process stops on the first layer of the first composite carrier; Perform a second polishing process to remove the first layer of the first composite carrier, wherein the second polishing process stops at the second layer of the first composite carrier; and A third polishing process is performed to remove multiple layers in the first composite carrier, wherein the multiple layers include the second layer, and wherein the third polishing process stops at the dielectric layer in the first packaging assembly.

2. The method according to claim 1, wherein, The plurality of layers removed by the third polishing process includes three layers.

3. The method according to claim 2, wherein, The third polishing process includes: Remove the second layer; Remove the alignment marks in the third layer and the third layer; and Remove the physical bond to the fourth layer of the first encapsulation component.

4. The method according to claim 3, wherein, The third and fourth layers are formed of the same material, different from the material of the second layer, and the same slurry is used to perform the third polishing process to remove the second, third, and fourth layers.

5. The method according to claim 1, wherein, Each of the first polishing process, the second polishing process, and the third polishing process includes a chemical mechanical polishing process.

6. The method according to claim 1, further comprising: The first encapsulation assembly is sealed in a first seal, wherein the first seal contacts the sidewall of the dielectric layer in the first encapsulation assembly, and wherein the third polishing process exposes the first seal.

7. The method according to claim 1, further comprising: The second encapsulation component is bonded to the first encapsulation component; The second composite carrier is bonded to the second encapsulation component; as well as The second composite carrier is sawn to form an encapsulation, wherein the encapsulation includes the first encapsulation component, the second encapsulation component, and a piece of the second composite carrier.

8. The method according to claim 7, wherein, The second composite carrier is the same as the first composite carrier.

9. The method according to claim 7, wherein, The second composite carrier and the first composite carrier have different structures.

10. The method according to claim 1, further comprising: The device wafer is bonded to the first packaging assembly; as well as After the third polishing process, the device wafer is sawn to form a package, wherein the package includes the first packaging assembly and the device die in the device wafer.

11. A semiconductor structure, comprising: Composite carrier, including: Silicon substrate carrier; An oxide-based layer is located on the silicon substrate carrier; A first nitride-based layer is situated on top of the oxide-based layer; A second nitride-based layer is situated on top of the first nitride-based layer; and A third nitride-based layer is situated on top of the second nitride-based layer, wherein the first material of the first nitride-based layer is different from the second material of the second nitride-based layer and the third material of the third nitride-based layer, and wherein the second material of the second nitride-based layer and the third material of the third nitride-based layer comprise the same elements, and the percentage of elements in the second material is different from the percentage of elements in the third material.

12. The structure according to claim 11, wherein, Each of the silicon substrate carrier, the oxide-based layer, the first nitride-based layer, and the third nitride-based layer is a homogeneous layer.

13. The structure according to claim 11, further comprising: Alignment marks are located in the second nitride-based layer.

14. The structure according to claim 13, wherein, The alignment mark extends from the top surface of the second nitride-based layer to an intermediate level between the top and bottom surfaces of the second nitride-based layer.

15. The structure according to claim 13, wherein, The alignment mark penetrates the second nitride-based layer.

16. The structure according to claim 11, wherein, The first nitride-based layer, the second nitride-based layer, and the third nitride-based layer have distinguishable interfaces.

17. The structure of claim 11, further comprising an encapsulation component, the encapsulation component comprising: A surface dielectric layer is bonded to the third nitride-based layer, wherein the surface dielectric layer and the oxide-based layer are formed of the same dielectric material.

18. A semiconductor structure comprising: Composite carrier, including: Substrate carrier; A silicon oxide layer is located on and in contact with the substrate carrier; A silicon nitride layer is located on top of and in contact with the silicon oxide layer; A first silicon oxynitride layer is located above and in contact with the silicon nitride layer; and A second silicon oxynitride layer is located above and in contact with the first silicon oxynitride layer, wherein the percentage of elements in the first silicon oxynitride layer is different from the percentage of elements in the second silicon oxynitride layer; and An encapsulation component, located on and bonded to the composite carrier, wherein the encapsulation component includes: The second silicon oxide layer is bonded to the second silicon oxynitride layer.

19. The structure according to claim 18, wherein, The packaging assembly also includes a semiconductor substrate spaced apart from the silicon oxide layer.

20. The structure according to claim 18, wherein, The packaging assembly also includes a semiconductor substrate in contact with the silicon oxide layer.

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