Semiconductor devices and manufacturing methods

Abstract

A semiconductor device and manufacturing method are proposed, wherein a gate dielectric is processed in an analog region of a semiconductor substrate. The gate dielectric can be processed using plasma exposure and / or annealing processes to form a recovery region of the gate dielectric. A separate gate dielectric is formed in a logic region of the semiconductor substrate, and a first gate electrode and a second gate electrode are formed on the gate dielectric.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more particularly to semiconductor devices and manufacturing methods. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that need to be addressed. Summary of the Invention

[0004] According to one aspect of this application, a method for manufacturing a semiconductor device is provided, the method comprising: depositing a first dielectric layer over a logic region and an analog region of a semiconductor substrate; processing the first dielectric layer to form a recovery layer; removing a first portion of the recovery layer from the logic region after processing the first dielectric layer; forming a second dielectric layer in the logic region; and depositing a gate electrode material over the remaining portion of the recovery layer and the second dielectric layer.

[0005] According to another aspect of this application, a method for manufacturing a semiconductor device is provided, the method comprising: depositing a first dielectric layer of uniform thickness over a first region of a substrate and a second region of a substrate; exposing the top surface of the first dielectric layer to a first plasma to form a processed region over an unprocessed region of the first dielectric layer; recovering the processed region using a first annealing process to form a recovered region over the unprocessed region; removing the first dielectric layer from the first region; forming a second dielectric layer in the first region; forming a first gate electrode over the first dielectric layer in the second region; and forming a second gate electrode over the second dielectric layer in the first region.

[0006] According to another aspect of this application, a semiconductor device is provided, comprising: a logic device located in a logic region of a substrate, the logic device including: a first dielectric layer having a constant density throughout the first dielectric layer; and a first gate electrode on the first dielectric layer; and an analog device located in an analog region of the substrate, the analog device including: a second dielectric layer including a recovery region and an unprocessed region, the recovery region having a different density than the unprocessed region; and a second gate electrode on the second dielectric layer. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood by reading in conjunction with the accompanying drawings through the following detailed description. It should be noted that, according to standard industry practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily enlarged or reduced.

[0008] Figure 1 The logic and analog regions of a substrate according to some embodiments are shown.

[0009] Figure 2 The formation of a first well according to some embodiments is shown.

[0010] Figure 3 The formation of a second well according to some embodiments is shown.

[0011] Figure 4 The formation of a first dielectric layer according to some embodiments is shown.

[0012] Figure 5 A first processing of the first dielectric layer according to some embodiments is shown.

[0013] Figure 6 An annealing process according to some embodiments is shown.

[0014] Figure 7 The removal of the first dielectric layer from a logic region is illustrated according to some embodiments.

[0015] Figure 8 A second dielectric layer is shown formed in a logic region according to some embodiments.

[0016] Figure 9 The formation of a first gate electrode and a second gate electrode according to some embodiments is shown.

[0017] Figure 10 The formation of a spacer according to some embodiments is shown.

[0018] Figure 11AThe formation of source / drain regions and silicide regions according to some embodiments is shown.

[0019] Figure 11B A graph illustrating the normalized current noise spectral density is shown according to some embodiments.

[0020] Figure 12 A back gate process according to some embodiments is shown.

[0021] Figure 13 Another post-gate process with a different sequence of process steps is shown according to some embodiments. Detailed Implementation

[0022] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0023] In addition, this document may use spatially related terms (e.g., "below," "under," "down," "above," "up," etc.) to facilitate the description of the relationship between one element or feature shown in the accompanying drawings and another element(s) or feature(s). These spatially related terms are intended to cover devices in use or operation in orientations other than those shown in the accompanying drawings. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted similarly.

[0024] Embodiments will now be described with respect to specific examples in which flicker noise in analog devices (e.g., in analog-to-digital devices for LCD panels) is reduced by processing the gate dielectric. However, the described embodiments are not intended to limit the ideas presented, and these ideas can be implemented in a variety of other embodiments. All of these embodiments are fully intended to be included within the scope of this disclosure.

[0025] Now for reference Figure 1The image shows a substrate 101 in which shallow trench isolation (STI) 103 is formed. The substrate 101 may comprise doped or undoped bulk silicon, or an active layer of a silicon-on-insulator (SOI) substrate. Typically, an SOI substrate comprises a layer of semiconductor material, such as silicon, germanium, silicon-germanium, SOI, silicon-germanium-on-insulator (SGOI), or combinations thereof. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0026] Additionally, substrate 101 may have a logic region 105 and an analog region 107. Devices subsequently formed in logic region 105 will be used to create logic devices, while devices subsequently formed in analog region 107 will be used to create analog devices. In some embodiments, logic region 105 may be adjacent to analog region 107, while in other embodiments, logic region 105 may be located away from analog region 107 (in... Figure 1 (Represented by the dashed line marked 109).

[0027] The STI 103 can be formed by etching the substrate 101 to create trenches and filling the trenches with a dielectric material known in the art. For example, the STI 103 can be filled with a dielectric material such as an oxide material or a high-density plasma (HDP) oxide. However, any suitable material and any suitable deposition method can be used.

[0028] Figure 2 The formation of a first well 203 in analog region 107 is illustrated. To begin creating the first well 203 in analog region 107, logic region 105 is first protected. In one embodiment, logic region 105 can be protected by placing a first photoresist 205 on substrate 101 and imaging the photoresist to create a difference between exposed and unexposed areas. Once the first photoresist 205 has been imaged, it is developed to remove the portion of the first photoresist 205 above analog region 107 and retain the portion of the first photoresist 205 above logic region 105, thereby protecting logic region 105.

[0029] Once logic region 105 is protected, a first well 203 can be created in analog region 107 by placing a first dopant into substrate 101. The first dopant can be a dopant suitable for the type of device to be manufactured. For example, in embodiments where the device to be formed is an n-type device, the first dopant can be a p-type dopant, such as boron, aluminum, gallium, indium, or combinations thereof. In other embodiments where the device to be formed is a p-type device, the first dopant can be an n-type dopant, such as phosphorus, arsenic, antimony, or combinations thereof. However, any suitable dopant can be used.

[0030] In one embodiment, a first injection process (in) can be used, for example, Figure 2 The first dopant is implanted into the substrate 101 by means of an arrow marked 201. In this embodiment, ions forming the first dopant are then accelerated toward the top surface of the substrate 101, thereby implanting the first dopant ions into the substrate 101. However, any suitable method for implanting the first dopant can be used.

[0031] Once the first dopant has been implanted into the substrate 101 to form the first well 203, the first photoresist 205 is removed. In one embodiment, an ashing process can be used to remove the first photoresist 205, in which the temperature of the first photoresist 205 is raised until the first photoresist 205 undergoes thermal decomposition and can be easily removed. However, any suitable method or combination of methods, such as wet etching, can also be used.

[0032] Figure 3 It is shown that once a first well 203 is formed in analog region 107, a second well 303 is formed in logic region 105. To begin creating the second well 303 in logic region 105, analog region 107 is first protected. In one embodiment, analog region 107 can be protected by placing a second photoresist 305 on substrate 101 and imaging the second photoresist 305 to create a difference between exposed and unexposed areas. Once the second photoresist 305 is exposed, it is developed to remove the portion of the second photoresist 305 above logic region 105 and retain the portion of the second photoresist 305 above analog region 107, thereby protecting analog region 107.

[0033] Once the analog region 107 is protected, a second well 303 can be created in the logic region 105 by placing a second dopant into the substrate 101. The second dopant can be a dopant suitable for the type of device to be fabricated. For example, in embodiments where the device to be formed is an n-type device, the second dopant can be a p-type dopant, such as boron, aluminum, gallium, indium, or combinations thereof. In other embodiments where the device to be formed is a p-type device, the second dopant can be an n-type dopant, such as phosphorus, arsenic, antimony, or combinations thereof. However, any suitable dopant can be used.

[0034] Furthermore, any suitable combination of devices between logic region 105 and analog region 107 can be used. For example, if the device formed in logic region 105 is an n-type device, then the device formed in analog region 107 can be either an n-type device or a p-type device. Similarly, if the device formed in logic region 105 is a p-type device, then the device formed in analog region 107 can be either an n-type device or a p-type device. Any suitable combination of devices can be used.

[0035] In one embodiment, a second injection process (in) can be used, for example. Figure 3 The second dopant is implanted into the substrate 101 by means of an arrow marked 301. In this embodiment, ions forming the second dopant are then accelerated toward the top surface of the substrate 101, thereby implanting the second dopant ions into the substrate 101. In one embodiment, the second dopant in the logic region 105 is implanted to have a higher concentration than the first dopant implanted in the analog region 107. For example, the first dopant may have a first concentration in the first well 203, which is approximately 1.0 × 10⁻⁶. 14 cm -3 From approximately 1.0 × 10 18 cm -3 The second dopant can have a second concentration in the second well 303 that is greater than the first concentration, which is approximately 1.0 × 10⁻⁶. 14 cm -3 From approximately 1.0 × 10 18 cm -3 However, any suitable method for implanting the second dopant and any suitable concentration of the first and second dopant can be used.

[0036] Once the second dopant has been implanted into the substrate 101 to form the second well 303, the second photoresist 305 is removed. In one embodiment, an ashing process can be used to remove the second photoresist 305, in which the temperature of the second photoresist 305 is raised until the second photoresist 305 undergoes thermal decomposition and can be easily removed. However, any suitable method or combination of methods, such as wet etching, can also be used.

[0037] Figure 4 The diagram illustrates the deposition of a first dielectric layer 401 on a substrate 101 to initiate the formation of the gate dielectric of a device in an analog region 107. The first dielectric layer 401 may be a high-k dielectric material, such as silicon oxide, silicon oxynitride, silicon nitride, oxides, nitrogen-containing oxides, aluminum oxide, lanthanum oxide, hafnium oxide, zirconium oxide, hafnium oxynitride, or combinations thereof. The first dielectric layer 401 may have a relative permittivity greater than about 4.

[0038] In embodiments where the first dielectric layer 401 includes an oxide layer, the first dielectric layer 401 can be formed by any oxidation process (e.g., wet or dry thermal oxidation in an environment containing oxides, H2O, NO, or combinations thereof), or by chemical vapor deposition (CVD) using tetraethyl orthosilicate (TEOS) and oxygen as precursors. In one embodiment, the first dielectric layer 401 may have a first thickness T1, which is approximately [missing information - likely a value]. to approximately Between, for example, thickness is

[0039] In other embodiments where the first dielectric layer 401 is a metal oxide such as hafnium oxide, a deposition process can be used to deposit the first dielectric layer 401. For example, atomic layer deposition, chemical vapor deposition, physical vapor deposition, or combinations thereof can be used to deposit the first dielectric layer 401. However, any suitable deposition method can be used.

[0040] Figure 5 It is shown that once the first dielectric layer 401 is deposited, the first dielectric layer 401 is processed. In one embodiment, this processing may be plasma processing (in... Figure 5 (Represented by the cloud labeled 501), through this process, the first dielectric layer 401 is exposed to plasma from one or more plasma precursors, which helps reduce flicker noise within the device formed in the simulation region 107. In a particular embodiment, the plasma precursor may be a precursor such as oxygen, nitrogen, fluorine, chlorine, or a combination thereof, but any suitable precursor may be used.

[0041] To initiate plasma treatment 501, the flow rate of the plasma precursor can be set from about 10 sccm to about 100 sccm, and the pressure of plasma treatment 501 can be from about 10 mTorr to about 10 Torr. The temperature of plasma treatment 501 can be set from about 400°C to about 800°C. The power of the plasma generator for plasma treatment 501 can be from about 5 W to about 500 W, and the frequency of the plasma generator can be about 13.56 MHz or higher. During plasma treatment 501, the substrate 101 can be biased from about 0.5 V to about 500 V. However, any suitable process parameters can be used.

[0042] During plasma treatment 501, plasma materials can damage exposed surfaces and diffuse into the exposed surfaces of the first dielectric layer 401 to form treated regions 503 in the first dielectric layer 401, while untreated regions 505 of the first dielectric layer 401 remain between the treated regions 503 and the substrate 101. For example, materials used for plasma (e.g., oxygen, nitrogen, fluorine, chlorine, etc.) can diffuse into the material forming the first dielectric layer 401 to a first depth D1 from the treated surface, which is equal to or less than about 100 nm (e.g., less than or equal to 5 nm). In some specific embodiments, such as when better noise control is desired, the first depth can be between about 1 / 10 and 1 / 2 of the first thickness T1. Finally, these materials may diffuse to a concentration of about 1.0 × 10⁻⁶. 10 cm -3 From approximately 1.0 × 10 15 cm -3 The concentration of these substances can decrease from the peak value at a certain depth from near the corresponding treated surface into the material.

[0043] Figure 6 It is shown that once the treated region 503 has been formed, it can be further processed to increase its density and restore the fixed oxide charge and traps, such that the treated region 503 has a different density than the rest of the first dielectric layer 401. In one embodiment, an annealing process, for example, can be used. Figure 6 The annealing process (represented by the wavy line marked 603) processes the treated area 503, creating a recovery area 601 from the treated area 503 (see [link]). Figure 5 However, any suitable method can be used.

[0044] In a specific embodiment, the annealing process 603 may be a thermal annealing performed in an environment containing oxygen (O2), nitrogen (N2), N2O, ammonia (NH3), or combinations thereof. Furthermore, the thermal annealing may be performed at a temperature between about 500°C and about 1000°C for a duration between about 10 seconds and about 1 hour, but any suitable temperature and time may be used. Additionally, while thermal annealing has been described, any suitable annealing process may be used, such as millisecond laser annealing, flash annealing, spike annealing, or soaking annealing.

[0045] After the processed region 503 has been formed and then restored to become the recovery region 601, the recovery region 601 may have a second depth D2 extending from the surface of the first dielectric layer 401. In one embodiment, the second depth D2 may be between about 5% and about 30% of the original first thickness T1 of the first dielectric layer 401. For example, if the first dielectric layer 401 is initially deposited to be 100 nm thick, the recovery region may be between 5 nm and about 30 nm. If the second depth D2 is too thin, the flicker noise of the formed analog device will not be improved, while if the second depth D2 is too thick, the plasma energy during the plasma processing 501 will cause excessive damage to the first dielectric layer 401, thereby impairing the overall quality of the subsequently formed gate dielectric layer.

[0046] Furthermore, while the above describes an embodiment utilizing both plasma treatment 501 and annealing process 603 to form the recovery region 601, this is intended to be illustrative and not to limit the embodiments. Rather, any suitable combination of processes can be utilized, such as using annealing process 603 alone. All these methods are fully intended to be included within the scope of the embodiments.

[0047] Figure 7 It is shown that once the recovery region 601 is formed in the first dielectric layer 401, the first dielectric layer 401 is patterned to remove the first dielectric layer 401 from the logic region 105. In one embodiment, the patterning of the first dielectric layer 401 can be initiated by placing a third photoresist 701 on the substrate 101 and imaging the third photoresist 701 to create a difference between the exposed and unexposed areas. Once the third photoresist 701 has been imaged, it is developed to remove the portion of the third photoresist 701 above the logic region 105 and retain the portion of the third photoresist 701 above the analog region 107.

[0048] Once the third photoresist 701 has been placed and patterned, portions of the first dielectric layer 401 (including the recovery region 601) located in the logic region 105 are removed. In one embodiment, an anisotropic etching process (e.g., reactive ion etching) can be used to remove the first dielectric layer 401. However, any suitable removal process can be used.

[0049] Furthermore, once the first dielectric layer 401 has been removed from logic region 105, the third photoresist 701 is removed. In one embodiment, the third photoresist 701 can be removed using, for example, an ashing process, in which the temperature of the third photoresist 701 is increased until it undergoes thermal decomposition, thereby easily removing the third photoresist 701. However, any suitable process can be used to remove the third photoresist 701.

[0050] Figure 8 A second dielectric layer 801 is shown formed over logic region 105. The second dielectric layer 801 may be a high-k dielectric material, such as silicon oxide, silicon oxynitride, silicon nitride, oxide, nitrogen-containing oxide, aluminum oxide, lanthanum oxide, hafnium oxide, zirconium oxide, hafnium oxynitride, or combinations thereof. The second dielectric layer 801 may have a relative permittivity greater than about 4.

[0051] In embodiments where the second dielectric layer 801 includes an oxide layer, the second dielectric layer 801 can be formed by any oxidation process (e.g., wet or dry thermal oxidation in an environment containing oxides, H2O, NO, or combinations thereof), or by chemical vapor deposition (CVD) using tetraethyl orthosilicate (TEOS) and oxygen as precursors. In one embodiment, the second dielectric layer 801 may have a second thickness T2, which is approximately to approximately Between, for example, thickness is

[0052] In other embodiments where the second dielectric layer 801 is a metal oxide such as hafnium oxide, a deposition process can be used to deposit the second dielectric layer 801. For example, atomic layer deposition, chemical vapor deposition, physical vapor deposition, or combinations thereof can be used to deposit the second dielectric layer 801. However, any suitable deposition method can be used.

[0053] Furthermore, since the second dielectric layer 801 is not present during processing 501 or the subsequent annealing process 603, the second dielectric layer 801 is unaffected by these processes. Therefore, the second dielectric layer 801 remains unprocessed and can have a constant composition and density throughout the second dielectric layer 801.

[0054] Figure 9The arrangement and patterning of a first gate electrode 901 (e.g., a logic gate electrode) and a second gate electrode 903 (e.g., an analog gate electrode) are illustrated. Materials for the first gate electrode 901 and the second gate electrode 903 are deposited at a uniform thickness on a first dielectric layer 401 and a second dielectric layer 801. In one embodiment, the first gate electrode 901 and the second gate electrode 903 may comprise conductive materials such as metals (e.g., tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium, ruthenium), metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, tantalum silicide), metal nitrides (e.g., titanium nitride, tantalum nitride), doped polycrystalline silicon, other conductive materials, or combinations thereof. In one example, amorphous silicon is deposited and recrystallized to produce polycrystalline silicon. Furthermore, while the first gate electrode 901 and the second gate electrode 903 are in… Figure 9 The first gate electrode 901 and the second gate electrode 903 may be represented as a single layer, but may include any number of suitable layers.

[0055] In one embodiment, the material for the first gate electrode 901 and the second gate electrode 903 is first deposited at a uniform thickness on the first dielectric layer 401 and the second dielectric layer 801. Once the material for the first gate electrode 901 and the second gate electrode 903 is in place, it is subsequently patterned into individual gate electrodes and desired shapes by etching through the material of the first gate electrode 901 and the second gate electrode 903, the first dielectric layer 401, and the second dielectric layer 801 using, for example, one or more photolithographic masks and etching processes. However, any suitable method can be used.

[0056] In one embodiment, the first gate electrode 901 may be patterned to have a first width W1 (e.g., the length of a first channel of the formed logic device), which is between about 0.05 μm and about 20 μm. Similarly, the second gate electrode 903 may be patterned to have a second width W2 (e.g., the length of a second channel of the formed analog device), which is greater than the first width W1, for example, the second width W2 is between about 0.1 μm and about 20 μm. However, any suitable size may be used.

[0057] Figure 10A first spacer 1001 is formed on a first gate electrode 901, and a second spacer 1003 is formed on a second gate electrode 903. The first spacer 1001 and the second spacer 1003 can be formed by depositing one or more spacer layers (not shown) of uniform thickness over the first gate electrode 901 and the second gate electrode 903. The spacer layers may comprise SiN, oxide nitride, SiC, SiON, and oxides, and can be formed by methods such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), sputtering, or combinations thereof. The spacer layers can be patterned, for example, by isotropic or anisotropic etching, thereby removing the spacer layers from the horizontal surface of the structure and forming the first spacer layer 1001 and the second spacer layer 1003, as shown. Figure 10 As shown.

[0058] However, as those skilled in the art will recognize, the above-described processes and such Figure 10 The resulting shapes of the first spacer 1001 and the second spacer 1003 shown are intended to be illustrative only and not to limit the embodiments to these descriptions. Rather, the first spacer 1001 and the second spacer 1003 for the first gate electrode 901 and the second gate electrode 903 can be formed using any suitable number and combination of spacer layers and shapes, and any suitable combination of spacers can be used.

[0059] Figure 11A A first source / drain region 1101 is shown formed in substrate 101 on the opposite side of the first gate electrode 901, and a second source / drain region 1103 is also shown formed in substrate 101 on the opposite side of the second gate electrode 903. In an embodiment where the second well 303 in logic region 105 contains an n-type dopant, the first source / drain region 1101 can be formed by first protecting the analog region 107 (e.g., by placing a photoresist over the analog region 107 and patterning the photoresist), and then implanting a suitable p-type dopant (e.g., boron, gallium, or indium). In other embodiments where the second well 303 in logic region 105 contains a p-type dopant, the first source / drain region 1101 can be formed by implanting a suitable n-type dopant (e.g., phosphorus or arsenic). However, any suitable combination of dopant can be used.

[0060] Similarly, for the second source / drain region 1103, in embodiments where the first well 203 contains an n-type dopant, the second source / drain region 1103 can be formed by first protecting the logic region 105 (e.g., by placing a photoresist over the device region 105 and patterning the photoresist), and then implanting a suitable p-type dopant (e.g., boron, gallium, or indium). In other embodiments where the first well 203 in the analog region 107 contains a p-type dopant, the second source / drain region 1103 can be formed by implanting a suitable n-type dopant (e.g., phosphorus or arsenic). However, any suitable combination of dopant can be used.

[0061] While the first gate electrode 901 and the first spacer 1001 can be used as masks to implant the first source / drain region 1101, and the second gate electrode 903 and the second spacer 1003 can be used as masks to implant the second source / drain region 1103, it should be noted that those skilled in the art will recognize that many other processes or steps can be used to form these first source / drain regions 1101 and second source / drain regions 1103. For example, those skilled in the art will recognize that various combinations of spacers and liners can be used to perform multiple implantations to form the first source / drain regions 1101 and second source / drain regions 1103 with a specific shape or characteristics suitable for a specific application. Any of these processes can be used to form the first source / drain regions 1101 and second source / drain regions 1103, and the above description is not intended to limit the embodiments to the steps described above.

[0062] Figure 11A Also shown is a silicide region 1105 formed over a first source / drain region 1101, a second source / drain region 1103, a first gate electrode 901, and a second gate electrode 903. In one embodiment, the silicide region 1105 comprises nickel silicide, but any other suitable metal silicide (e.g., titanium silicide, cobalt silicide, palladium silicide, platinum silicide, and erbium silicide) may also be used. The silicide region 1105 can be formed by performing an initial uniform-thickness deposition of a suitable metal layer, followed by an annealing process in which the metal reacts with the material below the substrate (e.g., silicon). Unreacted metal is then removed, for example, using a selective etching process. The thickness of the silicide region 1105 can be between about 3 nm and about 50 nm.

[0063] Furthermore, once the silicide region 1105 is formed, the top surface of the first gate electrode 901 can extend less relative to the substrate 101 than the second gate electrode 903. For example, the first gate electrode 901 can extend relative to the substrate 101 by a second distance D2, which is between about 25 nm and about 250 nm, while the second gate electrode 903 can extend by a third distance D3, which is between about 25 nm and about 250 nm. However, any suitable distance can be used.

[0064] Figure 11B The improvements that can be achieved by utilizing the embodiments described herein are shown. As shown, the normalized current noise spectral density (S) is scaled along the y-axis. id / Id 2 ), while plotting the frequency (Freq) along the x-axis. It can be seen that when compared with devices not using the embodiments described herein (in... Figure 11B Compared to the data line marked 1107, the device using the embodiments described herein (in...) Figure 11B A significant reduction can be seen in the data line marked 1109. In some cases, this significant reduction can lead to an improvement of 8 times or more.

[0065] In particular, by improving the quality of the first dielectric layer 401 formed in the analog region 107, the flicker noise performance of these MOSFETs (e.g., caused by trapping and detrapping in the first dielectric layer 401) can be reduced without using additional masks. Therefore, flicker noise can be reduced using a low-cost process fully compatible with the rest of the CMOS process, thereby also reducing the signal-to-noise ratio of the analog devices. Consequently, better overall device performance can be achieved, especially in devices used to transmit digital data (e.g., from a CPU) to analog signals (e.g., to a color display of an LCD panel).

[0066] Figure 12 Another embodiment is shown, which can be implemented in a "post-gate" process as described above. Figure 11A The described structure continues (but regarding) Figures 1 to 11B The described "gate-first process" can also be used without additional processing. In this embodiment, the materials of the first gate electrode 901 and the second gate electrode 903 are not the materials ultimately used, but rather dummy materials such as polysilicon that are subsequently removed. Specifically, once the silicide region 1105 is formed, in Figure 11AA first interlayer dielectric (ILD) 1201 is deposited on the structure shown. The first ILD 1201 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) is provided between the first ILD 1201 and the underlying structure. Figure 12 (Shown separately). CESL may contain a dielectric material (such as silicon nitride, silicon oxide, or silicon oxynitride, etc.) that has a lower etch rate than the material of the first ILD 1201 above.

[0067] Once the first ILD 1201 is formed, it is planarized to expose the first gate electrode 901 and the second gate electrode 903. In one embodiment, the planarization process may be a process such as chemical mechanical polishing, grinding, or a combination thereof. After the planarization process, the top surfaces of the first gate electrode 901 and the second gate electrode 903 are exposed through the first ILD 1201.

[0068] Once the first gate electrode 901 and the second gate electrode 903 are exposed, the first gate electrode 901 and the second gate electrode 903 are removed in one or more etching steps to form a recess. In some embodiments, the first gate electrode 901 and the second gate electrode 903 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the first gate electrode 901 and the second gate electrode 903 while barely etching the first ILD 1201 or the first spacer 1001 and the second spacer 1003. During removal, the first dielectric layer 401 and the second dielectric layer 801 may be used as etch stop layers when etching the first gate electrode 901 and the second gate electrode 903.

[0069] Once the recess has been formed, a gate dielectric layer 1205 and a gate electrode 1203 are formed to serve as a replacement gate. The gate dielectric layer 1205 is one or more layers deposited in the recess (e.g., deposited on the top surface of the first dielectric layer 401 and the top surface of the second dielectric layer 801, as well as on the sidewalls of the first spacer 1001 and the second spacer 1003). The gate dielectric layer 1205 may also be formed on the top surface of the first ILD 1201. In some embodiments, the gate dielectric layer 1205 comprises one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, or metal silicate. For example, in some embodiments, the gate dielectric layer 1205 comprises a high-k dielectric material, such as hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof in metal oxides or silicates. The gate dielectric layer 1205 may include a dielectric layer having a k value greater than about 7.0. Methods for forming the gate dielectric layer 1205 may include molecular beam deposition (MBD), ALD, and PECVD.

[0070] Gate electrodes 1203 are deposited on multiple gate dielectric layers 1205 and fill the remaining portion of the recess. Gate electrodes 1203 may comprise a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. Furthermore, although a single-layer gate electrode 1203 is shown, gate electrode 1203 may include any number of liner layers, any number of work function adjustment layers, and filler material. After filling the recess, a planarization process such as CMP may be performed to remove excess material from the gate dielectric layers 1205 and gate electrode 1203 located above the top surface of the first ILD 1201. Thus, the gate dielectric layer 1205 can extend along multiple sides of the gate 1203, and the top surfaces of the gate electrode 1203 in the analog region 107 and the gate electrode 1203 in the logic region 105 are equidistant from the substrate 101, for example, having a fourth distance D4 between approximately 20 nm and approximately 200 nm. Therefore, the remaining material of the gate electrode 1203 and the gate dielectric layer 1205 forms a replacement gate. The gate electrode 1203 and the gate dielectric layer 1205 can be collectively referred to as a "gate stack".

[0071] The formation of the gate dielectric layer 1205 in the logic region 105 and the formation of the gate dielectric layer 1205 in the analog region 107 can occur simultaneously, such that the gate dielectric layer 1205 in each region is formed of the same material, and the formation of the gate electrode 1203 can occur simultaneously, such that the gate electrode 1203 in each region is formed of the same material. In other embodiments, the gate dielectric layer 1205 in each region can be formed by different processes, such that the gate dielectric layer 1205 can be made of different materials, and the gate electrode 1203 in each region can be formed by different processes, such that the gate electrode 1203 can be made of different materials. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0072] Figure 13 Another "post-gate" embodiment is shown, in which the gate dielectric layer 1205 is formed before the formation of the first ILD 1201, rather than after it is formed. In this embodiment, the material of the gate dielectric layer 1205 is deposited over the first dielectric layer 401 and the second dielectric layer 801 before the materials of the first gate electrode 901 and the second gate electrode 903 are deposited. This can be described as above regarding... Figure 12 The gate dielectric layer 1205 in this embodiment is deposited as described.

[0073] Once the gate dielectric layer 1205 is deposited, a first gate electrode 901 and a second gate electrode 903 are formed and patterned. The patterning of the first gate electrode 901 and the second gate electrode 903 is also used to pattern the gate dielectric layer 1205. Therefore, the gate dielectric layer 1205 is patterned to have a single planar portion directly above the first dielectric layer 401 and the second dielectric layer 801.

[0074] Once the first gate electrode 901 and the second gate electrode 903 are formed, a first ILD 1201 is deposited and planarized, and the first gate electrode 901 and the second gate electrode 903 are removed. Once the first gate electrode 901 and the second gate electrode 903 are removed, a gate electrode 1203 is deposited (but not the gate dielectric layer 1205, as it has already been formed) to replace the first gate electrode 901 and the second gate electrode 903. Therefore, the gate electrode 1203 is deposited to make physical contact with the first spacer 1001 (in the logic region 105) and the second spacer (in the analog region 107). In one embodiment, as described above... Figure 12 The gate electrode 1203 is deposited as described. However, any suitable method and material can be used.

[0075] By processing the first dielectric layer 401 to form the recovery region 601, trapping and detrapping, which typically occur at sufficient frequencies in analog devices, can be reduced. Reducing trapping and detrapping lowers the overall flicker noise of the analog device, thereby improving its overall performance. These improvements can be achieved without additional masks, at low cost, and using processes fully compatible with the rest of the processes used to form CMOS devices.

[0076] Furthermore, while the embodiments presented herein are described as being for planar devices, these ideas are not intended to be limited to planar devices. Rather, these ideas can be implemented in a variety of devices, including fin field-effect transistors (finFETs), nanostructure devices, or combinations thereof. All of these methods are fully intended to be included within the scope of the embodiments.

[0077] According to one embodiment, a method of manufacturing a semiconductor device includes: depositing a first dielectric layer over a logic region and an analog region of a semiconductor substrate; processing the first dielectric layer to form a recovery layer; removing a first portion of the recovery layer from the logic region after processing the first dielectric layer; forming a second dielectric layer in the logic region; and depositing a gate electrode material over the remaining portion of the recovery layer and the second dielectric layer. In one embodiment, processing the first dielectric layer further includes: exposing the first dielectric layer to a plasma to form a processed region; and annealing the processed region. In one embodiment, the plasma includes oxygen, nitrogen, fluorine, or chlorine. In one embodiment, processing the first dielectric layer further includes annealing the first dielectric layer. In one embodiment, the annealing is performed in an oxygen environment. In one embodiment, the recovery layer has a first thickness, the first dielectric layer has a second thickness, and the first thickness is between 5% and 30% of the second thickness. In one embodiment, the method further includes patterning the gate electrode material into a first gate electrode over the recovery layer and a second gate electrode over the second dielectric layer, the width of the first gate electrode being greater than the width of the second gate electrode.

[0078] According to another embodiment, a method of manufacturing a semiconductor device includes: depositing a first dielectric layer of uniform thickness over a first region and a second region of a substrate; exposing a top surface of the first dielectric layer to a first plasma to form a processed region in the first dielectric layer over an unprocessed region of the first dielectric layer; recovering the processed region using a first annealing process to form a recovered region over the unprocessed region; removing the first dielectric layer from the first region; forming a second dielectric layer in the first region; forming a first gate electrode in the second region over the first dielectric layer; and forming a second gate electrode in the first region over the second dielectric layer. In one embodiment, the method further includes replacing the first gate electrode and the second gate electrode. In one embodiment, the first plasma comprises an oxygen plasma. In one embodiment, the first plasma comprises a chlorine plasma. In one embodiment, the first plasma comprises a nitrogen plasma. In one embodiment, the first thickness of the recovered region is less than 30% of the second thickness of the first dielectric layer. In one embodiment, the first region is a logic region, and the second region is an analog region.

[0079] In another embodiment, a semiconductor device includes: a logic device located in a logic region of a substrate, the logic device including: a first dielectric layer having a constant density throughout the first dielectric layer; and a first gate electrode on top of the first dielectric layer; and an analog device located in an analog region of the substrate, the analog device including: a second dielectric layer including a recovery region and an unprocessed region, the recovery region having a different density than the unprocessed region; and a second gate electrode on top of the second dielectric layer. In one embodiment, a first top surface of the first gate electrode is a first distance from the substrate, and wherein a second top surface of the second gate electrode is a second distance from the substrate, the second distance being greater than the first distance. In another embodiment, a first top surface of the first gate electrode is a first distance from the substrate, and wherein a second top surface of the second gate electrode is a first distance from the substrate. In one embodiment, the semiconductor device further includes a first high-k dielectric layer between the second dielectric layer and the second gate electrode, wherein the first high-k dielectric layer extends along multiple sides of the second gate electrode. In one embodiment, the semiconductor device further includes a first high-k dielectric layer between the second dielectric layer and the second gate electrode, wherein the second gate electrode is in contact with a spacer body. In one embodiment, the width of the second gate electrode is greater than the width of the first gate electrode.

[0080] Here are some examples.

[0081] Example 1. A method for manufacturing a semiconductor device, the method comprising:

[0082] A first dielectric layer is deposited on the logic region and analog region of the semiconductor substrate;

[0083] The first dielectric layer is processed to form a recovery layer;

[0084] After processing the first dielectric layer, the first portion of the recovery layer is removed from the logic region;

[0085] A second dielectric layer is formed in the logic region; and

[0086] Gate electrode material is deposited on the remaining portion of the recovery layer and the second dielectric layer.

[0087] Example 2. The method according to Example 1, wherein processing the first dielectric layer further includes:

[0088] Expose the first dielectric layer to plasma to form a treated region; and

[0089] The treated area is then annealed.

[0090] Example 3. The method according to Example 2, wherein the plasma comprises oxygen, nitrogen, fluorine or chlorine.

[0091] Example 4. According to the method of Example 1, the processing of the first dielectric layer further includes: annealing the first dielectric layer.

[0092] Example 5. The method according to Example 4, wherein the annealing is performed in an oxygen environment.

[0093] Example 6. The method according to Example 1, wherein the recovery layer has a first thickness, the first dielectric layer has a second thickness, and the first thickness is between 5% and 30% of the second thickness.

[0094] Example 7. The method according to Example 1 further includes: patterning the gate electrode material into a first gate electrode over the recovery layer and a second gate electrode over the second dielectric layer, wherein the width of the first gate electrode is greater than the width of the second gate electrode.

[0095] Example 8. A method of manufacturing a semiconductor device, the method comprising:

[0096] A first dielectric layer is deposited with uniform thickness over a first region of the substrate and a second region of the substrate;

[0097] The top surface of the first dielectric layer is exposed to the first plasma to form a treated region in the first dielectric layer above the untreated region of the first dielectric layer;

[0098] The treated area is restored using a first annealing process to form a restored area over the untreated area;

[0099] Remove the first dielectric layer from the first region;

[0100] A second dielectric layer is formed in the first region;

[0101] A first gate electrode is formed on the first dielectric layer in the second region; and

[0102] A second gate electrode is formed on top of the second dielectric layer in the first region.

[0103] Example 9. The method according to Example 8 further includes: replacing the first gate electrode and the second gate electrode.

[0104] Example 10. The method according to Example 8, wherein the first plasma comprises an oxygen plasma.

[0105] Example 11. The method according to Example 8, wherein the first plasma comprises chlorine plasma.

[0106] Example 12. The method according to Example 8, wherein the first plasma comprises a nitrogen plasma.

[0107] Example 13. The method according to Example 8, wherein the first thickness of the recovery region is less than 30% of the second thickness of the first dielectric layer.

[0108] Example 14. The method according to Example 8, wherein the first region is a logical region and the second region is a simulation region.

[0109] Example 15. A semiconductor device comprising:

[0110] A logic device, located in a logic region of a substrate, comprising:

[0111] A first dielectric layer, having a constant density throughout the first dielectric layer; and

[0112] A first gate electrode, the first gate electrode being disposed on the first dielectric layer; and

[0113] Analog device, located in an analog region of the substrate, the analog device comprising:

[0114] A second dielectric layer, the second dielectric layer including a restored region and an unprocessed region, the restored region having a different density than the unprocessed region; and

[0115] The second gate electrode is located on the second dielectric layer.

[0116] Example 16. The semiconductor device according to Example 15, wherein a first top surface of the first gate electrode is a first distance from the substrate, and wherein a second top surface of the second gate electrode is a second distance from the substrate, the second distance being greater than the first distance.

[0117] Example 17. The semiconductor device according to Example 15, wherein a first top surface of the first gate electrode is a first distance from the substrate, and wherein a second top surface of the second gate electrode is a first distance from the substrate.

[0118] Example 18. The semiconductor device according to Example 15 further includes a first high-k dielectric layer between the second dielectric layer and the second gate electrode, wherein the first high-k dielectric layer extends along multiple sides of the second gate electrode.

[0119] Example 19. The semiconductor device according to Example 15 further includes a first high-k dielectric layer between the second dielectric layer and the second gate electrode, wherein the second gate electrode is in contact with the spacer body.

[0120] Example 20. The semiconductor device according to Example 15, wherein the width of the second gate electrode is greater than the width of the first gate electrode. Features of several embodiments have been summarized above to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: A first dielectric layer is deposited on the logic region and analog region of the semiconductor substrate; The first dielectric layer is processed to form a recovery layer and an unprocessed layer, the unprocessed layer being located between the recovery layer and the semiconductor substrate; After processing the first dielectric layer, the first dielectric layer is removed from the logic region; A second dielectric layer is formed in the logic region; as well as Gate electrode material is deposited on the remaining portion of the recovery layer and the second dielectric layer.

2. The method according to claim 1, wherein, The processing of the first dielectric layer further includes: Expose the first dielectric layer to plasma to form a treated region; and The treated area is then annealed.

3. The method according to claim 2, wherein, The plasma includes oxygen, nitrogen, fluorine, or chlorine.

4. The method according to claim 1, wherein, The processing of the first dielectric layer also includes annealing the first dielectric layer.

5. The method according to claim 4, wherein, The annealing is performed in an oxygen environment.

6. The method according to claim 1, wherein, The recovery layer has a first thickness, the first dielectric layer has a second thickness, and the first thickness is between 5% and 30% of the second thickness.

7. The method according to claim 1, further comprising: The gate electrode material is patterned into a first gate electrode on the recovery layer and a second gate electrode on the second dielectric layer, wherein the width of the first gate electrode is greater than the width of the second gate electrode.

8. A method for manufacturing a semiconductor device, the method comprising: A first dielectric layer is deposited with uniform thickness over a first region of the substrate and a second region of the substrate; The top surface of the first dielectric layer is exposed to the first plasma to form a treated region in the first dielectric layer above the untreated region of the first dielectric layer; The treated area is restored using a first annealing process to form a restored area over the untreated area, the untreated area being located between the restored area and the substrate; Remove the first dielectric layer from the first region; A second dielectric layer is formed in the first region; A first gate electrode is formed on the first dielectric layer in the second region; as well as A second gate electrode is formed on top of the second dielectric layer in the first region.

9. The method according to claim 8, further comprising: Replace the first gate electrode and the second gate electrode.

10. The method according to claim 8, wherein, The first plasma includes oxygen plasma.

11. The method according to claim 8, wherein, The first plasma includes chlorine plasma.

12. The method according to claim 8, wherein, The first plasma includes nitrogen plasma.

13. The method according to claim 8, wherein, The first thickness of the recovery region is less than 30% of the second thickness of the first dielectric layer.

14. The method according to claim 8, wherein, The first region is a logical region, and the second region is an analog region.

15. A semiconductor device, comprising: A logic device, located in a logic region of a substrate, comprising: A first dielectric layer, having a constant density throughout the first dielectric layer; and A first gate electrode, the first gate electrode being disposed on the first dielectric layer; and Analog device, located in an analog region of the substrate, the analog device comprising: A second dielectric layer, the second dielectric layer including a recovery region and an untreated region, the recovery region having a different density than the untreated region, the untreated region being located between the recovery region and the substrate; and The second gate electrode is located on the second dielectric layer.

16. The semiconductor device according to claim 15, wherein, The first top surface of the first gate electrode is a first distance from the substrate, and the second top surface of the second gate electrode is a second distance from the substrate, the second distance being greater than the first distance.

17. The semiconductor device according to claim 15, wherein, The first top surface of the first gate electrode is a first distance from the substrate, and the second top surface of the second gate electrode is a first distance from the substrate.

18. The semiconductor device of claim 15, further comprising a first high-k dielectric layer, the first high-k dielectric layer being disposed between the second dielectric layer and the second gate electrode, wherein, The first high-k dielectric layer extends along multiple sides of the second gate electrode.

19. The semiconductor device of claim 15, further comprising a first high-k dielectric layer, the first high-k dielectric layer being disposed between the second dielectric layer and the second gate electrode, wherein, The second gate electrode is in contact with the spacer body.

20. The semiconductor device according to claim 15, wherein, The width of the second gate electrode is greater than the width of the first gate electrode.

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