Semiconductor device manufacturing method

Abstract

A method for manufacturing a semiconductor device may include forming a first silicon nitride layer in an opening of the semiconductor device and on a top surface of the semiconductor device, wherein the semiconductor device includes an epitaxial source / drain and a metal gate. The method may also include forming a second silicon nitride layer in the opening of the semiconductor device, on top of the first silicon nitride layer and on the top surface of the semiconductor device as a sacrificial layer; and removing the second silicon nitride layer from the sidewalls of the first silicon nitride layer in the opening. The method may further include removing the second silicon nitride layer and the first silicon nitride layer from the bottom of the opening; and depositing a metal layer in the opening to form a metal drain in the opening of the semiconductor device.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a spacer used for a metal drain electrode. Background Technology

[0002] A logic device is an electronic device that performs logical operations on one or more binary inputs, producing a single binary output. A logic device may include a multiplexer, recorder, arithmetic logic unit (ALU), computer memory, microprocessor, and / or the like. Some logic devices can be fabricated from metal-oxide-semiconductor field-effect transistors (MOSFETs). Static random access memory (SRAM) is a semiconductor random access memory device that uses bistable latch-up circuits (such as flip-flops) to store each bit. Summary of the Invention

[0003] Some embodiments described herein provide methods for manufacturing a semiconductor device. The method may include forming a first silicon nitride layer in an opening of the semiconductor device and on a top surface of the semiconductor device, wherein the semiconductor device includes an epitaxial source / drain and a metal gate. The method may include forming a second silicon nitride layer in the opening of the semiconductor device, on top of the first silicon nitride layer and on the top surface of the semiconductor device, wherein the second silicon nitride layer is a sacrificial layer. The method may include removing the second silicon nitride layer from the sidewalls of the first silicon nitride layer in the opening of the semiconductor device, and removing the second silicon nitride layer and the first silicon nitride layer from the bottom of the opening of the semiconductor device. The method may include forming a metal layer in the opening and on the top surface of the semiconductor device, and removing the metal layer from the top surface of the semiconductor device to form a metal drain in the opening of the semiconductor device.

[0004] As detailed above, the embodiments described herein provide a method for manufacturing a semiconductor device. The method may include forming an epitaxial source / drain in a dielectric layer; forming a first interlayer dielectric layer on the upper surface of the dielectric layer; and forming a metal gate in the dielectric layer and the first interlayer dielectric layer, adjacent to the epitaxial source / drain. The method may include forming a first silicon nitride layer on the upper surface of the semiconductor device, on a plurality of sidewalls of an opening in the first interlayer dielectric layer, and on the epitaxial source / drain; and forming a second silicon nitride layer on the first silicon nitride layer, wherein the second silicon nitride layer is a sacrificial layer. The method may include removing the second silicon nitride layer from the first silicon nitride layer on the sidewall of the opening, without removing the first silicon nitride layer from the sidewall of the opening; and removing the second silicon nitride layer and the first silicon nitride layer at the bottom of the opening, without removing the first silicon nitride layer from the sidewall of the opening. The method may include removing a second silicon nitride layer and a first silicon nitride layer on the upper surface of a semiconductor device without removing the first silicon nitride layer from the sidewall of the opening; and forming a metal drain in the opening and above an epitaxial source / drain, wherein the first silicon nitride layer on the sidewall of the opening forms a plurality of silicon nitride spacers for the metal drain.

[0005] As detailed above, some embodiments described herein provide methods for manufacturing a semiconductor device. The method may include forming a first silicon nitride layer in an opening of the semiconductor device and on a top surface of the semiconductor device, wherein the semiconductor device includes an epitaxial source / drain and a metal gate. The method may include performing a plasma-assisted atomic layer deposition (PAD) step to form a second silicon nitride layer in the opening of the semiconductor device, on top of the first silicon nitride layer and on the top surface of the semiconductor device, wherein the PAD step uses dichlorosilane and ammonia. The method may include performing a first etching step to remove the second silicon nitride layer from the sidewalls of the first silicon nitride layer in the opening of the semiconductor device, wherein the first etching step uses hydrofluoric acid diluted with water to a specific ratio. The method may include performing a second etching step to remove the second silicon nitride layer and the first silicon nitride layer at the bottom of the opening of the semiconductor device, wherein the second etching step does not remove the first silicon nitride layer from the sidewalls of the opening of the semiconductor device. The method may include depositing a metal layer in the opening of the semiconductor device to form a metal drain in the opening of the semiconductor device. Attached Figure Description

[0006] Figure 1 This is a diagram of an environment in which the systems and / or methods described herein are implemented, as exemplified by this example.

[0007] Figures 2A to 2I This is a diagram illustrating the relevant steps in manufacturing a semiconductor device.

[0008] Figure 3 This is a table of process conditions for depositing selective silicon nitride layers to create spacers for the metal drain of a semiconductor device.

[0009] Figure 4 In one example, Figure 1 A component of one or more tools and / or devices.

[0010] Figure 5 In one example, a flowchart of a process for manufacturing a semiconductor device is presented, in which a selectively deposited silicon nitride layer is used to create a spacer for the metal drain of the semiconductor device.

[0011] The reference numerals in the attached figures are explained as follows:

[0012] 100: Environment

[0013] 102: Pre-cleaning tools

[0014] 104: Sedimentation Tools

[0015] 106: Annealing tools

[0016] 108: Optical Resist Tool

[0017] 110: Etching tools

[0018] 112: Wafer / Die Transfer Tool

[0019] 114: Pre-cleaning chamber

[0020] 116: Gas Source

[0021] 118: Plasma Source

[0022] 120: Heat source

[0023] 200, 510, 520, 530, 540, 550, 560: Steps

[0024] 205: Silicon nitride layer

[0025] 210: Morphology-selective silicon nitride layer

[0026] 215, 220: Etching steps

[0027] 225: Pre-cleaning steps

[0028] 230: Adhesive layer

[0029] 235: Metal layer

[0030] 240: Metal drain electrode

[0031] 300: Form

[0032] 400: Device

[0033] 410: Bus

[0034] 420: Processor

[0035] 430: Memory

[0036] 440: Storage Component

[0037] 450: Input component

[0038] 460: Output Component

[0039] 470: Communication Interface

[0040] 500: Process

[0041] 2010: Epitaxial Source / Drain

[0042] 2020: First Dielectric Layer

[0043] 2030: Metal Gate

[0044] 2040: Fluorine-free tungsten layer

[0045] 2050: Sacrificial oxide layer

[0046] 2060: Second dielectric layer

[0047] 2070: Opening

[0048] 2080: First etch stop layer

[0049] 2090: First interlayer dielectric layer

[0050] 2100: First contact point

[0051] 2110: Second etch stop layer

[0052] 2120: Second interlayer dielectric layer

[0053] 2130: Second Node

[0054] 2140: Third etch stop layer

[0055] 2150: Third interlayer dielectric layer

[0056] 2160: Third Node Detailed Implementation

[0057] The following detailed description is accompanied by illustrations to aid in understanding all aspects of this disclosure. It should be noted that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of the various structures may be increased or decreased arbitrarily for clarity of explanation.

[0058] The different embodiments or examples provided below can implement different structures of this disclosure. The specific components and arrangements described below are intended to simplify the content of this disclosure and not to limit it. For example, the description of forming a first component on a second component includes embodiments where the two are in direct contact, or embodiments where the two are separated by other additional components and are not in direct contact. Furthermore, multiple embodiments of this disclosure may use the same reference numerals repeatedly for brevity, but elements with the same reference numerals in various embodiments and / or settings do not necessarily have the same correspondence.

[0059] In addition, spatial relative terms such as “below,” “lower,” “above,” “higher,” or similar terms are used to describe the relationship between some elements or structures in a diagram and another element or structure. These spatial relative terms include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned in a different orientation (rotated 90 degrees or other orientations), the spatial relative adjectives used will also be interpreted according to the orientation after the turn.

[0060] Semiconductor devices may include field-effect transistors (FETs). An FET can be a transistor that uses an electric field to control current. An FET includes three terminals: an epitaxial source / drain, a metal gate, and a metal drain. A voltage is applied to the metal gate to control the current, and the applied voltage can change the conductivity between the metal drain and the epitaxial source / drain. A spacer is provided between the metal drain and the metal gate to prevent leakage current between them. However, previous manufacturing processes may have removed portions of the spacer when manufacturing semiconductor devices such as FETs. Removing portions of the spacer may reduce its effectiveness, such as preventing leakage current between the metal drain and the metal gate, potentially causing the semiconductor device to malfunction. Furthermore, the step of removing portions of the spacer may increase defects in the semiconductor device, such as dark voltage contrast defects, bright voltage contrast defects, and / or similar defects.

[0061] In some embodiments described herein, a semiconductor device is manufactured using a method that selectively deposits a silicon nitride layer based on its deposition morphology to create spacers for a metal drain in a semiconductor device. For example, the method may include forming a first silicon nitride layer in an opening of the semiconductor device and on the upper surface of the semiconductor device, wherein the semiconductor device may include an epitaxial source / drain and a metal gate. The method may include forming a second silicon nitride layer in the opening of the semiconductor device and on the first silicon nitride layer on the upper surface of the semiconductor device, wherein the second silicon nitride layer may be morphology-selective. The method may include removing the second silicon nitride layer from the sidewalls of the first silicon nitride layer in the opening of the semiconductor device, and removing both the first and second silicon nitride layers from the bottom of the opening of the semiconductor device. The method may include removing the first and second silicon nitride layers from the upper surface of the semiconductor device, and forming a metal layer in the opening and on the upper surface of the semiconductor device. The method may include removing the metal layer from the upper surface of the semiconductor device to form a metal drain in the opening of the semiconductor device.

[0062] In this method, a semiconductor device is manufactured by depositing a morphology-selective silicon nitride layer as a spacer for forming the metal drain of the semiconductor device. The morphology-selective silicon nitride layer acts as a sacrificial layer, ensuring that the thickness of the spacer (formed from silicon nitride) avoids and / or reduces defects in the semiconductor device, avoids and / or reduces leakage current from the metal drain to the metal gate, and / or similar effects. For example, the sacrificial morphology-selective silicon nitride layer can reduce dark voltage contrast defects, bright voltage contrast defects, and / or similar defects in the semiconductor device. The morphology-selective silicon nitride layer can also prevent etch loss of the first silicon nitride layer from the opening sidewalls before the metal drain is formed.

[0063] Figure 1 This is a diagram of environment 100 in one example, in which the systems and / or methods described herein can be implemented. Figure 1As shown, environment 100 may include multiple pre-cleaning tools 102, deposition tools 104, annealing tools 106, photoresist tools 108, etching tools 110, and wafer / die transfer tools 112. The tools and / or devices included in environment 100 may be located in a semiconductor cleanroom, a semiconductor foundry, a semiconductor processing and / or manufacturing facility, and / or another location.

[0064] The pre-cleaning tool 102 includes a pre-cleaning chamber 114 and one or more devices for performing pre-cleaning processes on a semiconductor device to remove byproducts from the semiconductor device. The one or more devices may include a gas source 116, a plasma source 118, a heat source 120, and / or the like. The gas source 116 can provide various gases such as ammonia, nitrogen trifluoride, and / or the like to the pre-cleaning chamber 114. The plasma source 118 can generate plasma to cause a reaction between the gases input to the pre-cleaning chamber 114. For example, the plasma source 118 may include an inductively coupled plasma source, a transformer-coupled plasma source, or another plasma source that can cause ammonia and nitrogen trifluoride to react to form ammonium fluoride. The heat source 120 can heat the semiconductor device in the pre-cleaning chamber 114 to decompose one or more layers on the semiconductor device, as described herein. For example, heat source 120 may include a heating lamp, a heating coil, or another heating device that can heat the semiconductor device to decompose the ammonium fluoride layer on the semiconductor device into ammonia and hydrofluoric acid gas, as described herein.

[0065] The deposition tool 104 is a semiconductor process tool that includes a semiconductor process chamber and one or more devices for depositing various materials onto a semiconductor device. In some embodiments, the deposition tool 104 includes a chemical vapor deposition tool (such as an electrostatic spraying device, an epitaxial device, and / or another chemical vapor deposition device), a physical vapor deposition device (such as a sputtering device and / or another physical vapor deposition device), an ion implantation device, and / or the like. In some embodiments, the deposition tool 104 can deposit a metal layer on the source or drain region of the semiconductor device, and can deposit contact material to form contacts of the semiconductor device, and / or similar elements described herein.

[0066] Annealing tool 106 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more means for heating a semiconductor device. For example, annealing tool 106 may include a rapid thermal annealing tool or another type of annealing tool that heats the semiconductor device to cause a reaction between two or more materials or gases, to decompose materials, and / or similar functions. For example, annealing tool 106 can heat the semiconductor device to react a metal layer on an epitaxial region (such as a source region or drain region) to form a metal silicide layer, as described herein.

[0067] Photoresist tool 108 is a semiconductor manufacturing tool that can remove or supply material to a semiconductor device based on photoresist material (such as a photoresist mask) applied to the semiconductor device. Photoresist is a photosensitive material used in multiple processes (such as photolithography, photolithography, and / or similar processes) to form a patterned coating on the surface of a semiconductor device. Photoresist tool 108 can coat a photosensitive organic material onto the semiconductor device and can use a patterned photomask on the semiconductor device to block light, thus exposing only the unmasked areas of the photosensitive organic material. Photoresist tool 108 or another tool (such as etching tool 110) can apply a solvent (also called a developer) to the semiconductor device. In the example using positive photoresist, light can degrade the photosensitive organic material, and the developer can dissolve the exposed areas while retaining the masked coating. In the example using negative photoresist, light can strengthen (e.g., polymerize or crosslink) the photosensitive organic material, and the developer only dissolves the unexposed areas while retaining the unmasked coating.

[0068] Etching tool 110 is a semiconductor manufacturing tool that removes material from the surface of a semiconductor device. In some embodiments, a portion of the semiconductor device is protected from the etchant by an etch-resistant masking material. For example, the masking material may include photoresist, and photolithography may be used to pattern the photoresist. Etching tool 110 can perform wet etching or dry (e.g., plasma) etching processes on the semiconductor device. In a wet etching process, the semiconductor device may be immersed in a liquid phase (e.g., wet) etchant bath, which may be agitated to control the process. For example, buffered hydrofluoric acid may be used to etch silicon oxide instead of a silicon substrate. Plasma parameters can be adjusted to operate the plasma etching process in various modes. For example, the pressure of the plasma etching process may be approximately 0.01 Torr to approximately 5 Torr. Plasma can generate energized free radicals that may carry a neutral charge and react on the surface of the semiconductor device. Plasma etching can be isotropic (e.g., on a patterned surface, the lateral undercut rate is approximately equal to the downward etching rate) or anisotropic (e.g., the lateral undercut rate is less than the downward etching rate). The source gas used for plasma can include small molecules rich in chlorine or fluorine. For example, carbon tetrafluoride can be used to etch silicon, chlorine can be used to etch aluminum, fluoroform can be used to etch silicon oxide and silicon nitride, and / or similar substances can be used to etch specific materials. Plasma may also include oxygen to oxidize photoresist and facilitate its removal.

[0069] The wafer / die transfer tool 112 includes mobile robots, robotic arms, light rail or railcars, and / or other tools used to transfer wafers and / or dies between semiconductor process tools such as pre-cleaning tool 102 and etching tool 110, and / or from or to other locations (such as wafer racks, storage rooms, and / or similar locations). In some embodiments, the wafer and / or die transfer tool 112 is a programmed tool (for transport along a specific path) and / or operates automatically or semi-automatically.

[0070] Figure 1 The number and configuration of tools shown provide one or more examples. In practice, there may be... Figure 1 Additional tools, fewer tools, different tools, or different configurations beyond those shown. Furthermore, it can be implemented with a single tool. Figure 1 The functions of two or more tools are shown, or implemented by multiple distributed tools. Figure 1 The function of a single tool shown. A set of tools in environment 100 (e.g., one or more tools) may additionally or alternatively perform one or more functions performed by another set of tools in environment 100.

[0071] Figures 2A to 2I This is a diagram illustrating one or more related steps 200 in the manufacture of the semiconductor device described herein (such as a logic device, a memory device, a fin field-effect transistor, a metal-oxide-semiconductor field-effect transistor, and / or the like). Figure 2A As shown, the semiconductor device may include an epitaxial source / drain 2010, a first dielectric layer 2020 adjacent to the epitaxial source / drain 2010, a metal gate 2030 formed on both sides of the epitaxial source / drain 2010, a fluorine-free tungsten layer 2040 formed on the metal gate 2030, a sacrificial oxide layer 2050 formed on the fluorine-free tungsten layer 2040, and a second dielectric layer 2060 adjacent to the sacrificial oxide layer 2050. As described below, an opening 2070 may be formed on the epitaxial source / drain 2010.

[0072] The epitaxial source / drain 2010 may include an epitaxially grown silicon-germanium layer. In some embodiments, the epitaxial source / drain 2010 may form a source / drain plug that may be electrically coupled to one or more other components of the semiconductor device. The material of the first dielectric layer 2020 adjacent to the epitaxial source / drain 2010 may electrically insulate the epitaxial source / drain 2010 from one or more other components of the semiconductor device (such as a metal gate 2030). For example, the material of the first dielectric layer 2020 may include silicon, silicon nitride, silicon oxide, a low dielectric constant dielectric material (such as fluorine-doped silicon oxide, organosilicon glass, porous silicon oxide, spin-coated organic polymer dielectric layer, and / or the like), and / or the like.

[0073] The metal gate 2030 may include conductive metals such as titanium, cobalt, tungsten, aluminum, copper, ruthenium, iridium, and / or the like. The fluorine-free tungsten layer 2040 may include a fluorine-free tungsten material layer that provides a metal contact between the metal gate 2030 and a semiconductor device (e.g.,...). Figure 2IElectrical connections between (shown). The sacrificial oxide layer 2050 may include layers of silicon oxide, iron oxide, aluminum oxide, and / or the like, which will eventually be removed and replaced with components of the semiconductor device (such as metal contacts). The second dielectric layer 2060, adjacent to the sacrificial oxide layer 2050, the fluorine-free tungsten layer 2040, and a portion thereof with the metal gate 2030, may be made of silicon, silicon nitride, silicon oxide, and / or the like, to electrically insulate the metal gate 2030 from other components of the semiconductor device.

[0074] like Figure 2A As shown, a silicon nitride layer 205 (such as a first silicon nitride layer) can be formed in the opening 2070 and on the upper surface of the semiconductor device. In some embodiments, the thickness of the silicon nitride layer 205 can prevent and / or reduce defects in the semiconductor device, prevent and / or reduce leakage current between the metal gate 2030 and the metal drain 240 subsequently formed in the opening 2070 of the semiconductor device, and / or similar effects. For example, the thickness of the silicon nitride layer 205 can be between approximately 0.8 nm and approximately 3.0 nm, but other thicknesses are also possible, such as 1.0 nm to 2.5 nm, or 2.1 nm to 2.5 nm. For example, the thickness of the silicon nitride layer 205 on the sidewalls of the opening 2070 can be approximately 2.1 nm, the thickness at the bottom of the opening can be approximately 2.5 nm, the thickness on the upper surface of the semiconductor device can be approximately 2.5 nm, and / or similar thicknesses. In some embodiments, a thickness of approximately 2.5 nm can be used. Figure 1 The deposition tool 104 of the environment 100 shown is used to form a silicon nitride layer 205 in the opening 2070 and on the upper surface of the semiconductor device.

[0075] like Figure 2BAs shown, a plasma-assisted atomic layer deposition (PAD) step can be performed to form a morphology-selective silicon nitride layer 210 (such as a second silicon nitride layer) over the silicon nitride layer 205 (such as a first silicon nitride layer) within the opening 2070 and over the upper surface of the semiconductor device. In some embodiments, the thickness of the morphology-selective silicon nitride layer 210 can avoid and / or reduce defects in the semiconductor device, avoid and / or reduce leakage current between the metal gate 2030 and the metal drain 240 subsequently formed in the opening 2070 of the semiconductor device, and / or similar effects. For example, the thickness of the morphology-selective silicon nitride layer 210 can be approximately 2.5 nm to approximately 4.5 nm, but other thicknesses are also possible. The thicknesses of the sidewall and bottom morphology-selective silicon nitride layers 210 can be substantially the same. The ratio between the thickness of the sidewall morphology-selective silicon nitride layer 210 and the thickness of the bottom morphology-selective silicon nitride layer 210 can be approximately 0.9 to approximately 1.1. In some embodiments, the total thickness of the silicon nitride layer 205 and the morphology-selective silicon nitride layer 210 can avoid and / or reduce defects in the semiconductor device, avoid and / or reduce leakage current between the metal gate 2030 and the metal drain 240 subsequently formed in the opening 2070 of the semiconductor device, and / or similar effects. In some embodiments, the morphology-selective silicon nitride layer 210 is a sacrificial layer that will be removed in subsequent processes of the semiconductor device.

[0076] Since a portion of the morphology-selective silicon nitride layer 210 formed on the bottom of the opening 2070 of the semiconductor device is denser than a portion of the morphology-selective silicon nitride layer 210 formed on the sidewall of the opening 2070, the morphology-selective silicon nitride layer 210 can be referred to as morphology-selective. Additionally or alternatively, a portion of the morphology-selective silicon nitride layer 210 formed on the upper surface of the semiconductor device may be denser than a portion of the morphology-selective silicon nitride layer 210 formed on the sidewall of the opening 2070.

[0077] In some implementations... Figure 1The deposition tool of the environment 100 shown can be used to form a morphology-selective silicon nitride layer 210 over the silicon nitride layer 205 in the opening 2070 and over the upper surface of the semiconductor device. For example, the deposition tool 104 can perform a plasma-assisted atomic layer deposition (PAD) step to form the morphology-selective silicon nitride layer over the silicon nitride layer 205 in the opening 2070 and over the upper surface of the semiconductor device. In some embodiments, the PAD step can be performed under specific process conditions to form the morphology-selective silicon nitride layer 210. For example, the PAD step may include a deposition step with dichlorosilane and ammonia, which may employ specific heater power (e.g., approximately 10 watts to 45 watts, at least 10 watts and 45 watts, and / or similar power), specific temperature (e.g., approximately 450°C, at least 450°C, and / or similar temperature), and specific time (e.g., approximately 1.5 seconds, at least 1.5 seconds, and / or similar time) to form the morphology-selective silicon nitride layer 210, but other process conditions are also possible. In some implementations, the deposition step needs to be performed a specific number of times (e.g., three times), followed by a processing step (e.g., treatment with argon and nitrogen at approximately 450°C). Details of the specific process conditions for forming the morphology-selective silicon nitride layer 210 are as follows: Figure 3 As shown.

[0078] like Figure 2C As shown, an etching step 215 can be performed to remove the morphology-selective silicon nitride layer 210 from the sidewall of the silicon nitride layer 205 in the opening 2070 of the semiconductor device. In some embodiments, the morphology-selective silicon nitride layer 210 (such as a second silicon nitride layer) is removed from the sidewall of the silicon nitride layer 205 (such as a first silicon nitride layer) in the opening 2070 of the semiconductor device without removing the silicon nitride layer 205 (such as the first silicon nitride layer) on the sidewall of the opening 2070, i.e., without reducing the thickness of the silicon nitride layer 205 on the sidewall of the opening 2070. In some embodiments, Figure 1The etching tool 110 in the environment 100 described above can be used to remove the morphology-selective silicon nitride layer 210 from the sidewalls of the silicon nitride layer 205 in the opening 2070 of the semiconductor device. In some embodiments, the etching step can be performed under specific process conditions to remove the morphology-selective silicon nitride layer 210 from the sidewalls of the silicon nitride layer 205 in the opening 2070 of the semiconductor device. For example, the etching step may use hydrofluoric acid diluted with water to a specific ratio (e.g., approximately 60 seconds, less than 60 seconds, and / or similar time) for a specific time to remove the morphology-selective silicon nitride layer 210 from the sidewalls of the silicon nitride layer 205 in the opening 2070 of the semiconductor device without removing the silicon nitride layer 205 on the sidewalls of the opening 2070, i.e., without reducing the thickness of the silicon nitride layer 205 on the sidewalls of the opening 2070. However, other process conditions are also possible. After wet etching, the total thickness of the silicon nitride layer 205 and the morphology-selective silicon nitride layer 210 at the bottom of the opening 2070 is no greater than 5 nm, and the total thickness at the top of the sacrificial oxide layer 2050 is greater than 7 nm.

[0079] like Figure 2D As shown, etching step 220 can be performed to remove the topographically selective silicon nitride layer 210 and silicon nitride layer 205 at the bottom of the opening 2070 of the semiconductor device. In some embodiments, the topographically selective silicon nitride layer 210 and silicon nitride layer 205 at the bottom of the opening 2070 of the semiconductor device are removed. In some embodiments, the epitaxial source / drain 2010 may be exposed without removing the silicon nitride layer 205 on the sidewall of the opening 2070 (i.e., without reducing the thickness of the silicon nitride layer 205 on the sidewall of the opening 2070), and the topographically selective silicon nitride layer 210 and silicon nitride layer 205 on the upper surface of the semiconductor device are also not removed. In some embodiments, the thickness of the silicon nitride layer 205 on the sidewall of the opening 2070 is reduced, and the thickness of the topographically selective silicon nitride layer 210 on the upper surface of the semiconductor device is also reduced. For example, the total thickness of the silicon nitride layer 205 on top of the sacrificial oxide layer 2050 and the morphology-selective silicon nitride layer 210 can be reduced to 5.5 nm, while the thickness of the silicon nitride layer 205 on the sidewall of the opening 2070 can be reduced to 1.5 nm. In some embodiments, the above-described... Figure 1 The etching tool 110 and mask (such as a mask over the upper surface of the semiconductor device) are used to remove the topography-selective silicon nitride layer 210 and silicon nitride layer 205 at the bottom of the opening 2070 of the semiconductor device. Removing the top of the top of the opening 2070 of the semiconductor device exposes the upper surface of the epitaxial source / drain 2010. Figure 2D As shown.

[0080] like Figure 2EAs shown, a pre-cleaning step 225 can be performed to remove native oxides on the epitaxial source / drain 2010. In some embodiments, the morphology-selective silicon nitride layer 210 and silicon nitride layer 205 on the upper surface of the semiconductor device can be removed without removing the silicon nitride layer 205 on the sidewall of the opening 2070 (e.g., without reducing the thickness of the silicon nitride layer 205 on the sidewall of the opening 2070). In some embodiments, the pre-cleaning tool 102 of the environment 100 described above can be used to remove any native oxides on the exposed upper surface of the epitaxial source / drain 2010 (at the bottom of the opening 2070). The pre-cleaning tool 102 may include a Collins pre-cleaning tool. The Collins pre-cleaning tool may employ a reactive gas containing a combination of nitrogen trifluoride and ammonia to selectively remove native deep bottom oxide layers from the semiconductor device (e.g., minimizing silicon and nickel loss).

[0081] like Figure 2F As shown, a deposition step can be performed to form an adhesive layer 230 in the opening 2070 and on the upper surface of the semiconductor device. For example, the adhesive layer 230 can be deposited on the sacrificial oxide layer 2050, the second dielectric layer 2060, the silicon nitride layer 205, and portions of the epitaxial source / drain 2010. In some embodiments, the adhesive layer 230 may include materials such as titanium silicide, which can improve the subsequent deposition of the metal layer 235 in the opening 2070 of the semiconductor device. In some embodiments, the above-described... Figure 1 The deposition tool 104 of the environment 100 shown is used to form an adhesive layer 230 on top of the sacrificial oxide layer 2050, the second dielectric layer 2060, the silicon nitride layer 205, and the epitaxial source / drain 2010.

[0082] like Figure 2G As shown, a deposition step can be performed to form a metal layer 235 in the opening 2070 of the semiconductor device via the adhesive layer 230. In some embodiments, a deposition step can be performed to form the metal layer 235 in the opening 2070 and at least a portion of the upper surface of the semiconductor device via the adhesive layer 230. The metal layer 235 may include conductive metals such as titanium, cobalt, tungsten, aluminum, copper, ruthenium, iridium, and / or the like. In some embodiments, the metal layer 235 may be formed in the opening 2070 and on the upper surface of the semiconductor device, may be formed on the upper surface of the adhesive layer 230, may be merged with the adhesive layer 230, and / or similarly formed. In some embodiments, a deposition step can be performed on the opening 2070 and on the upper surface of the semiconductor device, may be formed on the upper surface of the adhesive layer 230, may be merged with the adhesive layer 230, and / or similarly formed. Figure 1 The deposition tool 104 of the environment 100 shown above performs a deposition step to form a metal layer 235 in the opening 2070 of the semiconductor device via an adhesive layer 230.

[0083] like Figure 2HAs shown, a polishing step can be performed to form the metal drain 240 for the semiconductor device from the metal layer 235, for example, removing a portion of the metal layer 235 on the upper surface of the semiconductor device and planarizing the metal layer 235 to make it flush with the upper surface of the semiconductor device. In some embodiments, the metal drain 240 contacts the upper surface of the epitaxial source / drain 2010, and the silicon nitride layers 205 on both sides of the metal drain 240 can form silicon nitride spacers for the metal drain 240. The silicon nitride spacers may each have a specific thickness range (e.g., approximately 1.5 nm to approximately 2.1 nm) to reduce defects in the semiconductor device and avoid leakage current from the metal drain 240 to the metal gate 2030. In some embodiments, a... Figure 1 The etching tool 110 or chemical mechanical polishing tool in the environment 100 shown above is used to perform a planarization step, which can form a metal drain 240 for a semiconductor device from the metal layer 235.

[0084] like Figure 2I As shown, one or more additional steps can be performed to complete the semiconductor device. For example, a first etch stop layer 2080 may be formed wholly or partially on the second dielectric layer 2060, the metal gate 2030, the silicon nitride layer 205, and the metal drain 240. The material comprising the first etch stop layer 2080 may be silicon nitride, silicon oxynitride, silicon nitride having oxygen or carbon elements, and / or the like. In some embodiments, a more advanced method may be used. Figure 1 The deposition tool 104 of the environment 100 shown above is used to form a first etch stop layer 2080 on the second dielectric layer 2060, the metal gate 2030, the silicon nitride layer 205, and the metal drain 240.

[0085] A first interlayer dielectric layer 2090 may be formed on the first etch stop layer 2080. The first interlayer dielectric layer 2090 formed on the first etch stop layer 2080 may comprise materials such as silicon, silicon nitride, silicon oxide, and / or the like, and may electrically insulate components of a semiconductor device. In some embodiments, a first interlayer dielectric layer 2090 may be used. Figure 1 The deposition tool 104 of the environment 100 shown above is used to form a first interlayer dielectric layer 2090 on the first etch stop layer 2080.

[0086] A first contact 2100 may be formed within the first interlayer dielectric layer 2090 and the first etch stop layer 2080, and above the metal gate 2030, the silicon nitride layer 205, and the metal drain 240. The first contact 2100 may include conductive metals such as titanium, cobalt, tungsten, aluminum, copper, ruthenium, iridium, and / or the like. In some embodiments, a [missing information - likely a specific metal or material] may be used. Figure 1The deposition tool 104 and etching tool 110 of the environment 100 shown above form a first contact 2100 in the first interlayer dielectric layer 2090 and the first etch stop layer 2080, as well as on the metal gate 2030, the silicon nitride layer 205, and the metal drain 240.

[0087] A second etch stop layer 2110 may be formed on the first contact 2100 and the first interlayer dielectric layer 2090. The material of the second etch stop layer 2110 may include silicon nitride, silicon oxynitride, silicon nitride having oxygen or carbon elements, and / or the like. In some embodiments, a second etch stop layer may be used. Figure 1 The deposition tool 104 of the environment 100 shown above is used to form a second etch stop layer 2110 on the first contact 2100 and the first interlayer dielectric layer 2090.

[0088] A second interlayer dielectric layer 2120 may be formed on the second etch stop layer 2110. The second interlayer dielectric layer 2120 formed on the second etch stop layer 2110 may comprise materials such as silicon, silicon nitride, silicon oxide, and / or similar electrically insulating components of a semiconductor device. In some embodiments, a second interlayer dielectric layer 2120 may be used. Figure 1 The deposition tool 104 of the environment 100 shown above is used to form a second interlayer dielectric layer 2120 on the second etch stop layer 2110.

[0089] A second contact 2130 may be formed within the second interlayer dielectric layer 2120 and the second etch stop layer 2110, and on a portion of the first contact 2100. The second contact 2130 may include a conductive metal such as titanium, cobalt, tungsten, aluminum, copper, ruthenium, iridium, and / or the like. In some embodiments, a second contact 2130 may be used. Figure 1 The deposition tool 104 and etching tool 110 of the environment 100 shown above form a second contact 2130 in the second interlayer dielectric layer 2120 and the second etch stop layer 2110, and on the first contact 2100.

[0090] A third etch stop layer 2140 may be formed on the second contact 2130 and the second interlayer dielectric layer 2120. The material of the third etch stop layer 2140 may include silicon nitride, silicon oxynitride, silicon nitride containing oxygen or carbon, and / or the like. In some embodiments, a third etch stop layer may be used. Figure 1 The deposition tool 104 of the environment 100 shown above is used to form a third etch stop layer 2140 on the second contact 2130 and the second interlayer dielectric layer 2120.

[0091] A third interlayer dielectric layer 2150 may be formed on the third etch stop layer 2140. The third interlayer dielectric layer 2150 formed on the third etch stop layer 2140 may comprise materials such as silicon, silicon nitride, silicon oxide, and / or similar electrically insulating components of a semiconductor device. In some embodiments, a third interlayer dielectric layer 2150 may be used. Figure 1 The deposition tool 104 of the environment 100 shown above is used to form a third interlayer dielectric layer 2150 on the third etch stop layer 2140.

[0092] A second contact 2130 may be formed within the second interlayer dielectric layer 2120 and the second etch stop layer 2110, and on a portion of the first contact 2100. The second contact 2130 may include a conductive metal such as titanium, cobalt, tungsten, aluminum, copper, ruthenium, iridium, and / or the like. In some embodiments, a second contact 2130 may be used. Figure 1 The deposition tool 104 and etching tool 110 of the environment 100 shown above form a second contact 2130 in the second interlayer dielectric layer 2120 and the second etch stop layer 2110, and on the first contact 2100.

[0093] A third contact 2160 may be formed within the third interlayer dielectric layer 2150 and the third etch stop layer 2140, and on a portion of the second contact 2130. The third contact 2160 may include a conductive metal such as titanium, cobalt, tungsten, aluminum, copper, ruthenium, iridium, and / or the like. In some embodiments, a third contact 2160 may be used. Figure 1 The deposition tool 104 and etching tool 110 of the environment 100 shown above form a third contact 2160 in the third interlayer dielectric layer 2150 and the third etch stop layer 2140, and on the second contact 2130.

[0094] As mentioned above, Figures 2A to 2I This is just one or more examples. Other examples may differ. Figures 2A to 2I The example shown.

[0095] Figure 3 Table 300 is an example of the process conditions for depositing a morphology-selective silicon nitride layer to create spacers for the metal drain of a semiconductor device. For example, Table 300 provides cycle times (e.g., 90 minutes) for the main deposition process and cycle times (e.g., 30 minutes) for the post-processing process associated with the deposition of the morphology-selective silicon nitride layer. Table 300 provides illustrative ranges (e.g., liters per minute) for dichlorosilane, argon, ammonia, and nitrogen during the formation of the morphology-selective silicon nitride layer; illustrative ranges for chamber pressure (e.g., mTorr); illustrative ranges for heater power (e.g., watts); illustrative ranges for gap (e.g., millimeters); and illustrative time ranges associated with dichlorosilane feed and decontamination, ammonia feed and decontamination, heater start-up, and post-processing decontamination; and / or similar parameters.

[0096] As mentioned above, Figure 3 This is just one or more examples. Other examples may differ. Figure 3 The content shown.

[0097] Figure 4 This is a diagram illustrating the components of device 400. Device 400 may correspond to a pre-cleaning tool 102, a deposition tool 104, an annealing tool 106, a photoresist tool 108, an etching tool 110, and / or a wafer / die transfer tool 112. In some embodiments, the pre-cleaning tool 102, deposition tool 104, annealing tool 106, photoresist tool 108, etching tool 110, and / or wafer / die transfer tool 112 may include one or more devices 400 and / or one or more components of device 400. Figure 4 As shown, the device 400 may include a bus 410, a processor 420, a memory 430, a storage component 440, an input component 450, an output component 460, and a communication interface 470.

[0098] The components included in bus 410 enable communication between components of device 400. Processor 420 may be implemented in hardware, firmware, or a combination of hardware and software. Processor 420 may be a central processing unit, graphics processing unit, accelerator processor, microprocessor, microcontroller, digital signal processor, field-programmable gate array, application-specific integrated circuit, or other processing component. In some embodiments, processor 420 includes one or more processors that are programmable to perform functions. Memory 430 includes random access memory, read-only memory, and / or other types of dynamic or static storage devices (such as flash memory, magnetic memory, and / or optical memory) to store information and / or instructions used by processor 420.

[0099] Storage component 440 stores information and / or software related to the operation and use of device 400. For example, storage component 440 may include hard disks (such as magnetic disks, optical disks, magneto-optical disks, and / or solid-state disks), compact disks, digital multifunction optical disks, floppy disks, cartridges, and / or other types of non-transitory computer-readable media and corresponding devices.

[0100] Input component 450 enables device 400 to receive information, such as user input (e.g., touchscreen, keyboard, keypad, mouse, buttons, switches, and / or microphone). Input component 450 may additionally or alternatively include sensors used for sensing signals (e.g., GPS components, accelerometers, gyroscopes, and / or actuators). Output component 460 may provide output signals from device 400 (e.g., via a display, speaker, and / or one or more light-emitting diodes).

[0101] Communication interface 470 includes transceiver-like components (such as a transceiver and / or separate receiver and transmitter) that enable device 400 to communicate with other devices (e.g., via wired lines, wireless lines, or combinations thereof). Communication interface 470 enables device 400 to receive information from another device and / or provide information to another device. For example, communication interface 470 may include an Ethernet interface, an optical interface, a coaxial interface, an infrared interface, an RF power interface, a Universal Serial Bus interface, a Wireless Local Area Interface, a Cellular Network Interface, and / or similar interfaces.

[0102] Apparatus 400 may perform one or more of the processes described herein. Non-transitory computer-readable media (such as memory 430 and / or storage element 440) may store software instructions executed by processor 420, which in turn may execute the software instructions to enable apparatus 400 to perform these processes. Computer-readable media are defined herein as non-transitory memory devices. Memory devices include memory space in a single physical storage device or memory space distributed across multiple physical storage devices.

[0103] Software instructions may be read into memory 430 and / or storage device 440 via communication interface 470 from another computer-readable medium (or another device). When executing the software instructions in memory 430 and / or storage device 440, processor 420 may perform one or more processes as described herein. Hardware circuitry may additionally or alternatively replace or combine with the software instructions to perform one or more processes as described herein. Therefore, the embodiments described herein are not limited to any specific combination of hardware circuitry and software.

[0104] Figure 4 The number and configuration of components shown are merely examples. Specifically, device 400 may include additional components, fewer components, different components, or components with... Figure 4 The components shown are configured differently. One or more functions performed by another set of components of device 400 may be performed by one set of components of device 400, either additionally or alternatively.

[0105] Figure 5 In one example, a flowchart of process 500 for manufacturing a semiconductor device is provided, based on the selective deposition of a silicon nitride layer to create a spacer for the metal drain of the semiconductor device. In some embodiments, the device (such as...) Figure 1 (One or more tools shown) to perform Figure 5 One or more process steps. In some embodiments, it may be composed of one or more process steps. Figure 1 The apparatus of one or more tools shown, or independent of Figure 1 Another device or set of devices for one or more tools shown, performing Figure 5One or more process steps. These steps may be performed additionally or alternatively by one or more components of device 400, such as processor 420, memory 430, storage component 440, input component 450, output component 460, communication interface 470, and / or the like. Figure 5 One or more process steps.

[0106] like Figure 5 As shown, step 510 of process 500 may include forming a first silicon nitride layer in an opening of a semiconductor device and on the upper surface of the semiconductor device, wherein the semiconductor device includes an epitaxial source / drain and a metal gate. For example, a silicon nitride layer 205 may be formed in an opening 2070 of the semiconductor device and on the upper surface of the semiconductor device, as described above. In some embodiments, the semiconductor device includes an epitaxial source / drain 2010 and a metal gate 2030.

[0107] like Figure 5 As shown, step 520 of process 500 may include forming a second silicon nitride layer over the first silicon nitride layer in the opening of the semiconductor device and over the upper surface of the semiconductor device. For example, a morphology-selective silicon nitride layer 210 may be formed over the silicon nitride layer 205 in the opening 2070 of the semiconductor device and over the upper surface of the semiconductor device, as described above. In some embodiments, the morphology-selective silicon nitride layer 210 may be a sacrificial layer.

[0108] like Figure 5 As shown, step 530 of process 500 may include removing a second silicon nitride layer from the sidewall of a first silicon nitride layer in an opening of the semiconductor device. For example, a morphology-selective silicon nitride layer 210 may be removed from the sidewall of silicon nitride layer 205 in an opening 2070 of the semiconductor device, as described above.

[0109] like Figure 5 As shown, step 540 of process 500 may include removing the second silicon nitride layer and the first silicon nitride layer at the bottom of the opening 2070 of the semiconductor device. For example, the morphology-selective silicon nitride layer 210 and the silicon nitride layer 205 at the bottom of the opening 2070 of the semiconductor device may be removed.

[0110] like Figure 5 As shown, step 550 of process 500 may include forming a metal layer in the opening and on the upper surface of the semiconductor device. For example, a metal layer 235 may be formed in the opening and on the upper surface of the semiconductor device, as described above.

[0111] like Figure 5As shown, step 560 of process 500 may include removing a metal layer from the upper surface of the semiconductor device to form a metal drain in an opening of the semiconductor device. For example, a metal layer 235 may be removed from the upper surface of the semiconductor device to form a metal drain 240 in an opening 2070 of the semiconductor device, as described herein.

[0112] Process 500 may include additional implementations, such as any single implementation or any combination of the implementations described below, and / or related to one or more other processes described in other paragraphs.

[0113] In the first embodiment, the step of forming the second silicon nitride layer includes performing a plasma-assisted atomic layer deposition step to form the second silicon nitride layer on the first silicon nitride layer in the opening of the semiconductor device.

[0114] In the second embodiment (which may be used alone or in combination with the first embodiment), the step of removing the second silicon nitride layer from the sidewall of the first silicon nitride layer includes an etching step using hydrofluoric acid diluted with water to a specific ratio for a specific time to remove the second silicon nitride layer from the sidewall of the first silicon nitride layer in the opening of the semiconductor device.

[0115] In the third embodiment (which may be used alone or in combination with one or more of the first and second embodiments), the step of forming a second silicon nitride layer on top of a first silicon nitride layer in an opening of a semiconductor device includes: forming a first portion of the second silicon nitride layer on a sidewall of the first silicon nitride layer in the opening of the semiconductor device; and forming a second portion of the second silicon nitride layer on top of the first silicon nitride layer at the bottom of the opening of the semiconductor device and on the upper surface of the semiconductor device, wherein the second portion of the second silicon nitride layer is denser than the first portion of the second silicon nitride layer.

[0116] In the fourth embodiment (which may be used alone or in combination with one or more of the first to third embodiments), a method for forming a second silicon nitride layer on top of a first silicon nitride layer in an opening of a semiconductor device includes a deposition step using dichlorosilane and ammonia, a specific heater power, a specific temperature, and a specific time to form the second silicon nitride layer on the first silicon nitride layer.

[0117] In the fifth embodiment (which may be used alone or in combination with one or more of the first to fourth embodiments), the first silicon nitride layer and the second silicon nitride layer formed on the opening sidewall of the semiconductor device can reduce defects in the semiconductor device and prevent leakage current from the metal drain to the metal gate.

[0118] In the sixth embodiment (which may be used alone or in combination with one or more of the first to fifth embodiments), process 500 includes forming a first interlayer dielectric layer on a metal gate, a first silicon nitride layer, and a metal drain; forming a first contact in the first interlayer dielectric layer and on the metal gate, the first silicon nitride layer, and the metal drain; forming a second interlayer dielectric layer on the first interlayer dielectric layer and on the first contact; forming a second contact in the second interlayer dielectric layer and on a portion of the first contact; forming a second interlayer dielectric layer on the second interlayer dielectric layer and on the second contact; and forming a third contact in the third interlayer dielectric layer and on a portion of the second contact.

[0119] In the seventh embodiment (which may be used alone or in combination with one or more of the first to sixth embodiments), process 500 includes forming a fluorine-free tungsten layer on the upper surface of the metal gate.

[0120] In the eighth embodiment (which may be used alone or in combination with one or more of the first to seventh embodiments), a first silicon nitride layer is provided on the sidewall to form a silicon nitride spacer for forming a metal drain, and the silicon nitride spacer isolates the metal drain from the metal gate.

[0121] In the ninth embodiment (which may be used alone or in combination with one or more of the first to eighth embodiments), a second silicon nitride layer is formed before the metal drain is formed to avoid etch loss of the first silicon nitride layer from the opening sidewall.

[0122] In the tenth embodiment (which may be used alone or in combination with one or more of the first to ninth embodiments), the step of removing the second silicon layer from the sidewall of the first silicon nitride layer includes performing an etching step in which hydrofluoric acid is diluted with water to a specific ratio, for example, approximately 500:1, to avoid removing the first silicon nitride layer from the opening sidewall of the semiconductor device.

[0123] In the eleventh embodiment (which may be used alone or in combination with one or more of the first to tenth embodiments), the step of forming the second silicon nitride layer includes performing a plasma-assisted atomic layer deposition step using a specific heater power, a specific temperature, and a specific time to form the second silicon nitride layer on the first silicon nitride layer in the opening of the semiconductor device.

[0124] Although Figure 5 Examples of steps shown in process 500; some embodiments of process 500 may include additional steps, fewer steps, different steps, or steps similar to those in process 500. Figure 5 Different steps can be configured. Two or more steps of process 500 can be performed in parallel, either additionally or alternatively.

[0125] In this approach, the method of manufacturing a semiconductor device may involve depositing a morphology-selective silicon nitride layer 210 to create spacers for the metal drain 240 of the semiconductor device. The morphology-selective silicon nitride layer 210 acts as a sacrificial layer, ensuring that the thickness of the spacers (e.g., formed of silicon nitride 205) avoids and / or reduces defects in the semiconductor device, avoids and / or reduces leakage current from the metal drain 240 to the metal gate 2030, and / or similar functions. For example, the morphology-selective silicon nitride layer 210 can reduce the formation of dark voltage contrast defects, bright voltage contrast defects, and / or similar defects in the semiconductor device.

[0126] As detailed above, some embodiments described herein provide methods for manufacturing a semiconductor device. The method may include forming a first silicon nitride layer in an opening of the semiconductor device and on a top surface of the semiconductor device, wherein the semiconductor device includes an epitaxial source / drain and a metal gate. The method may include forming a second silicon nitride layer in the opening of the semiconductor device, on top of the first silicon nitride layer and on the top surface of the semiconductor device, wherein the second silicon nitride layer is a sacrificial layer. The method may include removing the second silicon nitride layer from the sidewalls of the first silicon nitride layer in the opening of the semiconductor device, and removing the second silicon nitride layer and the first silicon nitride layer from the bottom of the opening of the semiconductor device. The method may include forming a metal layer in the opening and on the top surface of the semiconductor device, and removing the metal layer from the top surface of the semiconductor device to form a metal drain in the opening of the semiconductor device.

[0127] In some embodiments, the step of forming a second silicon nitride layer includes performing a plasma-assisted atomic layer deposition step to form a second silicon nitride layer on a first silicon nitride layer in an opening of a semiconductor device.

[0128] In some embodiments, the step of removing the second silicon nitride layer from the sidewall of the first silicon nitride layer includes an etching step for a specific time using hydrofluoric acid diluted with water to a specific ratio to remove the second silicon nitride layer from the sidewall of the first silicon nitride layer in the opening of the semiconductor device.

[0129] In some embodiments, the step of forming a second silicon nitride layer on a first silicon nitride layer in an opening of a semiconductor device includes forming a first portion of the second silicon nitride layer on a sidewall of the first silicon nitride layer in the opening of the semiconductor device; and forming a second portion of the second silicon nitride layer on a first silicon nitride layer at the bottom of the opening of the semiconductor device, wherein the second portion of the second silicon nitride layer is denser than the first portion of the second silicon nitride layer.

[0130] In some embodiments, the step of forming a second silicon nitride layer on a first silicon nitride layer in an opening of a semiconductor device includes a deposition step with dichlorosilane and ammonia, employing specific heater power, specific temperature, and specific time to form the second silicon nitride layer on the first silicon nitride layer.

[0131] In some embodiments, the thickness of the first silicon nitride layer and the second silicon nitride layer formed on the sidewall of the opening of the semiconductor device reduces defects in the semiconductor device and avoids leakage current from the metal drain to the metal gate.

[0132] In some embodiments, the method further includes forming a first interlayer dielectric layer on a metal gate, a first silicon nitride layer, and a metal drain; forming a first contact in the first interlayer dielectric layer and on the metal gate, the first silicon nitride layer, and the metal drain; forming a second interlayer dielectric layer on the first interlayer dielectric layer and the first contact; forming a second contact in the second interlayer dielectric layer and on a portion of the first contact; forming a third interlayer dielectric layer on the second interlayer dielectric layer and the second contact; and forming a third contact in the third interlayer dielectric layer and on a portion of the second contact.

[0133] As detailed above, the embodiments described herein provide a method for manufacturing a semiconductor device. The method may include forming an epitaxial source / drain in a dielectric layer; forming a first interlayer dielectric layer on the upper surface of the dielectric layer; and forming a metal gate in the dielectric layer and the first interlayer dielectric layer, adjacent to the epitaxial source / drain. The method may include forming a first silicon nitride layer on the upper surface of the semiconductor device, on a plurality of sidewalls of an opening in the first interlayer dielectric layer, and on the epitaxial source / drain; and forming a second silicon nitride layer on the first silicon nitride layer, wherein the second silicon nitride layer is a sacrificial layer. The method may include removing the second silicon nitride layer from the first silicon nitride layer on the sidewall of the opening, without removing the first silicon nitride layer from the sidewall of the opening; and removing the second silicon nitride layer and the first silicon nitride layer at the bottom of the opening, without removing the first silicon nitride layer from the sidewall of the opening. The method may include removing a second silicon nitride layer and a first silicon nitride layer on the upper surface of a semiconductor device without removing the first silicon nitride layer from the sidewall of the opening; and forming a metal drain in the opening and above an epitaxial source / drain, wherein the first silicon nitride layer on the sidewall of the opening forms a plurality of silicon nitride spacers for the metal drain.

[0134] In some embodiments, the method further includes forming a second interlayer dielectric layer on a metal gate, a metal drain, and a silicon nitride spacer; forming a first contact in the second interlayer dielectric layer and on the metal gate, the metal drain, and the silicon nitride spacer; forming a third interlayer dielectric layer on the second interlayer dielectric layer and on the first contact; forming a second contact in the third interlayer dielectric layer and on a portion of the first contact; forming a fourth interlayer dielectric layer on the third interlayer dielectric layer and on the second contact; and forming a third contact in the fourth interlayer dielectric layer and on a portion of the second contact.

[0135] In some embodiments, the method further includes forming a fluorine-free tungsten layer on the upper surface of the metal gate.

[0136] In some embodiments, the silicon nitride spacers each have a specific thickness to reduce defects in the semiconductor device and prevent leakage current from the metal drain to the metal gate.

[0137] In some embodiments, the step of forming a second silicon nitride layer on a first silicon nitride layer includes performing a plasma-assisted atomic layer deposition step to form a second silicon nitride layer on a first silicon nitride layer.

[0138] In some embodiments, silicon nitride spacers isolate the metal drain from the metal gate.

[0139] In some embodiments, before forming the metal drain, the second silicon nitride layer avoids etch loss of the first silicon nitride layer from the sidewalls of the opening.

[0140] As detailed above, some embodiments described herein provide methods for manufacturing a semiconductor device. The method may include forming a first silicon nitride layer in an opening of the semiconductor device and on a top surface of the semiconductor device, wherein the semiconductor device includes an epitaxial source / drain and a metal gate. The method may include performing a plasma-assisted atomic layer deposition (PAD) step to form a second silicon nitride layer in the opening of the semiconductor device, on top of the first silicon nitride layer and on the top surface of the semiconductor device, wherein the PAD step uses dichlorosilane and ammonia. The method may include performing a first etching step to remove the second silicon nitride layer from the sidewalls of the first silicon nitride layer in the opening of the semiconductor device, wherein the first etching step uses hydrofluoric acid diluted with water to a specific ratio. The method may include performing a second etching step to remove the second silicon nitride layer and the first silicon nitride layer at the bottom of the opening of the semiconductor device, wherein the second etching step does not remove the first silicon nitride layer from the sidewalls of the opening of the semiconductor device. The method may include depositing a metal layer in the opening of the semiconductor device to form a metal drain in the opening of the semiconductor device.

[0141] In some embodiments, hydrofluoric acid is diluted with water in a specific ratio of approximately 500:1 to avoid removal of the first silicon nitride layer from the sidewall of the opening in the semiconductor device.

[0142] In some embodiments, the plasma-assisted atomic layer deposition step employs specific heater power, specific temperature, and specific time.

[0143] In some embodiments, the thickness of the first silicon nitride layer and the second silicon nitride layer formed on the sidewall of the opening of the semiconductor device reduces defects in the semiconductor device and avoids leakage current from the metal drain to the metal gate.

[0144] In some embodiments, a first silicon nitride layer formed on the sidewall of the opening creates a plurality of spacers on a plurality of sides of the metal drain, wherein each spacer has a specific thickness to reduce defects in the semiconductor device and prevent leakage current from the metal drain to the metal gate.

[0145] In some embodiments, the method further includes forming a first interlayer dielectric layer on a metal gate, a first silicon nitride layer, and a metal drain; forming a first contact in the first interlayer dielectric layer and on the metal gate, the first silicon nitride layer, and the metal drain; forming a second interlayer dielectric layer on the first interlayer dielectric layer and the first contact; forming a second contact in the second interlayer dielectric layer and on a portion of the first contact; forming a third interlayer dielectric layer on the second interlayer dielectric layer and the second contact; and forming a third contact in the third interlayer dielectric layer and on a portion of the second contact.

[0146] The features of the above embodiments are beneficial for those skilled in the art to understand this disclosure. Those skilled in the art should understand that this disclosure can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of this disclosure, and changes, substitutions, or modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: A first silicon nitride layer is formed in an opening of the semiconductor device and on the upper surface of the semiconductor device, wherein the semiconductor device includes an epitaxial source / drain and a metal gate. A second silicon nitride layer is formed on the first silicon nitride layer in the opening of the semiconductor device and on the upper surface of the semiconductor device, wherein the second silicon nitride layer is a sacrificial layer; The second silicon nitride layer is removed from the sidewall of the first silicon nitride layer in the opening of the semiconductor device; Remove the second silicon nitride layer and the first silicon nitride layer from the bottom of the opening of the semiconductor device; A metal layer is formed in the opening and on the upper surface of the semiconductor device; as well as The metal layer is removed from the upper surface of the semiconductor device to form a metal drain in the opening of the semiconductor device.

2. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the step of forming the second silicon nitride layer comprises: A plasma-assisted atomic layer deposition step is performed to form the second silicon nitride layer on the first silicon nitride layer in the opening of the semiconductor device.

3. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the step of removing the second silicon nitride layer from the sidewall of the first silicon nitride layer comprises: The second silicon nitride layer is removed from the sidewall of the first silicon nitride layer in the opening of the semiconductor device by an etching step using hydrofluoric acid diluted with water to a specific ratio for a specific time.

4. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the step of forming the second silicon nitride layer on the first silicon nitride layer in the opening of the semiconductor device comprises: The first portion of the second silicon nitride layer is formed on the sidewall of the first silicon nitride layer in the opening of the semiconductor device; as well as The second portion of the second silicon nitride layer is formed on the first silicon nitride layer at the bottom of the opening of the semiconductor device. The second portion of the second silicon nitride layer is denser than the first portion of the second silicon nitride layer.

5. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the step of forming the second silicon nitride layer on the first silicon nitride layer in the opening of the semiconductor device comprises: A deposition step using dichlorosilane and ammonia is performed, employing specific heater power, specific temperature, and specific time to form the second silicon nitride layer on the first silicon nitride layer.

6. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the thicknesses of the first silicon nitride layer and the second silicon nitride layer formed on the sidewall of the opening of the semiconductor device reduce defects in the semiconductor device and prevent leakage current from the metal drain to the metal gate.

7. The method of manufacturing a semiconductor device as claimed in claim 1, further comprising: A first interlayer dielectric layer is formed on the metal gate, the first silicon nitride layer, and the metal drain. A first contact is formed in the first interlayer dielectric layer and above the metal gate, the first silicon nitride layer, and the metal drain; A second interlayer dielectric layer is formed on the first interlayer dielectric layer and the first junction; A second contact is formed in the second interlayer dielectric layer and on a portion of the first contact; A third interlayer dielectric layer is formed on the second interlayer dielectric layer and the second junction; and A third contact is formed in the third interlayer dielectric layer and on a portion of the second contact.

8. A method for manufacturing a semiconductor device, comprising: An epitaxial source / drain is formed in a dielectric layer; A first interlayer dielectric layer is formed on the upper surface of the dielectric layer; A metal gate is formed in the dielectric layer and the first interlayer dielectric layer to be adjacent to the epitaxial source / drain. A first silicon nitride layer is formed on the upper surface of the semiconductor device, on the multiple sidewalls of an opening in the first interlayer dielectric layer, and on the epitaxial source / drain. A second silicon nitride layer is formed on the first silicon nitride layer, wherein the second silicon nitride layer is a sacrificial layer; The second silicon nitride layer is removed from the first silicon nitride layer on the sidewall of the opening, without removing the first silicon nitride layer from the sidewall of the opening; Remove the second silicon nitride layer and the first silicon nitride layer at the bottom of the opening, without removing the first silicon nitride layer from the sidewall of the opening; Remove the second silicon nitride layer and the first silicon nitride layer from the upper surface of the semiconductor device, without removing the first silicon nitride layer from the sidewall of the opening; as well as A metal drain is formed in the opening and above the epitaxial source / drain, wherein the first silicon nitride layer on the sidewall of the opening forms a plurality of silicon nitride spacers for the metal drain.

9. The method of manufacturing a semiconductor device as claimed in claim 8, further comprising: A second interlayer dielectric layer is formed on the metal gate, the metal drain, and the silicon nitride spacer; A first contact is formed in the second interlayer dielectric layer and on the metal gate, the metal drain, and the silicon nitride spacer; A third interlayer dielectric layer is formed on the second interlayer dielectric layer and the first junction; A second contact is formed in the third interlayer dielectric layer and on a portion of the first contact; A fourth interlayer dielectric layer is formed on the third interlayer dielectric layer and the second junction; and A third contact is formed in the fourth interlayer dielectric layer and on a portion of the second contact.

10. The method of manufacturing a semiconductor device as claimed in claim 8, further comprising: A fluorine-free tungsten layer is formed on the upper surface of the metal gate.

11. The method of manufacturing a semiconductor device as claimed in claim 8, wherein each of the silicon nitride spacers has a specific thickness to reduce defects in the semiconductor device and prevent leakage current from the metal drain to the metal gate.

12. The method of manufacturing a semiconductor device as claimed in claim 8, wherein the step of forming the second silicon nitride layer on the first silicon nitride layer comprises: A plasma-assisted atomic layer deposition step is performed to form the second silicon nitride layer on the first silicon nitride layer.

13. The method of manufacturing a semiconductor device as claimed in claim 8, wherein the silicon nitride spacer isolates the metal drain from the metal gate.

14. The method of manufacturing a semiconductor device as claimed in claim 8, wherein, prior to forming the metal drain, the second silicon nitride layer avoids etch loss of the first silicon nitride layer from the sidewall of the opening.

15. A method for manufacturing a semiconductor device, comprising: A first silicon nitride layer is formed in an opening of the semiconductor device and on the upper surface of the semiconductor device, wherein the semiconductor device includes an epitaxial source / drain and a metal gate. A plasma-assisted atomic layer deposition step is performed to form a second silicon nitride layer on the first silicon nitride layer in the opening of the semiconductor device and on the upper surface of the semiconductor device, wherein the plasma-assisted atomic layer deposition step uses dichlorosilane and ammonia; A first etching step is performed to remove the second silicon nitride layer from the sidewall of the first silicon nitride layer in the opening of the semiconductor device, wherein the first etching step uses hydrofluoric acid diluted with water to a specific ratio; A second etching step is performed to remove the second silicon nitride layer and the first silicon nitride layer at the bottom of the opening of the semiconductor device, wherein the second etching step does not remove the first silicon nitride layer from the sidewall of the opening of the semiconductor device; as well as A metal layer is deposited in the opening of the semiconductor device to form a metal drain in the opening of the semiconductor device.

16. The method of manufacturing a semiconductor device as claimed in claim 15, wherein the hydrofluoric acid is diluted with water in a specific ratio of approximately 500:1 to avoid removal of the first silicon nitride layer from the sidewall of the opening of the semiconductor device.

17. The method of manufacturing a semiconductor device as claimed in claim 15, wherein the plasma-assisted atomic layer deposition step employs specific heater power, specific temperature, and specific time.

18. The method of manufacturing a semiconductor device as claimed in claim 15, wherein the thicknesses of the first silicon nitride layer and the second silicon nitride layer formed on the sidewall of the opening of the semiconductor device reduce defects in the semiconductor device and prevent leakage current from the metal drain to the metal gate.

19. The method of manufacturing a semiconductor device as claimed in claim 15, wherein the first silicon nitride layer formed on the sidewall of the opening creates a plurality of spacers on a plurality of sides of the metal drain. Each of the spacers has a specific thickness to reduce defects in the semiconductor device and prevent leakage current from the metal drain to the metal gate.

20. The method of manufacturing the conductor device as claimed in claim 15, further comprising: A first interlayer dielectric layer is formed on the metal gate, the first silicon nitride layer, and the metal drain. A first contact is formed in the first interlayer dielectric layer and above the metal gate, the first silicon nitride layer, and the metal drain; A second interlayer dielectric layer is formed on the first interlayer dielectric layer and the first junction; A second contact is formed in the second interlayer dielectric layer and on a portion of the first contact; A third interlayer dielectric layer is formed on the second interlayer dielectric layer and the second junction; and A third contact is formed in the third interlayer dielectric layer and on a portion of the second contact.

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