Method for manufacturing a semiconductor device

Abstract

A method for manufacturing a semiconductor device is provided. The semiconductor device manufacturing method according to an exemplary embodiment disclosed includes patterning a substrate to form an active pattern, forming a trench penetrating the active pattern, forming a support layer covering the trench, forming a first opening at the support layer, forming a gate electrode layer filling the trench through the first opening, and forming a bit line structure electrically connected to the active pattern. The support layer includes a base portion covering a top surface of the active pattern and a support portion disposed in the trench.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2021-0052343, filed on April 22, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The disclosed exemplary embodiments relate to a semiconductor device and a method for manufacturing the semiconductor device. Specifically, the disclosed exemplary embodiments relate to a semiconductor device including a gate structure and a method for manufacturing the semiconductor device. Background Technology

[0003] Semiconductor devices are highly valued in the electronics industry due to their characteristics, such as miniaturization, multifunctionality, and low manufacturing cost. Semiconductor devices can be classified into semiconductor memory devices for storing logical data, semiconductor logic devices for arithmetically processing logical data, and hybrid semiconductor devices that include both memory and logic elements. With advancements in the electronics industry, the demand for improved characteristics in semiconductor devices is increasing. For example, there is a growing need for higher reliability, higher speed, and greater multifunctionality. To meet these demands, the structures within semiconductor devices are becoming increasingly complex. Furthermore, semiconductor devices are becoming increasingly highly integrated. Summary of the Invention

[0004] The disclosed exemplary embodiments reduce the complexity of the processes used to manufacture semiconductor devices.

[0005] A method for manufacturing a semiconductor device according to some disclosed exemplary embodiments includes: patterning a substrate to form an active pattern; forming a trench penetrating the active pattern; forming a support layer covering the trench; forming a first opening in the support layer; forming a gate electrode layer filling the trench through the first opening; and forming a bit line structure electrically connected to the active pattern. The support layer includes a base covering a top surface of the active pattern and a support portion disposed in the trench.

[0006] A method for manufacturing a semiconductor device according to some disclosed exemplary embodiments includes: patterning a substrate to form an active pattern; forming a trench penetrating the active pattern; forming a support layer on the active pattern; forming a first opening at the support layer; forming a gate electrode layer filling the trench through the first opening; and forming a bit line structure electrically connected to the active pattern. The support layer and the gate electrode layer comprise the same conductive material.

[0007] A method for manufacturing a semiconductor device according to some disclosed exemplary embodiments includes: patterning a substrate to form an active pattern; forming a trench penetrating the active pattern; forming a preliminary barrier layer in the trench; forming a support layer on the preliminary barrier layer; forming a first opening at the support layer; forming a gate electrode layer filling the trench through the first opening; and forming a bit line structure electrically connected to the active pattern. The preliminary barrier layer and the support layer comprise the same conductive material.

[0008] A semiconductor device according to some exemplary embodiments disclosed includes: an active pattern; a trench penetrating the active pattern; a gate structure located in the trench; and a bit line structure electrically connected to the active pattern. The gate structure includes: a first electrode portion; and a second electrode portion located on the first electrode portion. The first electrode portion includes a first tilted top surface and a second tilted top surface in contact with the second electrode portion. The second electrode portion includes a first tilted bottom surface in contact with the first tilted top surface and a second tilted bottom surface in contact with the second tilted top surface. Attached Figure Description

[0009] Figure 1A This is a plan view of a semiconductor device according to some embodiments of the present disclosure.

[0010] Figure 1B It is along Figure 1A The sectional view taken by line A1-A1'.

[0011] Figure 1C It is along Figure 1A The sectional view taken by line B1-B1'.

[0012] Figure 1D It is along Figure 1A The sectional view taken by line C1-C1'.

[0013] Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A and Figure 8A This is a plan view illustrating the steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0014] Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 8B They are respectively along Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A and Figure 8A The sectional view taken by line A2-A2'.

[0015] Figure 2C , Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C and Figure 8C It is along 2A respectively, Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A and Figure 8A The sectional view taken by line B2-B2'.

[0016] Figure 2D , Figure 3D , Figure 4D , Figure 5D , Figure 6D , Figure 7D and Figure 8D They are respectively along Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A and Figure 8A The sectional view taken by line C2-C2'.

[0017] Figure 3E yes Figure 3D A magnified view of region E1.

[0018] Figure 6E yes Figure 6D A magnified view of region E2.

[0019] Figure 9 This is a cross-sectional view used to explain the gate structure of a semiconductor device according to some embodiments of the present disclosure.

[0020] Figure 10 This is a cross-sectional view used to explain the gate structure of a semiconductor device according to some embodiments of the present disclosure.

[0021] Figure 11 This is a cross-sectional view used to explain the gate structure of a semiconductor device according to some embodiments of the present disclosure.

[0022] Figure 12A , Figure 12B and Figure 12C This is for explaining the manufacturing process according to some embodiments of this disclosure. Figure 11 A cross-sectional view of a method for using a semiconductor device is shown in the figure. Detailed Implementation

[0023] Figure 1A This is a plan view of a semiconductor device according to some exemplary embodiments disclosed. Figure 1B It is along Figure 1A The sectional view taken by line A1-A1' in the diagram. Figure 1C It is along Figure 1A The sectional view taken by line B1-B1' in the diagram. Figure 1D It is along Figure 1A The sectional view taken by line C1-C1' in the diagram.

[0024] Reference Figure 1A , Figure 1B , Figure 1C and Figure 1D The semiconductor device 1 may include a substrate 100. The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may be a silicon substrate. The substrate 100 may be in the form of a plate extending along a plane defined by a first direction D1 and a second direction D2 and / or a plane parallel to the first direction D1 and the second direction D2. The first direction D1 and the second direction D2 may intersect each other. For example, the first direction D1 and the second direction D2 may intersect each other perpendicularly.

[0025] The substrate 100 may include an active pattern AP. The active pattern AP may extend in a third direction D3. The third direction D3 may intersect with the first direction D1 and the second direction D2. For example, the third direction D3 may be parallel to the plane defined by the first direction D1 and the second direction D2 and / or a plane parallel to the first direction D1 and the second direction D2. The upper portion of the substrate 100 projecting in a fourth direction D4 may be defined as an active pattern AP. The fourth direction D4 may intersect with the first direction D1, the second direction D2, and the third direction D3. For example, the fourth direction D4 may intersect perpendicularly with the first direction D1, the second direction D2, and the third direction D3. The active patterns AP may be spaced apart from each other.

[0026] A component isolation layer (STI) can be disposed in the space provided between active patterned APs. The active patterned APs can be defined by the component isolation layer STI. Each of the active patterned APs can be (e.g., in a planar view) surrounded by the component isolation layer STI. The active patterned APs can be spaced apart from each other by the component isolation layer STI. The component isolation layer STI can include or be formed of an insulating material. For example, the component isolation layer STI can include or be formed of an oxide.

[0027] A gate structure GT can be disposed on the second direction D2. The gate structures GT can be spaced apart from each other on the first direction D1. The gate structure GT can be disposed on the device isolation layer STI and the active pattern AP. One gate structure GT can contact multiple active pattern APs.

[0028] It will be understood that when an element is referred to as being "connected" or "bonded" to another element or "on" another element, the element may be directly connected or directly bonded to said other element or directly on said other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly connected" or "directly bonded" to another element, or referred to as being "in contact" with another element or "in contact with" another element, there are no intermediate elements at the point of contact.

[0029] The gate structure GT can penetrate the active pattern AP in the second direction D2. In some embodiments, two gate structures GT can penetrate one active pattern AP. Of course, the number of gate structures GT penetrating one active pattern AP is not limited to the above conditions.

[0030] In some embodiments, each of the active pattern APs may include a first impurity region RG1 between two gate structures GT penetrating the active pattern AP and second impurity regions RG2 spaced apart from each other with the first impurity region RG1 disposed therebetween. For example, each first impurity region RG1 may be disposed between a pair of second impurity regions RG2 (e.g., in a second direction D2 and / or a third direction D3). The gate structure GT may be disposed between the first impurity region RG1 and the second impurity region RG2 (e.g., in a plan view).

[0031] Each of the gate structures GT may include a gate insulating layer GI, a gate electrode GE, and a gate capping layer GP. The gate insulating layer GI may cover the surface of the active pattern AP and the surface of the device isolation layer STI. The gate electrode GE and the gate capping layer GP may be disposed within the gate insulating layer GI. The gate electrode GE may be spaced apart from the active pattern AP by the gate insulating layer GI. The gate capping layer GP may cover the top surface of the gate electrode GE. The gate insulating layer GI may include or be formed of an insulating material. For example, the gate insulating layer GI may include or be formed of an oxide. The gate electrode GE may include or be formed of a conductive material. For example, the gate electrode GE may include tungsten, ruthenium, titanium nitride, or molybdenum, or be formed of tungsten, ruthenium, titanium nitride, or molybdenum. The gate capping layer GP may include or be formed of an insulating material. For example, the gate capping layer GP may include or be formed of an oxide.

[0032] Interlayer insulating layer 110 may be disposed on gate cover layer GP, element isolation layer STI, and active pattern AP. Interlayer insulating layer 110 may include or be formed of insulating material. For example, interlayer insulating layer 110 may include or be formed of oxide. In some embodiments, interlayer insulating layer 110 may be a multilayer insulating layer.

[0033] A bit line structure BT can be disposed on a first direction D1. The bit line structures BT can be spaced apart from each other on a second direction D2. The bit line structures BT can be disposed on the interlayer insulating layer 110, the active pattern AP, and the component isolation layer STI. One bit line structure BT can be electrically connected to multiple active pattern APs. One bit line structure BT can contact multiple active pattern APs.

[0034] As used herein, a component described as an “electrical connection” is configured such that an electrical signal can be transmitted from one component to another (although such an electrical signal may attenuate in strength as it is transmitted and may be transmitted selectively).

[0035] Each of the bit line structures BT may include a bit line BL, a direct contact DC, a bit line spacer BS, and a bit line overlay BCP. The direct contact DC may each be disposed on a first impurity region RG1 of the active pattern AP. The direct contact DC may include or be formed of a conductive material.

[0036] Bit line BL can be disposed on direct contact DC and interlayer insulation layer 110. Bit line BL can contact multiple direct contacts DC. Bit line BL can be electrically connected to the first impurity region RG1 of active pattern AP via direct contacts DC.

[0037] Bit line BL may include a first conductive layer CL1 and a second conductive layer CL2. Each of the first conductive layers CL1 may extend in a first direction D1. Direct contacts DC may be disposed between the first conductive layers CL1 that are adjacent to each other in the first direction D1. For example, the first conductive layers CL1 may be disposed on opposite sides of the direct contacts DC. In some embodiments, the direct contacts DC and the first conductive layers CL1 may be combined without forming a boundary, thus constructing an integrated structure. For example, the direct contacts DC and the first conductive layers CL1 may be formed simultaneously and by the same manufacturing steps, including layer deposition and patterning. A second conductive layer CL2 may be disposed on the first conductive layers CL1 and the direct contacts DC. The second conductive layer CL2 may extend in the first direction D1. The second conductive layer CL2 may contact a plurality of first conductive layers CL1 and a plurality of direct contacts DC. Each of the first conductive layers CL1 and the second conductive layer CL2 may include or be formed of a conductive material.

[0038] Although the bit line BL is shown and described as including a first conductive layer CL1 and a second conductive layer CL2, the disclosed exemplary embodiments are not limited thereto. In some embodiments, the bit line BL may be a single conductive layer.

[0039] A bit line capping layer (BCP) may be disposed on the bit line BL. The bit line capping layer (BCP) may extend in a first direction D1. The bit line capping layer (BCP) may cover the top surface of the second conductive layer CL2 of the bit line BL. The bit line capping layer (BCP) may include or be formed of an insulating material. For example, the bit line capping layer (BCP) may include or be formed of an oxide.

[0040] Direct contact DC, bit line BL, and bit line cover layer BCP can be disposed between bit line spacers BS of bit line structure BT. The bit line spacers BS of bit line structure BT can be spaced apart from each other in a second direction D2, with the direct contact DC, bit line BL, and bit line cover layer BCP placed therebetween. The bit line spacers BS can cover the opposing sidewalls of each of the direct contact DC, bit line BL, and bit line cover layer BCP. The bit line spacers BS can extend in a first direction D1. The bit line spacers BS can include or be formed of an insulating material. For example, the bit line spacers BS can include or be formed of an oxide. In some embodiments, the bit line spacers BS can be multiple insulating layers.

[0041] A buried contact BC can be provided. The second impurity region RG2 of the active pattern AP can each contact the buried contact BC. The buried contact BC can be disposed between bit line structures BT. For example, the bit line structures BT can be disposed on opposite sides of the buried contact BC. The buried contact BC can include or be formed of a conductive material.

[0042] A fence 120 may be provided. The fence 120 may be disposed on the gate capping layer GP of the gate structure GT. The fence 120 may be disposed between buried contacts BC. For example, the buried contacts BC may be disposed on opposite sides of the fence 120. The fence 120 may be disposed between bit line structures BT. For example, the bit line structures BT may be disposed on opposite sides of the fence 120. The fence 120 may include or be formed of an insulating material. For example, the fence 120 may include or be formed of an oxide. In some embodiments, the fence 120 may be a multilayer insulating layer.

[0043] An insulating structure IS can be provided. The insulating structure IS can be provided on the bit line structure BT and the fence 120. The insulating structure IS can include or be formed of an insulating material. For example, the insulating structure IS can include or be formed of an oxide. In some embodiments, the insulating structure IS can be a multilayer insulating layer.

[0044] Landing pads (or "pads") can be provided. Each landing pad LP can individually contact the buried contact BC. The lower portion of the landing pad LP can be positioned between bit line structures BT. The lower portion of the landing pad LP can be positioned between fences 120. The upper portion of the landing pad LP can be surrounded by an insulating structure IS. The landing pad LP can penetrate the insulating structure IS. Multiple landing pads LP can be spaced apart from each other by bit line structures BT, fences 120, and insulating structure IS. The landing pad LP can include or be formed of conductive material.

[0045] The capacitor structure CS can be disposed on the bonding pad LP and the insulating structure IS. The capacitor structure CS may include a lower electrode LE, a capacitor insulating layer CI, and an upper electrode UE.

[0046] Each lower electrode LE can individually contact a bonding pad LP. Each of the lower electrodes LE can be electrically connected to a second impurity region RG2 of the active pattern AP via the bonding pad LP and the buried contact BC. A capacitor insulating layer CI can be disposed between the lower electrode LE and the upper electrode UE. The capacitor insulating layer CI can include or be formed of an insulating material. For example, the capacitor insulating layer CI can include or be formed of an oxide. The lower electrode LE and the upper electrode UE can include or be formed of a conductive material.

[0047] Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A and Figure 8A This is a plan view used to explain a method for manufacturing a semiconductor device according to some exemplary embodiments disclosed. Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 8B They are respectively along Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A and Figure 8A The sectional view taken by line A2-A2' in the diagram. Figure 2C , Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C and Figure 8C They are respectively along Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A and Figure 8A The sectional view taken by line B2-B2' in the figure. Figure 2D , Figure 3D , Figure 4D , Figure 5D , Figure 6D , Figure 7D and Figure 8D They are respectively along Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A and Figure 8A The sectional view taken by line C2-C2' in the diagram. Figure 3E yes Figure 3D A magnified view of region E1. Figure 6E yes Figure 6D A magnified view of region E2.

[0048] Reference Figure 2A , Figure 2B , Figure 2C and Figure 2D The substrate 100 can be patterned to form active patterns AP. Element isolation layers STI can be formed in the space provided between the active patterns AP.

[0049] Subsequently, a trench TR penetrating the active pattern AP can be formed. The trench TR can extend in the second direction D2. The trench TR can be formed by etching the active pattern AP and the component isolation layer STI. The trench TR can be defined by the surface of the active pattern AP and the surface of the component isolation layer STI.

[0050] Reference Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E Gate insulating layers GI can be formed separately in trench TR. The gate insulating layers GI can be conformally formed on the surfaces of the active pattern AP and the device isolation layer STI defining the trench TR. The formation of the gate insulating layers GI may include: conformally forming a preliminary gate insulating layer on the surface of the active pattern AP and the surface of the device isolation layer STI, and removing the upper portion of the preliminary gate insulating layer, thereby dividing the preliminary gate insulating layer into multiple gate insulating layers GI.

[0051] Subsequently, a support layer SCL can be formed on the active pattern AP, gate insulating layer GI, and component isolation layer STI. The support layer SCL can cover the trench TR. The support layer SCL can close the trench TR. For example, the upper part of the trench TR can be blocked by the support layer SCL. As the support layer SCL is formed to close the trench TR, a closed empty space SP can be formed in the trench TR. The closed empty space SP can be surrounded by the gate insulating layer GI and the support layer SCL. The closed empty space SP can be defined by the surface of the gate insulating layer GI and the surface of the support layer SCL. In some embodiments, the support layer SCL can include or be formed of a conductive material. For example, the support layer SCL can include, or be formed of, tungsten, titanium nitride, molybdenum, or ruthenium. For example, the closed empty space SP can be in a vacuum state or can be filled with gas / air.

[0052] In some embodiments, a formation process with relatively poor step coverage can be used to form the support layer SCL. For example, physical vapor deposition (PVD) or chemical vapor deposition (CVD) can be used to form the support layer SCL.

[0053] Reference Figure 3E The support layer SCL may include a base BA and multiple support portions SU. The portion of the support layer SCL covering the top surface AP_T of the active pattern AP may be defined as the base BA. The portion of the support layer SCL covering the top surface GI_T of the gate insulating layer GI may be defined as the base BA. The base BA may be in the form of a plate extending along a plane defined by a first direction D1 and a second direction D2 and / or a plane parallel to the first direction D1 and the second direction D2. The bottom surface BA_B of the base BA may contact the top surface AP_T of the active pattern AP. The base BA may be disposed at a level higher than the level (or height) of the top surface AP_T of the active pattern AP. The bottom surface BA_B of the base BA may contact the top surface GI_T of the gate insulating layer GI. The base BA may be disposed at a level higher than the level of the top surface GI_T of the gate insulating layer GI. For example, the base BA can be the entire upper part of the support layer SCL (e.g., on the fourth direction D4) disposed at a vertical level higher than the vertical level of the top surface GI_T of the gate insulating layer GI.

[0054] The support portion SU may protrude from the base BA in a direction opposite to the fourth direction D4. The support portion SU may be positioned at a level lower than the level of the base BA. The portion of the support layer SCL disposed in the trench TR may be defined as the support portion SU. The level of the boundary BO between the support portion SU and the base BA may be equal to the level of the bottom surface BA_B of the base BA, the level of the top surface AP_T of the active pattern AP, and the level of the top surface GI_T of the gate insulating layer GI. The support portion SU may be positioned at a level lower than the level of the top surface AP_T of the active pattern AP. The support portion SU may be positioned at a level lower than the level of the top surface GI_T of the gate insulating layer GI. For example, the support portion SU may be the entire lower portion of the support layer SCL (e.g., in the fourth direction D4) positioned at a vertical level lower than the vertical level of the top surface GI_T of the gate insulating layer GI.

[0055] The opposing sidewalls SU_S of the support portion SU can respectively contact the inner sidewall GI_IS of the gate insulating layer GI. The inner sidewall GI_IS of the gate insulating layer GI can be opposite to the outer sidewall of the gate insulating layer GI. The outer sidewall of the gate insulating layer GI can contact the active pattern AP. The support portion SU can be disposed between the inner sidewalls GI_IS of the gate insulating layer GI. The support portion SU can include a first inclined bottom surface SU_B1 and a second inclined bottom surface SU_B2. As each of the first inclined bottom surface SU_B1 and the second inclined bottom surface SU_B2 extends toward the gate insulating layer GI, the level of each of the first inclined bottom surface SU_B1 and the second inclined bottom surface SU_B2 of the support portion SU can gradually decrease. For example, the level of each of the first inclined bottom surface SU_B1 and the second inclined bottom surface SU_B2 of the support portion SU can gradually decrease in a direction close to the horizontal of the gate insulating layer GI (e.g., in a direction close to the sidewall of the trench TR). Each of the first inclined bottom surface SU_B1 and the second inclined bottom surface SU_B2 of the support portion SU can have a minimum level at its portion that contacts the gate insulating layer GI. The first inclined bottom surface SU_B1 and the second inclined bottom surface SU_B2 of the support portion SU may (e.g., at the central region of the trench TR) contact each other. As the first inclined bottom surface SU_B1 and the second inclined bottom surface SU_B2 (e.g., in a horizontal direction receding from the sidewall of the trench TR) extend toward each other, the level of each of the first inclined bottom surface SU_B1 and the second inclined bottom surface SU_B2 of the support portion SU may be raised. Each of the first inclined bottom surface SU_B1 and the second inclined bottom surface SU_B2 of the support portion SU may have its highest level at the portion where the first inclined bottom surface SU_B1 and the second inclined bottom surface SU_B2 contact each other. The first inclined bottom surface SU_B1 and the second inclined bottom surface SU_B2 of the support portion SU may (e.g., together with the inner sidewall GI_IS of the gate insulating layer GI) define a closed empty space SP.

[0056] Reference Figure 4A , Figure 4B , Figure 4C and Figure 4D A mask layer MA can be formed on the support layer SCL. The mask layer MA may include a plurality of first openings OP1. The first openings OP1 of the mask layer MA may extend in a first direction D1. A portion of the top surface BA_T of the base BA of the support layer SCL may be exposed by the first openings OP1 of the mask layer MA.

[0057] The formation of the mask layer MA may include forming a preliminary mask layer on the support layer SCL and patterning the preliminary mask layer.

[0058] Reference Figure 5A , Figure 5B , Figure 5C and Figure 5D The support layer SCL can be etched using a mask layer MA as an etching mask. For example, the support layer SCL can be etched by dry etching or wet etching. As the support layer SCL is etched, a second opening OP2 can be formed at the support layer SCL. As the first opening OP1 of the mask layer MA is transferred, the second opening OP2 can be formed. The second opening OP2 can extend in the first direction D1. The second opening OP2 can penetrate the support layer SCL. The trench TR can be reopened through the second opening OP2. The second opening OP2 can connect to the empty space SP in the trench TR. Through the second opening OP2, a portion of the top surface of the active pattern AP, a portion of the top surface of the element isolation layer STI, and a portion of the top surface of the gate insulating layer GI can be exposed. The second opening OP2 can be defined by the sidewalls of the support layer SCL.

[0059] Reference Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E A gate electrode layer (GEL) can be formed. The formation of the gate electrode layer (GEL) may include: depositing a conductive material in a direction toward the substrate 100 to form a preliminary gate electrode layer, and removing the upper portion of the preliminary gate electrode layer. For example, the upper portion of the preliminary gate electrode layer can be removed by a chemical mechanical polishing (CMP) process.

[0060] In some embodiments, when removing the upper portion of the preliminary gate electrode layer, the upper portion of the support layer SCL may also be removed. For example, the upper portion of the preliminary gate electrode layer and the upper portion of the support layer SCL can be removed simultaneously by a chemical mechanical polishing (CMP) process. As the upper portions of the preliminary gate electrode layer and the upper portions of the support layer SCL are removed, the top surfaces of the gate electrode layer GEL and the top surfaces of the support layer SCL can be planarized.

[0061] In some embodiments, the gate electrode layer (GEL) may comprise or be formed of the same material as the support layer (SCL). For example, the support layer (SCL) and the gate electrode layer (GEL) may comprise or be formed of tungsten.

[0062] In some embodiments, after the gate electrode layer (GEL) is formed, an annealing process may be performed to align the grains of the gate electrode layer (GEL) with the grains of the support layer (SCL).

[0063] The gate electrode layer (GEL) may include an intermediate portion (IN) disposed between the support layer (SCL) and the active pattern (AP). The intermediate portion (IN) may be stacked with the support layer (SCL) and the active pattern (AP) in the fourth direction (D4). For example, the intermediate portion (IN) may be stacked vertically with the support layer (SCL) and the active pattern (AP).

[0064] The intermediate portion IN may include a first inclined top surface IN_T1 that contacts a first inclined bottom surface SU_B1 of the support portion SU of the support layer SCL, and a second inclined top surface IN_T2 that contacts a second inclined bottom surface SU_B2 of the support portion SU of the support layer SCL. The first inclined top surface IN_T1 of the intermediate portion IN may be inclined in a manner corresponding to the first inclined bottom surface SU_B1 of the support portion SU. The second inclined top surface IN_T2 of the intermediate portion IN may be inclined in a manner corresponding to the second inclined bottom surface SU_B2 of the support portion SU. As each of the first inclined top surface IN_T1 and the second inclined top surface IN_T2 (e.g., in a horizontal direction near the sidewall of the gate insulating layer GI and / or the trench TR) extends toward the gate insulating layer GI, the level of each of the first inclined top surface IN_T1 and the second inclined top surface IN_T2 of the intermediate portion IN may decrease. Each of the first inclined top surface IN_T1 and the second inclined top surface IN_T2 of the intermediate portion IN may have a minimum level at its portion contacting the gate insulating layer GI. The first inclined top surface IN_T1 and the second inclined top surface IN_T2 of the intermediate portion IN can contact each other. As the first inclined top surface IN_T1 and the second inclined top surface IN_T2 (e.g., in a horizontal direction receding from the sidewall of the trench TR) extend toward each other, the level of each of the first inclined top surface IN_T1 and the second inclined top surface IN_T2 of the intermediate portion IN can be raised. Each of the first inclined top surface IN_T1 and the second inclined top surface IN_T2 of the intermediate portion IN can have its highest level at the portion where it contacts each other (e.g., in the central region of the trench TR).

[0065] A gate electrode layer (GEL) can be formed by depositing conductive material through the second opening OP2 of the support layer SCL. The gate electrode layer (GEL) can fill the trench TR. The gate electrode layer (GEL) can fill the empty space SP in the trench TR. The gate electrode layer (GEL) can fill the second opening OP2 of the support layer SCL.

[0066] Reference Figure 7A , Figure 7B , Figure 7C and Figure 7D The support layer SCL and the gate electrode layer GEL can be etched. For example, the support layer SCL and the gate electrode layer GEL can be etched by dry etching or wet etching.

[0067] In some embodiments, as shown in the accompanying drawings, the support layer SCL may be etched so that the support layer SCL is completely removed. In some embodiments, unlike the case shown in the accompanying drawings, the support layer SCL may be etched so that a portion of the support layer SCL is retained.

[0068] As the gate electrode layer (GEL) is etched, it can be divided into multiple gate electrodes (GE). As the gate electrode layer (GEL) and the support layer (SCL) are etched, the top surface of the active pattern (AP) and the top surface of the component isolation layer (STI) can be exposed.

[0069] As the support layer SCL and the gate electrode layer GEL are etched, the upper part of the trench TR can be opened.

[0070] Reference Figure 8A , Figure 8B , Figure 8C and Figure 8D A gate capping layer GP can be formed on the gate electrode GE. An interlayer insulating layer 110 can be formed on the active pattern AP, the element isolation layer STI, and the gate capping layer GP.

[0071] Bit line structures BT can be formed on the interlayer insulating layer 110, the active pattern AP, and the component isolation layer STI. In some embodiments, the formation of the bit line structure BT may include: forming a preliminary first conductive layer; forming a first contact recess that exposes a portion of the active pattern AP while penetrating the preliminary first conductive layer and the interlayer insulating layer 110; forming a preliminary direct contact layer in the first contact recess; forming a preliminary second conductive layer on the preliminary first conductive layer and the preliminary direct contact layer; forming a preliminary bit line cover layer on the preliminary second conductive layer; patterning the preliminary direct contact layer, the preliminary first conductive layer, the preliminary second conductive layer, and the preliminary bit line cover layer to form a direct contact DC, a first conductive layer CL1, a second conductive layer CL2, and a bit line cover layer BCP; and forming bit line spacers BS on the sidewalls of the direct contact DC, the first conductive layer CL1, the second conductive layer CL2, and the bit line cover layer BCP.

[0072] A first impurity region RG1 can be formed in the active pattern AP. The first impurity region RG1 can be formed by doping the portion of the active pattern AP exposed by the first contact groove with impurities before forming a preliminary direct contact layer in the first contact groove.

[0073] A buried contact BC, a bonding pad LP, a fence 120, and an insulating structure IS can be formed. In some embodiments, the formation of the buried contact BC, the bonding pad LP, the fence 120, and the insulating structure IS may include: forming a second contact groove that exposes a portion of the active pattern AP while penetrating the interlayer insulation layer 110; forming a preliminary buried contact layer that fills the second contact groove; patterning the preliminary buried contact layer to form the buried contact BC; forming a fence 120 between the buried contacts BC; forming a preliminary bonding pad layer that covers the fence 120; patterning the preliminary bonding pad layer to form the bonding pad LP; and forming the insulating structure IS in the space formed by the patterning of the preliminary bonding pad layer.

[0074] Reference Figure 1A , Figure 1B , Figure 1C and Figure 1D A capacitor structure CS can be formed on the bonding pad LP and the insulating structure IS. The formation of the capacitor structure CS may include forming a lower electrode LE, forming a capacitor insulating layer CI covering the lower electrode LE, and forming an upper electrode UE on the bonding pad LP.

[0075] In the semiconductor device manufacturing method according to the disclosed exemplary embodiments, a support layer SCL is formed to support the active pattern AP, thereby preventing the active pattern AP from tilting during the process for forming the gate electrode layer GEL.

[0076] In the semiconductor device manufacturing method according to the disclosed exemplary embodiments, the support layer SCL and the gate electrode layer GEL comprise the same material or are formed from the same material, thereby reducing the difficulty of the processes for polishing and etching the support layer SCL and the gate electrode layer GEL.

[0077] Figure 9 This is a cross-sectional view used to explain the gate structure of a semiconductor device according to some exemplary embodiments disclosed.

[0078] Reference Figure 9 Semiconductor device 2 may include an active pattern APa and a gate structure GTa that penetrates the active pattern APa. The gate structure GTa may include a gate insulating layer GIa, a gate electrode GEa, and a gate capping layer GPa. The gate electrode GEa may include a first electrode portion GEP1a and a second electrode portion GEP2a. The second electrode portion GEP2a may be disposed on the first electrode portion GEP1a.

[0079] The entire bottom surface of the second electrode portion GEP2a can contact the first electrode portion GEP1a. The second electrode portion GEP2a may include a first inclined bottom surface GEP2a_B1 and a second inclined bottom surface GEP2a_B2. The first electrode portion GEP1a may include a first inclined top surface GEP1a_T1 and a second inclined top surface GEP1a_T2. The first inclined top surface GEP1a_T1 can contact the first inclined bottom surface GEP2a_B1. The second inclined top surface GEP1a_T2 can contact the second inclined bottom surface GEP2a_B2. The entire bottom surface of the gate capping layer GPa can contact the top surface of the second electrode portion GEP2a.

[0080] In some embodiments, the first electrode portion GEP1a and the second electrode portion GEP2a may include or be formed of the same conductive material. For example, the first electrode portion GEP1a and the second electrode portion GEP2a may include or be formed of tungsten. When the first electrode portion GEP1a and the second electrode portion GEP2a include or are formed of the same conductive material, the first electrode portion GEP1a and the second electrode portion GEP2a may be distinguished from each other at their boundary according to their crystal structures. For example, the size / density of the grain boundary between the first electrode portion GEP1a and the second electrode portion GEP2a may be relatively larger than the size / density of the grain boundary in the first electrode portion GEP1a (e.g., in the bulk portion or center of the first electrode portion GEP1a) and the grain boundary in the second electrode portion GEP2a (e.g., in the bulk portion or center of the second electrode portion GEP2a). Of course, the disclosed exemplary embodiments are not limited to the above conditions, and the first electrode portion GEP1a and the second electrode portion GEP2a may have a continuous / uniform crystal structure at their boundary.

[0081] In some embodiments, the first electrode portion GEP1a and the second electrode portion GEP2a may comprise or be formed of different conductive materials. For example, the first electrode portion GEP1a may comprise or be formed of tungsten, and the second electrode portion GEP2a may comprise or be formed of molybdenum.

[0082] In the process of etching a support layer and a gate electrode layer in a semiconductor device manufacturing method according to some exemplary embodiments disclosed, a portion of the support layer may be retained to form a second electrode portion GEP2a of the gate electrode GEa, and a portion of the gate electrode layer may be retained to form a first electrode portion GEP1a of the gate electrode GEa.

[0083] Figure 10This is a cross-sectional view used to explain the gate structure of a semiconductor device according to some exemplary embodiments disclosed.

[0084] Reference Figure 10 Semiconductor device 3 may include an active pattern APb and a gate structure GTb penetrating the active pattern APb. The gate structure GTb may include a gate insulating layer GIb, a gate electrode GEb, and a gate capping layer GPb. The gate electrode GEb may include a first electrode portion GEP1b and a second electrode portion GEP2b. The second electrode portion GEP2b may be disposed on the first electrode portion GEP1b. The second electrode portions GEP2b may be spaced apart from each other with the first electrode portions GEP1b placed therebetween. For example, the second electrode portions GEP2b may be spaced apart from each other with the upper portion of the first electrode portion GEP1b (e.g., in the horizontal direction) placed therebetween.

[0085] The second electrode portion GEP2b may include a sloped bottom surface GEP2b_B. The first electrode portion GEP1b may include sloped surfaces GEP1b_SL that respectively contact the sloped bottom surface GEP2b_B of the second electrode portion GEP2b. The top surface GEP1b_T of the first electrode portion GEP1b may be disposed between the sloped surfaces GEP1b_SL of the first electrode portion GEP1b. The top surface of the second electrode portion GEP2b and the top surface GEP1b_T of the first electrode portion GEP1b may contact the bottom surface of the gate capping layer GPb. For example, the top surface of the second electrode portion GEP2b and the top surface GEP1b_T of the first electrode portion GEP1b may (e.g., in the fourth direction) be at the same vertical level.

[0086] In some embodiments, the first electrode portion GEP1b and the second electrode portion GEP2b may include the same conductive material or be formed of the same conductive material. In some embodiments, the first electrode portion GEP1b and each of the second electrode portions GEP2b may include different conductive materials from each other or be formed of different conductive materials from each other.

[0087] Figure 11 This is a cross-sectional view used to explain the gate structure of a semiconductor device according to some exemplary embodiments disclosed.

[0088] Reference Figure 11 Semiconductor device 4 may include an active pattern APc and a gate structure GTc that penetrates the active pattern APc. The gate structure GTc may include a gate insulating layer GIc, a gate electrode GEc, and a gate capping layer GPc. The gate electrode GEc may include a blocking portion BRc, a first electrode portion GEP1c, and a second electrode portion GEP2c.

[0089] The blocking portion BRc can be disposed on the gate insulating layer GIc. The first electrode portion GEP1c can be disposed on the blocking portion BRc. The second electrode portion GEP2c can be disposed on the first electrode portion GEP1c. The first electrode portion GEP1c and the second electrode portion GEP2c can be separated from the gate insulating layer GIc by the blocking portion BRc.

[0090] The top surface of the second electrode portion GEP2c and the top surface BRc_T of the blocking portion BRc can contact the bottom surface of the gate capping layer GPc.

[0091] In some embodiments, the blocking portion BRc and the second electrode portion GEP2c may comprise or be formed of the same conductive material. For example, the blocking portion BRc and the second electrode portion GEP2c may comprise or be formed of titanium nitride. When the blocking portion BRc and the second electrode portion GEP2c comprise or are formed of the same conductive material, the blocking portion BRc and the second electrode portion GEP2c may be distinguished from each other at their boundary based on their crystal structures. For example, the size / density of the grain boundary disposed between the blocking portion BRc and the second electrode portion GEP2c may be relatively larger than the size / density of the grain boundary in the blocking portion BRc (e.g., in the main body or center of the blocking portion BRc) and the size / density of the grain boundary in the second electrode portion GEP2c (e.g., in the main body or center of the second electrode portion GEP2c). Of course, the disclosed exemplary embodiments are not limited to the above conditions, and the blocking portion BRc and the second electrode portion GEP2c may have a continuous / uniform crystal structure at their boundary.

[0092] In some embodiments, the first electrode portion GEP1c may include a conductive material different from or formed of a conductive material different from the conductive material of the blocking portion BRc and the second electrode portion GEP2c. For example, the first electrode portion GEP1c may include or be formed of tungsten, and the blocking portion BRc and the second electrode portion GEP2c may include or be formed of titanium nitride.

[0093] Figure 12A , Figure 12B and Figure 12C It is an explanation used to manufacture according to Figure 11 A cross-sectional view of a method for constructing a semiconductor device.

[0094] Reference Figure 12AA trench TRc can be formed that penetrates the active pattern APc. A gate insulating layer GIc can be formed in the trench TRc. A preliminary barrier layer pBRc can be formed that covers the active pattern APc and the gate insulating layer GIc. A portion of the preliminary barrier layer pBRc can be formed in the trench TRc.

[0095] Reference Figure 12B A support layer SCLc can be formed on the initial barrier layer pBRc. In some embodiments, the support layer SCLc may include the same conductive material as the conductive material of the initial barrier layer pBRc or be formed of the same conductive material as the conductive material of the initial barrier layer pBRc.

[0096] The support layer SCLc can seal the trench TRc. As the support layer SCLc forms, a closed void space SPc can be defined within the trench TRc. The void space SPc can be defined by the surface of the initial barrier layer pBRc and the surface of the support layer SCLc. For example, the closed void space SPc can be in a vacuum state or can be filled with gas / air.

[0097] Reference Figure 12C A gate electrode layer (GELc) can be formed. The formation of the gate electrode layer (GELc) may include forming an opening at the support layer (SCLc) and forming the gate electrode layer (GELc) through the opening in the support layer (SCLc). The gate electrode layer (GELc) can completely fill the trench (TRc). The gate electrode layer (GELc) can fill the empty space (SPc) in the trench (TRc).

[0098] In some embodiments, the gate electrode layer GELc may include a conductive material that is different from the conductive material of the initial barrier layer pBRc and the support layer SCLc.

[0099] Reference Figure 11 The initial barrier layer pBRc, the support layer SCLc, and the gate electrode layer GELc can be etched to form a gate electrode GEc comprising a barrier portion BRc, a first electrode portion GEP1c, and a second electrode portion GEP2c. The barrier portion BRc can be formed by etching the initial barrier layer pBRc, the second electrode portion GEP2c can be formed by etching the support layer SCLc, and the first electrode portion GEP1c can be formed by etching the gate electrode layer GELc.

[0100] A semiconductor device manufacturing method according to the disclosed exemplary embodiments may include forming a support layer, thereby reducing the complexity of the processes used to manufacture the semiconductor device. For example, the support layer may help improve structural stability during the manufacturing process and improve the characteristics of the semiconductor device.

[0101] Although the disclosed embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various modifications can be made without departing from the scope of the disclosure and without changing the essential features disclosed. Therefore, the above embodiments should be considered in a descriptive sense only and not for limiting purposes.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: Patterning the substrate creates an active pattern. Forming grooves that penetrate the active pattern; Forming a support layer to cover the trench; A first opening is formed at the support layer; A gate electrode layer filling the trench is formed through the first opening; as well as A bitline structure is formed that is electrically connected to the active pattern. The support layer includes a base covering the top surface of the active pattern and a support portion disposed in the trench.

2. The method according to claim 1, further comprising: A gate insulating layer is formed in the trench. The support portion contacts the sidewall of the gate insulating layer.

3. The method according to claim 1, wherein, The support layer and the gate electrode layer are made of the same material.

4. The method according to claim 1, wherein, The support includes an inclined bottom surface.

5. The method according to claim 4, wherein, The gate electrode layer includes an inclined top surface that contacts the inclined bottom surface of the support.

6. The method according to claim 1, wherein, The step of forming the first opening at the support layer includes: A mask layer is formed on the support layer to expose a portion of the support layer; and Use a mask layer as an etching mask to etch the support layer.

7. The method according to claim 1, wherein, The step of forming the gate electrode layer includes filling the first opening with the gate electrode layer.

8. A method for manufacturing a semiconductor device, the method comprising: Patterning the substrate creates an active pattern. Forming grooves that penetrate the active pattern; A support layer is formed on the active pattern; A first opening is formed at the support layer; A gate electrode layer filling the trench is formed through the first opening; as well as A bitline structure is formed that is electrically connected to the active pattern. The support layer and the gate electrode layer both contain the same conductive material.

9. The method according to claim 8, wherein: The first opening extends in the first direction; and The trench extends in a second direction that intersects with the first direction.

10. The method according to claim 8, further comprising: This flattens the top surface of the support layer and the top surface of the gate electrode layer.

11. The method according to claim 8, further comprising: The support layer and the gate electrode layer are etched to form the gate electrode.

12. The method according to claim 11, wherein, The steps for forming the gate electrode include: Completely remove the support layer.

13. The method according to claim 11, wherein, The gate electrode includes a portion of the support layer and a portion of the gate electrode layer.

14. The method according to claim 8, wherein, The steps to form the support layer include: A closed, empty space is formed in the trench.

15. A method for manufacturing a semiconductor device, the method comprising: Patterning the substrate creates an active pattern. Forming grooves that penetrate the active pattern; A preliminary barrier layer is formed in the trench; A support layer is formed on the initial barrier layer; A first opening is formed at the support layer; A gate electrode layer filling the trench is formed through the first opening; as well as A bitline structure is formed that is electrically connected to the active pattern. The initial barrier layer and the support layer both contain the same conductive material.

16. The method of claim 15, wherein: The steps of forming the support layer include creating closed voids in the trench; and The enclosed space is defined by the surface of the support layer and the surface of the initial barrier layer.

17. The method according to claim 15, wherein, A portion of the support layer is set in the trench.

18. The method according to claim 17, wherein, The portion of the support layer includes a sloping bottom surface.

19. The method of claim 17, further comprising: The initial barrier layer, support layer, and gate electrode layer are etched to form the gate electrode.

20. The method according to claim 19, wherein, The steps of forming a gate electrode include etching a preliminary barrier layer to form a barrier portion, etching a gate electrode layer to form a first electrode portion on the barrier portion, and etching a support layer to form a second electrode portion on the first electrode portion.

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