Packaging structure

Abstract

A package structure includes a redistribution structure, a semiconductor die over the redistribution structure, and a plurality of bonding elements under the redistribution structure. The semiconductor die has a first sidewall and a second sidewall connected to each other. The plurality of bonding elements includes a first column of bonding elements and a second column of bonding elements. In a top view, the second column of bonding elements is configured between the first column of bonding elements and an extension line of the second sidewall. A minimum distance between the second column of bonding elements and the first sidewall is greater than a minimum distance between the first column of bonding elements and the first sidewall.

Description

Technical Field

[0001] The embodiments of the present invention relate to packaging structures, and more particularly to three-dimensional packaging structures. Background Technology

[0002] The integrated circuit (IC) industry has experienced rapid growth. Continuous advancements in semiconductor manufacturing processes have led to the creation of semiconductor devices with more precise components and / or higher levels of integration. In the development of ICs, functional density (the number of interconnects per unit chip area) generally increases while feature size (the smallest element (or line) that can be manufactured using the process) decreases. This miniaturization process generally contributes to increased production efficiency and reduced associated costs.

[0003] Chip packaging not only protects semiconductor devices from environmental contaminants but also provides an interface for the packaged semiconductor devices. Currently, smaller package structures with smaller areas or lower heights have been developed for packaging semiconductor devices.

[0004] To further improve the density and functionality of semiconductor dies, new packaging technologies have been developed. These relatively new semiconductor die packaging technologies are facing manufacturing challenges. Summary of the Invention

[0005] This invention provides a packaging structure including a redistribution structure; a semiconductor die above the redistribution structure, wherein the semiconductor die has a first sidewall and a second sidewall connected to each other; and a plurality of bonding elements below the redistribution structure, including a first column of bonding elements and a second column of bonding elements, wherein in a top view, the second column of bonding elements is disposed between the extension lines of the first column of bonding elements and the second sidewall, wherein the minimum distance between the second column of bonding elements and the first sidewall is greater than the minimum distance between the first column of bonding elements and the first sidewall.

[0006] This invention provides a packaging structure including a redistribution structure; a semiconductor die above the redistribution structure, wherein the semiconductor die has a first sidewall and a second sidewall; and a first row of bonding elements electrically coupled to the semiconductor die via the redistribution structure. In a top view, the first row of bonding elements is adjacent to the first sidewall and includes a first bonding element, a second bonding element, and a third bonding element arranged consecutively. An extension line of the second sidewall passes between the second bonding element and the third bonding element, and a first distance between the first bonding element and the second bonding element is less than a second distance between the second bonding element and the third bonding element.

[0007] This invention provides a packaging structure including a redistribution structure; a semiconductor die above a first surface of the redistribution structure, wherein the semiconductor die has a first sidewall and a second sidewall intersecting at a corner; and a first column of bonding elements above a second surface of the redistribution structure, wherein in a top view, the first column of bonding elements is adjacent to the second sidewall and spaced apart from the second sidewall by a first distance, the first column of bonding elements includes a first bonding element, which is the bonding element closest to the corner in the first column of bonding elements, and a second distance between the first bonding element and the corner is greater than the first distance. Attached Figure Description

[0008] The embodiments of the invention can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of various components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of the invention.

[0009] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G as well as Figure 1H This is a cross-sectional schematic diagram illustrating the formation of the packaging structure at various intermediate stages according to some embodiments of the present disclosure.

[0010] Figure 1A-1 Some embodiments of this disclosure are shown Figure 1A The diagram shows a top view of the packaging structure.

[0011] Figure 1B-1 Some embodiments of this disclosure are shown Figure 1B The diagram shows a top view of the packaging structure.

[0012] Figure 1G-1 Some embodiments of this disclosure are shown Figure 1G The diagram shows a top view of the packaging structure.

[0013] Figure 1G-2 Some embodiments of this disclosure are shown Figure 1G-1 The diagram shows an enlarged top view of region R to show more details of the joining elements.

[0014] Figure 2 Some embodiments of this disclosure are shown Figure 1G-2 A top-view diagram illustrating the variations.

[0015] Figure 3 Some embodiments of this disclosure are shown Figure 2A top-view diagram illustrating the variations.

[0016] Figure 4 Some embodiments of this disclosure are shown Figure 1H Examples of variations of the cross-sectional schematic diagram shown in the figure.

[0017] Figure 4-1 Some embodiments of this disclosure are shown Figure 4 The diagram shows a top view of the packaging structure.

[0018] Figure 5 Some embodiments of this disclosure are shown Figure 4 Examples of variations of the cross-sectional schematic diagram shown in the figure.

[0019] Figure 5-1 Some embodiments of this disclosure are shown Figure 5 The diagram shows a top view of the packaging structure.

[0020] Figure 6 Some embodiments of this disclosure are shown Figure 4-1 or Figure 5-1 The diagram shows an enlarged top view of region R to show more details of the joining elements.

[0021] Figure 7 Some embodiments of this disclosure are shown Figure 4-1 or Figure 5-1 The diagram shows an enlarged top view of region R to show more details of the joining elements.

[0022] Figure 8 Some embodiments of this disclosure are shown Figure 4-1 or Figure 5-1 The diagram shows an enlarged top view of region R to show more details of the joining elements.

[0023] Figure 9 Some embodiments of this disclosure are shown Figure 5-1 The diagram shows an enlarged top view of region R1 to show more details of the joining elements.

[0024] Figure 10 Some embodiments of this disclosure are shown Figure 5-1 The diagram shows an enlarged top view of region R1 to show more details of the joining elements.

[0025] Figure 11 Some embodiments of this disclosure are shown Figure 5-1 The diagram shows an enlarged top view of region R1 to show more details of the joining elements.

[0026] The attached figures are labeled as follows: 102: Supporting substrate 104: Adhesive tape 106: Relay Structure 106A: Top surface of the re-reinforced structure 106B: Bottom surface of the reconstituted structure 106I: Fan-in area 106O: Fan-out region 108: Conductive components 110: Conductive components 112: Conductive components 1141 / 1142 / 1143 / 1144: Insulation layer 116: Conductive components 120: Semiconductor die 122: Semiconductor substrate 122B: Back surface of semiconductor substrate 122F: Front surface of semiconductor substrate 124: Integrated Circuits 126: Internal Wiring Structure 128: Intermetallic dielectric layer 130: Conductive pad 132: Passivation layer 134: Under-bump metal 136: Connecting element 138: Bottom filling material 140: Molded compound 142: Adhesive tape 144: Supporting substrate 146: Packaging Structure 148: Connecting element 148I: Internal bonding element 148O: External coupling element 148P: Boundary Joining Element 160: Substrate 162: Conductive pad 164: Bottom Filling Material 502: Package 504: Memory chip 506: Conductive via 508: Conductive pad 602: Packaged Component 604: Packaged Component 902: Packaged Component 904: Packaged Components 906: Packaged Components a1 / a2 / a3 / a4: (Lines) A1 / A2 / A3 / A4 / A5 / A6 / A7 / A8: Line b1 / b2 / b3 / b4: Column B1 / B2 / B3 / B4 / B5 / B6 / B7 / B8: Column C1 / C2 / C3 / C4: Corner D1: Dimensions D2 / D2': Distance D3 / D4: Distance D5: Width D6: Diameter D7 / D8 / D9 / D10 / D11 / D12 / D13: Distance D14 / D15 / D16 / D17 / D18 / D19: Distance I12 / I21 / I56 / I65: Connecting elements R: Region R1: Region S1 / S2 / S3 / S4: Sidewall SE1 / SE2: Extension lines O23 / O24 / O25: Connecting elements O32 / O36 / O37: Connecting elements O42 / O52 / O63 / O73: Connecting elements O83 / O93 / O103: Connecting elements P46 / P47: Connecting elements P / P': Pitch Detailed Implementation

[0027] Numerous embodiments or examples are disclosed below for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, the embodiments of the invention may repeat reference values ​​and / or letters in various examples. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0028] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," and "higher," may be used to facilitate the description of the relationship between one or more components or features in the accompanying drawings and another component or feature(s). Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0029] Those skilled in the art will understand that the term "substantially" as used herein refers to terms such as "substantially flat" or "substantially coplanar." In some embodiments, the adjective "substantially" may be removed. Where applicable, the term "substantially" may also include embodiments with "completely," "entirely," "all," etc. Where applicable, the term "substantially" may also represent 90% or higher, such as 95% or higher, particularly 99% or higher, encompassing 100%. Furthermore, terms such as "substantially parallel" or "substantially perpendicular" should be interpreted as not excluding minor variations from a particular configuration, and in some embodiments may include, for example, deviations of up to 10°. The term "substantially" does not exclude "entirely," for example, in some embodiments, a composition "substantially Y-free" may be completely Y-free.

[0030] The term “about” as used herein in relation to a particular distance or size should be interpreted as not excluding minor variations from the particular distance or size, and in some embodiments may include, for example, deviations of up to 10%. The term “about” in relation to the numerical value x may, in some embodiments, represent a value of x ± 5% or ± 10%.

[0031] This document describes some embodiments of the present disclosure. Additional operating steps may be provided before, during, and after these embodiments. Some described stages may be replaced or eliminated for different embodiments. Additional components may be added to the semiconductor device structure. Some described components may be replaced or eliminated for different embodiments. Although some embodiments described herein perform operating steps in a specific order, these operating steps may also be performed in another logical order.

[0032] This invention relates to three-dimensional (3D) packaged or three-dimensional integrated circuit devices. Other components and processes may also be included. For example, test structures may be included to assist in verification testing of the 3D packaged or three-dimensional integrated circuit device. Test structures may include test pads, such as those formed in a redistribution layer or on a substrate, which allow for testing of the 3D packaged or three-dimensional integrated circuit, the use of probes and / or probe cards, and similar applications. Verification testing can be performed on intermediate and final structures. Furthermore, several structures and methods disclosed herein can be used in conjunction with test research methods, including intermediate verification of known good dies, to improve yield and reduce costs.

[0033] This document provides embodiments of several package structures. The package structure may include a semiconductor die above the overlay structure and bonding elements below the overlay structure. By defining a keep-out region for the bonding elements, an appropriate distance can be maintained between the bonding elements and the corners of the semiconductor die, thereby reducing or mitigating tensile stress caused by the bonding elements. Therefore, the risk of underfill material cracking can be reduced, thereby improving the performance and reliability of the package structure.

[0034] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G as well as Figure 1H This is a cross-sectional schematic diagram illustrating the formation of the packaging structure at various intermediate stages according to some embodiments of the present disclosure.

[0035] According to some embodiments of this disclosure, such as Figure 1A As shown, a carrier substrate 102 is received or provided. In some embodiments, the carrier substrate 102 is a ceramic substrate, a glass substrate, a polymer substrate, a semiconductor substrate, or other suitable substrate.

[0036] According to some embodiments of this disclosure, such as Figure 1A As shown, adhesive tape 104 is disposed above the carrier substrate 102. In some embodiments, adhesive tape 104 is sensitive to energy beam irradiation. In some embodiments, adhesive tape 104 comprises or is formed of a release layer of a light-to-heat conversion (LTHC) material. For example, in a subsequent process, adhesive tape 104 may be irradiated with a laser beam. Irradiation allows the encapsulation structure formed on adhesive tape 104 to be separated from the carrier substrate 102.

[0037] According to some embodiments of this disclosure, a re-fabricated structure 106 is formed above the adhesive tape 104, such as... Figure 1A As shown, the redistribution structure 106 is configured for routing, which ensures the formation of a package structure with fan-out components. The redistribution structure 106 may also be referred to as an interposer. According to some embodiments of this disclosure, the redistribution structure 106 has a bottom surface 106B facing the carrier substrate 102 and a top surface 106A away from the carrier substrate 102.

[0038] In some embodiments, the redistribution structure 106 includes a plurality of insulating layers, such as insulating layer 1141, insulating layer 1142, insulating layer 1143, and insulating layer 1144; and a plurality of conductive components formed in the insulating layers, such as conductive component 108, conductive component 110, and conductive component 112. Although Figure 1A Only four insulating layers 1141, 1142, 1143 and 1144 are shown in the diagram. The number of insulating layers in this disclosure is not limited thereto, and the redistribution structure 106 may contain fewer or more insulating layers.

[0039] In some embodiments, the conductive member 108 is surrounded by and / or embedded in the insulating layer 1141. In some embodiments, the conductive member 108 is an under-bump metallurgy (UBM). In some embodiments, the conductive member 108 is exposed or protrudes from the bottom surface 106B of the weighted fabric structure 106 and is used to grasp or receive a bonding element.

[0040] In some embodiments, the conductive component 108 comprises or is formed of a metallic material, such as titanium, copper, nickel, tantalum, vanadium, chromium, gold, tungsten, the alloys described above, the multilayers described above, or combinations thereof. In some embodiments, the conductive component 108 is formed of a non-solder metallic material.

[0041] In some embodiments, the conductive component 110 is covered by an insulating layer 114. 2、 114 3、 1144 surrounds and / or embeds into the insulating layer 114 2、 114 3、 In 1144. In some embodiments, conductive component 110 includes conductive pads, conductive lines and / or conductive traces, and is configured to provide horizontal electronic routing. In some embodiments, conductive component 108 contacts conductive component 110 (e.g., conductive pad) in insulating layer 1142.

[0042] In some embodiments, the conductive component 112 is covered by an insulating layer 114. 2、 1143、 1144 surrounds and / or embeds into the insulating layer 114 2、 114 3、 In 1144. In some embodiments, the conductive member 112 is a conductive via and is configured to provide vertical electron routing. In some embodiments, the conductive member 112 rests on the conductive pad of the conductive member 110, thereby electrically coupling the conductive member 110 to different insulating layers 114. In some embodiments, the conductive member 112 located in the insulating layer 1144 exposes and / or protrudes from the top surface 106A of the insulating layer 1144 of the weight-bearing structure 106 and is used to grasp or receive one or more bonding elements.

[0043] In some embodiments, insulating layer 114 may be formed of one or more polymeric materials. The one or more polymeric materials may include polybenzoxazole (PBO), benzocyclobutene (BCB), polyimide (PI), epoxy-based resin, one or more other suitable polymeric materials, or combinations thereof. In some embodiments, the polymeric material is a photosensitive material. Optical lithography processes can therefore be used to form a plurality of openings with a desired pattern in insulating layers 1141-1144. In alternative embodiments, insulating layer 114 is formed of one or more dielectric materials, such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0044] In some embodiments, conductive components 110 and 112 are formed of metallic materials such as copper, aluminum, gold, palladium, cobalt, titanium, nickel, silver, graphene, one or more other suitable conductive materials, alloys described above, or combinations thereof. In some embodiments, conductive components 110 and 112 are formed of non-welded metallic materials. In some embodiments, conductive components 110 and 112 comprise multiple sub-layers. For example, each of conductive components 110 and 112 comprises multiple sub-layers, including Ti / Cu, Ti / Ni / Cu, Ti / Cu / Ti, Al / Ti / Ni / Ag, other suitable sub-layers, or combinations thereof.

[0045] The formation of the redistributed structure 106 may involve multiple deposition processes, multiple patterning processes, and / or multiple planarization processes. The deposition processes can be used to form multiple insulating layers and / or multiple conductive layers. The deposition processes may include spin coating, electroplating, electroless processes, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), one or more other suitable processes, or combinations thereof.

[0046] Patterning processes can be used to pattern existing insulating layers and / or existing conductive layers. Patterning processes may include photolithography, energy beam drilling (such as laser beam drilling, ion beam drilling, or electron beam drilling), etching, mechanical drilling, one or more other suitable processes, or combinations thereof.

[0047] Planarization can be used to provide a flat top surface for a formed insulating layer and / or a formed conductive layer to facilitate subsequent processes. Planarization may include mechanical grinding, chemical mechanical polishing (CMP), dry polishing, one or more other suitable processes, or a combination of the above.

[0048] Figure 1A-1 Some embodiments of this disclosure are shown Figure 1A The diagram shows a top view of the packaging structure. Figure 1A-1 A redistribution structure 106 is shown, comprising a fan-in region 106I to which semiconductor dies will subsequently be disposed, and a fan-out region 106O adjacent to the fan-in region 106I. According to some embodiments, the fan-out region 106O continuously surrounds the fan-in region 106I. Embodiments of the invention are not limited thereto. The redistribution structure 106 may include one or more fan-in regions 106I to which a plurality of semiconductor dies and / or other packaging elements will be disposed accordingly.

[0049] See back Figure 1A According to some embodiments, a conductive member 116 is formed above the top surface 106A of the reconstituted structure 106. In some embodiments, the conductive member 116 is formed on and in contact with the conductive member 112.

[0050] In some embodiments, the conductive member 116 is under-bump metal. In some embodiments, the conductive member 116 is a bonding element for gripping or receiving one or more solder balls. In some embodiments, the conductive member 116 comprises or is formed of a metallic material such as titanium, copper, nickel, tantalum, vanadium, chromium, gold, tungsten, alloys thereof, multilayers thereof, or combinations thereof. In some embodiments, the conductive member 116 is formed of a non-soldering metallic material.

[0051] According to some embodiments, the semiconductor die 120 is positioned above the top surface 106A of the redistribution structure 106, such as... Figure 1B As shown. According to some embodiments, the semiconductor die 120 is disposed within the fan-in region 106I of the redistribution structure 106. According to some embodiments, the semiconductor die 120 is bonded to the conductive component 116 via a bonding element 136.

[0052] Semiconductor die 120 may include an application processor, a power management integrated circuit, a logic device, a memory device (e.g., static random access memories (SRAMs)), a radio frequency (RF) device, an input / output (I / O) device, a system-on-chip (SoC) device, one or more other suitable circuits, or a combination thereof.

[0053] In some embodiments, the semiconductor die 120 includes a semiconductor substrate 122 having a back surface 122B and a front surface 122F. In some embodiments, the semiconductor die 120 also includes an integrated circuit 124 formed in and / or on the front surface 122F of the semiconductor substrate 122. In some embodiments, the semiconductor die 120 also includes an interconnect structure 126 surrounded by an intermetallic dielectric (IMD) layer 128 and electrically coupled to the integrated circuit 124. In some embodiments, the semiconductor die 120 also includes a conductive pad 130 formed over and electrically coupled to the interconnect structure 126. In some embodiments, the semiconductor die 120 also includes a passivation layer 132 partially covering the conductive pad 130 and a bump under-metal 134 extending through the passivation layer 132 and formed on the conductive pad 130.

[0054] According to some embodiments, the under-bump metal 134 of the semiconductor die 120 is bonded to the conductive component 116 above the redistribution structure 106 via a method such as flip-chip bonding (e.g., by using bonding element 136). In some embodiments, a thermal reflow operation step is performed. In some embodiments, the bonding element 136 corresponds to and connects the under-bump metal 134 of the semiconductor die 120 and the conductive component 116. Thus, according to some embodiments, the integrated circuit 124 is electrically coupled to the conductive components 108, 110, and 112 of the redistribution structure 106.

[0055] In some embodiments, the bonding element 136 is a solder joint, microbumps, solder bumps, solder balls, ball grid array (BGA) balls, controlled collapse chip connection (C4) bumps, other suitable bonding elements, and / or combinations thereof. In some embodiments, the bonding element 136 is a tin-containing solder bump or solder ball. The tin-containing solder bump or solder ball may contain copper, silver, gold, aluminum, lead, one or more other suitable materials, or combinations thereof. In some embodiments, the bonding element 136 is lead-free.

[0056] Figure 1B-1 Some embodiments of this disclosure are shown Figure 1B The diagram shows a top view of the package structure. In some embodiments, the semiconductor die 120 has a rectangular or square outline, such as... Figure 1B-1 As shown. In some embodiments, the periphery (or edge) of the semiconductor die 120 is aligned with the boundary between the fan-in region 106I and the fan-out region 106O of the redistribution structure 106.

[0057] In some embodiments, the periphery of the semiconductor die 120 includes four sidewalls S1, S2, S3, and S4. Sidewalls S1 and S2 intersect at corner C1; sidewalls S2 and S3 intersect at corner C2; sidewalls S3 and S4 intersect at corner C3; and sidewalls S4 and S1 intersect at corner C4.

[0058] According to some embodiments, an underfill material 138 is formed over the top surface 106A of the re-lay structure 106 to encapsulate the semiconductor die 120, bonding element 136, and conductive component 116, such as... Figure 1C As shown. According to some embodiments, the underfill material 138 fills the space between the bonding elements 136. In some embodiments, the upper portions of the plurality of sidewalls of the semiconductor substrate 122 are not covered by the underfill material 138.

[0059] In some embodiments, the underfill material 138 is an electrically insulating adhesive material used to protect the bonding element 136 and the conductive component 116 and / or fix the semiconductor die 120. In some embodiments, the underfill material 138 is formed of epoxy resin, resin, epoxy molding compounds, other suitable underfill materials, and / or combinations thereof.

[0060] According to some embodiments, a molding compound 140 is formed over the top surface 106A of the reconstituted structure 106 to encapsulate the underfill material 138 and the semiconductor die 120, such as Figure 1C As shown. In some embodiments, the molding compound 140 is a single-layer film or a composite stack. In some embodiments, the molding compound 140 comprises various materials, such as a molding underfill, epoxy resin, resin, or similar materials. In some embodiments, the molding compound 140 has high thermal conductivity, low moisture absorption rate, and high flexural strength.

[0061] According to some embodiments, the planarization molding compound 140 is then applied until the back surface 122B of the semiconductor substrate 122 is exposed. The planarization process may include mechanical polishing, chemical mechanical polishing, dry polishing, one or more other suitable processes, or a combination thereof.

[0062] According to some embodiments, Figure 1C The upper surface of the structure shown (e.g., the back surface 122B of the semiconductor substrate 122) is attached to the carrier substrate 144 and then flipped up and down, as shown. Figure 1D As shown. According to some embodiments, a carrier substrate 144 is attached to the semiconductor substrate 122 and the molding compound 140 by adhesive tape 142, thereby covering the semiconductor substrate 122 and the molding compound 140. According to some embodiments, the carrier substrate 144 is configured to protect the semiconductor substrate 122 from damage during subsequent processes.

[0063] In some embodiments, the carrier substrate 144 is a ceramic substrate, a glass substrate, a polymer substrate, a semiconductor substrate, or other suitable substrate. In some embodiments, the adhesive tape 142 is a release layer comprising or formed of a photothermal conversion material. In some embodiments, the adhesive tape 142 is formed of a material different from that of the adhesive tape 104.

[0064] According to some embodiments, the substrate 102 is then removed from the reeling structure 106 by separating the adhesive tape 104 from the substrate 102. Figure 1E As shown. For example, the release process can be performed by irradiating the structure with a laser beam, an ultraviolet beam, or other suitable energy beam. After irradiation, the adhesive properties of the adhesive tape 104 can be disrupted or reduced. In some embodiments, the adhesive tape 142 maintains its adhesiveness even when irradiated with an energy beam. According to some embodiments, after the release process, the insulating layer 1141 of the re-woven structure 106 is exposed.

[0065] According to some embodiments, the insulating layer 1141 of the redistribution structure 106 is planarized until the conductive component 106 is exposed from the insulating layer 1141, such as... Figure 1E As shown. Planarization may include mechanical grinding, chemical mechanical polishing, dry polishing, one or more other applicable processes, or a combination of the above.

[0066] According to some embodiments, a sawing operation step is performed to... Figure 1E The structure shown is cut into multiple package structures 146 that are separated from each other, as follows: Figure 1F As shown. Figure 1F A cross-sectional schematic diagram of one of the resulting packaging structures 146 is shown.

[0067] According to some embodiments, the carrier substrate 144 is then removed from the encapsulation structure 146 by separating the adhesive tape 142 from the carrier substrate 144 and the semiconductor die 120 (and molding compound 140). For example, the release process can be performed by irradiating the structure with a laser beam, an ultraviolet beam, or other suitable energy beam. After irradiation, the adhesive properties of the adhesive tape 142 can be disrupted or reduced.

[0068] According to some embodiments, a packaging structure 146 is disposed above a substrate 160 and bonded to the substrate 160 via a bonding element 148, such as Figure 1G As shown. According to some embodiments, the bonding element 148 disposed within the fan-in region 106I is referred to as the inner bonding element 148I, while the bonding element 148 disposed within the fan-out region 106O is referred to as the outer bonding element 148O. In some embodiments, a plurality of inner bonding elements 148I and a plurality of outer bonding elements 148O are respectively arranged in an array.

[0069] In some embodiments, substrate 160 is a printed circuit board (PCB). In alternative embodiments, substrate 160 is an interposer substrate that may then be bonded to other substrates. In some embodiments, substrate 160 is fabricated with circuitry having a predetermined function. For example, the functional circuitry may include conductive pads, conductive lines, conductive traces, conductive vias, and / or active circuit elements such as transistors, diodes, and similar elements. In some embodiments, substrate 160 includes conductive pads 162 that protrude and / or extend from the upper surface of substrate 160.

[0070] In some embodiments, the bonding element 148 is a solder joint, a chip connection bump for controlling collapse height, a solder bump, a solder ball, a ball gate array ball, other suitable bonding elements, and / or a combination thereof. In some embodiments, the bonding element 148 is a tin-containing solder bump or solder ball. The tin-containing solder bump or solder ball may contain copper, silver, gold, aluminum, lead, one or more other suitable materials, or a combination thereof. In some embodiments, the bonding element 148 is lead-free.

[0071] According to some embodiments, conductive components 108 of the redistribution structure 106 are bonded to conductive pads 162 of the substrate 160 using bonding elements 148. In some embodiments, a thermal reflow operation step is performed. Thus, according to some embodiments, the integrated circuit 124 of the semiconductor die 120 is electrically coupled to the substrate 160.

[0072] Figure 1G-1 Some embodiments of this disclosure are shown Figure 1G The diagram shows a top view of the packaging structure. Figure 1G-2 Some embodiments of this disclosure are shown Figure 1G-1 The enlarged top view of region R shown in the diagram illustrates more details of the bonding element 148 near corner C1 of semiconductor die 120. For ease of illustration, components of the package structure can be described below using the bonding element 148 near corner C1 of semiconductor die 120, but these components can be applied to other regions of the package structure, such as bonding elements 148 near corners C2, C3, and C4 of semiconductor die 120.

[0073] Figure 1G-2 The diagram shows the footprint (or projection) of the bonding element 148 onto the fan-in region 106I and fan-out region 106O of the relay structure 106. According to some embodiments, in Figure 1G-2 In the process, the sidewalls S1 and S2 of the semiconductor die 120 are aligned with the boundaries of the fan-in region 106I and the fan-out region 106O of the redistribution structure 106.

[0074] According to some embodiments, the bonding element 148 includes an inner bonding element 148I disposed within the fan-in region 106I and an outer bonding element 148O disposed within the fan-out region 106O. In some embodiments, a plurality of inner bonding elements 148I and a plurality of outer bonding elements 148O are respectively arranged in an array.

[0075] Figure 1G-2 An exemplary array of external bonding elements 148O is shown, comprising multiple rows A1, A2, A3, A4, A5, A6, and A7 and multiple columns B1, B2, B3, B4, B5, B6, B7, and B8; and an exemplary array of internal bonding elements 148I is shown, comprising multiple rows a1, a2, a3, and a4 and multiple columns b1, b2, b3, and b4. The directions of rows A1, A2, A3, A4, A5, A6, and A7 are parallel to the directions of rows a1, a2, a3, and a4, which are parallel to the sidewalls S1 of the semiconductor die 120, while the directions of columns B1, B2, B3, B4, B5, B6, B7, and B8 are parallel to the directions of columns b1, b2, b3, and b4, which are parallel to the sidewalls S2 of the semiconductor die 120. The directions of rows A1, A2, A3, A4, A5, A6, and A7 are substantially perpendicular to the directions of columns B1, B2, B3, B4, B5, B6, B7, and B8, while the directions of rows a1, a2, a3, and a4 are substantially perpendicular to the directions of columns b1, b2, b3, and b4.

[0076] In some embodiments, the extension line SE1 of the sidewall S1 of the semiconductor die 120 passes through row A4, while the extension line SE2 of the sidewall S2 of the semiconductor die 120 passes through column B4.

[0077] In some embodiments, the bonding element 148 (including an outer bonding element 148O and an inner bonding element 148I) has a size D1 ranging from about 50 micrometers to about 150 micrometers. In some embodiments, the distance D2 between adjacent outer bonding elements 148O ranges from about 50 micrometers to about 200 micrometers. In some embodiments, the pitch P of the outer bonding elements 148O ranges from about 100 micrometers to about 250 micrometers.

[0078] In some embodiments, the distance D2' between adjacent inner bonding elements 148I ranges from about 50 micrometers to about 200 micrometers. Distance D2' may be less than distance D2. In some embodiments, the pitch P' of the inner bonding elements 148I ranges from about 100 micrometers to about 250 micrometers. Pitch P' may be less than pitch P. In some embodiments, the ratio of pitch P' to pitch P ranges from about 0.5 to about 1.

[0079] In some embodiments, such as Figure 1G-2As shown, the inner bonding element 148I is separated from the periphery of the semiconductor die 120. According to some embodiments, the coverage area of ​​the inner bonding element 148I does not overlap with the periphery of the semiconductor die 120. For example, row a1 of the inner bonding element 148I is spaced from sidewall S1 by distance D3. Column b1 of the inner bonding element 148I is spaced from sidewall S2 by distance D3. In some embodiments, distance D3 ranges from about 50 micrometers to about 200 micrometers. Distance D3 may be greater than distance D2'. In some embodiments, the ratio of distance D3 to distance D2' ranges from about 1 to about 3.

[0080] In some embodiments, such as Figure 1G-2 As shown, the external bonding element 148O is separated from the periphery of the semiconductor die 120. According to some embodiments, the coverage area of ​​the external bonding element 148O does not overlap with the periphery of the semiconductor die 120. For example, row A3 of the external bonding element 148O is spaced from sidewall S1 by distance D4. Column B3 of the external bonding element 148O is spaced from sidewall S2 by distance D4. In some embodiments, distance D4 ranges from about 50 micrometers to about 200 micrometers. Distance D4 may be greater than distance D2. Distance D4 may be equal to distance D3. In some embodiments, the ratio of distance D4 to distance D2 ranges from about 1 to about 3.

[0081] Therefore, according to some embodiments, a first exclusion region KO1 is defined. In some embodiments, neither the inner bonding element 148I nor the outer bonding element 148O is disposed within the first exclusion region KO1. In other words, in some embodiments, the first exclusion region KO1 may not include the inner bonding element 148I and the outer bonding element 148O. In some embodiments, such as Figure 1G-2 As shown, the first exclusion region KO1 is aligned with and extends along the periphery of the semiconductor die 120. In some embodiments, the first exclusion region KO1 has a width D5 spanning the semiconductor die 120. The first exclusion region KO1 may be a hollow annular region. In some embodiments, the distance D3 and / or the distance D4 is greater than or equal to half the width D5. In some embodiments, the width D5 ranges from about 100 micrometers to about 400 micrometers.

[0082] In some embodiments, such as Figure 1G-2As shown, the inner bonding element 148I and the outer bonding element 148O are spaced apart from the corner (e.g., C1) of the semiconductor die 120 by a distance. For example, the bonding elements 148 marked O63, O52, O42, O32, O23, O24, O25, O36, I12, and I21 are a group of bonding elements 148 closest to the corner C1 of the semiconductor die 120. The bonding elements O63, O52, O42, O32, O23, O24, O25, O36, I12, and I21 are spaced apart from the corner C1 of the semiconductor die 120 by a distance D7. The distance D7 may not be the same value for these bonding elements. In some embodiments, the distance D7 is greater than the dimension D1, distance D2, distance D2', pitch P, pitch P', distance D3, and distance D4. In some embodiments, the distance D7 ranges from about 200 micrometers to about 500 micrometers.

[0083] In some embodiments, the ratio of distance D7 to dimension D1 ranges from about 1.5 to about 8, such as about 2.5 to about 8, or about 4 to about 8. In some embodiments, the ratio of distance D7 to distance D2 ranges from about 1.5 to about 10, such as about 2.5 to about 10, or about 4 to about 10. In some embodiments, the ratio of distance D7 to distance D3 or distance D4 ranges from about 1.5 to about 10, such as about 2.5 to about 10, or about 4 to about 10.

[0084] Therefore, according to some embodiments, a second exclusion region KO2 is defined. In some embodiments, neither the inner bonding element 148I nor the outer bonding element 148O is disposed within the second exclusion region KO2. In other words, in some embodiments, the second exclusion region KO2 may not contain the inner bonding element 148I and the outer bonding element 148O. By defining the second exclusion region KO2 for the bonding element 148, the inner bonding element 148I and the outer bonding element 148O can be kept at an appropriate distance from the corners C1, C2, C3, and C4 of the semiconductor die 120, thereby reducing or mitigating the tensile stress caused by the bonding element 148 and applied to the subsequently formed underfill material.

[0085] The second exclusion zone KO2 can be a circular area. In some embodiments, such as Figure 1G-2 As shown, the center of the circular region of the second exclusion zone KO2 is located at corner C1. In some embodiments, the circular region of the second exclusion zone KO2 has a diameter D6, which is greater than the dimensions D1, distances D2, D2', pitch P, pitch P', distances D3, distances D4, and width D5. In some embodiments, the distance D7 is greater than or equal to half the diameter D6. In some embodiments, the diameter D6 ranges from about 350 micrometers to about 450 micrometers. In some embodiments, the ratio of the diameter D6 to the pitch P ranges from about 1.5 to about 10.

[0086] If the diameter D6 of the second exclusion region KO2 (or the ratio of diameter D6 to pitch P) is too small, the stress applied to the subsequently formed underfill material may not be effectively relieved, thus increasing the risk of cracking of the subsequently formed underfill material. If the diameter D6 of the second exclusion region KO2 is too large, it may reduce the routing density of the formed package structure.

[0087] In the illustrated embodiment, due to the presence of the second exclusion zone KO2, the positions (A5,B3), (A4,B3), (A3,B3), (A3,B4), (A3,B5), and (a1,b1) of the array of inner bonding elements 148I and outer bonding elements 148O are retained and no bonding elements are provided.

[0088] In the illustrated embodiment, column B3 includes a plurality of bonding elements O73, O63, and O23 arranged consecutively. Bonding elements O73, O63, and O23 are located on opposite sides of an extension line SE1 of the sidewall S1 of the semiconductor die 120. The distance D8 between bonding element O23 and bonding element O63 is greater than the dimensions D1, distances D2, D2', pitch P, pitch P', distances D3, D4, width D5, distance D7, and diameter D6.

[0089] In the illustrated embodiment, row A3 includes a plurality of bonding elements O37, O36, and O32 arranged consecutively. Bonding elements O37, O36, and O32 are located on opposite sides of an extension line SE2 of the sidewall S2 of the semiconductor die 120. The distance D8 between bonding elements O32 and O36 is greater than the dimensions D1, distance D2, distance D2', pitch P, pitch P', distance D3, distance D4, width D5, distance D7, and diameter D6.

[0090] In the illustrated embodiment, the minimum distance D9 between column b1 and sidewall S1 (e.g., the distance between engagement element I21 and sidewall S1) is greater than the minimum distance D3 between column b2 and sidewall S1 (e.g., the distance between engagement element I12 and sidewall S1).

[0091] In the illustrated embodiment, the minimum distance D10 between column B5 and sidewall S1 (e.g., the distance between engagement element O25 and sidewall S1) is greater than the minimum distance D4 between column B6 and sidewall S1 (the distance between engagement element O36 and sidewall S1).

[0092] According to some embodiments, an underfill material 164 is formed above the upper surface of the substrate 160, and the encapsulation structure 146 and the bonding element 148 are encapsulated, such as... Figure 1HAs shown. According to some embodiments, bottom filler material 164 fills the space between the joining elements 148. According to some embodiments, bottom filler material 164 covers the sidewalls of molding compound 140 and the sidewalls of rewoven structure 106.

[0093] In some embodiments, the underfill material 164 is an electrically insulating adhesive material used to protect the bonding element 148 and / or secure the encapsulation structure 146. In some embodiments, the underfill material 164 is formed of epoxy resin, resin, epoxy molding compound, other suitable underfill materials, and / or combinations thereof.

[0094] There may be a significant difference in the coefficients of thermal expansion (CTE) between the substrate 160 and the semiconductor die 120. Therefore, during reliability testing, package operation, and / or heating processes, tensile stress may be introduced and applied to the underfill material 138. The bonding element 148 is more rigid than its neighboring elements, which may concentrate tensile stress at the corners C1, C2, C3, and C4 of the semiconductor die 120. Therefore, this concentration of tensile stress may cause cracks to form from the corners of the semiconductor die 120 within the underfill material 138.

[0095] According to an embodiment of the present invention, by defining a second exclusion region KO2, the inner bonding element 148I and the outer bonding element 148O of the resulting package structure will maintain appropriate distances from the corners C1, C2, C3 and C4 of the semiconductor die 120, thereby reducing or mitigating the tensile stress caused by the bonding element 148 and applied to the underfill material 138. Therefore, the risk of cracking of the underfill material 138 can be reduced, thereby improving the performance and reliability of the package structure.

[0096] Figure 2 Some embodiments of this disclosure are shown Figure 1G-2 Examples of changes. Figure 2 The packaging structure shown is approximately Figure 1G-2 The package structure shown is different in that the inner bonding element 148I and the outer bonding element 148O have the same pitch P.

[0097] In some embodiments, the inner coupling element 148I and the outer coupling element 148O have the same pitch P and are arranged in an array. Figure 2 An exemplary array of inner junction element 148I and outer junction element 148O is shown, comprising multiple rows A1, A2, A3, A4, A5, A6 and A7 and multiple columns B1, B2, B3, B4, B5, B6, B7 and B8.

[0098] In the illustrated embodiment, row A6 includes bonding elements O63 and I65, which are continuously arranged and located on opposite sides of the sidewall S2 of the semiconductor die 120. In the illustrated embodiment, row A5 includes bonding elements O52 and I56, which are continuously arranged and located on opposite sides of the sidewall S2 of the semiconductor die 120. In some embodiments, the distance D11 between bonding elements O63 and I65 is less than the distance D8 between bonding elements O52 and I56.

[0099] Figure 3 Some embodiments of this disclosure are shown Figure 2 Examples of changes. Figure 3 The packaging structure shown is approximately Figure 2 The packaging structure shown is different, but the difference lies in Figure 3 There is no first exclusion zone KO1.

[0100] According to some embodiments, bonding elements 148 are provided to overlap with the boundary between the fan-in region 106I and the fan-out region 106O (or the periphery of the semiconductor die 120), and are referred to as on-boundary bonding elements 148P. That is, in Figure 3 In this configuration, sidewalls S1 and S2 pass through the boundary engagement element 148P. In some embodiments, the inner engagement element 148I, the outer engagement element 148O, and the boundary engagement element 148P are arranged in an array.

[0101] In the illustrated embodiment, row A4 includes consecutively arranged bonding elements P47, P46, and O42. Bonding elements P47, P46, and O42 are located on opposite sides of an extension line SE2 of the sidewall S2 of the semiconductor die 120. The distance D8 between bonding elements O42 and P46 is greater than the distance D2 between bonding elements P46 and P47.

[0102] Figure 4 Some embodiments of this disclosure are shown Figure 1H Examples of variations of the cross-sectional schematic diagram shown. According to some embodiments, Figure 4 The packaging structure shown is approximately Figure 1H The packaging structure shown is different, but the difference lies in Figure 4 The package structure shown contains four semiconductor dies 120.

[0103] According to some embodiments, four semiconductor dies 120 are disposed above the top surface 106A of the redistribution structure 106, such as... Figure 4 As shown. According to some embodiments, Figure 4 The semiconductor die 120 shown is approximately Figure 1BThe semiconductor die 120 is shown. According to some embodiments, the semiconductor die 120 is bonded to the conductive component 116 via a bonding element 136. According to some embodiments, the integrated circuit (not shown) of the semiconductor die 120 is electrically coupled to a substrate 160.

[0104] According to some embodiments of this disclosure Figure 4-1 yes Figure 4 The diagram shows a top view of the package structure. In some embodiments, the semiconductor dies 120 are arranged side-by-side. In some embodiments, the semiconductor dies 120 are correspondingly positioned within the fan-in region 106I of the redistribution structure 106. According to some embodiments, in Figure 4-1 In this process, the sidewalls of the semiconductor die 120 are aligned with the boundaries between the fan-in region 106I and the fan-out region 106O of the redistribution structure 106.

[0105] Figure 4-1 A second exclusion region KO2 is shown at each corner of the semiconductor die 120. Although two adjacent second exclusion regions KO2 are shown merged together, they may also be separated from each other. Some configuration details of the bonding element 148 near the corner of the semiconductor die 120 will be described below.

[0106] Figure 5 Some embodiments of this disclosure are shown Figure 4 Examples of variations of the cross-sectional schematic diagram shown. According to some embodiments, Figure 5 The packaging structure shown is approximately Figure 4 The packaging structure shown is different in that... Figure 5 The package structure shown includes two semiconductor dies 120 and two packages 502.

[0107] According to some embodiments, two packages 502 are disposed above the top surface 106A of the redistribution structure 106, such as... Figure 5 As shown. In some embodiments, package 502 includes a high bandwidth memory (HBM) device. For example, package 502 includes a plurality of stacked memory chips 504 and conductive through holes 506 electrically coupled to the memory chips 504. According to some embodiments, package 502 also includes conductive pads 508 that contact the conductive through holes 506 and are coupled to conductive members 116 via bonding elements 136.

[0108] Figure 5The components of package 502 shown are for illustrative purposes only. In alternative embodiments, package 502 is a chip-scale package (CSP), a chip-on-wafer-on-substrate (CoWoS) package, a system-on-integrated-chip (SoIC) package, and / or a three-dimensional integrated circuit (3DIC).

[0109] According to some embodiments of this disclosure Figure 5-1 for Figure 5 The diagram shows a top view of the package structure. The semiconductor die 120 and the package 502 are positioned within the fan-in region 106I of the redistribution structure 106. According to some embodiments, in... Figure 5-1 In this configuration, the sidewalls of the semiconductor die 120 and the package 502 are aligned with the boundaries between the fan-in region 106I and the fan-out region 106O of the redistribution structure 106. In some embodiments, the size of the package 502 is smaller than the size of the semiconductor die 120. Multiple packages 502 may be configured along the sidewalls of the semiconductor die 120.

[0110] Figure 5-1 A second exclusion region KO2 is shown at the corner of each of the semiconductor die 120 and the package 502. Although two adjacent second exclusion regions KO2 are shown merged together, two adjacent second exclusion regions KO2 may also be separated from each other. Some configuration details of the bonding elements 148 near the corners of the semiconductor die 120 and / or package 502 will be described below.

[0111] According to some embodiments of this disclosure Figure 6 yes Figure 4-1 or Figure 5-1 The diagram shows an enlarged top view of region R, detailing the joining element 148 near the corner of the packaged element. According to some embodiments, Figure 6 The illustrated package structure includes package elements 602 and 604. According to some embodiments, either or both of package elements 602 and 604 may be the semiconductor die 120 or package 502 described above. Figure 6 The diagram shows the coverage area (or projection) of the bonding element 148 onto the fan-in region 106I and the fan-out region 106O of the relay structure 106.

[0112] In some embodiments, the inner bonding element 148I and the outer bonding element 148O are arranged in an array. Figure 6An exemplary array of inner junction element 148I and outer junction element 148O is shown, comprising multiple rows A1, A2, A3, A4, A5, A6, A7, A8, A9 and A10 and multiple columns B1, B2, B3, B4, B5, B6 and B7.

[0113] According to some embodiments, the packaging element 602 is spaced apart from the packaging element 604 by a distance D12, such as Figure 6 As shown. In some embodiments, distance D12 is greater than or equal to the diameter D6 of the second exclusion zone KO2. In some embodiments, the circular regions of the two second exclusion zones KO2 may be separated from each other or tangent to each other at a point. In some embodiments, distance D12 is greater than distance D7, where distance D7 is the distance between corner C1 and the engagement element 148 closest to corner C1.

[0114] In the illustrated embodiment, column B3 includes consecutively arranged bonding elements O103, O93, and O23. Due to the presence of the second exclusion zone KO2, the distance D13 between bonding elements O93 and O23 is greater than the distance D2 between bonding elements O103 and O93 and greater than D12.

[0115] According to some embodiments of this disclosure Figure 7 yes Figure 4-1 or Figure 5-1 The diagram shows an enlarged top view of region R, which reveals details of the bonding element 148 near the corner of the packaged element. Figure 7 The packaging structure shown is approximately Figure 6 The packaging structure shown is different, but the difference lies in the spacing between packaging elements 602 and 604. Figure 7 The distance shown is smaller than in Figure 6 The distance shown in the figure.

[0116] According to some embodiments, the packaging element 602 is spaced apart from the packaging element by a distance D14, such as Figure 7 As shown. In some embodiments, distance D14 is less than the diameter D6 of the second exclusion zone KO2. In some embodiments, the circular regions of the two second exclusion zones KO2 overlap each other. In some embodiments, distance D14 is equal to or less than distance D7, where distance D7 is the distance between corner C1 and the engagement element 148 closest to corner C1.

[0117] In the illustrated embodiment, column B3 includes consecutively arranged bonding elements O93, O83, and O23. The distance D15 between bonding elements O83 and O23 is greater than the distance D2 between bonding elements O93 and O83 and is also greater than D14.

[0118] According to some embodiments of this disclosure Figure 8This is an enlarged top view of region R shown in Figure 4-1 or Figure 5-1, which shows details of the bonding element 148 near the corner of the packaged element. Figure 8 The packaging structure shown is approximately Figure 7 The packaging structure shown is different, but the difference lies in the spacing between packaging elements 602 and 604. Figure 8 The distance shown is smaller than in Figure 7 The distance shown in the figure.

[0119] According to some embodiments, the packaging element 602 is spaced apart from the packaging element by a distance D16, such as Figure 8 As shown. In some embodiments, the distance D16 is less than the width D5 of the first exclusion region KO1. In some embodiments, the regions of the two first exclusion regions KO1 overlap each other. Therefore, the external bonding element 148O is not disposed between the package elements 602 and 604. In other words, in some embodiments, the space between the package elements 602 and 604 may not contain the external bonding element 148O.

[0120] According to some embodiments of this disclosure Figure 9 yes Figure 5-1 The diagram shows an enlarged top view of region R1, detailing the joining element 148 near the corner of the packaged element. According to some embodiments, Figure 9 The illustrated package structure includes package elements 902, 904, and 906. According to some embodiments, any one, both, or all of package elements 902, 904, and 906 may be the semiconductor die 120 or package 502 described above.

[0121] The size of package element 904 may be larger than the size of package element 902 and larger than the size of package element 906. In some embodiments, package elements 902 and 906 are disposed along the sidewall of package element 904. Figure 9 The diagram shows the coverage area (or projection) of the bonding element 148 onto the fan-in region 106I and the fan-out region 106O of the relay structure 106.

[0122] In some embodiments, inner bonding element 148I and outer bonding element 148O are arranged in an array. According to some embodiments, package element 904 is spaced apart from package elements 902 and / or 906 by a distance D17, such as... Figure 9 As shown. In some embodiments, the distance D17 is greater than or equal to the sum of dimension D1, half the width D5, and half the diameter D6.

[0123] According to some embodiments of this disclosure Figure 10 yes Figure 5-1The diagram shows an enlarged top view of region R1, which reveals details of the bonding element 148 near the corner of the packaged element. Figure 10 The packaging structure shown is approximately Figure 9 The packaging structure shown is different, but the difference lies in the spacing between package elements 902 and 904. Figure 10 The distance shown is smaller than in Figure 9 The distance shown in the figure.

[0124] According to some embodiments, package element 904 is spaced apart from package elements 902 and / or 906 by a distance D18, such as Figure 10 As shown. In some embodiments, the distance D17 is less than or equal to the sum of half the width D5 and half the diameter D6.

[0125] According to some embodiments of this disclosure Figure 11 yes Figure 5-1 The diagram shows an enlarged top view of region R1, which reveals details of the bonding element 148 near the corner of the packaged element. Figure 11 The packaging structure shown is approximately Figure 10 The packaging structure shown is different, but the difference lies in the spacing between package elements 902 and 904. Figure 11 The distance shown is smaller than in Figure 10 The distance shown in the figure.

[0126] According to some embodiments, package element 904 is spaced apart from package elements 902 and / or 906 by a distance D19, such as Figure 11 As shown. In some embodiments, the distance D19 is less than or equal to half the diameter D6. In some embodiments, the circular regions of the first exclusion region KO1 and the second exclusion region KO2 overlap. Therefore, the external bonding element 148O is not disposed between package elements 902 and 904 or between package elements 906 and 904. In other words, in some embodiments, the space between package elements 902 and 904 and the space between package elements 906 and 904 may not contain the external bonding element 148O.

[0127] As described above, embodiments of the present invention provide a packaging structure comprising a semiconductor die 120 located above a top surface 106A of a reflow structure 106 and a bonding element 148 located above a bottom surface 106B of the reflow structure 106. The bonding element 148 can be positioned at appropriate distances from the corners C1, C2, C3, and C4 of the semiconductor die 120 by defining a second exclusion region KO2, thereby reducing or mitigating the tensile stress caused by the bonding element 148 and applied to the underfill material 138. Therefore, the risk of cracking of the underfill material 138 can be reduced, thereby improving the performance and reliability of the packaging structure.

[0128] This disclosure provides embodiments of several packaging structures. The packaging structure may include a redistribution structure; a semiconductor die above the redistribution structure; and a plurality of bonding elements below the redistribution structure. The semiconductor die has a first sidewall and a second sidewall intersecting at a corner. In a top view, a plurality of columns of bonding elements may be adjacent to the second sidewall and spaced apart from the second sidewall by a first distance. The first column of bonding elements may be the bonding element closest to the corner in the first column. A second distance between the second bonding element and the corner is greater than the first distance. Therefore, the bonding elements can maintain an appropriate distance from the corner of the semiconductor die. This reduces the risk of underfill material cracking, thereby improving the performance and reliability of the packaging structure.

[0129] In some embodiments, a packaging structure is provided. The packaging structure includes a redistribution structure and a semiconductor die located above the redistribution structure, and a plurality of bonding elements located below the redistribution structure. The semiconductor die has a first sidewall and a second sidewall connected to each other. The plurality of bonding elements includes a first column of bonding elements and a second column of bonding elements. In a top view, the second column of bonding elements is disposed between the first column of bonding elements and an extension line of the second sidewall. The minimum distance between the second column of bonding elements and the first sidewall is greater than the minimum distance between the first column of bonding elements and the first sidewall.

[0130] In some embodiments, a packaging structure is provided. The packaging structure includes a redistribution structure, a semiconductor die above the redistribution structure, and a first row of bonding elements electrically coupled to the semiconductor die via the redistribution structure. The semiconductor die has a first sidewall and a second sidewall. In a top view, the first row of bonding elements is adjacent to the first sidewall and includes a first bonding element, a second bonding element, and a third bonding element arranged sequentially. An extension line of the second sidewall passes between the second and third bonding elements. A first distance between the first and second bonding elements is smaller than a second distance between the second and third bonding elements.

[0131] In some embodiments, a packaging structure is provided. The packaging structure includes a relay structure, a semiconductor die located above a first surface of the relay structure, and a first row of bonding elements located above a second surface of the relay structure. The semiconductor die has a first sidewall and a second sidewall intersecting at a corner. In a top view, the first row of bonding elements is adjacent to the second sidewall and spaced apart from the second sidewall by a first distance. The first row of bonding elements includes a first bonding element, which is the bonding element closest to the corner in the first row of bonding elements. A second distance between the first bonding element and the corner is greater than the first distance.

[0132] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the appended claims.

Claims

1. A packaging structure, comprising: Single-layer fabric structure; A semiconductor die is located above the redistribution structure, wherein the semiconductor die has a first sidewall and a second sidewall connected to each other; as well as Multiple connecting elements are located below the redistribution structure, including: A first column of connecting elements, a second column of connecting elements, and a third column of connecting elements, wherein, in a top view, the second column of connecting elements is disposed between the first column of connecting elements and an extension line of the second sidewall, wherein the minimum distance between the second column of connecting elements and the first sidewall is greater than the minimum distance between the first column of connecting elements and the first sidewall, wherein, in a top view, the extension line of the second sidewall passes through the third column of connecting elements, and the minimum distance between the third column of connecting elements and the first sidewall is greater than the minimum distance between the first column of connecting elements and the first sidewall, and the minimum distance between the third column of connecting elements and the first sidewall is equal to the minimum distance between the second column of connecting elements and the first sidewall.

2. The packaging structure of claim 1, wherein the plurality of bonding elements further comprises: A fourth column of connecting elements and a fifth column of connecting elements, wherein, in a top view, the fifth column of connecting elements is disposed between the fourth column of connecting elements and the second sidewall, wherein the minimum distance between the fifth column of connecting elements and the first sidewall is greater than the minimum distance between the fourth column of connecting elements and the first sidewall.

3. The packaging structure of claim 2, wherein the first column of bonding elements and the second column of bonding elements are located outside the region of the semiconductor die, and the fourth column of bonding elements and the fifth column of bonding elements are located within the region of the semiconductor die.

4. The packaging structure as described in claim 1, further comprising: A bottom filler material surrounds the plurality of said bonding elements; as well as A substrate is electrically coupled to the semiconductor die via the redistribution structure and the plurality of said bonding elements.

5. The packaging structure of claim 1, wherein the first sidewall and the second sidewall intersect at a corner, a circular region does not contain the plurality of said bonding elements, the center of the circular region is located at the corner, and the diameter of the circular region is greater than the pitch between two adjacent bonding elements.

6. A packaging structure, comprising: Single-layer fabric structure; A semiconductor die is located above the redistribution structure, wherein the semiconductor die has a first sidewall and a second sidewall; A first row of bonding elements is electrically coupled to the semiconductor die via the redistribution structure, wherein, in a top view, the first row of bonding elements is adjacent to the first sidewall and includes: A first coupling element, a second coupling element, and a third coupling element are sequentially arranged, wherein an extension line of the second sidewall passes between the second coupling element and the third coupling element, and a first distance between the first coupling element and the second coupling element is less than a second distance between the second coupling element and the third coupling element; and A second row of bonding elements is electrically coupled to the semiconductor die via the redistribution structure, wherein, in a top view, the first row of bonding elements is located between the first sidewall and the second row of bonding elements, and the second row of bonding elements includes: A fourth, a fifth, and a sixth coupling element are arranged in succession, wherein the extension line of the second sidewall passes through the fifth coupling element, the minimum distance between the fifth coupling element and the first sidewall is greater than the minimum distance between the second coupling element and the first sidewall, and the minimum distance between the fifth coupling element and the first sidewall is equal to the minimum distance between the sixth coupling element and the first sidewall.

7. The packaging structure of claim 6, wherein, in a top view, the first row of bonding elements is located outside the region of the semiconductor die.

8. The packaging structure as described in claim 7, further comprising: A third row of bonding elements is electrically coupled to the semiconductor die via the redistribution structure, wherein, in a top view, the third row of bonding elements is located within a region of the semiconductor die, and the third row of bonding elements includes: A seventh bonding element and an eighth bonding element are arranged in succession, wherein a third distance between the seventh bonding element and the eighth bonding element is less than the first distance.

9. The packaging structure as described in claim 6, further comprising: A packaged element is located above the redistribution structure, wherein, in a top view, the first row of bonding elements is located between the semiconductor die and the packaged element.

10. The packaging structure of claim 9, further comprising: A row of bonding elements is electrically coupled to the semiconductor die, wherein, in a top view, the row of bonding elements is adjacent to the second sidewall of the semiconductor die and a third sidewall of the package element, and the row of bonding elements includes: A seventh bonding element and an eighth bonding element are arranged consecutively on opposite sides of an extension line of the first sidewall, wherein a third distance between the seventh bonding element and the eighth bonding element is greater than a fourth distance between the semiconductor die and the package element.

11. The packaging structure of claim 9, wherein the packaging element is a second semiconductor die or a package.

12. A packaging structure, comprising: Single-layer fabric structure; A semiconductor die is located above a first surface of the redistribution structure, wherein the semiconductor die has a first sidewall and a second sidewall intersecting at a corner; A first column of joining elements is located above a second surface of the redistribution structure, wherein, in a top view, the first column of joining elements is adjacent to the second sidewall and spaced apart from the second sidewall by a first distance, the first column of joining elements includes a first joining element which is the joining element closest to the corner in the first column of joining elements, and a second distance between the first joining element and the corner is greater than the first distance; as well as A second column of connecting elements is located above the second surface of the redistribution structure, wherein, in a top view, the first column of connecting elements is located between the second sidewall and the second column of connecting elements. The second column of connecting elements includes a second connecting element and a third connecting element. The minimum distance between the second connecting element and the second sidewall is greater than the minimum distance between the first connecting element and the second sidewall, and the minimum distance between the second connecting element and the second sidewall is equal to the minimum distance between the third connecting element and the second sidewall.

13. The packaging structure of claim 12, wherein the first row of bonding elements further comprises: A fourth bonding element is adjacent to the first bonding element, wherein the second distance is greater than a third distance between the first bonding element and the fourth bonding element.

14. The packaging structure of claim 12, wherein the minimum distance between the first column of bonding elements and the first sidewall is less than the minimum distance between the second column of bonding elements and the first sidewall.

15. The packaging structure of claim 14, wherein the minimum distance between the first row of bonding elements and the first sidewall is greater than the first distance.

16. The packaging structure of claim 14, wherein, in top view, the first column of bonding elements and the second column of bonding elements are located within the region of the semiconductor die.

17. The packaging structure of claim 12, further comprising: A second semiconductor die is located above the first surface of the redistribution structure, wherein the semiconductor die is spaced apart from the second semiconductor die by a third distance; as well as A row of bonding elements is located above the second surface of the redistribution structure and, in a top view, between the semiconductor die and the second semiconductor die, wherein the row of bonding elements includes: A fourth bonding element, which is the bonding element in the row of bonding elements closest to the corner of the semiconductor die, wherein a fourth distance between the fourth bonding element and the corner is greater than the third distance.

18. The packaging structure of claim 12, wherein the ratio of the second distance to the first distance is in the range of 1.5 to 10.

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