A three-dimensional packaging structure for a chip and its packaging method

Abstract

This application provides a three-dimensional packaging structure and packaging method for a chip, including a first packaging unit, a second packaging unit, a plurality of first conductive pillars spaced apart on the second packaging unit, a first molding compound structure covering the first packaging unit, the second packaging unit, and the plurality of first conductive pillars, and an electromagnetic shielding structure. The first packaging unit is disposed on the second packaging unit, and the first and second packaging units are electrically connected. The second packaging unit has a first double-sided conductive structure, which is exposed to air relative to the surface of the first packaging unit. The first conductive pillars are electrically connected to the first double-sided conductive structure of the second packaging unit. The first molding compound structure exposes the first double-sided conductive structure to air relative to the surface of the first packaging unit. The electromagnetic shielding structure covers the first molding compound structure and is electrically connected to the first conductive pillars. This application can prevent electromagnetic interference generated between chips and components.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a three-dimensional chip packaging structure and its packaging method. Background Technology

[0002] As portable electronic systems become increasingly complex, the demands for low-power, lightweight, and small-package integrated circuits are constantly rising. Stacking different functional chips can achieve advantages such as high density, small size, and high speed. However, as electronic products are used in high-frequency communication fields, the chips and components in these products are prone to electromagnetic interference. Summary of the Invention

[0003] To address the problem of electromagnetic interference easily generated between chips and components in existing electronic products, this application provides a three-dimensional chip packaging structure and its packaging method:

[0004] This application provides a three-dimensional packaging structure for a chip, including: a first packaging unit, a second packaging unit, a plurality of first conductive pillars, a first molding structure, and an electromagnetic shielding structure;

[0005] The first encapsulation unit is disposed on the second encapsulation unit, and the first encapsulation unit and the second encapsulation unit are electrically connected.

[0006] The second encapsulation unit has a first double-sided conductive structure, and the first double-sided conductive structure is exposed to air relative to the surface of the first encapsulation unit.

[0007] The first conductive pillars of the plurality of first conductive pillars are spaced apart on the second encapsulation unit, and the first conductive pillars are electrically connected to the first double-sided conductive structure of the second encapsulation unit;

[0008] The first molding structure encapsulates the first encapsulation unit, the second encapsulation unit, and a plurality of first conductive pillars, and exposes the surface of the first double-sided conductive structure relative to the surface of the first encapsulation unit to air;

[0009] The electromagnetic shielding structure covers the first plastic encapsulation structure, and the electromagnetic shielding structure is electrically connected to the first conductive column.

[0010] Furthermore, the second packaging unit includes:

[0011] The substrate has a first double-sided conductive structure.

[0012] Multiple first chips are disposed at intervals on a substrate.

[0013] A dielectric layer is disposed on at least a portion of the first chip, such that a portion of the first chip is exposed to air;

[0014] A conductive layer is disposed on a portion of the first chip exposed to air; the conductive layer is electrically connected to a first double-sided conductive structure; the conductive layer is electrically connected to a first conductive pillar.

[0015] Furthermore, the first package unit includes:

[0016] Flip chip;

[0017] The second chip has a second double-sided conductive structure.

[0018] Multiple second conductive pillars; one end of the second conductive pillar is electrically connected to the flip chip, and the other end of the second conductive pillar is connected to the second double-sided conductive structure.

[0019] Furthermore, the first package unit also includes:

[0020] The second molding compound structure encapsulates the flip chip and the second conductive pillar;

[0021] A protective layer is disposed on the second chip and on a portion of the surface of the second double-sided conductive structure relative to the second chip, such that the portion of the surface of the second double-sided conductive structure relative to the second chip is exposed to air.

[0022] A redistribution layer is disposed on the protective layer and on a portion of the surface of the second double-sided conductive structure exposed to air. The redistribution layer is electrically connected to the second conductive pillar.

[0023] Furthermore, the electromagnetic shielding structure has multiple conductive vias on its surface relative to the first packaged unit;

[0024] The conductive vias in the multiple conductive vias are spaced apart on the electromagnetic shielding structure;

[0025] The position of the conductive via on the electromagnetic shielding structure corresponds to the position of the first conductive pillar.

[0026] Accordingly, embodiments of this application provide a packaging method for a three-dimensional structure of a chip, including:

[0027] Obtain a first packaged unit and a second packaged unit; the second packaged unit has a first double-sided conductive structure;

[0028] The first and second packaged units are electrically connected using a reflow soldering process.

[0029] The first encapsulation unit and the second encapsulation unit are plastic-filled, such that the first plastic-filled structure covers the first encapsulation unit and the second encapsulation unit, and the first double-sided conductive structure is exposed to air relative to the surface of the first encapsulation unit.

[0030] Multiple first conductive pillars are prepared in multiple areas to be prepared in the first encapsulation structure; the first conductive pillars among the multiple first conductive pillars are spaced apart on the second encapsulation unit, and the first conductive pillars are electrically connected to the first double-sided conductive structure of the second encapsulation unit;

[0031] A metal layer is sputtered onto the first encapsulated structure to obtain an electromagnetic shielding structure; the electromagnetic shielding structure covers the first encapsulated structure and is electrically connected to the first conductive pillar.

[0032] Furthermore, the packaging method for the three-dimensional structure of the chip also includes: preparing a second packaging unit;

[0033] The preparation of the second encapsulation monomer includes:

[0034] A substrate and multiple first chips are acquired; the substrate is provided with a first double-sided conductive structure.

[0035] The first chip among a plurality of first chips is attached to the substrate at intervals;

[0036] A dielectric layer is prepared on at least a portion of the first chip, such that a portion of the first chip is exposed to air;

[0037] A conductive layer is fabricated on a portion of the first chip exposed to air; the conductive layer is electrically connected to a first double-sided conductive structure; the conductive layer is electrically connected to a first conductive pillar.

[0038] Furthermore, the packaging method for the three-dimensional structure of the chip also includes: preparing a first packaging unit;

[0039] The preparation of the first encapsulation monomer includes:

[0040] Obtain a flip chip, a second chip, and multiple second conductive pillars; the second chip is provided with a second double-sided conductive structure, and one end of the second conductive pillar is electrically connected to the flip chip;

[0041] The flip chip is assembled onto the second chip using a reflow soldering process, so that the other end of the second conductive pillar is connected to the second double-sided conductive structure.

[0042] Furthermore, before assembling the flip chip onto the second chip using the reflow soldering process, the following steps are also included:

[0043] A first protective carrier is attached to the surface of the second chip relative to the flip chip.

[0044] A protective layer is prepared on the surface of the second chip near the flip chip and on the surface of the second double-sided conductive structure relative to the second chip, such that the surface of the second double-sided conductive structure relative to the second chip is exposed to air.

[0045] A redistribution layer is separately applied to a portion of the protective layer and the second double-sided conductive structure exposed to air, and the redistribution layer is electrically connected to the second conductive pillar.

[0046] Remove the first protective carrier.

[0047] Furthermore, before assembling the flip chip onto the second chip using the reflow soldering process, the process also includes:

[0048] A second protective carrier is attached to the surface of the second chip near the flip chip.

[0049] A passivation layer is prepared on the surface of the second chip relative to the flip chip, and ball-mounting is performed to obtain connection bumps; the connection bumps are used to electrically connect the first package unit and the second package unit.

[0050] Remove the second protective carrier.

[0051] This application provides a three-dimensional chip packaging structure and packaging method, which has the following technical effects: By interleaving the first conductive pillars with the first double-sided conductive structure and the electromagnetic shielding structure, electromagnetic interference generated by the chips and components can be prevented, thus improving the electromagnetic shielding effect of the packaging structure. The first double-sided conductive structure forms a complete conductive path, improving electromagnetic shielding capability and solving the grounding problem of the electromagnetic shielding structure. The second double-sided conductive structure enables interconnection between the front and back sides of the second chip, increasing output pins and realizing the packaging of multi-chip modules. Attached Figure Description

[0052] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 This is a schematic diagram of a three-dimensional packaging structure of a chip provided in an embodiment of this application;

[0054] Figure 2 This is a partial schematic diagram of a three-dimensional packaging structure of a chip provided in an embodiment of this application;

[0055] Figure 3 This is a partial schematic diagram of another three-dimensional packaging structure of a chip provided in an embodiment of this application;

[0056] Figure 4 This is a schematic diagram of the structure of a second encapsulation unit provided in an embodiment of this application;

[0057] Figure 5 This is a schematic diagram of the structure of a first encapsulation unit provided in an embodiment of this application;

[0058] Figure 6 This is a top view schematic diagram of a three-dimensional packaging structure of a chip provided in an embodiment of this application;

[0059] Figure 7 This is a schematic flowchart of a three-dimensional chip packaging method provided in an embodiment of this application. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely one embodiment of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0061] The term "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of this application. In the description of embodiments of this application, it should be understood that the terms "first" and "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" and "second," etc., may explicitly or implicitly include one or more of that feature. Furthermore, the terms "first" and "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data used can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "comprising," "having," and "being," and any variations thereof, are intended to cover non-exclusive inclusion.

[0062] The following describes a specific embodiment of a three-dimensional chip packaging structure according to this application. Figure 1 This is a schematic diagram of a three-dimensional packaging structure of a chip provided in an embodiment of this application. Figure 2 This is a partial schematic diagram of a three-dimensional packaging structure of a chip provided in an embodiment of this application. Figure 3 This is a partial schematic diagram of another three-dimensional packaging structure of a chip provided in an embodiment of this application. This specification provides the composition structure as shown in the embodiments or accompanying drawings, but based on conventional or non-inventive labor, more or fewer elements, modules, and devices may be included. The composition structure listed in the embodiments is merely one of many possible compositions and does not represent the only composition structure. In actual implementation, the composition structure shown in the embodiments or accompanying drawings can be followed.

[0063] Specifically, such as Figure 1 , 2 As shown in Figure 3, the three-dimensional packaging structure of the chip may include a first packaging unit 100, a second packaging unit 200, a plurality of first conductive pillars 300, a first molding compound structure 400, and an electromagnetic shielding structure 500. The first packaging unit 100 may be disposed on the second packaging unit 200, and the first packaging unit 100 may be electrically connected to the second packaging unit 200. The second packaging unit 200 may have a first double-sided conductive structure 211, the surface of which is exposed to air relative to the surface of the first packaging unit 100. The first conductive pillars 300 may be spaced apart on the second packaging unit 200, and the first conductive pillars 300 may be electrically connected to the first double-sided conductive structure 211 of the second packaging unit 200. The first molding compound structure 400 may cover the first packaging unit 100, the second packaging unit 200, and the plurality of first conductive pillars 300, and may expose the surface of the first double-sided conductive structure 211 relative to the surface of the first packaging unit 100 to air. The electromagnetic shielding structure 500 can cover the first plastic encapsulation structure 400, and the electromagnetic shielding structure 500 is electrically connected to the first conductive pillar 300. By interleaving the first conductive pillar 300 with the first double-sided conductive structure 211 and the electromagnetic shielding structure 500, electromagnetic interference generated by each chip and component can be prevented, thereby improving the electromagnetic shielding effect of the packaging structure.

[0064] In one alternative embodiment, the electromagnetic shielding structure 500 may be made of metal, and the first conductive pillar 300 may be made of copper.

[0065] In one alternative implementation, the connection bumps of the first package unit 100 can be assembled onto the second package unit 200 using a reflow soldering process, and then plastic encapsulation can be performed. The encapsulation material on the upper surface can be thinned by grinding to reduce the package volume.

[0066] Figure 4This is a schematic diagram of the structure of a second packaged unit 200 provided in an embodiment of this application. In this embodiment, the second packaged unit 200 may include a substrate 210, a plurality of first chips 220, a dielectric layer 230, and a conductive layer 240. The substrate 210 may have a first double-sided conductive structure 211. The first chips 220 may be spaced apart on the substrate 210. The dielectric layer 230 may be disposed on at least a portion of the first chips 220, allowing a portion of the first chips 220 to be exposed to air. The conductive layer 240 may be disposed on the portion of the first chips 220 exposed to air, and the conductive layer 240 may be connected to the first double-sided conductive structure and to a first conductive pillar 300. The first double-sided conductive structure 211 forms a complete conductive path, improving electromagnetic shielding capability and solving the grounding problem of the electromagnetic shielding structure 500.

[0067] In an optional embodiment, the substrate 210 may include a ground metal layer, namely a first double-sided conductive structure 211, which may penetrate the substrate 210. The ground metal layer may be irregularly shaped and penetrate the substrate 210; there may be one or more ground metal layers, which may be spaced apart and penetrate the substrate 210. The back side of each of the plurality of first chips 220 may be adhered to the substrate 210, and the front side of each first chip 220 may be coated with a dielectric layer 230, exposing the solder pad area and the ground metal layer. A conductive layer 240 may then be sputtered onto the substrate 210, connecting the conductive layer 240 to the ground metal layer to obtain the second package unit 200.

[0068] Figure 5 This is a schematic diagram of the structure of a first packaged unit 100 provided in an embodiment of this application. In this embodiment, the first packaged unit 100 may include a flip chip 110 (Flip Chip, FC), a second chip 120, and a plurality of second conductive pillars 130. The second chip 120 may have a second double-sided conductive structure 121. One end of each second conductive pillar 130 may be electrically connected to the flip chip 110, and the other end of each second conductive pillar 130 may be connected to the second double-sided conductive structure 121. Utilizing three-dimensional packaging can improve product integration and achieve multi-functionality.

[0069] In this embodiment, the first package unit 100 may further include a second molding compound structure 140, a protective layer 150, and a redistribution layer 160. The second molding compound structure 140 may cover the flip chip 110 and the second conductive pillar 130. The protective layer 150 may be disposed on the second chip 120 and may also be disposed on a portion of the surface of the second double-sided conductive structure 121 relative to the second chip 120, exposing that portion of the surface to air. The redistribution layer 160 may be disposed on the protective layer 150 and may also be disposed on a portion of the exposed surface of the second double-sided conductive structure 121. The redistribution layer 160 may be electrically connected to the second conductive pillar 130. The second double-sided conductive structure 121 allows for interconnection between the front and back sides of the second chip 120, increasing the number of output pins and enabling multi-chip module packaging. Furthermore, by stacking along the Z-axis of the second chip 120, the system integration density can be improved.

[0070] In one alternative embodiment, the second conductive pillar 130 may be made of copper with tin.

[0071] In one optional embodiment, the second chip 120 can be a silicon wafer Si-2 electroplated using a double-sided electroplating packaging process. In practical applications, a carrier protection layer can be first applied to the back side of the silicon wafer Si-2 to protect the back side during electroplating of the front side. Then, a passivation layer can be prepared to protect the front side of the silicon wafer Si-2. A copper-titanium seed layer can be sputtered onto the silicon wafer Si-2, and a photoresist layer can be prepared, followed by electroplating of the redistribution layer 160 (RDL). After electroplating on the front side of the silicon wafer Si-2, the carrier protection layer on the back side can be peeled off, and a carrier protection layer can be applied to the front side of the silicon wafer Si-2 to protect the front side during electroplating of the back side. Then, a passivation layer, adhesive, and ball-mounting processes can be prepared on the back side of the silicon wafer Si-2 to obtain connection bumps for connection with the second package unit 200. After electroplating is completed on the back side of the silicon wafer Si-2, the carrier protection on the front side of the silicon wafer Si-2 can be peeled off.

[0072] In this embodiment, the electromagnetic shielding structure 500 may have a plurality of conductive vias 310 on its surface relative to the first encapsulation unit 100. The conductive vias 310 may be spaced apart on the electromagnetic shielding structure 500, and the positions of the conductive vias 310 on the electromagnetic shielding structure 500 may correspond to and coincide with the positions of the first conductive pillars 300. Figure 6 This is a top view schematic diagram of a three-dimensional packaging structure of a chip provided in an embodiment of this application.

[0073] The three-dimensional packaging structure of the chip provided in this application, by interleaving the first conductive pillars with the first double-sided conductive structure and the electromagnetic shielding structure, can prevent electromagnetic interference generated by the chips and components, thereby improving the electromagnetic shielding effect of the packaging structure. The first double-sided conductive structure forms a complete conductive path, improving electromagnetic shielding capability and solving the grounding problem of the electromagnetic shielding structure. The second double-sided conductive structure allows for interconnection between the front and back sides of the second chip, increasing output pins and enabling the packaging of multi-chip modules. Furthermore, the stacking along the Z-axis of the second chip improves system integration.

[0074] The following describes a specific embodiment of a three-dimensional chip packaging method according to this application. Figure 7 This is a flowchart illustrating a three-dimensional chip packaging method provided in an embodiment of this application. This specification provides method steps as shown in the embodiments or accompanying drawings, but based on conventional or non-inventive labor, more or fewer method steps may be included. The method steps listed in the embodiments are merely one of many possible structures and do not represent the only possible structure. In actual execution, the structure shown in the embodiments or accompanying drawings can be followed.

[0075] Specifically, such as Figure 7 As shown, the packaging method for the three-dimensional structure of a chip may include:

[0076] S701: Obtain the first packaged unit and the second packaged unit; the second packaged unit has a first double-sided conductive structure.

[0077] In this embodiment, the method for preparing the first packaged unit may include obtaining a flip chip, a second chip, and a plurality of second conductive pillars. The second chip may have a second double-sided conductive structure, and one end of each second conductive pillar may be electrically connected to the flip chip. The flip chip can then be assembled onto the second chip using a reflow soldering process, allowing the other end of each second conductive pillar to be connected to the second double-sided conductive structure.

[0078] In one alternative embodiment, the second chip can be double-sided plated before the flip chip is assembled onto the second chip using a reflow soldering process. Optionally, a first protective carrier can be attached to the surface of the second chip relative to the flip chip to protect the surface of the second chip relative to the flip chip during the plated process. A protective layer 150 can then be formed on the surface of the second chip relative to the flip chip and on a portion of the second double-sided conductive structure relative to the second chip, exposing the portion of the second double-sided conductive structure relative to the second chip to air. A redistribution layer can then be separately applied to the protective layer 150 and the air-exposed portion of the second double-sided conductive structure, the redistribution layer being electrically connected to a second conductive pillar. After the plated surface of the second chip relative to the flip chip is completed, the first protective carrier can be peeled off. A second protective carrier can then be attached to the surface of the second chip relative to the flip chip to protect the surface of the second chip relative to the flip chip during the plated process. A passivation layer can then be prepared on the surface of the second chip relative to the flip chip, and ball-mounting processing can be performed to obtain connection bumps, which can be used to electrically connect the first and second package monomers. After electroplating is completed on the surface of the second chip relative to the flip chip, the second protective carrier can be peeled off.

[0079] In this embodiment, the method for fabricating the second encapsulation unit may include obtaining a substrate and a plurality of first chips. The substrate may have a first double-sided conductive structure. The first chips can be spaced and adhered to the substrate. A dielectric layer can then be fabricated on at least a portion of the first chips, exposing a portion of the first chips to air. A conductive layer can then be fabricated on the air-exposed portion of the first chips. The conductive layer is electrically connected to the first double-sided conductive structure and to a first conductive pillar.

[0080] S703: The first and second packaged units are electrically connected using a reflow soldering process.

[0081] S705: The first encapsulation unit and the second encapsulation unit are plastic-filled, such that the first plastic-filled structure covers the first encapsulation unit and the second encapsulation unit, and the first double-sided conductive structure is exposed to air relative to the surface of the first encapsulation unit.

[0082] S707: A plurality of first conductive pillars are prepared in a plurality of regions to be prepared in the first encapsulation structure; the first conductive pillars among the plurality of first conductive pillars are spaced apart on the second encapsulation unit, and the first conductive pillars are electrically connected to the first double-sided conductive structure of the second encapsulation unit.

[0083] S709: A metal layer is sputtered onto the first plastic encapsulation structure to obtain an electromagnetic shielding structure; the electromagnetic shielding structure covers the first plastic encapsulation structure and is electrically connected to the first conductive pillar.

[0084] The three-dimensional chip packaging structure obtained by the chip three-dimensional packaging method provided in this application, through the interconnection of the first conductive pillars with the first double-sided conductive structure and the electromagnetic shielding structure at intervals, can prevent electromagnetic interference generated by each chip and component, and improve the electromagnetic shielding effect of the packaging structure. The first double-sided conductive structure can form a complete conductive path, improving electromagnetic shielding capability and solving the grounding problem of the electromagnetic shielding structure. The second double-sided conductive structure can realize the interconnection of the front and back sides of the second chip, increasing output pins and realizing the packaging of multi-chip modules. Furthermore, by stacking along the Z-axis direction of the second chip, the system integration can be improved.

[0085] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, while this specification describes specific embodiments, other embodiments are also within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in the order shown in different embodiments and still achieve the desired results. Additionally, the processes depicted in the drawings do not necessarily require a specific order or sequence of connections to achieve the desired results; in some implementations, parallel processing of multiple tasks is possible or may be advantageous.

[0086] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, embodiments of apparatus and electronic devices are described simply because they are based on similar method embodiments; relevant parts can be referred to the descriptions of the method embodiments.

[0087] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A three-dimensional packaging structure for a chip, characterized in that, include: The package consists of a first encapsulation unit, a second encapsulation unit, multiple first conductive pillars, a first plastic encapsulation structure, and an electromagnetic shielding structure. The first encapsulation unit is disposed on the second encapsulation unit, and the first encapsulation unit and the second encapsulation unit are electrically connected; The second packaged unit has a first double-sided conductive structure, wherein the first double-sided conductive structure is exposed to air relative to the surface of the first packaged unit; The first conductive pillars of the plurality of first conductive pillars are spaced apart on the second encapsulation unit, and the first conductive pillars are electrically connected to the first double-sided conductive structure of the second encapsulation unit; The first molding structure covers the first encapsulation unit, the second encapsulation unit, and a plurality of the first conductive pillars, such that the first double-sided conductive structure is exposed to air relative to the surface of the first encapsulation unit; The electromagnetic shielding structure covers the first plastic encapsulation structure, and the electromagnetic shielding structure is electrically connected to the first conductive pillar; wherein, the second encapsulation unit includes: A substrate, wherein the first double-sided conductive structure is provided on the substrate and the first double-sided conductive structure is disposed through the substrate; A plurality of first chips are disposed at intervals on the substrate; A dielectric layer is disposed on at least a portion of the first chip, such that a portion of the first chip is exposed to air; A conductive layer is disposed on a portion of the first chip exposed to air; the conductive layer is electrically connected to the first double-sided conductive structure; and the conductive layer is electrically connected to the first conductive pillar.

2. The structure according to claim 1, characterized in that, The first packaged unit includes: Flip chip; The second chip has a second double-sided conductive structure. Multiple second conductive pillars; one end of the second conductive pillar is electrically connected to the flip chip, and the other end of the second conductive pillar is connected to the second double-sided conductive structure.

3. The structure according to claim 2, characterized in that, The first packaged unit also includes: A second molding compound structure, wherein the second molding compound structure encapsulates the flip chip and the second conductive pillar; A protective layer is disposed on the second chip and on a portion of the surface of the second double-sided conductive structure relative to the second chip, such that the portion of the surface of the second double-sided conductive structure relative to the second chip is exposed to air. A redistribution layer is disposed on the protective layer and on a portion of the surface of the second double-sided conductive structure exposed to air, the redistribution layer being electrically connected to the second conductive pillar.

4. The structure according to claim 1, characterized in that, The electromagnetic shielding structure has multiple conductive through holes on the surface of the first encapsulation unit. The conductive vias of the plurality of conductive vias are spaced apart on the electromagnetic shielding structure; The position of the conductive through hole on the electromagnetic shielding structure corresponds to the position of the first conductive column.

5. A method for packaging a three-dimensional structure of a chip, characterized in that, include: Obtain the first and second packaged units; The second packaged unit has a first double-sided conductive structure; The first packaged unit and the second packaged unit are electrically connected using a reflow soldering process; The first encapsulation unit and the second encapsulation unit are subjected to plastic encapsulation filling, such that the first plastic encapsulation structure covers the first encapsulation unit and the second encapsulation unit, and the first double-sided conductive structure is exposed to air relative to the surface of the first encapsulation unit. Multiple first conductive pillars are fabricated in multiple areas to be fabricated in the first encapsulated structure; The first conductive pillars of the plurality of first conductive pillars are spaced apart on the second encapsulation unit, and the first conductive pillars are electrically connected to the first double-sided conductive structure of the second encapsulation unit; A metal layer is sputtered onto the first plastic encapsulation structure to obtain an electromagnetic shielding structure; The electromagnetic shielding structure covers the first plastic encapsulation structure, and the electromagnetic shielding structure is electrically connected to the first conductive column; The method further includes: preparing the second encapsulating monomer; the preparation of the second encapsulating monomer includes: A substrate and multiple first chips are obtained; the substrate is provided with the first double-sided conductive structure. The first chip among the plurality of the first chips is attached to the substrate at intervals; A dielectric layer is prepared on at least a portion of the first chip, such that a portion of the first chip is exposed to air; A conductive layer is fabricated on a portion of the first chip exposed to air; the conductive layer is electrically connected to the first double-sided conductive structure; the conductive layer is electrically connected to the first conductive pillar.

6. The method according to claim 5, characterized in that, Also includes: Prepare the first encapsulation monomer; The preparation of the first encapsulation monomer includes: Obtain a flip chip, a second chip, and multiple second conductive pillars; the second chip is provided with a second double-sided conductive structure, and one end of the second conductive pillar is electrically connected to the flip chip; The flip chip is assembled onto the second chip using a reflow soldering process, so that the other end of the second conductive pillar is connected to the second double-sided conductive structure.

7. The method according to claim 6, characterized in that, Before assembling the flip chip onto the second chip using the reflow soldering process, the method further includes: A first protective carrier is attached to the surface of the second chip relative to the flip chip; A protective layer is prepared on the surface of the second chip near the flip chip and on a portion of the surface of the second double-sided conductive structure relative to the second chip, such that a portion of the surface of the second double-sided conductive structure relative to the second chip is exposed to air. On the protective layer and a portion of the second double-sided conductive structure exposed to air, a redistribution layer is separately applied, the redistribution layer being electrically connected to the second conductive pillar; Remove the first protective carrier.

8. The method according to claim 6, characterized in that, The flip chip is assembled using a reflow soldering process. Before being attached to the second chip, it also includes: A second protective carrier is attached to the surface of the second chip near the flip chip; A passivation layer is prepared on the surface of the second chip relative to the flip chip, and ball-mounting is performed to obtain connection bumps; the connection bumps are used to electrically connect the first package unit and the second package unit; Peel off the second protective carrier.

Images