Scribe line structure for memory devices
By forming a support structure and a capping layer on a semiconductor wafer, etching grooves, and depositing a conductive seed layer, the cracking problem caused by the fragility of low-k films is solved, achieving continuity of conductive pillars and high yield of semiconductor devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MICRON TECHNOLOGY INC
- Filing Date
- 2022-02-10
- Publication Date
- 2026-06-12
AI Technical Summary
Low-k films are fragile during semiconductor wafer dicing, leading to crack propagation and affecting yield. Furthermore, the conductive seed layer is deposited discontinuously in the recessed areas, making it impossible to effectively form conductive pillar bumps.
A support structure and a cover layer are formed in the scribing area. Grooves are formed by etching, and conductive seed layers and conductive pillars are deposited therein to ensure continuity.
It effectively suppresses crack propagation, ensures the continuity of the conductive seed layer, and improves the yield and reliability of semiconductor devices.
Smart Images
Figure CN115241182B_ABST
Abstract
Description
Technical Field
[0001] This application generally relates to memory devices. Specifically, this application relates to a scribe line structure for a memory device. Background Technology
[0002] High data reliability, high-speed memory access, low power consumption, and reduced chip size are the required characteristics of semiconductor memories. In recent years, some semiconductor devices, such as dynamic random-access memory (DRAM) devices, have incorporated low-k films of insulating materials with low dielectric constant (k) that exhibit weak polarization between conductive layers, such as silicon oxycarbide (SiOC) and silicon carbonitride (SiCN). The inclusion of low-k films reduces parasitic capacitance between conductive layers, thereby enabling high-speed operation of electronic circuitry within the semiconductor device.
[0003] However, low-k materials exhibit weak thermomechanical properties. For example, compared to silicon dioxide (SiO2) and silicon nitride (Si3N4) films, low-k films have lower adhesion to adjacent conductive layers or conductive components (e.g., interconnects). Additionally, low-k materials are brittle. Once semiconductor devices are formed on a semiconductor wafer, the wafer is diced into semiconductor chips. During the dicing process, cracks can form, and these cracks can propagate through the film interface between the low-k film and another dielectric film (e.g., between SiO2 and SiOC films, between SiCN / SiO2 films, etc.) and reach the device formation region of the semiconductor device, resulting in a lower yield of the semiconductor device.
[0004] To reduce the aforementioned cracks in the scribe line process, grooves can be formed in the scribe line area by etching through the layer containing the low-k film before scribe. However, due to the brittle nature of the low-k material, the cut cross-section of the low-k film facing the groove tends to have a concave shape along the groove. To form conductive pillar bumps on the wires coupled to the interconnects through the layer, a conductive seed layer can be formed as an initial step in the electroplating of the conductive material. However, because the deposition of the conductive seed layer on the concave portions of the low-k film tends to fail, the conductive seed layer tends to be discontinuous from one concave portion to another, and therefore fails to function as a seed layer. Summary of the Invention
[0005] On one hand, this application provides an apparatus comprising: a multilayer structure including: a first circuit region; a first edge surrounding the first circuit region; a second circuit region; a second edge surrounding the second circuit region and facing the first edge; a substrate spanning the first circuit region and the second circuit region; a plurality of dielectric layers spanning the first circuit region and the second circuit region over the substrate, the plurality of dielectric layers including: a groove at least partially between the first edge and the second edge; a support structure between the first edge and the second edge; and a cover layer on the plurality of dielectric layers.
[0006] On the other hand, this application provides an apparatus comprising: a substrate; a first dielectric layer over the substrate; a second dielectric layer over the first dielectric layer; a cover layer on the second dielectric layer; a chip comprising: a portion of the substrate; a first portion of the first dielectric layer; a first portion of the second dielectric layer; a first portion of the cover layer; an edge; and a residual support structure projecting from and connected to the edge, the residual support structure comprising: a second portion of the first dielectric layer continuous with the first portion of the first dielectric layer; a second portion of the second dielectric layer continuous with the first portion of the second dielectric layer; and a second portion of the cover layer continuous with the first portion of the cover layer.
[0007] On the other hand, this application provides a method for manufacturing a first chip and a second chip, the method comprising: forming at least one dielectric layer over a substrate; forming a capping layer over the at least one dielectric layer; shielding a first portion and a second portion of the capping layer, the first portion of the capping layer being defined by a first edge of the first chip and the second portion of the capping layer being in a cut region between the first edge of the first chip and a second edge of the second chip facing the first edge; removing a third portion of the capping layer in the cut region and the at least one dielectric layer below the third portion of the capping layer to form a groove, and forming a support structure including the second portion of the capping layer and the at least one dielectric layer below the second portion of the capping layer; removing a fourth portion of the capping layer in the first portion of the capping layer and a portion of the at least one dielectric layer below the fourth portion of the capping layer to form a hole on the first chip; depositing a conductive layer to cover the capping layer and the hole, the capping layer including the second portion of the capping layer of the support structure; forming a conductive pillar on the conductive layer in the hole; and removing the conductive layer on the edge surfaces of the capping layer and the hole. Attached Figure Description
[0008] Figure 1A This is a layout diagram of a semiconductor device according to an embodiment of the present disclosure.
[0009] Figure 1B This is a top view illustrating a semiconductor chip according to an embodiment of the present disclosure.
[0010] Figure 2A This is a layout diagram of a portion of a semiconductor device according to an embodiment of the present disclosure.
[0011] Figure 2B and 2C This is a vertical cross-sectional view illustrating a schematic structure of a semiconductor device according to an embodiment of the present disclosure.
[0012] Figure 3A This is a layout diagram of a portion of a semiconductor device according to an embodiment of the present disclosure.
[0013] Figure 3B This is a vertical cross-sectional view illustrating a schematic structure of a semiconductor device according to an embodiment of the present disclosure.
[0014] Figure 4A This is a layout diagram of a portion of a semiconductor device according to an embodiment of the present disclosure.
[0015] Figure 4B and 4C This is a vertical cross-sectional view illustrating a schematic structure of a semiconductor device according to an embodiment of the present disclosure.
[0016] Figure 5A This is a layout diagram of a portion of a semiconductor device according to an embodiment of the present disclosure.
[0017] Figure 5B and 5C This is a vertical cross-sectional view illustrating a schematic structure of a semiconductor device according to an embodiment of the present disclosure.
[0018] Figure 6A This is a layout diagram of a portion of a semiconductor device according to an embodiment of the present disclosure.
[0019] Figure 6B and 6C This is a vertical cross-sectional view illustrating a schematic structure of a semiconductor device according to an embodiment of the present disclosure.
[0020] Figure 7A This is a layout diagram of a portion of a semiconductor device according to an embodiment of the present disclosure.
[0021] Figure 7B and 7CThis is a vertical cross-sectional view illustrating a schematic structure of a semiconductor device according to an embodiment of the present disclosure.
[0022] Figure 8A This is a layout diagram of a portion of a semiconductor device according to an embodiment of the present disclosure.
[0023] Figure 8B and 8C This is a vertical cross-sectional view illustrating a schematic structure of a semiconductor device according to an embodiment of the present disclosure.
[0024] Figure 9A This is a layout diagram of a portion of a semiconductor device according to an embodiment of the present disclosure.
[0025] Figure 9B and 9C This is a vertical cross-sectional view illustrating a schematic structure of a semiconductor device according to an embodiment of the present disclosure.
[0026] Figure 10A This is a layout diagram of a portion of a semiconductor device according to an embodiment of the present disclosure.
[0027] Figure 10B and 10C This is a vertical cross-sectional view illustrating a schematic structure of a semiconductor device according to an embodiment of the present disclosure.
[0028] Figure 11A This is a layout diagram of a portion of a semiconductor device according to an embodiment of the present disclosure.
[0029] Figure 11B and 11C This is a vertical cross-sectional view illustrating a schematic structure of a semiconductor device according to an embodiment of the present disclosure.
[0030] Figure 12 This is a layout diagram of a portion of a semiconductor device according to an embodiment of the present disclosure.
[0031] Figure 13 This is a layout diagram of a portion of a semiconductor device according to an embodiment of the present disclosure.
[0032] Figure 14A This is a top view illustrating a portion of a semiconductor device according to an embodiment of the present disclosure.
[0033] Figure 14B and 14C This is a vertical cross-sectional view illustrating a schematic structure of a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation
[0034] The various embodiments of the invention will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustrate specific aspects and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.
[0035] Figure 1A This is a layout diagram of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 1A This is a plan view illustrating a schematic configuration of the layout of a plurality of circuit regions 3 and scribing regions 2 formed on a semiconductor device 100. In some embodiments, the semiconductor device 100 may be a semiconductor wafer. The semiconductor device 100 may include a mask region (not shown) including a mask region 5. The semiconductor device 100 may be fabricated using photopatterning by applying a mask, such as a photoresist, to each mask region 5. The semiconductor device 100 may include a boundary region 5A surrounding each mask region 5.
[0036] In some embodiments, the circuit regions 3 may be arranged in a matrix, and each circuit region 3 may have a rectangular shape. In each circuit region 3, transistors and circuit components, such as conductive interconnects, may be disposed. For example, the transistors and circuit components may include a plurality of memory cells, one or more circuits providing memory access functions (e.g., read and write operations to the memory cells), and control circuitry for controlling the circuitry.
[0037] Figure 1A The semiconductor wafer 100 may be in a state prior to being divided into semiconductor chips 1. A scribing region 2 may be disposed around each circuit region 3. The scribing region 2 may include an edge 2A surrounding each circuit region 3 of each chip 1. In some embodiments, the edge 2A may include a group of test elements (not shown) including test circuitry. A portion of the scribing region 2 between the mutually facing edges 2A of adjacent chips 1 may include a dicing region 2B for dividing the semiconductor wafer 100 into individual semiconductor chips 1. In some embodiments, a portion of the dicing region 2B may be etched to form a recess 6. A portion of the dicing region 2B may include a support structure 7. The support structure 7 may be located in the middle of the edge 2A adjacent to the semiconductor chip 1. The support structure 7 may have one end and another end on the edge 2A adjacent to the semiconductor chip 1. Therefore, the support structure 7 may physically connect to the adjacent semiconductor chip 1. The support structure 7 may have a side facing the recess 6.
[0038] Figure 1BThis is a top view illustrating a semiconductor chip 1 according to an embodiment of the present disclosure. The semiconductor chip 1 may include a circuit region 3 surrounded by an edge 2A of the semiconductor chip 1. In some embodiments, Figure 1A The semiconductor wafer 100 can be divided into chip 1 by a dicing step. Figure 1A The dividing line (not shown) between edges 2A in the middle is executed. For example, it can be done during the dividing step by... Figure 1B The semiconductor chip 1 is separated by a dividing line 103. After the dividing step, a residual support structure 7' having a support structure 7 on one side facing the portion 6' of the recess 6 may remain on the edge 2A of the semiconductor chip 1. The residual support structure 7' may protrude from the edge 2A and may be connected to the edge 2A. A capping layer 8 may be disposed on top of the semiconductor chip 1 and the support structure 7. In some embodiments, the capping layer 8 may be a dielectric film comprising silicon nitride (Si3N4) and / or silicon carbide (SiC). The capping layer 8 may include holes, and conductive posts 12 passing through the capping layer 8 may be disposed in the circuit region 3. The conductive posts 12 may be coupled to a pad of the chip 1. In some embodiments, the conductive posts 12 may comprise copper (Cu) or nickel (Ni).
[0039] Figure 2A According to embodiments of this disclosure Figure 1A A layout diagram of portion 4 of the semiconductor device 100. In some embodiments, Figure 2A This may be a plan view of portion 4 of the semiconductor device 100. Portion 4 of the semiconductor device 100 may be... Figure 1AA portion 4 of a semiconductor device 100. In some embodiments, portion 4 may be a multilayer structure. Portion 4 may include semiconductor chip 1, which is included in adjacent semiconductor chips 1A and 1B before separation. Semiconductor chip 1 may include circuit regions 3 surrounded by edges 2A. Portion 4 may include scribe regions 2 disposed between the circuit regions 3 of semiconductor chip 1. Scribe regions 2 may include adjacent semiconductor chip 1 edges 2A facing each other. Scribe regions 2 may include cut regions 2B between adjacent semiconductor chip 1 edges 2A. A portion of cut region 2B may be etched to form a groove 6. Another portion of cut region 2B may be retained to include support structures 7 between adjacent semiconductor chip 1 edges 2A. Each support structure 7 may have one end on one edge of adjacent edge 2A and another end on the other edge of adjacent edge 2A. Thus, each support structure 7 may be physically connected to adjacent semiconductor chip 1. Each support structure 7 may have a side facing the groove 6. In some embodiments, a support structure 7 may be between grooves 6. A cover layer 8 may be disposed as the top layer of semiconductor chip 1 and support structure 7. In some embodiments, the capping layer 8 may be a dielectric film. For example, the capping layer 8 may comprise silicon nitride (Si3N4) and / or silicon carbide (SiC). The capping layer 8 may include a hole near the edge 2A of the semiconductor chip 1, and conductive posts 12 may be disposed through the capping layer 8. In some embodiments, the conductive posts 12 may comprise a conductive material, such as copper (Cu) or nickel (Ni).
[0040] Figure 2B and 2C This is a vertical cross-sectional view illustrating a schematic structure of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 2B Part 4 of the semiconductor device 100 can be displayed along Figure 2A The image shows a cross-sectional view of the line X-X' or Z-Z'. Figure 2C Part 4 of the semiconductor device 100 can be displayed along Figure 2A The image shows a cross-sectional view of line Y-Y'.
[0041] A portion 4 of the semiconductor device 100 may include a semiconductor substrate 13. For example, the semiconductor substrate 13 may include a single-crystal silicon substrate. Alternatively, the semiconductor substrate 13 may include silicon oxide (SiO2). The semiconductor substrate 13 may include components respectively contained in… Figure 2AThe semiconductor substrate 13 may include portions 13A and 13B of chips 1A and 1B. The semiconductor substrate 13 may include a through electrode 16 in the circuit region 3. A portion 4 of the semiconductor device 100 may also include a dielectric layer 14 disposed on the semiconductor substrate 13. In some embodiments, the dielectric layer 14 may include a low-k insulating material having a low dielectric constant (k) and exhibiting weak polarization between conductive components relative to a dielectric material, such as silicon dioxide (SiO2). For example, the low-k insulating material may include silicon oxycarbide (SiOC) and / or silicon carbonitride (SiCN). The dielectric layer 14 may include portions respectively contained in… Figure 2A The semiconductor device 100 includes portions 14A and 14B in chips 1A and 1B. Portion 14A may be disposed in the circuit region 3 of chip 1A and the edge 2A of chip 1A facing the adjacent edge 2A of chip 1B. Portion 14B may be disposed in the circuit region 3 of chip 1B and the edge 2A of chip 1B facing the adjacent edge 2A of chip 1A. Portion 4 of the semiconductor device 100 may also include conductive lines 18A disposed in the dielectric layer 14. In some embodiments, conductive lines 18A may include copper (Cu). Portion 4 of the semiconductor device 100 may also include a dielectric layer 15 disposed on the dielectric layer 14. In some embodiments, the dielectric layer 15 may include silicon dioxide (SiO2). The dielectric layer 15 may also include a material such as phosphorus (P) or boron (B). The dielectric layer 15 may contain materials respectively... Figure 2A The semiconductor device 100 includes portions 15A and 15B in chips 1A and 1B. Portion 15A may be disposed in the circuit region 3 of chip 1A and the edge 2A of chip 1A facing the adjacent edge 2A of chip 1B. Portion 15B may be disposed in the circuit region 3 of chip 1B and the edge 2A of chip 1B facing the adjacent edge 2A of chip 1A. Portion 4 of the semiconductor device 100 may also include conductive lines 18B disposed in dielectric layer 15. In some embodiments, conductive lines 18B may comprise aluminum (Al). Substrate 13, dielectric layers 14 and 15 may be insulated from each other by dielectric layers 17 disposed between adjacent dielectric layers 14 and 15 and between substrate 13 and dielectric layer 14 adjacent to substrate 13. In some embodiments, dielectric layer 17 may comprise silicon nitride (Si3N4). Portion 4 of the semiconductor device 100 may include interconnects 20. Each interconnect 20 may include a through electrode 19. Each through electrode 19 may be disposed through two adjacent layers of dielectric layers 14 and 15 and the dielectric layer 17 between the two adjacent layers. Interconnect 20 may couple (e.g., electrically connect) conductive lines 18A and 18B to the through electrode 16. Interconnect 20 may be disposed in circuit region 3. In some embodiments, interconnect 20 may be further disposed in edge 2A of semiconductor chip 1. In some embodiments, a portion of interconnect 20 may be included in a test circuit (not shown) disposed in edge 2A of semiconductor chip 1.
[0042] A portion 4 of the semiconductor device 100 may further include a cover layer 8. The cover layer 8 may comprise components respectively made of… Figure 2A The portions 8A and 8B defined by the edges 2A of chips 1A and 1B. In some embodiments, the capping layer 8 may be a dielectric layer comprising silicon nitride (Si3N4) and / or silicon carbide (SiC). The capping layer 8 and the dielectric layer 17 may prevent the diffusion of conductive materials (e.g., copper diffusion). A portion 4 of the semiconductor device 100 may further include a conductive seed / barrier layer 11A disposed on conductive lines 18B in the dielectric layer 15 at one end of the interconnect 20 in the circuit region 3 opposite to the other end on the substrate 13. A portion 4 of the semiconductor device 100 may also include a conductive pillar 12 passing through the capping layer 8 and a portion of the dielectric layer 15 in the circuit region 3. The conductive pillar 12 may be disposed on the conductive seed / barrier layer 11A in the circuit region 3. Thus, each of the interconnects 20 below each of the conductive pillars 12 may couple each of the conductive pillars 12 and the corresponding conductive lines 18A and 18B to each corresponding through electrode 16 below each of the conductive pillars 12.
[0043] A portion 4 of the semiconductor device 100 may include a groove 6 disposed in a cut region 2B between edges 2A in the scribing region 2, such as Figure 2B As shown in the figure. In some embodiments, the groove 6 may be formed by etching the cut area 2B. The cross-section along line X-X' or Z-Z' may include the cross-section of the groove 6 along line X-X' or Z-Z', respectively. The edge surface of the dielectric layer 14 facing the groove 6 may have roughness. For example, the edge surface of the dielectric layer 14 may include a recessed portion along the cut cross-section of the dielectric layer 14 facing the groove 6. In another example, the edge surface of the dielectric layer 14 may be uneven.
[0044] In some embodiments, a portion of the dielectric layer 15 beneath the cover layer 8, including the conductor 18B, may have a thickness in the same cross-section greater than the thickness of said portion of the dielectric layer 15 between the edge 2A of the chip 1 and the conductive post 12. In some embodiments, said portion of the dielectric layer 15 with greater thickness may include the conductive post 12. In some embodiments, said portion of the dielectric layer 15 with greater thickness may be in the edge 2A. The thicker portion of the dielectric layer 15 may provide support for the portion 4 containing the interconnect 20, thereby suppressing cracks around the interconnect 20 in the circuit region 3 and the edge 2A.
[0045] A portion 4 of the semiconductor device 100 may include a support structure 7 disposed in a dicing region 2B between edges 2A of chips 1A and 1B, such as Figure 2CAs shown in the illustration. In some embodiments, the support structure 7 may include portions 14C of dielectric layer 14, 15C of dielectric layer 15, and 17 of dielectric layer 15 on a portion 13A of substrate 13. The support structure 7 may also include a portion 8C of capping layer 8 on a portion 15C of dielectric layer 15. Portions 13C, 14C, 15C, and 8C of the support structure 7 may be continuous with portions 13A, 14A, 15A, and 8A of chip 1A and portions 13B, 14B, 15B, and 8B of chip 1B, respectively. In some embodiments, the support structure 7 may be formed without being removed after etching the groove 6. The process for providing the support structure 7 will be described in detail later in this disclosure. A cross-section along line Y-Y' may include a cross-section of the support structure 7 along line Y-Y'.
[0046] Reference Figures 3A to 10C The process of providing a recess 6, a support structure 7, and a conductive post 12 for a semiconductor device 100 according to embodiments of the present disclosure is described. Figures 3A to 10C The semiconductor substrate 13, the dielectric layers 14 and 17 disposed on the semiconductor substrate 13, the conductive lines 18A and 18B, and the interconnect 20 including the through electrode 19 have a common characteristic with Figure 2C The semiconductor substrate 13, dielectric layers 14 and 17, conductive lines 18A and 18B, and through electrode 19 have similar structures. Therefore, for the sake of brevity, the description of the structure of the semiconductor substrate 13, the dielectric layers 14 and 17 disposed on the semiconductor substrate 13, the conductive lines 18A, and the through electrode 19 is omitted.
[0047] Figure 3A This is a layout diagram of part 4 of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 3A This can be done by etching to form Figure 2A-2C A plan view of portion 4 of the semiconductor device 100 prior to the recess 6. Portion 4 may contain the semiconductor chip 1 before separation. Portion 4 may contain circuit regions to be included in the corresponding semiconductor chip 1. Portion 4 may also contain an edge 2A surrounding the circuit region 3 of the semiconductor chip 1. Portion 4 may contain a scribing region 2 disposed between the circuit regions 3. The scribing region 2 may contain a cut region 2B between the edge 2A of the semiconductor chip 1 and an adjacent edge 2A of the adjacent semiconductor chip 1. A capping layer 8 may be disposed on top of portion 4. In some embodiments, the capping layer 8 may be a dielectric film. For example, the capping layer 8 may contain silicon nitride (Si3N4) and / or silicon carbide (SiC).
[0048] Figure 3B This is a vertical cross-sectional view illustrating a schematic structure of a semiconductor device 100 according to an embodiment of the present disclosure. In some embodiments, Figure 3B Part 4 of the semiconductor device 100 may be along Figure 3AThe image shows a cross-sectional view along lines X-X', Y-Y', or Z-Z'. Prior to the etching process, the cut region 2B may include a semiconductor substrate 13, dielectric layers 14, 15, and 17, and a capping layer 8, contained in the cross-section along lines X-X', Y-Y', and Z-Z'. For example, one of the dielectric layers 17 may be formed on the semiconductor substrate 13. Dielectric layers 14 (e.g., a dielectric layer containing a low-k material) and 17 may be repeatedly formed, while conductors 18A and through electrodes 19 coupling conductors 18A may be formed through dielectric layers 14 and 17. In some embodiments, the dielectric layer 14 containing a low-k material film is formed, for example, by a chemical vapor deposition (CVD) method. A dielectric layer 15 (e.g., a dielectric layer comprising silicon dioxide) and a dielectric layer 17 on the dielectric layer 15 can be repeatedly formed, while conductors 18B and through electrodes 19 coupling conductors 18B to conductors 18A can be formed through the dielectric layers 15 and 17. A top dielectric layer 15 can be formed on the dielectric layer 17. In some embodiments, the portion of the top dielectric layer 15 containing conductors 18B may have a thickness greater than the region of the top dielectric layer 15 between conductors 18B. The thicker portion of the top dielectric layer 15 may provide support for the portion 4 containing interconnects 20, thereby suppressing cracks around interconnects 20 in the circuit region 3.
[0049] Figure 4A This is a layout diagram of part 4 of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 4B and 4C This is a vertical cross-sectional view illustrating a schematic structure of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 4A This can be achieved by etching after the formation of photoresist 9. Figure 2A-2C A plan view of part 4 of the semiconductor device 100 before the recess 6 in the middle. Figure 4B Part 4 of the semiconductor device 100 can be displayed along Figure 4A The image shows a cross-sectional view of the line X-X' or Z-Z'. Figure 4C Part 4 of the semiconductor device 100 can be displayed along Figure 4A The image shows a cross-sectional view of line Y-Y'.
[0050] Photoresist 9 can be disposed on cover layer 8 to cover the edge 2A of the circuit region 3 and the scribing region 2 surrounding the circuit region 3. For example, photoresist 9 can be disposed by photo-patterning using a photomask. In some embodiments, photoresist 9 can cover a portion 4 of the semiconductor device 100. Photoresist 9 may include a portion 9A to cover along... Figure 4CThe portion 8C of the covering layer 8 in the cut area 2B between the edges 2A in the scribed area 2, in the cross section of line Y-Y'. Because along... Figure 4C In the cross-section of line Y-Y', the cut region 2B is covered by a portion 9A of photoresist 9, so the structure below portion 9A is not exposed and may not be removed by etching, thus forming a layer below portion 9A. Figure 2A 7. Supporting structure along Figure 4B The cut area 2B in the cross-section of line X-X' or Z-Z' is not covered by a portion 9A of photoresist 9. Therefore, photoresist 9 can expose a portion of the cover layer 8 in the cut area 2B along the cross-section of line X-X' or Z-Z'. Therefore, the cut area 2B containing the exposed portion of cover layer 8 and the dielectric layer below the exposed portion of cover layer 8 can be etched to form a groove 6. The etching can be dry etching or wet etching.
[0051] Figure 5A This is a layout diagram of part 4 of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 5B and 5C This is a vertical cross-sectional view illustrating a schematic structure of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 5A This can be done by etching to form Figure 2A-2C A plan view of part 4 of the semiconductor device 100 after the groove 6 in the middle. Figure 5B Part 4 of the semiconductor device 100 can be displayed along Figure 5A The image shows a cross-sectional view of the line X-X' or Z-Z'. Figure 5C Part 4 of the semiconductor device 100 can be displayed along Figure 5A The image shows a cross-sectional view of line Y-Y'.
[0052] In passing Figure 4A and 4B The aforementioned groove 6 can be formed after the cover layer 8 and dielectric layers 14, 15, and 17 are etched through the exposed cut region 2B. In some embodiments, etching may be performed until the etching is stopped by the semiconductor substrate 13. Therefore, the groove may be disposed on or above the semiconductor substrate 13. The groove 6 may have an edge surface comprising a recessed portion along a cut cross-section facing the dielectric layer 14, such as Figure 5B As shown in the diagram. Simultaneously with forming the groove 6, a support structure 7 can be formed between the edge 2A and the groove 6 as the remaining portion of the cover layer 8 in the cut area 2B and the dielectric layers 14, 15, and 17. The support structure 7 may include an end adjacent to the edge 2A and a side facing the groove 6. The photoresist 9 on the cover layer 8 can be removed from portion 4 of the semiconductor device 100, exposing the circuit area 3, the edge 2A, and the cover layer 8 on the support structure 7.
[0053] Figure 6A This is a layout diagram of part 4 of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 6B and 6C This is a vertical cross-sectional view illustrating a schematic structure of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 6A This can be achieved by etching after the formation of photoresist 9'. Figure 2A-2C A plan view of part 4 of the semiconductor device 100 before the conductive pillar 12. Figure 6B Part 4 of the semiconductor device 100 can be displayed along Figure 6A The image shows a cross-sectional view of the line X-X' or Z-Z'. Figure 6C Part 4 of the semiconductor device 100 can be displayed along Figure 6A The image shows a cross-sectional view of line Y-Y'.
[0054] Photoresist 9' can be disposed on capping layer 8 to cover portion 4 of semiconductor device 100. For example, photoresist 9' can be disposed by photopatterning. Photoresist 9' may include vias 9'A to expose capping layer 8 in circuit region 3 to form conductive pillars 12. Figure 6B and 6C As shown in the image, along Figure 6A Holes 9'A in the cross-section of lines X-X', Y-Y', or Z-Z' can be provided above interconnects 20 in circuit region 3. Holes for photoresist 9' may not be present in scribing region 2. Photoresist 9' can be formed to fill grooves 6, such as... Figure 6B As shown in the diagram. Therefore, the exposed portion of the cover layer 8 can be removed by etching. Furthermore, a portion of the dielectric layer 15 beneath the exposed portion of the cover layer 8 can be removed by etching until the etching stops at the conductor 18B at the end of the interconnect 20. The etching can be dry etching or wet etching.
[0055] Figure 7A This is a layout diagram of part 4 of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 7B and 7C This is a vertical cross-sectional view illustrating a schematic structure of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 7A This can be done by etching to form Figure 2A-2C A plan view of part 4 of the semiconductor device 100 after the conductive pillar 12. Figure 7B Part 4 of the semiconductor device 100 can be displayed along Figure 7A The image shows a cross-sectional view of the line X-X' or Z-Z'. Figure 7C Part 4 of the semiconductor device 100 can be displayed along Figure 7AThe image shows a cross-sectional view of line Y-Y'.
[0056] Etching through hole 9'A Figure 6A and 6B After the cover layer 8 and the dielectric layer 15 beneath it are formed, a hole 10 may be formed. In some embodiments, etching may be performed until the wires 18B on the ends of the interconnects 20 in the dielectric layer 15 are exposed. The cover layer 8 may be removed from portion 4 of the semiconductor device 100 after etching. Figures 6A-6C Photoresist 9'. After removing the photoresist 9', the conductor 18B at the bottom of the recess 6 and the hole 10, as well as the cover layer 8 on the circuit area 3, the edge 2A, and the support structure 7, can be exposed.
[0057] Figure 8A This is a layout diagram of part 4 of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 8B and 8C This is a vertical cross-sectional view illustrating a schematic structure of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 8A It can be formed by electroplating. Figure 2A-2C A plan view of part 4 of the semiconductor device 100 after the conductive pillar 12 forms a potential barrier and a conductive seed layer 11. Figure 8B Part 4 of the semiconductor device 100 can be displayed along Figure 8A The image shows a cross-sectional view of the line X-X' or Z-Z'. Figure 8C Part 4 of the semiconductor device 100 can be displayed along Figure 8A The image shows a cross-sectional view of line Y-Y'.
[0058] A barrier and conductive seed layer 11 may be deposited on a capping layer 8 to cover a portion 4 of the semiconductor device 100. In some embodiments, the barrier and conductive seed layer 11 may be deposited by a physical vapor deposition (PVD) method, such as sputtering. The barrier and conductive seed layer 11 may comprise a barrier film and a conductive seed film. For example, the barrier film may comprise a corrosion-resistant material, such as titanium nitride (TiN). For example, the conductive seed film may comprise copper (Cu) or nickel (Ni). The barrier and conductive seed layer 11 may cover the hole 10, including the edge surface and bottom of the hole 10. The barrier and conductive seed layer 11 may include a portion 11A on the exposed conductor 18B at the bottom of the hole 10. As previously explained, the recess 6 may have an edge surface comprising a recessed portion along a cut cross-section of the dielectric layer 14 facing the recess 6. Due to the recessed portion of the recess 6, the barrier and conductive seed layer 11 may include gaps in the dielectric layer 14 along the recessed portion of the recess 6, such as Figure 8B As shown in the diagram. The barrier and conductive seed layer 11 may include a portion 11B on the support structure 7, such as... Figure 8CAs shown in the figure. Through the inclusion of portion 11B, all portions 11A of the barrier and conductive seed layer 11 can be coupled to the rest of the barrier and conductive seed layer 11.
[0059] Figure 9A This is a layout diagram of part 4 of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 9B and 9C This is a vertical cross-sectional view illustrating a schematic structure of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 9A This can be done after forming the photoresist 9”, followed by electroplating to form Figure 2A-2C A plan view of part 4 of the semiconductor device 100 before the conductive pillar 12. Figure 9B Part 4 of the semiconductor device 100 can be displayed along Figure 9A The image shows a cross-sectional view of the line X-X' or Z-Z'. Figure 9C Part 4 of the semiconductor device 100 can be displayed along Figure 9A The image shows a cross-sectional view of line Y-Y'.
[0060] Photoresist 9" can be disposed on the barrier and conductive seed layer 11 to cover a portion 4 of the semiconductor device 100. For example, photoresist 9" can be disposed by photopatterning. Photoresist 9" may include holes 9"A to expose a portion 11A of the barrier and conductive seed layer 11 to form conductive pillars 12. Figure 9B and 9C As shown in the image, along Figure 9A Holes 9”A in the cross-section of lines X-X', Y-Y', or Z-Z' can be provided above interconnects 20 in circuit region 3. Holes for photoresist 9” may not be present in scribe region 2, such as... Figure 9B and 9C As shown in the image. A photoresist 9” can be formed to fill the groove 6, as... Figure 9B As shown in the diagram, a photoresist 9” can be formed to cover a portion 11B of the barrier and conductive seed layer 11 above the support structure 7, such as... Figure 9C As shown in the image.
[0061] Figure 10A This is a layout diagram of part 4 of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 10B and 10C This is a vertical cross-sectional view illustrating a schematic structure of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 10A It can be formed by electroplating. Figure 2A-2C A plan view of part 4 of the semiconductor device 100 after the conductive pillar 12. Figure 10B Part 4 of the semiconductor device 100 can be displayed along Figure 10AThe image shows a cross-sectional view of the line X-X' or Z-Z'. Figure 10C Part 4 of the semiconductor device 100 can be displayed along Figure 10A The image shows a cross-sectional view of line Y-Y'.
[0062] All portions 11A of the barrier and conductive seed layer 11, as well as the remainder of the barrier and conductive seed layer 11, are coupled via portion 11B of the barrier and conductive seed layer 11 above the support structure 7. Electroplating can be performed, and conductive pillars 12 can be formed on portions 11A of the barrier and conductive seed layer 11 within the hole 9”A. Because the remainder of the barrier and conductive seed layer 11, excluding portion 11A, is covered by photoresist 9”, the conductive pillars 12 can be selectively developed on the exposed portion 11A through the hole 9”A. Figure 10B and 10C As shown in the image, along Figure 10A Conductive pillars 12 in the cross-section of lines X-X', Y-Y', or Z-Z' can be provided above the interconnects 20 in the circuit region 3. After the conductive pillars 12 are formed by electroplating, they can be... Figure 2A , 2B As shown in 2C, the photoresist 9” along with the remaining portion of the barrier and conductive seed layer 11 is removed. The barrier and portion 11A of the conductive seed layer 11 between the conductor 18B and the conductive post 12 can be retained. However, it can be as follows... Figure 2B and 2C The barrier and conductive seed layer 11 on the edge surface of the hole 10 are removed as shown in the figure.
[0063] Figure 11A According to another embodiment of this disclosure Figure 1A A layout diagram of portion 4A of the semiconductor device 100. In some embodiments, Figure 11A This may be a plan view of part 4A of the semiconductor device 100. Figure 11B and 11C This is a vertical cross-sectional view illustrating a schematic structure of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 11B Part 4A of the semiconductor device 100 can be displayed along Figure 11A The image shows a cross-sectional view of the line X-X' or Z-Z'. Figure 11C Part 4A of the semiconductor device 100 can be displayed along Figure 11A The image shows a cross-sectional view along line Y-Y'. In some embodiments, portion 4A of the semiconductor device 100 may be... Figure 1A Part 4A of the semiconductor device 100. In some embodiments, part 4A may be a multilayer structure. Figure 11A-11CThe semiconductor substrate 13, dielectric layers 14, 15 and 17 disposed on the semiconductor substrate 13, conductive pillars 12, conductive lines 18A and 18B, interconnect 20 including a through electrode 19 below the conductive pillar 12, groove 6 and support structure 7 may have the same characteristics as those in the semiconductor substrate 13. Figure 2A-2C The semiconductor substrate 13, dielectric layers 14, 15, and 17 disposed on the semiconductor substrate 13, conductive pillars 12, conductive lines 18A and 18B, interconnect 20 including a through electrode 19 below the conductive pillar 12, groove 6, and support structure 7 are similar structures. Therefore, for the sake of simplicity, details are omitted. Figure 11A-11C The description of the structure of the semiconductor substrate 13, the dielectric layers 14, 15 and 17 disposed on the semiconductor substrate 13, the conductive pillars 12, the conductive lines 18A and 18B, the interconnect 20 including the through electrode 19, the groove 6 and the support structure 7.
[0064] Part 4A may include the semiconductor chip 1 before separation. The semiconductor chip 1 may include a circuit region 3 surrounded by an edge 2A. Part 4A may include a scribing region 2 disposed between the circuit regions 3 of the semiconductor chip 1. The scribing region 2 may include a cut region 2B between the edge 2A of the semiconductor chip 1 and an adjacent edge 2A of the adjacent semiconductor chip 1. Interconnects 20 may be disposed in the circuit region 3. In some embodiments, neither wires 18A and 18B nor interconnects 20 disposed in the edge 2A of the semiconductor chip 1 may be present. In some embodiments, a portion of the dielectric layer 15 below the cover layer containing wires 18B and surrounding the conductive pillar 12 may have a greater thickness in the same cross-section than the thickness of said portion of the dielectric layer 15 between the edge 2A of the chip 1 and the conductive pillar 12. A portion of the dielectric layer 15 below the cover layer 8 in the edge 2A may have the same thickness in the same cross-section as the thickness of said portion of the dielectric layer 15 between the edge 2A of the chip 1 and the conductive pillar 12.
[0065] Figure 12 This is a layout diagram of portion 4B of a semiconductor device 100 according to an embodiment of the present disclosure. In some embodiments, Figure 12 This may be a plan view of portion 4B of the semiconductor device 100. In some embodiments, portion 4B of the semiconductor device 100 may be... Figure 1AA portion 4B of the semiconductor device 100. In some embodiments, portion 4B may be a multilayer structure. Portion 4B of the semiconductor device 100 may include a boundary region 5A surrounding the edge of portion 4B of the semiconductor device 100. Portion 4B may include semiconductor chips 1 before separation. Each of the semiconductor chips 1 may include a circuit region 3 surrounded by an edge 2A. Portion 4B may include a scribing region 2 disposed between the circuit regions 3 of the semiconductor chips 1. The scribing region 2 may include a cut region 2B between the edge 2A of the semiconductor chip 1 and adjacent edges 2A of adjacent semiconductor chips 1. A portion of the cut region 2B may be etched to form a groove 6. Although... Figure 1A-1B Each semiconductor chip 1 of 2A-2C includes a support structure 7 on each edge 2A on each side of the semiconductor chip 1, but Figure 12 The semiconductor chip 1 may include a plurality of support structures 7 on each edge 2A on each side of the semiconductor chip 1. A portion of the plurality of support structures 7 may be disposed in a cut area 2B between adjacent edges 2A of the semiconductor chip 1. Another portion of the plurality of support structures 7 may be disposed in a cut area 2B between an edge 2A of the semiconductor chip 1 and an adjacent boundary region 5A. Each portion of the support structures 7 on each edge 2A on each side of the semiconductor chip 1 may be disposed at equal intervals.
[0066] Figure 13 This is a layout diagram of a portion 4C of a semiconductor device 100 according to an embodiment of the present disclosure. In some embodiments, portion 4C may be a multilayer structure. Figure 12 Similar to part 4B of the semiconductor device 100, part 4C of the semiconductor device may include a semiconductor chip 1 including a circuit region 3 and an edge 2A, a scribing region 2 including an edge 2A and a cutting region 2B, and a boundary region 5A. Figure 13 Each part of the support structure 7 on each edge 2A on each side of the semiconductor chip 1 can be arranged at different intervals. The support structures 7 on opposite edges 2A of the semiconductor chip 1 can be arranged asymmetrically, such as... Figure 13 As shown in the diagram. Due to the location of the test circuit (not shown) within edge 2A, the position of the support structure 7 on edge 2A is limited. By using... Figure 13 The layout allows the end of the support structure 7 to be placed away from the test circuit.
[0067] Support structure 7 can help control each mask area covered by each photoresist (e.g., Figure 1AThe electroplating current of the mask region 5). In some embodiments, the number of support structures 7 in each mask region may be equal across the mask regions 5 in the semiconductor device 100. In some embodiments, the total area of the support structures 7 in each mask region 5 may be constant across the mask regions 5 in the semiconductor device 100. In some embodiments, the scribe line region 2 including the boundary region 5 may have a width that is approximately half the width of the scribe line region 2 between adjacent edges 2A of the semiconductor device 1. The patterns of equal or unequal intervals of the support structures 7 in the scribe line region 2 with half the width may be symmetrically arranged.
[0068] Figure 14A This is a top view illustrating a portion 1400 of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 14B and 14C This is a vertical cross-sectional view illustrating a schematic structure of a semiconductor device 1400' according to an embodiment of the present disclosure. In some embodiments, portion 1400 may be a semiconductor chip. Portion 1400' may include portions of the semiconductor chip 1400 before separation. In some embodiments, portions 1400 and 1400' of the semiconductor device 100 may be a multilayer structure. Figures 14A-14C The multi-layer structure 1400 shown in the figure is comparable to the previous reference. Figure 2A-2C The description and in Figure 2A-2C The structures shown in the text are similar. For example, Figures 14A-14C The semiconductor substrate 1414, dielectric layers 1416 and 1418, capping layer 1420, and circuit region 1402 have the same characteristics as those in the semiconductor substrate 1414, dielectric layers 1416 and 1418, capping layer 1420, and circuit region 1402. Figure 2A-2C The semiconductor substrate 13, dielectric layers 14 and 15, capping layer 8, and circuit region 3 have similar structures. Therefore, for the sake of brevity, the description of the structure of semiconductor substrate 1414, dielectric layers 1416 and 1418, capping layer 1420, and circuit region 1402 is omitted.
[0069] A portion 1400' of the semiconductor device 100 may have a scribe line 1404. The scribe line is disposed between circuit regions 1402 of the semiconductor chip 1400. The portion 1400' of the semiconductor device 100 may also include a sub-region 1402' of the circuit region 1402. The scribe line 1404 may include edges 1408a and 1408b of adjacent semiconductor chips 1400 facing each other across the scribe line central region 1410. In some embodiments, the scribe line central region 1410 may include a dividing line 1411. After being divided at the dividing line 1411, a portion 1410' of the scribe line central region 1410 may be retained together with the chip 1400, including the circuit region 1402' and the edges 1408a and 1408b. Figure 14A As shown in the figure. A portion 1400' of the semiconductor device 100 may include recesses 1406a and 1406b in the scribing region 1404, such as Figure 14BAs shown in the figure. In some embodiments, the groove 1406a can be formed by etching a portion of the area between the edge 1408a and the scribe center region 1410'. The edge surface of the dielectric layer 1416 facing the groove 1406a or 1406b may have roughness. For example, the edge surface of the dielectric layer 1416 may include a recessed portion along a cut cross-section of the dielectric layer 1416 facing the groove 1406a or 1406b. In another example, the edge surface of the dielectric layer 1416 may be non-uniform.
[0070] A portion 1400' of the semiconductor device 100 may further include a support structure 1407 between edges 1408a and / or 1408b and the scribing center region 1410, such as Figure 14C As shown in the diagram. Each support structure 1407 may have one end on one of the adjacent edges 1408a and 1408b and the other end on the scribing center region 1410. Therefore, the support structure 1407 and the scribing center region 1410 can be physically connected to the adjacent semiconductor chip 1400 before slitting. Figure 14A As shown, each support structure 1407 may have a recess 1406 facing the groove (e.g., Figure 14B On one side of the groove 1406a or 1406b in the [recess]. In some embodiments, a support structure 1407 may be located in the groove, such as […]. Figure 14A The grooves 1406 shown are between the substrate 1414. In some embodiments, the support structure 1407 may include a portion of a dielectric layer 1416, a portion of a dielectric layer 1418, and a portion of a dielectric layer 1440 on the substrate 1414, such as... Figure 14C As shown in the figure. The support structure 1407 may also include a portion of the overlay layer 1420 on a portion 1418 of the dielectric layer 15. The support structure 1407 may be continuous with a portion of the edge 1408a and the scribe center region 1410' of the chip 1400. In some embodiments, the support structure 1407 may be formed without being removed after etching the grooves 1406a and 1406b.
[0071] The types of apparatus, materials, and methods used in the embodiments described above are merely examples. However, in other embodiments, combinations of types of apparatus, materials, and methods other than those specifically described in this disclosure may be used without departing from the scope of this disclosure. For example, instead of using photoresist covering portions of a semiconductor device formed on a wafer, a hard mask may be used to cover the entire semiconductor device.
[0072] Although the invention has been disclosed in the context of certain preferred embodiments and examples, those skilled in the art will understand that the invention extends beyond the specific disclosed embodiments to other alternative embodiments and / or uses of the invention, as well as obvious modifications and equivalents thereof. Furthermore, other modifications within the scope of the invention will be apparent to those skilled in the art based on this disclosure. Various combinations or sub-combinations of the specific features and aspects of the described embodiments are also contemplated and will still fall within the scope of the invention. It should be understood that the various features and aspects of the disclosed embodiments can be combined or interchanged with each other to form variations of the disclosed invention. Therefore, the scope of at least some of the invention disclosed herein is not intended to be limited to the specific disclosed embodiments described above.
Claims
1. An apparatus comprising: A multi-layered structure, comprising: First circuit region; A first edge surrounds the first circuit area; Second circuit region; The second edge surrounds the second circuit area and faces the first edge; A substrate that spans the first circuit region and the second circuit region; A plurality of dielectric layers are disposed over the substrate across the first circuit region and the second circuit region, the plurality of dielectric layers comprising: A groove, at least partially located between the first edge and the second edge; and A support structure located between the first edge and the second edge, the support structure having a side facing the groove; A cover layer, which is on the plurality of dielectric layers; and A conductive seed layer comprising a first portion on the support structure and a second portion on the cover layer, the first portion and the second portion being coupled to each other.
2. The device according to claim 1, further comprising: A wire, which is in at least one dielectric layer of the plurality of dielectric layers in the first circuit region and the second circuit region; and Conductive pillars, which are located in holes in at least one dielectric layer, wherein The conductive seed layer includes a third portion on the wire; and The conductive post is placed on the third portion of the conductive seed layer.
3. The device of claim 2, further comprising an interconnect coupled to the wire, the interconnect disposed in the first circuit region via a first dielectric layer and a second dielectric layer of the plurality of dielectric layers.
4. The device of claim 3, further comprising a through electrode in the substrate, the through electrode being coupled to the interconnect.
5. The device according to claim 1, further comprising a plurality of support structures, Each of the support structures has one end on the first edge and the other end on the second edge.
6. The device according to claim 5, wherein the plurality of support structures are arranged at equal intervals.
7. The device of claim 5, further comprising circuitry disposed on a portion of the first edge, and The portion of the plurality of support structures is located away from the first edge.
8. The device according to claim 5, further comprising: Multiple mask areas; and Boundary regions that surround the plurality of mask regions; The total area of the plurality of support structures in each mask region is constant across the plurality of mask regions.
9. The device according to claim 5, further comprising: Multiple mask areas; and Boundary regions that surround the plurality of mask regions; The number of the plurality of support structures in each mask region is equal across the plurality of mask regions.
10. An apparatus comprising: Substrate; A first dielectric layer is situated above the substrate; A second dielectric layer is placed above the first dielectric layer; A cover layer, which is on the second dielectric layer; The chip comprises: A portion of the substrate; The first portion of the first dielectric layer; The first portion of the second dielectric layer; The first portion of the covering layer; edge; A residual support structure, which protrudes from and connects to the edge, the residual support structure comprising: The second portion of the first dielectric layer is continuous with the first portion of the first dielectric layer; The second portion of the second dielectric layer is continuous with the first portion of the second dielectric layer; and The second portion of the covering layer is continuous with the first portion of the covering layer; as well as A conductive seed layer comprising a first portion on the residual support structure and a second portion on the cover layer, wherein the first portion and the second portion of the conductive seed layer are coupled to each other.
11. The device according to claim 10, wherein The first portion of the second dielectric layer includes a conductor. The conductive seed layer includes a third portion on the wire. The device further includes a conductive post in a hole in the first portion of the second dielectric layer, the conductive post being disposed on the third portion of the conductive seed layer.
12. The device of claim 11, wherein the conductive post comprises at least one of copper or at least one of nickel.
13. The device of claim 11, wherein the first dielectric layer comprises a material having a dielectric constant lower than that of the material contained in the second dielectric layer.
14. The device of claim 13, wherein the first dielectric layer comprises at least one of silicon carbide or at least one of silicon carbonitride.
15. The device of claim 13, wherein the second dielectric layer comprises silicon dioxide.
16. The device of claim 13, wherein the first portion of the second dielectric layer has a third portion in the edge, the third portion having a thickness greater than the thickness of the fourth portion between the edge and the conductive post.
17. A method for manufacturing a first chip and a second chip, the method comprising: At least one dielectric layer is formed over the substrate; A cover layer is formed over the at least one dielectric layer; The first portion of the cover layer is defined by a first edge of the first chip, and the second portion of the cover layer is located in a cut area between the first edge of the first chip and a second edge of the second chip facing the first edge. Remove the third portion of the cover layer in the cutting area and the at least one dielectric layer below the third portion of the cover layer to form a groove, and form a support structure including the second portion of the cover layer and the at least one dielectric layer below the second portion of the cover layer; Remove a fourth portion of the cover layer and a portion of the at least one dielectric layer below the fourth portion of the cover layer to form a hole on the first chip; A conductive layer is deposited to cover the cover layer and the aperture, the cover layer comprising the second portion of the cover layer of the support structure; A conductive pillar is formed on the conductive layer in the hole; and Remove the cover layer and the conductive layer on the edge surface of the hole.
18. The method of claim 17, wherein forming the conductive pillar comprises electroplating.
19. The method of claim 18, further comprising: A fifth portion of the cover layer is located in another cut area between the first edge of the first chip and a portion of the boundary region surrounding the mask area, which is covered by photoresist during electroplating.
20. The method of claim 17, wherein the at least one dielectric layer comprises: A first dielectric layer is placed over the substrate, the first dielectric layer comprising a first material having a first dielectric constant; and A second dielectric layer, situated above the first dielectric layer, comprises a second material having a second dielectric constant. The first dielectric constant is lower than the second dielectric constant.