Semiconductor structure with dielectric features and method of manufacturing the same

Abstract

The present disclosure relates to semiconductor structures having dielectric features and methods of manufacturing the same. Semiconductor structures and methods of manufacturing the same are provided. A semiconductor structure includes a substrate and a nanostructure formed over the substrate. The semiconductor structure also includes a gate structure surrounding the nanostructure and a first dielectric feature dividing the gate structure into a first portion and a second portion. The semiconductor structure further includes a metal layer formed over the gate structure. Moreover, a top surface of the first portion of the gate structure, a top surface of the second portion of the gate structure, and a top surface of the first dielectric feature are covered by the metal layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and more specifically, to semiconductor structures having dielectric characteristics and methods for manufacturing the same. Background Technology

[0002] The electronics industry's demand for smaller and faster electronic devices capable of performing an increasing number of increasingly complex and sophisticated functions is constantly growing. Therefore, in the semiconductor industry, manufacturing low-cost, high-performance, and low-power integrated circuits (ICs) is an ongoing trend. To date, these goals have been largely achieved by shrinking the size of semiconductor ICs (e.g., miniaturization of the smallest feature size), thereby increasing production efficiency and reducing associated costs. However, this miniaturization introduces greater complexity into semiconductor manufacturing processes. Therefore, continued advancements in semiconductor ICs and devices require similar progress in semiconductor manufacturing processes and technologies.

[0003] Recently, attempts have been made to introduce multi-gate devices to improve gate control by increasing gate-channel coupling, reducing off-state current, and minimizing short-channel effects (SCE). However, the fabrication and integration of multi-gate devices can be challenging. Summary of the Invention

[0004] According to one aspect of this disclosure, a semiconductor structure is provided, comprising: a substrate; a nanostructure formed on the substrate; a gate structure surrounding the nanostructure; a first dielectric feature dividing the gate structure into a first portion and a second portion; and a metal layer formed on the gate structure, wherein the top surface of the first portion of the gate structure, the top surface of the second portion of the gate structure, and the top surface of the first dielectric feature are covered by the metal layer.

[0005] According to one aspect of this disclosure, a semiconductor structure is provided, comprising: a substrate; a first fin substrate structure protruding relative to the substrate; a first nanostructure formed on the first fin substrate structure; a gate structure including a first portion, a second portion, and a third portion located on the substrate, wherein the first portion of the gate structure surrounds the first nanostructure; a first dielectric feature sandwiched between the first portion and the second portion of the gate structure; a second dielectric feature sandwiched between the first portion and the third portion of the gate structure; a metal layer formed on the gate structure; and a dielectric layer formed on the metal layer and dividing the metal layer into a first portion and a second portion, wherein the first portion of the metal layer extends continuously from the first portion of the gate structure to the second portion of the gate structure.

[0006] According to one aspect of this disclosure, a method for manufacturing a semiconductor structure is provided, comprising: alternately stacking a first semiconductor material layer and a second semiconductor material layer to form a semiconductor stack on a substrate; patterning the semiconductor stack to form a fin structure; forming a first dielectric feature on a first side of the fin structure; removing the first semiconductor material layer of the fin structure to form a nanostructure; forming a gate structure surrounding the nanostructure and covering the first dielectric feature; removing a portion of the gate structure to expose the first dielectric feature; forming a metal layer covering the gate structure and the first dielectric feature; forming an opening in the metal layer to expose a top surface of the first dielectric feature; and forming a dielectric layer on the metal layer and in the opening of the metal layer. Attached Figure Description

[0007] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 A schematic top view of a semiconductor structure according to some embodiments is shown.

[0009] Figures 2A to 2W A schematic perspective view is shown of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments.

[0010] Figure 3 Illustrations are shown according to some embodiments Figure 2W The semiconductor structure shown along Figure 1 A cross-sectional view of line A-A' in the diagram.

[0011] Figure 4A A schematic top view of a semiconductor structure according to some embodiments is shown.

[0012] Figure 4B The following is illustrated according to some embodiments. Figure 4A The cross-sectional view of the semiconductor structure shown by line B-B' in the figure.

[0013] Figure 5 A cross-sectional view of a semiconductor structure according to some embodiments is shown.

[0014] Figure 6 A cross-sectional view of a semiconductor structure according to some embodiments is shown.

[0015] Figure 7 A cross-sectional view of a semiconductor structure according to some embodiments is shown.

[0016] Figure 8A and Figure 8B A cross-sectional view is shown of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments.

[0017] Figure 9A and Figure 9B A cross-sectional view is shown of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments.

[0018] Figure 10A and Figure 10B A cross-sectional view is shown of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments.

[0019] Figure 11A and Figure 11B A cross-sectional view is shown of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments.

[0020] Figure 12A and Figure 12B A cross-sectional view is shown of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments.

[0021] Figure 13A and Figure 13B A cross-sectional view is shown of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments.

[0022] Figure 14A and Figure 14B A cross-sectional view is shown of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments.

[0023] Figure 15A and Figure 15B A cross-sectional view is shown of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments. Detailed Implementation

[0024] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0025] Some variations of the embodiments are described. Similar reference numerals are used to denote similar elements in the various views and illustrative embodiments. It should be understood that additional operations may be provided before, during, and after the method, and some of the described operations may be replaced or eliminated for other embodiments of the method.

[0026] The gate all-around (GAA) transistor structure described below can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the created patterns to have, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0027] Embodiments of a semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure may include a nanostructure formed on a substrate and a gate structure surrounding the nanostructure. Dielectric features may be formed to divide the gate structure into different portions, and a metal layer may be formed on the gate structure to connect some portions of the gate structure, while other portions of the gate structure are not connected by the metal layer. The formation of the dielectric features and the metal layer does not require additional space to prevent misalignment, thus reducing device size.

[0028] Figure 1 A schematic top view of a semiconductor structure 100 according to some embodiments is shown. For clarity, simplified details have been provided. Figure 1To better understand the inventive concept of this disclosure, additional features can be added to the semiconductor structure 100, and some of the features described below can be replaced, modified, or eliminated.

[0029] Semiconductor structure 100 may include multi-gate devices and may be included in a microprocessor, memory, or other IC device. For example, semiconductor structure 100 may be part of an IC chip that includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof.

[0030] In some embodiments, the semiconductor structure 100 includes fin structures 104a, 104b, and 104c (which may include nanostructures) and dielectric features 124a, 124b, and 124c formed between adjacent fin structures 104a, 104b, and 104c. Furthermore, according to some embodiments, the fin structures 104a, 104b, and 104c and the dielectric features 124a, 124b, and 124c all extend along a first direction. Furthermore, according to some embodiments, a gate structure 156 is formed over the fin structures 104a, 104b, and 104c and the dielectric features 124a, 124b, and 124c, and the gate structure 156 extends along a second direction substantially perpendicular to the first direction. Details of these elements are explained in more detail in the following description.

[0031] Figures 2A to 2W A schematic perspective view is shown illustrating intermediate stages in the fabrication of a semiconductor structure 100 according to some embodiments. More specifically, Figures 2A to 2N Manufacturing according to some embodiments is shown. Figure 1 A schematic perspective view of an intermediate stage of the semiconductor structure 100 shown in the dashed box C1. Figure 1 The similar element shown can have the same Figures 2A to 2N The components shown have similar characteristics, although Figure 1 The similar components shown are not in Figures 2A to 2N As shown in the diagram. For example, the process and materials used to form the fin structure 104a can be the same as those used to form... Figures 2A to 2N The fin structures 104b and 104c shown and described below are made of the same process and materials.

[0032] First, according to some embodiments, such as Figure 2AAs shown, a semiconductor stack including a first semiconductor material layer 106 and a second semiconductor material layer 108 is formed on a substrate 102.

[0033] Substrate 102 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, substrate 102 may include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0034] In some embodiments, a first semiconductor material layer 106 and a second semiconductor material layer 108 are alternately stacked on a substrate 102 to form a semiconductor stack. In some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 are made of different semiconductor materials. In some embodiments, the first semiconductor material layer 106 is made of SiGe, and the second semiconductor material layer 108 is made of silicon. It should be noted that although three first semiconductor material layers 106 and three second semiconductor material layers 108 are formed, the semiconductor structure may include more or fewer first semiconductor material layers 106 and second semiconductor material layers 108. For example, the semiconductor structure may include two to five first semiconductor material layers 106 and two to five second semiconductor material layers 108.

[0035] The first semiconductor material layer 106 and the second semiconductor material layer 108 may be formed using low-pressure chemical vapor deposition (LPCVD), epitaxial growth processes, other suitable methods, or combinations thereof. In some embodiments, the epitaxial growth process includes molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE).

[0036] According to some embodiments, such as Figure 2B As shown, after the first semiconductor material layer 106 and the second semiconductor material layer 108 are formed as a semiconductor material stack on the substrate 102, the semiconductor material stack is patterned to form a fin structure 104a. Figure 2B(not shown in the diagram), 104b, and 104c. In some embodiments, fin structures 104a, 104b, and 104c include a base fin structure 105 and a semiconductor material stack, the semiconductor material stack including a first semiconductor material layer 106 and a second semiconductor material layer 108 formed on the base fin structure 105. In some embodiments, the widths of fin structures 104a, 104b, and 104c are substantially the same. In some embodiments, the distance D1 between adjacent first structures (e.g., fin structures 104b and 104c) is in the range of about 20 nm to about 1000 nm.

[0037] In some embodiments, the patterning process includes forming a mask structure 110 over a semiconductor material stack, and etching the semiconductor material stack and the underlying substrate 102 through the mask structure 110. In some embodiments, the mask structure 110 is a multilayer structure including a pad oxide layer 112 and a nitride layer 114 formed over the pad oxide layer 112. The pad oxide layer 112 may be made of silicon oxide, which may be formed by thermal oxidation or CVD, while the nitride layer 114 may be made of silicon nitride, which may be formed by CVD (e.g., LPCVD or plasma-enhanced CVD (PECVD)).

[0038] According to some embodiments, such as Figure 2C As shown, after forming fin structures 104a, 104b, and 104c, an isolation structure 116 is formed around the fin structures 104a, 104b, and 104c, and the mask structure 110 is removed. According to some embodiments, the isolation structure 116 is configured as an active region of the electrically isolated semiconductor structure 100 (e.g., fin structures 104a, 104b, and 104c) and is also referred to as a shallow trench isolation (STI) feature.

[0039] The isolation structure 116 can be formed by depositing an insulating layer on the substrate 102 and recessing the insulating layer so that the fin structures 104a, 104b, and 104c protrude relative to the isolation structure 116. In some embodiments, the isolation structure 116 is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), another suitable insulating material, or a combination thereof. In some embodiments, a dielectric liner (not shown) is formed prior to the formation of the isolation structure 116, and the dielectric liner is made of silicon nitride, and the isolation structure formed on the dielectric liner is made of silicon oxide.

[0040] According to some embodiments, such as Figure 2D As shown, after the isolation structure 116 is formed, a covering layer 118 is formed on the top surface and sidewalls of the fin structures 104a, 104b and 104c above the isolation structure 116.

[0041] In some embodiments, the cladding layer 118 is made of a semiconductor material. In some embodiments, the cladding layer 118 is made of silicon germanium (SiGe). The cladding layer 118 can be formed by performing an epitaxial process (e.g., VPE and / or UHV CVD, molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof). After depositing the cladding layer 118, an etching process (e.g., using a plasma dry etching process) can be performed to remove portions of the cladding layer 118 that are not on the sidewalls of the fin structures 104a, 104b, and 104c. In some embodiments, portions of the cladding layer 118 formed on the top surfaces of the fin structures 104a, 104b, and 104c are partially or completely removed by the etching process, such that the thickness of the cladding layer 118 above the top surfaces of the fin structures 104a, 104b, and 104c is thinner than the thickness of the cladding layer 118 on the sidewalls of the fin structures 104a, 104b, and 104c.

[0042] Prior to forming the cladding layer 118, a semiconductor liner (not shown) may be formed on the fin structures 104a, 104b, and 104c. The semiconductor liner may be a Si layer and may be incorporated into the cladding layer 118 during the epitaxial growth process used to form the cladding layer 118.

[0043] According to some embodiments, such as Figure 2E As shown, a dielectric liner 120 is then formed over the cladding layer 118 and the isolation structure 116. In some embodiments, the dielectric liner 120 is made of SiN, SiCN, SiOCN, SiON, etc. In some embodiments, the dielectric liner 120 is made of a dielectric material, such as HfO2 or HfSiO. x (e.g., HfSiO4), HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlOx, ZrO2, ZrSiO2, AlSiO, Al2O3, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable dielectric materials, or combinations thereof. The dielectric liner 120 can be deposited using methods such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof. In some embodiments, the thickness of the dielectric liner 120 is in the range of about 1 nm to about 6 nm.

[0044] According to some embodiments, such as Figure 2FAs shown, after forming the dielectric liner 120, a dielectric filling layer 122 is formed on the dielectric liner 120 to completely fill the space between adjacent fin structures 104a, 104b and 104c, and a polishing process is performed until the top surface of the overlay layer 118 is exposed.

[0045] In some embodiments, the dielectric filler layer 122 and the dielectric liner 120 are made of different dielectric materials. In some embodiments, the dielectric filler layer 122 is made of a low-k dielectric material, and the dielectric liner 120 is made of a high-k dielectric material. In some embodiments, the dielectric filler layer 122 is made of SiN, SiCN, SiOCN, SiON, etc. The dielectric filler layer 122 can be deposited using a flowable CVD (FCVD) process, which includes, for example, depositing a flowable material (e.g., a liquid compound) and converting the flowable material into a solid material using suitable techniques (e.g., thermal annealing and / or ultraviolet radiation treatment).

[0046] According to some embodiments, such as Figure 2G As shown, a recess is then formed between the fin structures 104a, 104b, and 104c, and a dielectric material is formed within the recess to form dielectric features 124a, 124b, and 124c separating the fin structures 104a, 104b, and 104c. In some embodiments, the dielectric features 124a, 124b, and 124c include a bottom portion (including a dielectric filling layer 122 and a dielectric liner 120) and an upper portion 126 formed above the bottom portion. In some embodiments, the interface between the bottom portion and the upper portion 126 of the dielectric feature is substantially flush with the top surface of the uppermost second semiconductor material layer 108. In some embodiments, the dielectric constant of the upper portion 126 is higher than that of the bottom portion.

[0047] In some embodiments, an etching process is performed to partially remove the dielectric filler layer 122 and the dielectric liner 120 to form a recess. The recess is then filled with a dielectric material to form an upper portion 126. In some embodiments, the dielectric material used to form the upper portion 126 of the dielectric features 124a, 124b, and 124c is SiN, SiCN, SiOCN, SiON, HfO2, ZrO2, or HfAlO. x HfSiO x Materials such as Al2O3 can be used. Dielectric materials can be formed by performing ALD, CVD, PVD, oxidation-based deposition processes, other suitable processes, or combinations thereof. According to some embodiments, after the dielectric material is formed, a CMP process is performed until the mask structure 110 is exposed.

[0048] Because the dielectric features 124a, 124b, and 124c are spatially self-aligned with the fin structures 104a, 104b, and 104c, a complex alignment process is not required when forming the dielectric features. Furthermore, the width of the dielectric features can be determined by the width of the space between the fin structures 104a, 104b, and 104c and the thickness of the overlay layer 118. In some embodiments, the dielectric features 124a, 124b, and 124c have substantially the same width. Meanwhile, in some embodiments, the spacing between the fin structures 104a, 104b, and 104c has different widths, and the dielectric features 124a, 124b, and 124c also have different widths.

[0049] According to some embodiments, such as Figure 1 As shown, dielectric features 124a, 124b and 124c are formed between adjacent fin structures 104a, 104b and 104c and are substantially parallel to fin structures 104a, 104b and 104c.

[0050] According to some embodiments, such as Figure 2H As shown, next, the mask structure 110 is removed and the cladding layer 118 is partially removed to expose the top surface of the uppermost second semiconductor material layer 108. In some embodiments, the top surface of the cladding layer 118 is substantially flush with the top surface of the uppermost second semiconductor material layer 108.

[0051] The mask structure 110 and the cladding layer 118 can be recessed using one or more etching processes that have a higher etching rate for the mask structure 110 and the cladding layer 118 than for the dielectric features 124a, 124b, and 124c, such that the dielectric features 124a, 124b, and 124c are only slightly etched during the etching process. The selective etching process can be dry etching, wet etching, reactive ion etching, or other suitable etching methods.

[0052] According to some embodiments, such as Figure 2I As shown, the transfin structures 104a, 104b, and 104c, along with the dielectric features 124a, 124b, and 124c, then form a dummy gate structure 128. The dummy gate structure 128 can be used to define the source / drain region and the channel region of the resulting semiconductor structure 100.

[0053] In some embodiments, the dummy gate structure 128 includes a dummy gate dielectric layer 130 and a dummy gate electrode layer 132. In some embodiments, the dummy gate dielectric layer 130 is made of one or more dielectric materials (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), HfO2, HfZrO, HfSiO, HfTiO, HfAlO, or combinations thereof). In some embodiments, the dummy gate dielectric layer 130 is formed using thermal oxidation, CVD, ALD, physical vapor deposition (PVD), another suitable method, or a combination thereof.

[0054] In some embodiments, the dummy gate electrode layer 132 is made of a conductive material, including polysilicon (poly-Si), polysilicon germanium (poly-SiGe), metal nitride, metal silicide, metal, or combinations thereof. In some embodiments, CVD, PVD, or combinations thereof are used to form the dummy gate electrode layer 132.

[0055] In some embodiments, a hard mask layer 134 is formed over the dummy gate structure 128. In some embodiments, the hard mask layer 134 includes multiple layers, such as an oxide layer 136 and a nitride layer 138. In some embodiments, the oxide layer 136 is silicon oxide and the nitride layer 138 is silicon nitride.

[0056] The formation of the dummy gate structure 128 may include conformally forming a dielectric material as a dummy gate dielectric layer 130. Then, a conductive material may be formed on the dielectric material as a dummy gate electrode layer 132, and a hard mask layer 134 may be formed on the conductive material. Next, the dielectric material and the conductive material may be patterned using the hard mask layer 134 to form the dummy gate structure 128.

[0057] According to some embodiments, such as Figure 2J As shown, after forming the dummy gate structure 128, gate spacers 140 are formed along the opposite sidewalls of the dummy gate structure 128, and these gate spacers 140 cover these opposite sidewalls. In some embodiments, the gate spacers 140 also cover portions of the top surfaces of the sidewalls of the dielectric features 124a, 124b, and 124c.

[0058] Gate spacer 140 may be configured to separate the source / drain structure (which is subsequently formed) from the dummy gate structure 128. In some embodiments, gate spacer 140 is made of a dielectric material (e.g., silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and / or combinations thereof).

[0059] According to some embodiments, such as Figure 2J As shown, after the gate spacer 140 is formed, a source / drain recess 142 adjacent to the gate spacer 140 is formed. More specifically, according to some embodiments, the fin structures 104a, 104b, and 104d not covered by the dummy gate structure 128 and the gate spacer 140, as well as the cladding layer 118 not covered by the dummy gate structure 128 and the gate spacer 140, are recessed. Furthermore, according to some embodiments, the upper portion 126 of the dielectric features 124a, 124b, and 124c is also partially recessed to have a recessed portion 127 at the source / drain region.

[0060] In some embodiments, the fin structures 104a, 104b, and 104c, as well as the cladding layer 118, are recessed by performing an etching process. The etching process may be an anisotropic etching process (e.g., dry plasma etching), and the dummy gate structure 128 and the gate spacer 140 are used as etching masks during the etching process.

[0061] According to some embodiments, such as Figure 2K As shown, after the source / drain recess 142 is formed, the first semiconductor material layer 106 and the cladding layer 118 exposed by the source / drain recess 142 are laterally recessed to form a notch 144.

[0062] In some embodiments, an etching process is performed to laterally recess the first semiconductor material layer 106 and the cladding layer 118 of the fin structures 104a, 104b, and 104c relative to the source / drain recess 142. In some embodiments, during the etching process, the etching rate (or etching amount) of the first semiconductor material layer 106 and the cladding layer 118 is greater than the etching rate (or etching amount) of the second semiconductor material layer 108, thereby forming a notch 144 between and around adjacent second semiconductor material layers 108. In some embodiments, the etching process is isotropic etching, such as dry chemical etching, remote plasma etching, wet chemical etching, another suitable technique, and / or combinations thereof.

[0063] According to some embodiments, such as Figure 2L As shown, next, an internal spacer 146 is formed in the notch 144 (which is located between and around the second semiconductor material layers 108). The internal spacer 146 can be configured to separate the source / drain structure and the gate structure formed in subsequent manufacturing processes. In some embodiments, the internal spacer 146 is made of a dielectric material (e.g., silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or combinations thereof).

[0064] According to some embodiments, such as Figure 2M As shown, after forming the internal spacer 146, a source / drain structure 148 is formed in the source / drain recess 142. In some embodiments, the source / drain structure 148 is separated by dielectric features 124a, 124b, and 124c. More specifically, the source / drain structure 148 is formed in the space between the dielectric features 124a, 124b, and 124c in the source / drain region. Furthermore, according to some embodiments, the source / drain structure 148 is in direct contact with the dielectric liner 120 at the bottom portions of the dielectric features 124a, 124b, and 124c. In some embodiments, an air gap is formed below the source / drain structure 148. In some embodiments, the air gap is surrounded by the source / drain structure 148, the dielectric features 124a, 124b, and 124c, and the isolation structure 116. In some embodiments, the top surface of the recessed portion 127 of the upper portion 126 of dielectric features 124a, 124b and 124c is higher than the top surface of the source / drain structure 148.

[0065] In some embodiments, the source / drain structure 148 is formed using an epitaxial growth process such as MBE, MOCVD, VPE, other suitable epitaxial growth processes, or combinations thereof. In some embodiments, the source / drain structure 148 is made of any suitable material (e.g., Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or combinations thereof).

[0066] In some embodiments, the source / drain structure 148 is in-situ doped during the epitaxial growth process. For example, the source / drain structure 148 may be boron (B)-doped epitaxially grown SiGe. Alternatively, the source / drain structure 148 may be epitaxially grown Si, which may be doped with carbon to form a silicon:carbon (Si:C) source / drain feature, or it may be doped with phosphorus to form a silicon:phosphorus (Si:P) source / drain feature, or it may be doped with both carbon and phosphorus to form a silicon-carbon-phosphorus (SiCP) source / drain feature. In some embodiments, the source / drain structure 148 is doped in one or more implantation processes after the epitaxial growth process.

[0067] According to some embodiments, such as Figure 2N As shown, after forming the source / drain structure 148, a contact etch stop layer (CESL) 150 is conformally formed to cover the source / drain structure 148, and an interlayer dielectric (ILD) layer 152 is formed on the contact etch stop layer 150.

[0068] In some embodiments, the contact etch stop layer 150 is made of a dielectric material (e.g., silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric material, or a combination thereof). The dielectric material for the contact etch stop layer 150 can be conformally deposited on the semiconductor structure by performing CVD, ALD, other application methods, or a combination thereof.

[0069] The interlayer dielectric layer 152 may comprise a multilayer made of various dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BPSG), or other suitable low-k dielectric materials. The interlayer dielectric layer 152 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0070] According to some embodiments, such as Figure 2N As shown, after depositing the contact etch stop layer 150 and the interlayer dielectric layer 152, a planarization process (e.g., CMP or etch-back process) is performed until the dummy gate electrode layer 132 of the dummy gate structure 128 is exposed, and a protective layer 154 is formed over the interlayer dielectric layer 152. More specifically, after performing the planarization process, the interlayer dielectric layer 152 is recessed to a level below the top surface of the dummy gate electrode layer 132, and a protective layer 154 is deposited over the interlayer dielectric layer 152 to protect it from subsequent etching processes. In some embodiments, the protective layer 154 is made of the same or similar material as that in the contact etch stop layer 150. In some embodiments, the protective layer 154 is made of Si3N4, SiCN, SiOC, metal oxides (e.g., HrO2, ZrO2, hafnium aluminum oxide, and hafnium silicate, etc.), or other suitable materials. The protective layer 154 can be formed by CVD, PVD, ALD, or other suitable methods.

[0071] Figures 20 to 2W Manufacturing according to some embodiments is shown. Figure 1 A schematic perspective view of an intermediate stage of the semiconductor structure 100 shown in the dashed box C2. Although Figure 1 Some of the components shown are not in Figures 20 to 2W As shown in the diagram, they can have the same characteristics as... Figures 20 to 2W Features similar to those of the components shown. For example, dielectric feature 124c can have the same characteristics as... Figures 20 to 2W The dielectric feature 124b shown has the same shape.

[0072] According to some embodiments, such as Figure 2OAs shown, after forming the interlayer dielectric layer 152 and the protective layer 154, the dummy gate structure 128, the cladding layer 118, and the first semiconductor material layer 106 are removed to form a gate trench, and the gate structure 156 is formed in the gate trench. More specifically, according to some embodiments, the dummy gate structure 128, the cladding layer 118, and the first semiconductor material layer 106 are removed to utilize the second semiconductor material layer 108 to form a nanostructure 108'. The removal process may include one or more etching processes. For example, when the dummy gate electrode layer 132 is polysilicon, a wet etchant such as tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the dummy gate electrode layer 132. Subsequently, plasma dry etching, dry chemical etching, and / or wet etching can be used to remove the dummy gate dielectric layer 130. The first semiconductor material layer 106 and the cladding layer 118 can be removed by performing a selective wet etching process (e.g., APM (e.g., ammonium hydroxide-hydrogen peroxide-water mixture) etching process). For example, wet etching processes use etchants such as ammonium hydroxide (NH4OH), TMAH, ethylenediamine catechol (EDP), and / or potassium hydroxide (KOH) solutions.

[0073] In some embodiments, the upper portion of the gate spacer 140 is also removed, such that the upper portion of the gate trench can be enlarged and the gate structure 156 can be more easily formed in the gate trench. In some embodiments, the height of the gate spacer is in the range of about 5 nm to about 50 nm.

[0074] According to some embodiments, such as Figure 2O As shown, after forming the nanostructure 108', a gate structure 156 is formed around the nanostructure 108'. According to some embodiments, the gate structure 156 surrounds the nanostructure 108' to form a gate-all-around transistor structure. In some embodiments, the gate structure 158 includes an interface layer 160, a gate dielectric layer 162, and a gate electrode layer 164.

[0075] In some embodiments, the interface layer 160 is an oxide layer formed around the nanostructure 108' and on the exposed portion of the base fin structure 105. In some embodiments, the interface layer 160 is formed by performing a thermal process.

[0076] In some embodiments, a gate dielectric layer 162 is formed on the interface layer 160 such that the nanostructure 108' is surrounded (e.g., encircled) by the gate dielectric layer 162. Furthermore, according to some embodiments, the gate dielectric layer 162 also covers the sidewalls of the gate spacer 140, the sidewalls of the inner spacer 146, and the sidewalls of the dielectric features 124a, 124b, and 124c. In some embodiments, the gate dielectric layer 162 is made of one or more dielectric materials (e.g., HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, or combinations thereof). In some embodiments, the gate dielectric layer 162 is formed using CVD, ALD, other suitable methods, or combinations thereof.

[0077] In some embodiments, a gate electrode layer 164 is formed on the gate dielectric layer 162. In some embodiments, the gate electrode layer 164 is made of one or more layers of conductive material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, another suitable material, or combinations thereof. In some embodiments, the gate electrode layer 164 is formed using CVD, ALD, electroplating, another suitable method, or combinations thereof. Other conductive layers (e.g., work function metal layers) may also be formed in the gate structure 156, although they are not shown in the figures. After the interface layer 160, the gate dielectric layer 162, and the gate electrode layer 164 are formed, a planarization process such as CMP or etch-back may be performed until the protective layer 154 is exposed.

[0078] According to some embodiments, such as Figure 2P As shown, after forming the gate structure 156, an etch-back process is performed to remove the upper portion of the gate structure 156 and the upper portions of the dielectric features 124a, 124b, and 124c (not shown) in the channel region. More specifically, according to some embodiments, the upper portions of the gate structure 156 and the upper portions of the dielectric features 124a, 124b, and 124c are removed to form a recess 166 between the gate spacers 140.

[0079] In some embodiments, the top surface of the gate structure 156 is substantially flush with the top surfaces of the dielectric features 124a, 124b, and 124c in the channel region. According to some embodiments, such as Figure 1 and Figure 2PAs shown, after performing the etch-back process, the gate structure 156 is divided into portions 156a, 156b, 156c and 156d by dielectric features 124a, 124b and 124c.

[0080] According to some embodiments, such as Figure 2P As shown, the upper portion 126 of dielectric features 124a, 124b, and 124c has a recessed portion 127' in the channel region and a recessed portion 127' in the source / drain region. Figure 2P Not shown in the image, see [link / reference]. Figure 2J The original portion 127” between the recessed portion 127 and the recessed portion 127'. In some embodiments, the original portion 127” is embedded in the gate spacer 140, and the top surface of the original portion 127” of the upper portion 126 of the dielectric features 124a, 124b, and 124c is lower than the top surface of the gate spacer 140. In some embodiments, the top surface of the original portion 127” is higher than both the recessed portion 127' at the channel region and the recessed portion 127 at the source / drain region.

[0081] In some embodiments, the interface between the recessed portion 127' and the bottom portion of the dielectric feature 124a is substantially flush with the uppermost surface of the nanostructure 108'. In some embodiments, the thickness of the recessed portion 127' in the channel region is in the range of about 5 nm to about 30 nm. In some embodiments, the thickness of the recessed portion 127' is controlled such that the k value is not too high and the electrical performance of the resulting device is not compromised.

[0082] According to some embodiments, such as Figure 2Q As shown, a metal layer 168 is then conformally formed on the bottom surface and sidewalls of the recess 166. More specifically, according to some embodiments, the metal layer 168 covers the top surface of the gate structure 156, the top surface of the recessed portion 127', the sidewalls of the original portions 127" of the dielectric features 124a, 124b, and 124c, the top surface of the protective layer 154, and the sidewalls of the CESL 150. In some embodiments, the metal layer 168 is made of Ru, W, TiN, TaN, Co, Ti, TiAl, etc.

[0083] According to some embodiments, such as Figure 2R As shown, next, the metal layer 168 formed on the sidewalls of the gate spacer 140, the sidewalls of the CESL 150, and the top surface of the protective layer 154 is removed. In some embodiments, a wet etching process is performed to partially remove the metal layer 168.

[0084] The metal layer 168 can be configured to electrically connect the portions of the gate structure 156 defined by the dielectric feature 124. In some embodiments, the thickness of the metal layer 168 is in the range of about 2 nm to about 10 nm. The metal layer 168 must be thick enough to avoid breakage during subsequent manufacturing processes, which would affect the connection between the different portions of the gate structure 156. On the other hand, the metal layer 168 should not be too thick, otherwise the capacitance of the resulting device may increase and the device speed may decrease.

[0085] According to some embodiments, such as Figure 2S As shown, after forming the metal layer 168, a photoresist structure 170 is formed to pattern the metal layer 168. In some embodiments, the photoresist structure 170 includes a bottom layer 172, an intermediate layer 174, and a top photoresist layer 176. Because advanced semiconductor manufacturing processes can push the limits of photolithography, a thinner top photoresist layer is needed to achieve a smaller process window. However, a thin top photoresist layer can be easily removed during the etching process. Therefore, the intermediate layer 174 and the bottom layer 172 are formed below the top photoresist layer 176 to obtain more robust etch support, allowing patterning of the metal layer 168 to be performed while still providing a relatively thin top photoresist layer 176.

[0086] In some embodiments, the intermediate layer 174 includes an anti-reflective material (e.g., a back anti-reflective coating (BARC) layer) to aid exposure and focusing during processing of the top photoresist layer 176. In some embodiments, the bottom layer 172 includes a hard mask material, such as a nitride (e.g., silicon nitride or silicon oxynitride), a polymer, an amorphous material film (e.g., an amorphous carbon film or an amorphous silicon film), polycrystalline silicon, or any other material that can be patterned and selectively removed.

[0087] According to some embodiments, such as Figure 2T As shown, an opening 178 is then formed in the photoresist structure 170, and the metal layer 168 is patterned through the opening 178. More specifically, according to some embodiments, an opening 169 is formed in the metal layer 168, and the top surface of the upper portion 126 of the dielectric feature 124a through the recessed portion 127 is exposed by the opening 169.

[0088] According to some embodiments, such as Figure 2UAs shown, after patterning the metal layer 168 to form the opening 169, the photoresist structure 170 is removed. According to some embodiments, more specifically, the metal layer 168 now includes portions 168a and 168b spaced apart from each other. In some embodiments, portion 168a covers portion 156a of the gate structure 156, and portion 168b covers portions 156b and 156c of the gate structure 156 and the dielectric feature 124b.

[0089] According to some embodiments, such as Figure 2V As shown, a dielectric layer 180 is then formed over the metal layer 168, and the dielectric layer 180 extends into the opening 169. According to some embodiments, since the opening 169 is filled with the dielectric layer 180, portions 168a and 168b of the metal layer 168 are separated by the dielectric layer 180.

[0090] The dielectric layer 180 may comprise a multilayer made of various dielectric materials, such as Al₂O₃, ZrO₂, silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BPSG), or other suitable dielectric materials. The dielectric layer 180 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0091] According to some embodiments, such as Figure 2W As shown, after forming the dielectric layer 180, a conductive structure 182 is formed through the dielectric layer 180, and the conductive structure 182 is located on a portion 168b of the metal layer 168. A source / drain contact 184 is formed through the interlayer dielectric layer 152 and the protective layer 154, and the source / drain contact 184 is located on the source / drain structure 148. In some embodiments, a silicide layer 186 is formed on the source / drain structure 148 before forming the source / drain contact 184.

[0092] In some embodiments, the conductive structure 182 and the source / drain contact 184 are made of the same conductive material. The conductive material may include aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt, tantalum nitride (TaN), nickel silicide (NiS), cobalt silicide (CoSi), copper silicide, tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminum nitride (TiAl), titanium aluminum nitride (TiAlN), other suitable conductive materials, or combinations thereof.

[0093] A liner and / or barrier layer (not shown) may be formed prior to the formation of the conductive material. The liner may be made of silicon nitride, but any other suitable dielectric may be used as an alternative. The barrier layer may be made of tantalum nitride, but other materials such as tantalum, titanium, titanium nitride, etc., may also be used.

[0094] The conductive structure 182 and the source / drain contact 184 can be formed in separate processes. A trench can be formed through the interlayer dielectric layer 152 and the protective layer 154 to expose the source / drain structure 148, and a silicide layer 186 can be formed by forming a metal layer over the top surface of the source / drain structure 148 and annealing the metal layer to react with the source / drain structure 148 to form the silicide layer 186. After forming the silicide layer 186, any unreacted metal layer can be removed. The conductive material can then be formed in the trench to form the source / drain contact 184 using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other suitable deposition process.

[0095] Similarly, the conductive structure 182 can be formed by forming a trench exposing the metal layer 168 and forming a conductive material in the trench using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other suitable deposition process.

[0096] Figure 3 Illustrations are shown according to some embodiments Figure 2W The semiconductor structure 100 shown is along Figure 1 A cross-sectional view of line A-A' in the diagram. According to some embodiments, such as... Figure 3 As shown, the gate structure 156 includes a portion 156a surrounding a nanostructure 108' of a fin structure 104a, a portion 156b surrounding a nanostructure 108' of a fin structure 104b, and a portion 156c surrounding a nanostructure 108' of a fin structure 104c. According to some embodiments, portions 156a, 156b, and 156c of the gate structure 156 are separated by dielectric features 124a and 124b. Furthermore, according to some embodiments, a portion 168b of a metal layer 168 continuously covers portions 156b and 156c of the gate structure 156 and the dielectric feature 124b, such that portions 156b and 156c are electrically connected through the metal layer 168.

[0097] In some embodiments, the top surface of the first dielectric feature 124a in the channel region is substantially flush with the top surface of the gate structure 156. In some embodiments, the dielectric features 124a, 124b, and 124c in the channel region are substantially flush with each other. In some embodiments, an isolation structure 116 is formed around the base fin structure 105 below the dielectric features 124a, 124b, and 124c. In some embodiments, a portion 156b of the gate structure 156 is in direct contact with the sidewalls of the dielectric features 124a and 124b and the top surface of the isolation structure 116.

[0098] Meanwhile, according to some embodiments, a portion 168a of the metal layer 168 covers a portion 156a of the gate structure 156 but is separated from the portion 168b of the metal layer by the dielectric layer 180, such that the portion 156a of the gate structure 156 is electrically isolated from the portions 156b and 156c of the gate structure 156. In some embodiments, the dielectric layer 180 is in direct contact with the top surface of the dielectric feature 124a and the metal layer 168. In some embodiments, dielectric features 124a, 124b, and 124c all pass through the gate structure 156, and dielectric feature 124a is in direct contact with the dielectric layer 180, while dielectric features 124b and 124c are separated from the dielectric layer 180 by the metal layer 168.

[0099] Furthermore, according to some embodiments, a conductive structure 182 is formed on a portion 156b of the gate structure 156, and the conductive structure 182 is electrically connected to a portion 156b of the gate structure 156 via a portion 168b of the metal layer 168. In some embodiments, the interface between the upper portion 126 (e.g., via the recessed upper portion 127') and the bottom portion of the dielectric features 124a, 124b, and 124c in the channel region is substantially flush with the uppermost nanostructure 108'.

[0100] Because the gate structure 156 is divided into different portions by the dielectric feature, and these portions of the gate structure are connected by a subsequently formed metal layer 168, the space between the nanostructure 108' and the dielectric feature may be relatively small. In some embodiments, the distance D2 between the nanostructure 108' and the dielectric feature 124a is in the range of about 5 nm to about 20 nm.

[0101] Figure 4A A schematic top view of a semiconductor structure 100-1 according to some embodiments is shown. Figure 4B The following is illustrated according to some embodiments. Figure 4A The image shows a cross-sectional view of semiconductor structure 100-1 along line B-B'. According to some embodiments, semiconductor structure 100-1 may be similar to... Figure 1 and Figure 3The semiconductor structure 100 shown is different in that the fin structures in semiconductor structure 100-1 have different widths. The materials and processes used to manufacture semiconductor structure 100-1 can be similar to or the same as those used to manufacture the semiconductor structure 100 described above, and will not be repeated here.

[0102] According to some embodiments, more specifically, the semiconductor stack is patterned to form fin structures 104a-1, 104b, and 104c. In some embodiments, fin structure 104a-1 is wider than fin structures 104b and 104c, and the width of fin structure 104b is substantially the same as the width of fin structure 104c. The processes and materials used to form fin structure 104a-1 are the same as those used to form fin structure 104a, and will not be described again here.

[0103] After the fin structure 104a-1 is formed, the following can be performed: Figures 2C to 2W The process shown and previously described is used to form the semiconductor structure 100-1. In some embodiments, a portion 156a-1 of the gate structure 156-1 is wider than portions 156b-1 and 156c-1 of the gate structure 156-1. The processes and materials used to form the gate structure 156-1 are the same as those used to form the gate structure 156, and will not be described again here.

[0104] Figure 5 A cross-sectional view of a semiconductor structure 100-2 according to some embodiments is shown. According to some embodiments, the semiconductor structure 100-2 may be similar to... Figure 3 and Figure 4B The semiconductor structures 100 and 100-1 shown are different in that the bottom portion of the dielectric feature in semiconductor structure 100-2 is made of a single material. The materials and processes used to manufacture semiconductor structure 100-2 can be similar to or the same as those used to manufacture semiconductor structures 100 and 100-1, and will not be described again here.

[0105] According to some embodiments, more specifically, the execution Figures 2A to 2D The process shown is such that the space between fin structures 104a, 104b and 104c is completely filled by dielectric layer 120-2.

[0106] In some embodiments, the dielectric layer 120-2 is made of SiN, SiCN, SiOCN, or SiON. In some embodiments, the dielectric liner 120-2 is made of a high-k dielectric material, such as HfO2 or HfSiO2. x (e.g., HfSiO4), HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO xZrO2, ZrSiO2, AlSiO, Al2O3, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, or combinations thereof. Dielectric layers can be deposited using the following methods: CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof.

[0107] According to some embodiments, such as Figure 5 As shown, after depositing dielectric layer 120-2, dielectric layer 120-2 is polished until the cladding layer is exposed (e.g., Figure 2F The top surface of the covering layer 118 shown is subjected to, and is performed on Figures 2G to 2W The process shown is used to form semiconductor structure 100-2. According to some embodiments, such as... Figure 5 As shown, dielectric layer 120-2 forms the bottom portion of dielectric features 124a-1 and 124b-1, and an upper portion 126 is formed on top of dielectric layer 120-1.

[0108] Figure 6 A cross-sectional view of a semiconductor structure 100-3 according to some embodiments is shown. According to some embodiments, the semiconductor structure 100-3 may be similar to... Figure 3 and Figure 4B The semiconductor structures 100 and 100-1 shown are distinguished by the relatively low interface between the upper and lower portions of the dielectric feature. The materials and processes used to manufacture semiconductor structure 100-3 can be similar to or the same as those used to manufacture semiconductor structures 100 and 100-1, and will not be described further here.

[0109] According to some embodiments, more specifically, the execution Figures 2A to 2F The process is illustrated, and the dielectric liner 120 and dielectric fill layer 122 are recessed to form relatively deep recesses above the bottom portions of dielectric features 124a-3 and 124b-3. According to some embodiments, after the dielectric liner 120 and dielectric fill layer 122 are recessed, the top surface of the bottom portions of dielectric features 124a-3 and 124b-3 is slightly lower than the top surface of the uppermost second semiconductor material layer (e.g., second semiconductor material layer 108). According to some embodiments, next, the upper portions 126-3 of dielectric features 124a-3 and 124b-3 are formed, and the process is performed... Figures 2H to 2W The process shown is used to form semiconductor structure 100-3.

[0110] According to some embodiments, such as Figure 6 As shown, the interface between the upper portion 126-3 (including the recessed portion 127'-3) and the bottom portion of dielectric features 124a-3 and 124b-3 is lower than the top surface of the uppermost nanostructure 108' in the channel region. In some embodiments, the interface between the upper portion 126-3 and the bottom portion of dielectric features 124a-3 and 124b-3 is higher than the bottom surface of the uppermost nanostructure 108' in the channel region.

[0111] Figure 7 A cross-sectional view of a semiconductor structure 100-4 according to some embodiments is shown. According to some embodiments, the semiconductor structure 100-4 may be similar to... Figure 3 and Figure 4B The semiconductor structures 100 and 100-1 shown are distinguished by the relatively high interface between the upper and lower portions of the dielectric feature. The materials and processes used to manufacture semiconductor structure 100-4 can be similar to or the same as those used to manufacture semiconductor structures 100 and 100-1, and will not be described further here.

[0112] According to some embodiments, more specifically, the execution Figures 2A to 2F The process shown involves recessing the dielectric liner 120 and the dielectric filler layer 122 to form relatively shallow recesses above the bottom portions of the dielectric features 124a-4 and 124b-4. According to some embodiments, such as... Figure 7 As shown, the upper portion 126-4 of dielectric features 124a-4 and 124b-4 is then formed, and the following is performed: Figures 2H to 2W The process shown is used to form semiconductor structure 100-4. According to some embodiments, such as... Figure 7 As shown, the interface between the upper portion 126-4 (including the recessed portion 127'-4) and the bottom portion of dielectric features 124a-4 and 124b-4 is higher than the top surface of the uppermost nanostructure 108' in the channel region.

[0113] Figure 8A and Figure 8B A cross-sectional view of an intermediate stage in the fabrication of semiconductor structure 100-5 according to some embodiments is shown. According to some embodiments, semiconductor structure 100-5 may be similar to… Figure 3 and Figure 4B The semiconductor structures 100 and 100-1 shown are different in that the dielectric characteristics of the channel region in semiconductor structure 100-5 are higher than those of the gate structure. The materials and processes used to manufacture semiconductor structure 100-5 can be similar to or the same as those used to manufacture semiconductor structures 100 and 100-1, and will not be described in detail here.

[0114] According to some embodiments, such as Figure 8A As shown, more specifically, execute Figures 2A to 2O The process is illustrated, and an etch-back process is performed to remove the upper portion of the gate structure 156-5 and the upper portions of the dielectric features 124a-5 and 124b-5 in the channel region. In some embodiments, the etch rates for the gate structure 156-5 and the dielectric features 124a-5 and 124b-5 are different during the etch-back process, so the top surface of the gate structure 156-5 and the top surfaces of the dielectric features 124a-5 and 124b-5 are not flush. In some embodiments, the top surface of the gate structure 156-5 is lower than the top surface of the recessed portions 127'-5 of the dielectric features 124a-5 and 124b-5. In some embodiments, the height difference between the top surface of the gate structure 156-5 and the top surface of the recessed portion 127'-5 of the dielectric features 124a-5 and 124b-5 in the channel region is less than 2 nm, so that the metal layer formed subsequently can still correctly connect portions 156b-5 and 156c-5 of the gate structure 156-5.

[0115] According to some embodiments, such as Figure 8B As shown, then execute Figures 2Q to 2W The process shown is used to form semiconductor structure 100-5. According to some embodiments, since the top surface of gate structure 156-5 is not flush with the top surfaces of dielectric features 124a-5 and 124b-5, the metal layer 168-5 formed on them is not flat. In some embodiments, metal layer 168-5 has portions 168a-5 and 168b-5, and portion 168b-5 has a protruding portion. In some embodiments, the uppermost portion of portion 168b-5 is higher than the uppermost portion of portion 168a-5. The processes and materials used to form gate structure 156-5, dielectric features 124a-5 and 124b-5, and metal layer 168-5 can be the same as those used to form gate structure 156, dielectric features 124a and 124b, and metal layer 168, and therefore will not be described again here.

[0116] Figure 9A and Figure 9B A cross-sectional view is shown of an intermediate stage in the fabrication of semiconductor structure 100-6 according to some embodiments. According to some embodiments, semiconductor structure 100-6 may be similar to... Figure 3 and Figure 4B The semiconductor structures 100 and 100-1 shown are different in that the dielectric characteristics of semiconductor structure 100-6 are lower than those of the gate structure. The materials and processes used to manufacture semiconductor structure 100-6 can be similar to or the same as those used to manufacture semiconductor structures 100 and 100-1, and will not be described again here.

[0117] According to some embodiments, such as Figure 9A As shown, more specifically, execute Figures 2A to 2O The process is illustrated, and an etch-back process is performed to remove the upper portion of the gate structure 156-6 and the upper portions of the dielectric features 124a-6 and 124b-6 in the channel region. In some embodiments, the etch rates for the gate structure 156-6 and the dielectric features 124a-6 and 124b-6 are different during the etch-back process, so the top surface of the gate structure 156-6 and the top surfaces of the dielectric features 124a-6 and 124b-6 are not flush. In some embodiments, the top surface of the gate structure 156-6 is higher than the top surface of the recessed portions 127'-6 of the dielectric features 124a-6 and 124b-6. In some embodiments, the height difference between the top surface of the gate structure 156-6 and the top surface of the recessed portion 127'-6 of the dielectric features 124a-6 and 124b-6 is less than 2 nm, so that the metal layer formed subsequently can still correctly connect portions 156b-6 and 156c-6 of the gate structure 156-6.

[0118] According to some embodiments, such as Figure 9B As shown, then execute Figures 2Q to 2W The process shown is used to form semiconductor structure 100-6. According to some embodiments, since the top surface of gate structure 156-6 is not flush with the top surfaces of dielectric features 124a-6 and 124b-6, the metal layer 168-6 formed on them is not flat. In some embodiments, metal layer 168-6 has portions 168a-6 and 168b-6, and portion 168b-6 has a recessed portion. In some embodiments, the lowermost portion of portion 168b-6 is lower than the lowermost portion of portion 168a-6. The processes and materials used to form gate structure 156-6, dielectric features 124a-6 and 124b-6, and metal layer 168-6 can be the same as those used to form gate structure 156, dielectric features 124a and 124b, and metal layer 168, and therefore will not be described again here.

[0119] Figure 10A and Figure 10B A cross-sectional view is shown of an intermediate stage in the fabrication of semiconductor structure 100-7 according to some embodiments. According to some embodiments, semiconductor structure 100-7 may be similar to... Figure 3 and Figure 4B The semiconductor structures 100 and 100-1 shown are different in that the openings in the metal layer are wider than the dielectric features. The materials and processes used to manufacture semiconductor structure 100-7 can be similar to or the same as those used to manufacture semiconductor structures 100 and 100-1, and will not be described again here.

[0120] According to some embodiments, such as Figure 10A As shown, more specifically, execute Figures 2A to 2S The process is illustrated, and the metal layer 168-7 is patterned through openings 178-7 in the photoresist structure 170-7. In some embodiments, openings 178-7 in the photoresist structure 170-7 are wider than dielectric feature 124a. According to some embodiments, openings 169-7 in the metal layer 168-7 are also wider than dielectric feature 124a, such that portions 156a-7 and 156b-7 of the gate structure 156-7 are also partially exposed by openings 169-7 in the metal layer 168-7. In some embodiments, the edges of openings 169-7 in the metal layer 168-7 are not aligned with the edges of dielectric feature 124a-7.

[0121] According to some embodiments, such as Figure 10B As shown, then execute Figures 2U to 2W The process shown forms semiconductor structure 100-7. Since portions 156a-7 and 156b-7 are exposed by opening 169-7, the subsequently formed dielectric layer 180-7 is in direct contact with portions 156a-7 and 156b-7 of gate structure 156-7. According to some embodiments, although some portions of gate structure 156-7 are not covered by metal layer 168-7, the nanostructure 108' is entirely covered by metal layer 168-7 vertically (e.g., vertically overlapped). The processes and materials used to form gate structure 156-7, metal layer 168-7, and dielectric layer 180-7 can be the same as those used to form gate structure 156, metal layer 168, and dielectric layer 180, and therefore will not be described again here.

[0122] Figure 11A and Figure 11B A cross-sectional view of an intermediate stage in the fabrication of semiconductor structure 100-8 according to some embodiments is shown. According to some embodiments, semiconductor structure 100-8 may be similar to… Figure 3 and Figure 4B The semiconductor structures 100 and 100-1 shown are different in that the openings in the metal layer are narrower than the dielectric features. The materials and processes used to manufacture semiconductor structure 100-8 can be similar to or the same as those used to manufacture semiconductor structures 100 and 100-1, and will not be described again here.

[0123] According to some embodiments, such as Figure 11A As shown, more specifically, execute Figures 2A to 2SThe process is illustrated, and the metal layer 168-8 is patterned through openings 178-8 in the photoresist structure 170-8. In some embodiments, the openings 178-8 in the photoresist structure 170-8 are narrower than the dielectric feature 124a-8. According to some embodiments, therefore, the openings 169-8 in the metal layer 168-8 are narrower than the dielectric feature 124a-8, such that the dielectric feature 124a-8 is partially exposed by the openings 169-8 and partially covered by the metal layer 168-8.

[0124] According to some embodiments, such as Figure 11B As shown, then execute Figures 2U to 2W The process shown is used to form semiconductor structure 100-8. In some embodiments, dielectric features 124a-8 are partially covered by dielectric layer 180-8 and partially covered by metal layer 168-8. The processes and materials used to form dielectric features 124a-8, metal layer 168-8, and dielectric layer 180-8 can be the same as those used to form dielectric features 124a, metal layer 168, and dielectric layer 180, and therefore will not be described again here.

[0125] Figure 12A and Figure 12B A cross-sectional view is shown of an intermediate stage in the fabrication of semiconductor structure 100-9 according to some embodiments. According to some embodiments, semiconductor structure 100-9 may be similar to... Figure 3 and Figure 4B The semiconductor structures 100 and 100-1 shown are different in that the openings in the metal layer are not aligned with the dielectric features. The materials and processes used to manufacture semiconductor structure 100-9 can be similar to or the same as those used to manufacture semiconductor structures 100 and 100-1, and will not be described again here.

[0126] According to some embodiments, such as Figure 12A As shown, more specifically, execute Figures 2A to 2S The process is illustrated, and the metal layer 168-9 is patterned through openings 178-9 in the photoresist structure 170-9. In some embodiments, openings 178-9 in the photoresist structure 170-7 are not fully aligned with the dielectric feature 124a. According to some embodiments, therefore, openings 169-9 in the metal layer 168-9 are not fully aligned with the dielectric feature 124a, such that portions 156a-9 of the gate structure 156-9 are also partially exposed by openings 169-9. In some embodiments, the edges of portions 168b-9 of the metal layer 168-9 are substantially aligned with the first sidewall of the dielectric feature 124a, and the edges of portions 168a-9 of the metal layer 168-9 are not aligned with the second sidewall (opposite to the first sidewall) of the dielectric feature 124a.

[0127] According to some embodiments, such as Figure 12B As shown, then execute Figures 2U to 2W The process shown is used to form semiconductor structure 100-9. Since portions 156a-9 are exposed by openings 169-9, the subsequently formed dielectric layer 180-9 is in direct contact with portions 156a-9 of the gate structure 156-9. According to some embodiments, although some portions of the gate structure 156-9 are not covered by the metal layer 168-9, the nanostructure 108' is entirely covered by the metal layer 168-9 vertically (e.g., vertically overlapping). The processes and materials used to form the gate structure 156-9 including portions 156a-9, 156b-9, and 156c-9, the metal layer 168-9 including portions 168a-9 and 168b-9, and the dielectric layer 180-9 can be the same as those used to form the gate structure 156 including portions 156a, 156b, and 156c, the metal layer 168 including portions 168a and 168b, and the dielectric layer 180, and therefore will not be described again here.

[0128] Figure 13A and Figure 13B A cross-sectional view is shown of an intermediate stage in the fabrication of semiconductor structure 100-10 according to some embodiments. According to some embodiments, semiconductor structure 100-10 may be similar to... Figure 3 and Figure 4B The semiconductor structures 100 and 100-1 shown are different in that the opening in the metal layer is wider than the dielectric feature and the dielectric layer extends into the gate structure. The materials and processes used to manufacture semiconductor structure 100-10 can be similar to or the same as those used to manufacture semiconductor structures 100 and 100-1, and will not be described again here.

[0129] According to some embodiments, such as Figure 13A As shown, more specifically, execute Figures 2A to 2SThe process is illustrated, and the metal layer 168-10 is patterned through openings 178-10 in the photoresist structure 170-10. In some embodiments, the openings 178-10 of the photoresist structure 170-10 are wider than the dielectric feature 124a-10. According to some embodiments, therefore, the openings 169-10 of the metal layer 168-10 are wider than the dielectric feature 124a-10, such that portions 156a-10 and 156b-10 of the gate structure 156-10 are partially exposed by the openings 169-10. Furthermore, according to some embodiments, when the metal layer 168-10 is patterned, portions 156a-10 and 156b-10 of the gate structure 156-10 are also partially etched, such that the openings 178-10 have extensions 179 extending into portions 156a-10 and 156b-10 of the gate structure 156-10. In some embodiments, when the metal layers 168-10 are patterned, the dielectric features 124a-10 are also slightly etched and removed.

[0130] In some embodiments, the upper portion of the sidewall of dielectric features 124a-10 is exposed by an extension 179 of openings 178-10. In some embodiments, the depth of the extension 179 is less than about 2 nm, such that the nanostructure 108' is not damaged by the etching process.

[0131] According to some embodiments, such as Figure 13B As shown, then execute Figures 2U to 2W The process shown is used to form a semiconductor structure 100-10. A dielectric layer 180-10 is formed over a metal layer 168-10, and the dielectric layer 180-10 is in direct contact with portions 156a-10 and 156b-10 of the gate structure 156-10. Furthermore, according to some embodiments, the dielectric layer 180-10 has an extension 181 formed in an extension 179 of the opening 178-10.

[0132] In some embodiments, the extension 181 is sandwiched between portions 156a-10 of the gate structure 156-10 and the dielectric feature 124a-10, and is also sandwiched between portions 156b-10 of the gate structure 156-10 and the dielectric feature 124a-10. In some embodiments, the thickness of the extension 181 is less than about 2 nm. The extension should not be too thick, otherwise it may compromise control over the gate structure 156-10. In some embodiments, the extension 181 has a curved bottom surface.

[0133] In some embodiments, the lowermost portion of the extension 181 of the dielectric layer 180-10 is below the lowermost surface of the metal layer 168-10. According to some embodiments, although some portions of the gate structure 156-10 are not covered by the metal layer 168-10, the nanostructure 108' is entirely vertically covered (e.g., vertically overlapped) by the metal layer 168-10. The processes and materials used to form the gate structure 156-10, the metal layer 168-10, and the dielectric layer 180-10 can be the same as those used to form the gate structure 156, the metal layer 168, the dielectric feature 124a, and the dielectric layer 180, and therefore will not be described again here.

[0134] Figure 14A and Figure 14B A cross-sectional view is shown of an intermediate stage in the fabrication of semiconductor structure 100-11 according to some embodiments. According to some embodiments, semiconductor structure 100-11 may be similar to... Figure 3 and Figure 4B The semiconductor structures 100 and 100-1 shown are different in that the openings in the metal layer are not aligned with the dielectric features and the dielectric layer extends into the gate structure. The materials and processes used to manufacture semiconductor structure 100-11 can be similar to or the same as those used to manufacture semiconductor structures 100 and 100-1, and will not be described again here.

[0135] According to some embodiments, such as Figure 14A As shown, more specifically, execute Figures 2A to 2S The process is illustrated, and the metal layer 168-11 is patterned through openings 178-11 in the photoresist structure 170-11. In some embodiments, the openings 178-11 of the photoresist structure 170-11 are not aligned with the dielectric feature 124a-11, therefore the openings 169-11 of the metal layer 168-11 are not aligned with the dielectric feature 124a-11. In some embodiments, portions 156a-11 of the gate structure 156-11 and the dielectric feature 124a-11 are partially exposed by the openings 169-11 of the metal layer 168-11. Meanwhile, according to some embodiments, the dielectric feature 124a-11 is partially covered by portions 168b-11 of the metal layer 168-11.

[0136] Furthermore, according to some embodiments, when the metal layers 168-11 are patterned, portions 156a-11 of the gate structures 156-11 are also partially etched, such that the openings 178-11 have extensions 179' extending into the portions 156a-11 of the gate structures 156-11. In some embodiments, the upper portion of the sidewall of the dielectric feature 124a-11 is exposed by the extensions 179' of the openings 178-11. In some embodiments, the depth of the extensions 179' is less than about 2 nm, such that the nanostructure 108' is not damaged by the etching process.

[0137] According to some embodiments, such as Figure 14B As shown, then execute Figures 2U to 2W The process shown is used to form semiconductor structure 100-11. A dielectric layer 180-11 is formed over metal layer 168-11, and the dielectric layer 180-11 is in direct contact with portions 156a-11 of gate structure 156-11. Furthermore, according to some embodiments, dielectric layer 180-11 has an extension 181' formed in an extension 179 of opening 178-11. In some embodiments, extension 181' has a curved bottom surface.

[0138] In some embodiments, the extension 181' is sandwiched between portions 156a-11 of the gate structure 156-11 and the dielectric feature 124a-11. In some embodiments, the lowermost portion of the extension 181' of the dielectric layer 180-11 is below the lowermost surface of the metal layer 168-11. In some embodiments, the thickness of the extension 181' is less than about 2 nm. The extension 181' should not be too thick, otherwise it may compromise control over the gate structure 156-11.

[0139] According to some embodiments, although some portions of the gate structures 156-11 are not covered by the metal layers 168-11, the entire nanostructure 108' is vertically covered (e.g., vertically overlapped) by the metal layers 168-11. The processes and materials used to form the gate structures 156-111, the metal layers 168-11, the dielectric features 124a-11, and the dielectric layers 180-11 can be the same as those used to form the gate structures 156, the metal layer 168b, the dielectric features 124a, and the dielectric layers 180, and therefore will not be described again here.

[0140] Figure 15A and Figure 15B A cross-sectional view is shown of an intermediate stage in the fabrication of semiconductor structures 100-12 according to some embodiments. According to some embodiments, semiconductor structures 100-12 may be similar to... Figure 3 and Figure 4BThe semiconductor structures 100 and 100-1 shown are different in that the gate spacer in semiconductor structure 100-12 is relatively low. The materials and processes used to manufacture semiconductor structure 100-12 can be similar to or the same as those used to manufacture semiconductor structures 100 and 100-1, and will not be described again here.

[0141] According to some embodiments, more specifically, the execution Figures 2A to 2N The process shown involves removing the dummy gate structure, the cladding layer, the first semiconductor material layer, and the upper portion of the gate spacers 140-12 to form a gate trench exposing the nanostructure 108'. According to some embodiments, such as... Figure 15A As shown, the gate structure 156-12 is then formed and etched back to expose the gate spacer 140-12.

[0142] According to some embodiments, such as Figure 15A As shown, the uppermost portion of the gate spacer 140-12 is below the top surface of the original portion 127” of the dielectric features 124a and 124b. Furthermore, according to some embodiments, after performing an etch-back process, the uppermost portion of the gate spacer 140-12 is above the top surface of the gate structure 156-12. As previously described, by removing the upper portion of the gate spacer 140-12, the gate trench can have a larger top portion, and the gate structure 156-12 can be formed more easily within the gate trench.

[0143] According to some embodiments, such as Figure 15B As shown, then execute Figures 2Q to 2W The process shown is used to form semiconductor structures 100-12. The processes and materials used to form gate spacers 140-12 and gate structures 156-12 can be the same as those used to form gate spacers 140 and gate structures 156, and therefore will not be described again here.

[0144] Typically, in semiconductor devices, it may be necessary to divide the gate structure into multiple parts, and isolation structures may be formed between these parts to isolate different gate structures. However, as device dimensions continue to shrink, the alignment used to form the isolation structures may become increasingly challenging. Therefore, in some embodiments of this disclosure, dielectric features are formed between the gate structures to separate the different parts of the gate structure.

[0145] According to some embodiments, as previously described, dielectric features (e.g., dielectric features 124a, 124b, and 124c) are formed to separate the gate structure (e.g., gate structure 156) into different portions. Furthermore, since the dielectric features are self-aligned with the fin structures (e.g., fin structures 104a, 104a-1, 104b, and 104c), complex alignment processes are not required, and device size can be reduced.

[0146] Furthermore, according to some embodiments, a metal layer (e.g., metal layer 168) is patterned to connect portions of the gate structure, while other portions of the gate structure remain electrically isolated from other portions. Since multiple portions of the gate structure are first separated by dielectric features, and then the portions requiring electrical connection to each other are connected via the metal layer, the tolerance for misalignment in the metal layer patterning is large. That is, openings in the metal layer (e.g., opening 169 of metal layer 168) can be slightly misaligned with the dielectric features without affecting the performance of the resulting semiconductor structure. Therefore, the additional spacing between devices used to prevent misalignment can be reduced, and the device size can also be reduced without sacrificing the performance of the resulting device.

[0147] It should be understood that the elements shown in semiconductor structures 100, 100-1, 100-2, 100-3, 100-4, 100-5, 100-6, 100-7, 100-8, 100-9, 100-10, 100-11, and 100-12 can be combined and / or interchanged. For example, the semiconductor structure may include at least two dielectric features shown in semiconductor structures 100, 100-1, 100-2, 100-3, 100-4, 100-5, 100-6, 100-7, 100-8, 100-9, 100-10, 100-11, and 100-12.

[0148] In addition, it should be noted that Figures 1 to 15B The same elements in the same way can be represented by the same numbers, and can include similar or the same materials, and can be formed by similar or the same processes. Therefore, for the sake of brevity, these redundant details have been omitted. Furthermore, although... Figures 1 to 15B This is a description of the method, but it should be understood that... Figures 1 to 15B The structure disclosed herein is not limited to this method, but can exist independently of this method. Similarly, Figures 1 to 15B The methods shown are not limited to the disclosed structures, but can be used independently of them. Furthermore, according to some embodiments, the above-described nanostructures may include nanowires, nanosheets, or other suitable nanostructures.

[0149] Furthermore, although the disclosed methods are illustrated and described below as a series of actions or events, it should be understood that the order of these actions or events shown may be changed in some other embodiments. For example, some actions may be performed in a different order than those shown and / or described above, and / or in parallel with other actions or events. Moreover, implementing one or more aspects or embodiments described above may not require all the actions shown. Furthermore, one or more actions described above may be performed in one or more separate actions and / or phases.

[0150] Furthermore, the terms “approximately,” “basically,” “essentially,” and “about” described above take into account minor variations and may vary in different technologies and within the range of deviations understood by those skilled in the art. For example, when used in conjunction with an event or situation, these terms can refer to a situation where the event or situation occurred precisely or where the event or situation occurred very approximately.

[0151] Embodiments for forming semiconductor structures can be provided. The semiconductor structure may include a gate structure surrounding a nanostructure. Furthermore, dielectric features may be formed to divide the gate structure into multiple portions. A metal layer may be formed over some portions of the gate structure, while other portions of the gate structure remain electrically disconnected. By forming a gate structure with multiple portions initially separated by dielectric features, and then reconnecting some of these portions via metal layers, the spacing in the device can be reduced and performance can be improved.

[0152] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a substrate and a nanostructure formed on the substrate. The semiconductor structure also includes a gate structure surrounding the nanostructure and a first dielectric feature dividing the gate structure into a first portion and a second portion. The semiconductor structure also includes a metal layer formed on the gate structure. Furthermore, the top surface of the first portion of the gate structure, the top surface of the second portion of the gate structure, and the top surface of the first dielectric feature are covered by the metal layer.

[0153] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a substrate and a first fin substrate structure projecting relative to the substrate. The semiconductor structure also includes a first nanostructure formed on the first fin substrate structure and a gate structure including a first portion, a second portion, and a third portion located on the substrate. Furthermore, the first portion of the gate structure surrounds the first nanostructure. The semiconductor structure also includes a first dielectric feature sandwiched between the first and second portions of the gate structure, and a second dielectric feature sandwiched between the first and third portions of the gate structure. The semiconductor structure also includes a metal layer formed on the gate structure and a dielectric layer formed on the metal layer and separating the metal layer into the first and second portions. Furthermore, the first portion of the metal layer extends continuously from the first portion of the gate structure to the second portion of the gate structure.

[0154] In some embodiments, a method for manufacturing a semiconductor structure is provided. The method includes: alternately stacking a first semiconductor material layer and a second semiconductor material layer to form a semiconductor stack on a substrate; and patterning the semiconductor stack to form a fin structure. The method further includes: forming a first dielectric feature on a first side of the fin structure; and removing the first semiconductor material layer of the fin structure to form a nanostructure. The method also includes: forming a gate structure surrounding the nanostructure and covering the first dielectric feature; and removing a portion of the gate structure to expose the first dielectric feature. The method further includes: forming a metal layer covering the gate structure and the first dielectric feature; and forming an opening in the metal layer to expose a top surface of the first dielectric feature. Finally, the method includes: forming a dielectric layer on the metal layer and in the opening of the metal layer.

[0155] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0156] Example 1. A semiconductor structure comprising:

[0157] Substrate;

[0158] Nanostructures formed on the substrate;

[0159] A gate structure, the gate structure surrounding the nanostructure;

[0160] A first dielectric feature, wherein the first dielectric feature divides the gate structure into a first portion and a second portion; and

[0161] A metal layer is formed on the gate structure.

[0162] The top surface of the first portion of the gate structure, the top surface of the second portion of the gate structure, and the top surface of the first dielectric feature are covered by the metal layer.

[0163] Example 2. The semiconductor structure according to Example 1, wherein the first dielectric feature includes:

[0164] The bottom part; and

[0165] The upper portion is formed above the bottom portion.

[0166] The upper portion and the bottom portion of the first dielectric feature are made of different dielectric materials.

[0167] Example 3. The semiconductor structure according to Example 2, wherein the interface between the upper portion and the bottom portion of the first dielectric feature is higher than the bottom surface of the uppermost nanostructure in the nanostructure.

[0168] Example 4. The semiconductor structure according to Example 1 further includes:

[0169] A second dielectric feature, wherein the second dielectric feature is formed adjacent to the nanostructure; and

[0170] A dielectric layer is formed on the metal layer.

[0171] The first dielectric feature and the second dielectric feature are formed on opposite sides of the nanostructure, and the dielectric layer is in direct contact with the top surface of the second dielectric feature.

[0172] Example 5. The semiconductor structure according to Example 4, wherein the dielectric layer is in direct contact with a portion of the gate structure.

[0173] Example 6. The semiconductor structure according to Example 4, wherein the dielectric layer has an extension between the gate structure and the second dielectric feature.

[0174] Example 7. The semiconductor structure according to Example 4, wherein the second dielectric feature is partially covered by the metal layer.

[0175] Example 8. A semiconductor structure comprising:

[0176] Substrate;

[0177] A first fin substrate structure, the first fin substrate structure protruding relative to the substrate;

[0178] A first nanostructure, wherein the first nanostructure is formed on the first fin substrate structure;

[0179] A gate structure comprising a first portion, a second portion, and a third portion located on the substrate, wherein the first portion of the gate structure surrounds the first nanostructure;

[0180] A first dielectric feature, the first dielectric feature being sandwiched between a first portion and a second portion of the gate structure;

[0181] A second dielectric feature, which is sandwiched between the first and third portions of the gate structure;

[0182] A metal layer formed on the gate structure; and

[0183] A dielectric layer is formed on the metal layer, dividing the metal layer into a first portion and a second portion.

[0184] The first portion of the metal layer extends continuously from the first portion of the gate structure to the second portion of the gate structure.

[0185] Example 9. The semiconductor structure according to Example 8, wherein a second portion of the metal layer covers a third portion of the gate structure.

[0186] Example 10. The semiconductor structure according to Example 8, wherein the top surface of the first dielectric feature is substantially flush with the top surface of the second dielectric feature.

[0187] Example 11. The semiconductor structure according to Example 10, wherein the top surface of the first dielectric feature is substantially flush with the top surface of the gate structure.

[0188] Example 12. The semiconductor structure according to Example 8 further includes:

[0189] A gate spacer is formed on the sidewall of the gate structure and covers the first dielectric feature and the second dielectric feature.

[0190] Example 13. The semiconductor structure according to Example 8 further includes:

[0191] A second fin substrate structure and a third fin substrate structure, the second fin substrate structure and the third fin substrate structure protruding relative to the substrate; and

[0192] A second nanostructure and a third nanostructure, wherein the second nanostructure is formed on the second fin substrate structure and the third nanostructure is formed on the third fin substrate structure;

[0193] The second portion of the gate structure surrounds the second nanostructure, and the third portion of the gate structure surrounds the third nanostructure.

[0194] Example 14. The semiconductor structure according to Example 13 further includes:

[0195] A first source / drain structure is connected to the first nanostructure;

[0196] A second source / drain structure, wherein the second source / drain structure is connected to the second nanostructure; and

[0197] The first dielectric feature is located between the first source / drain structure and the second source / drain structure.

[0198] Example 15. A method for manufacturing a semiconductor structure, comprising:

[0199] Alternately stacking a first semiconductor material layer and a second semiconductor material layer to form a semiconductor stack on a substrate;

[0200] The semiconductor stack is patterned to form a fin structure;

[0201] A first dielectric feature is formed on the first side of the fin structure;

[0202] Remove the first semiconductor material layer of the fin structure to form a nanostructure;

[0203] A gate structure is formed around the nanostructure and covering the first dielectric feature;

[0204] Remove a portion of the gate structure to expose the first dielectric feature;

[0205] A metal layer is formed covering the gate structure and the first dielectric feature;

[0206] An opening is formed in the metal layer to expose the top surface of the first dielectric feature; and

[0207] A dielectric layer is formed on top of the metal layer and in the openings of the metal layer.

[0208] Example 16. A method for manufacturing a semiconductor structure according to Example 15, wherein the first dielectric feature includes a bottom portion and an upper portion, and the upper portion of the first dielectric feature is partially removed before the metal layer is formed.

[0209] Example 17. A method for manufacturing a semiconductor structure according to Example 15, wherein the opening of the metal layer is not aligned with the first dielectric feature.

[0210] Example 18. A method for manufacturing a semiconductor structure according to Example 15, wherein the opening in the metal layer further exposes a portion of the gate structure.

[0211] Example 19. The method for manufacturing a semiconductor structure according to Example 15 further includes:

[0212] A portion of the gate structure is removed through an opening in the metal layer.

[0213] Example 20. The method for manufacturing a semiconductor structure according to Example 15 further includes:

[0214] A second dielectric feature is formed on the second side of the fin structure.

[0215] The second dielectric feature passes through the gate structure and is separated from the dielectric layer by the metal layer.

Claims

1. A semiconductor structure, comprising: Substrate; Nanostructures formed on the substrate; A gate structure, the gate structure surrounding the nanostructure; A first dielectric feature, which divides the gate structure into a first portion and a second portion, wherein the first dielectric feature includes: a bottom portion; and an upper portion formed on the bottom portion, wherein the upper portion and the bottom portion of the first dielectric feature are made of different dielectric materials; A metal layer formed on the gate structure; and A dielectric layer is formed on the metal layer, dividing the metal layer into a first portion and a second portion. The top surface of the first portion of the gate structure, the top surface of the second portion of the gate structure, and the top surface of the first dielectric feature are covered by the metal layer. The first portion of the metal layer extends continuously from the first portion of the gate structure to the second portion of the gate structure.

2. The semiconductor structure according to claim 1, wherein, The interface between the upper portion and the bottom portion of the first dielectric feature is higher than the bottom surface of the uppermost nanostructure in the nanostructure.

3. The semiconductor structure according to claim 1, further comprising: A second dielectric feature, wherein the second dielectric feature is formed adjacent to the nanostructure. The first dielectric feature and the second dielectric feature are formed on opposite sides of the nanostructure, and the dielectric layer is in direct contact with the top surface of the second dielectric feature.

4. The semiconductor structure according to claim 3, wherein, The dielectric layer is in direct contact with a portion of the gate structure.

5. The semiconductor structure according to claim 3, wherein, The dielectric layer has an extension between the gate structure and the second dielectric feature.

6. The semiconductor structure according to claim 3, wherein, The second dielectric feature is partially covered by the metal layer.

7. A semiconductor structure comprising: Substrate; A first fin substrate structure, the first fin substrate structure protruding relative to the substrate; A first nanostructure, wherein the first nanostructure is formed on the first fin substrate structure; A gate structure comprising a first portion, a second portion, and a third portion located on the substrate, wherein the first portion of the gate structure surrounds the first nanostructure; A first dielectric feature, sandwiched between a first portion and a second portion of the gate structure, wherein the first dielectric feature includes: a bottom portion; and an upper portion formed on top of the bottom portion, wherein the upper portion and the bottom portion of the first dielectric feature are made of different dielectric materials; A second dielectric feature, which is sandwiched between the first and third portions of the gate structure; A metal layer formed on the gate structure; and A dielectric layer is formed on the metal layer, dividing the metal layer into a first portion and a second portion. The first portion of the metal layer extends continuously from the first portion of the gate structure to the second portion of the gate structure.

8. The semiconductor structure according to claim 7, wherein, The second portion of the metal layer covers the third portion of the gate structure.

9. The semiconductor structure according to claim 7, wherein, The top surface of the first dielectric feature is substantially flush with the top surface of the second dielectric feature.

10. The semiconductor structure according to claim 9, wherein, The top surface of the first dielectric feature is substantially flush with the top surface of the gate structure.

11. The semiconductor structure according to claim 7, further comprising: A gate spacer is formed on the sidewall of the gate structure and covers the first dielectric feature and the second dielectric feature.

12. The semiconductor structure according to claim 7, further comprising: A second fin base structure and a third fin base structure, the second fin base structure and the third fin base structure protruding relative to the substrate; as well as A second nanostructure and a third nanostructure, wherein the second nanostructure is formed on the second fin substrate structure and the third nanostructure is formed on the third fin substrate structure; The second portion of the gate structure surrounds the second nanostructure, and the third portion of the gate structure surrounds the third nanostructure.

13. The semiconductor structure according to claim 12, further comprising: A first source / drain structure is connected to the first nanostructure; The second source / drain structure is connected to the second nanostructure; as well as The first dielectric feature is located between the first source / drain structure and the second source / drain structure.

14. A method for manufacturing a semiconductor structure, comprising: Alternately stacking a first semiconductor material layer and a second semiconductor material layer to form a semiconductor stack on a substrate; The semiconductor stack is patterned to form a fin structure; A first dielectric feature is formed on the first side of the fin structure; Remove the first semiconductor material layer of the fin structure to form a nanostructure; A gate structure is formed around the nanostructure and covering the first dielectric feature; Remove a portion of the gate structure to expose the first dielectric feature; A metal layer is formed covering the gate structure and the first dielectric feature; An opening is formed in the metal layer to expose the top surface of the first dielectric feature; as well as A dielectric layer is formed on top of the metal layer and in the openings of the metal layer. The first dielectric feature includes a bottom portion and an upper portion, and the upper portion of the first dielectric feature is partially removed before the metal layer is formed.

15. The method for manufacturing a semiconductor structure according to claim 14, wherein, The opening in the metal layer is not aligned with the first dielectric feature.

16. The method for manufacturing a semiconductor structure according to claim 14, wherein, The opening in the metal layer also exposes a portion of the gate structure.

17. The method for manufacturing a semiconductor structure according to claim 14, further comprising: A portion of the gate structure is removed through an opening in the metal layer.

18. The method for manufacturing a semiconductor structure according to claim 14, further comprising: A second dielectric feature is formed on the second side of the fin structure. The second dielectric feature passes through the gate structure and is separated from the dielectric layer by the metal layer.

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