Integrated wafer and method of forming the same

Abstract

An integrated wafer and a method for forming the same are disclosed. In some embodiments, this disclosure relates to an integrated wafer (IC), including a substrate, a floating gate electrode disposed above the substrate, a contact etch stop layer (CESL) structure disposed above the floating gate electrode, and an insulating stack separating the floating gate electrode from the CESL structure. The insulating stack includes a first resistive protective layer disposed above the floating gate electrode, a second resistive protective layer disposed above the first resistive protective layer, and an insulating layer separating the first resistive protective layer from the second resistive protective layer.

Description

Technical Field

[0001] This disclosure relates to an integrated wafer and a method for forming the same. Background Technology

[0002] Many modern electronic devices include non-volatile memory (NVMemory). NVMemory is electronic memory that can store data even when power is off. Various types of NVMemory can have relatively simple structures and are compatible with complementary metal-oxide-semiconductor (CMOS) logic manufacturing processes. Summary of the Invention

[0003] In some embodiments, this disclosure relates to an integrated chip (IC) comprising a substrate, a floating gate electrode disposed above the substrate, a contact etch stop layer (CESL) structure disposed above the floating gate electrode, and an insulating stack separating the floating gate electrode from the CESL structure. The insulating stack includes a first resistive protective layer disposed above the floating gate electrode, a second resistive protective layer disposed above the first resistive protective layer, and an insulating layer separating the first resistive protective layer from the second resistive protective layer.

[0004] In other embodiments, this disclosure relates to a method for forming an integrated chip (IC), including forming a floating gate electrode and a select gate electrode over a substrate, forming an insulating stack over the floating gate electrode and the select gate electrode, the insulating stack including a first resistive protective layer, a second resistive protective layer disposed over the first resistive protective layer, and an insulating layer separating the first resistive protective layer and the second resistive protective layer, removing a portion of the insulating stack to expose the select gate electrode, and forming a contact etch stop layer (CESL) structure over the insulating stack and the select gate electrode.

[0005] In other embodiments, this disclosure relates to an integrated chip (IC) comprising a substrate, a floating gate electrode disposed above the substrate, a first resistive protective layer having a first thickness disposed above the floating gate electrode, a contact etch stop layer (CESL) structure disposed above the floating gate electrode, wherein the CESL structure has a second thickness less than the first thickness, a second resistive protective layer having a first thickness disposed between the CESL structure and the first resistive protective layer, and an insulating layer separating the first resistive protective layer and the second resistive protective layer. Attached Figure Description

[0006] The state of this disclosure is in relation to the accompanying documents. Figure 1 The best way to understand this text is by referring to the detailed description below. Note that, according to industry standards, the features are not drawn to scale. In practice, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 Cross-sectional views of some embodiments of an integrated chip (IC) are shown, which includes a floating gate transistor having an insulating stack separating the floating gate electrode from the contact etchstop layer (CESL) structure;

[0008] Figures 2A to 2B Schematic diagrams and top views of some embodiments of a memory cell are shown, the memory cell including a floating gate electrode and an insulating stack covering the floating gate electrode and a capacitor;

[0009] Figure 3 The diagram shows the section intercepted along line A-A'. Figure 2B Cross-sectional views of some embodiments of memory cells;

[0010] Figure 4 The cut-off line along line B-B' is shown. Figure 2B A cross-sectional view of a memory cell;

[0011] Figure 5 A graphical representation of IC data storage is shown, which includes an insulating stack that separates the floating gate electrode from the CESL structure;

[0012] Figures 6 to 24 A series of cross-sectional views are shown of some embodiments of a method for forming an IC, which includes a floating gate electrode, a select gate electrode, and an insulating stack separating the floating gate electrode from the CESL structure.

[0013] Figure 25 It shows Figures 6 to 24 Flowcharts of some embodiments of the method described herein.

[0014] [Symbol Explanation]

[0015] 100: Cross-sectional view

[0016] 101: Floating Gate Transistor

[0017] 102:Substrate

[0018] 102a: Part 1 of 102

[0019] Part 2 of 102b:102

[0020] 104: Gate electrode

[0021] 106: Sidewall spacers

[0022] 108: Floating gate dielectric layer

[0023] 110: First inhibitor protective layer

[0024] 110a: First lateral wall

[0025] 110b: Second lateral wall

[0026] 110c: Third lateral wall

[0027] 110s: Laterally extended surface

[0028] 112: Insulation layer

[0029] 112a: First lateral wall

[0030] 112b: Second lateral wall

[0031] 114: Second inhibitor protective layer

[0032] 114a: First lateral wall

[0033] 114b: Second lateral wall

[0034] 116: Insulating Stack

[0035] 118a: Lower oxide layer

[0036] 118b: Upper oxide layer

[0037] 120a: Lower nitride layer

[0038] 120b: Upper nitride layer

[0039] 122: CESL Structure

[0040] 124: Silicide layer

[0041] 126: Doped region

[0042] 126c: Common doped region

[0043] 128: Dielectric Structure

[0044] 200A: Schematic Diagram

[0045] 200B: Top View

[0046] 201: Select Gate Transistor

[0047] 202: Select gate electrode

[0048] 204: Isolation Structure

[0049] 206: Contact

[0050] 206a: First contact point

[0051] 206b: Second contact

[0052] 206c: Third contact

[0053] 206d: Fourth contact

[0054] 208: Capacitor

[0055] 208a: Top capacitor plate

[0056] 208b: Bottom capacitor plate

[0057] 210: Coupled segment

[0058] 214: First Direction

[0059] 216: Second Direction

[0060] 300: Cross-sectional view

[0061] 302: Sidewall spacers

[0062] 304: Selected gate dielectric layer

[0063] 306: Bulk Semiconductor Layer

[0064] 308: Doped Buried Layer

[0065] 310: Doped Well Zone

[0066] 400: Cross-sectional view

[0067] 402: Doped capacitor region

[0068] 404: Capacitor dielectric layer

[0069] 406: Sidewall spacers

[0070] 500: Graphical representation of IC data storage

[0071] 502: Curve

[0072] 504: Curve

[0073] 600: Cross-sectional view

[0074] 700: Cross-sectional view

[0075] 702: Gate Dielectric Structure

[0076] 704: Gate Electrode Structure

[0077] 800: Cross-sectional view

[0078] 900: Cross-sectional view

[0079] 1000: Cross-sectional view

[0080] 1100: Cross-sectional view

[0081] 1200: Cross-sectional view

[0082] 1300: Cross-sectional view

[0083] 1302: First photoresist structure

[0084] 1400: Cross-sectional view

[0085] 1500: Cross-sectional view

[0086] 1600: Cross-sectional view

[0087] 1602: Second photoresist structure

[0088] 1700: Cross-sectional view

[0089] 1800: Cross-sectional view

[0090] 1900: Cross-sectional view

[0091] 2000: Cross-sectional view

[0092] 2100: Cross-sectional view

[0093] 2200: Cross-sectional view

[0094] 2300: Cross-sectional view

[0095] 2400: Cross-sectional view

[0096] 2500: Process

[0097] 2502~2522: Operation

[0098] A-A': line

[0099] B-B': line

[0100] BL: Bitline

[0101] CGL: Control gate line

[0102] FG: Floating gate electrode

[0103] SG: Select gate electrode

[0104] SGL: Select Gate Line

[0105] SL: Source Line

[0106] T1: First thickness

[0107] T2: Second thickness

[0108] T3: Third Thickness

[0109] T4: Fourth Thickness

[0110] T5: Fifth Thickness

[0111] T6: Sixth Thickness

[0112] T7: Seventh Thickness

[0113] T8: Eighth Thickness

[0114] T9: Ninth Thickness Detailed Implementation

[0115] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0116] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted similarly accordingly.

[0117] Contact etch stop layer (CESL) structures are commonly used in non-volatile memory devices to induce tensile strain in the channel regions of the memory device. In doing so, CESL structures enhance carrier mobility in non-volatile memory and significantly contribute to improving the performance of these memory devices.

[0118] Some non-volatile memory devices may include a floating gate electrode disposed above a substrate, a resist protective layer disposed above the floating gate electrode, and a CESL structure disposed above the resist protective layer. However, depending on the growth conditions of the CESL structure, the CESL structure may simultaneously possess both positive and negative defect charges. At high temperatures, with the electric field from the floating gate electrode, the defect charges within the CESL structure can diffuse according to the electric field. This can lead to the formation of dipoles between the defect charges within the CESL structure and the charges stored in the floating gate electrode. Therefore, some non-volatile memory devices may exhibit unintended capacitive effects on the resist protective layer. This unintended capacitive effect can lead to a decrease in the data retention capability of the non-volatile memory device.

[0119] To avoid unintended capacitance effects and consequent data retention degradation, some non-volatile memory devices incorporate a CESL structure with nitrogen-rich silicon nitride (SiN), which has fewer defect charges, thus reducing the impact on data retention. However, this approach negatively affects the parameters of the logic device, leading to other performance issues. Alternatively, a portion of the CESL structure with a floating gate electrode can be removed to avoid unintended capacitance effects and consequent data retention degradation. However, this approach has a very small process window, making both excessively large and excessively small etches highly risky, resulting in metal contamination in the machining tool.

[0120] In view of the above, this disclosure relates to a non-volatile memory device comprising an insulating stack separating a floating gate electrode from a CESL structure. The insulating stack includes a first resistive protective layer disposed above the floating gate electrode, a second resistive protective layer disposed above the first resistive protective layer, and an insulating layer separating the first and second resistive protective layers. By separating the floating gate electrode from the CESL structure using a multi-layer insulating stack, the distance between the CESL structure and the floating gate electrode is increased. Therefore, unintended capacitance effects in the non-volatile memory device are reduced, thereby reducing data retention degradation. This is achieved without the risk of metal contamination and is a manufacturing-friendly method.

[0121] Figure 1A cross-sectional view 100 is shown of some embodiments of an IC including a floating gate transistor 101, which includes an insulating stack 116 separating a floating gate electrode (FG) 104 from a CESL structure 122. The floating gate electrode 104 is disposed above a substrate 102. Sidewall spacers 106 are disposed on opposite sidewalls of the floating gate electrode 104, and a floating gate dielectric layer 108 separates the floating gate electrode 104 from the substrate 102. Doped regions 126 of the substrate 102 are disposed on opposite sides of the floating gate electrode 104 and correspond to the source / drain regions of the floating gate transistor 101. In some embodiments, the doped regions 126 have a first doping type (e.g., n-type). One or more silicide layers 124 are disposed along the top surface of the doped regions 126 and have ohmic connections with the source / drain regions. A dielectric structure 128 is disposed above the CESL structure 122.

[0122] The CESL structure 122 includes multiple oxide layers and multiple nitride layers, alternately stacked above the floating gate electrode 104 and the substrate 102. In some embodiments, there are no more than two oxide layers. In some embodiments, there are no more than two nitride layers. For example, in the illustrated embodiment, the CESL structure 122 includes a lower oxide layer 118a, a lower nitride layer 120a above the lower oxide layer 118a, an upper oxide layer 118b above the lower nitride layer 120a, and an upper nitride layer 120b above the upper oxide layer 118b. In some embodiments, the CESL structure 122 is conformally disposed above the insulating stack 116. In some embodiments, the CESL structure 122 is subjected to high stress and provides tensile stress in the channel region of the substrate 102 to improve the saturation drive current.

[0123] An insulating stack 116 separates the CESL structure 122 from the floating gate electrode 104. The insulating stack 116 includes a first resistive protective layer 110 disposed above the floating gate electrode 104, a second resistive protective layer 114 disposed above the first resistive protective layer 110, and an insulating layer 112 separating the first resistive protective layer 110 and the second resistive protective layer 114. The first resistive protective layer 110 extends from above the floating gate electrode 104 to the substrate 102 along the curved surface of the sidewall spacer 106. In some embodiments, the first resistive protective layer 110 directly covers the doped region 126 of the substrate 102.

[0124] The first resistive protective layer 110 includes a first outer sidewall 110a and a second outer sidewall 110b, the insulating layer 112 includes a first outer sidewall 112a and a second outer sidewall 112b, and the second resistive protective layer 114 includes a first outer sidewall 114a and a second outer sidewall 114b. In some embodiments, the first outer sidewall 114a or the second outer sidewall 114b of the second resistive protective layer 114 extends below the top surface of the insulating layer 112. In some embodiments, the first outer sidewall 112a and the second outer sidewall 112b of the insulating layer 112 are aligned with the first outer sidewall 114a and the second outer sidewall 114b of the second resistive protective layer 114 along substantially vertical axes, respectively. In some embodiments, the first resistive protective layer 110 further includes a third outer sidewall 110c, which generally faces the same direction as the second outer sidewall 110b. In a further embodiment, the second outer sidewall 110b and the third outer sidewall 110c are connected by a laterally extending surface 110s of the first resistive protective layer 110.

[0125] The insulating stack 116 has a first thickness T1 measured above the floating gate electrode 104. The CESL structure 122 has a second thickness T2 measured above the floating gate electrode 104. In some embodiments, the first thickness T1 is greater than the second thickness T2. In some embodiments, the first thickness T1 may range from about two to about four times the second thickness T2, from about three to about four times the second thickness T2, or some other suitable value.

[0126] Because the floating gate electrode 104 is separated from the CESL structure 122 by an insulating stack 116 comprising multiple layers, there is a sufficient distance (e.g., a first thickness T1) between the CESL structure 122 and the floating gate electrode 104 to ensure that the unintended capacitive effect between the CESL structure 122 and the floating gate electrode 104 is reduced compared to an IC without an insulating stack. Therefore, data retention degradation of the device is reduced.

[0127] In some embodiments, the first thickness T1 may range from about 1100 angstroms to about 3200 angstroms, from about 1875 angstroms to about 3200 angstroms, from about 1100 angstroms to about 1875 angstroms, or some other suitable value. In some embodiments, if the first thickness T1 is too large (e.g., greater than about 3200 angstroms), a portion of the insulating stack 116 may be difficult to remove. In some embodiments, if the first thickness T1 is too small (e.g., less than about 1100 angstroms), the unintended capacitive effect between the CESL structure 122 and the floating gate electrode 104 may not be sufficiently reduced compared to an IC without an insulating stack. In some embodiments, the second thickness T2 may range from about 500 angstroms to about 900 angstroms, from about 500 angstroms to about 750 angstroms, from about 750 angstroms to about 900 angstroms, or some other suitable value.

[0128] In some embodiments, substrate 102 may have a second doping type (e.g., p-type) opposite to the first doping type. In some embodiments, substrate 102 may be or may comprise, for example, a single-crystal silicon substrate, a silicon-on-insulator (SOI) substrate, a polymer substrate, silicon germanium, a group III-V material, a group II-VI material, some other suitable semiconductor material, or any combination thereof. Group III-V material may be, for example, gallium arsenide (e.g., GaAs), gallium indium arsenide (e.g., GaAsIn), some other suitable group III-V material, or any combination thereof. Group II-VI material may be or may comprise, for example, zinc oxide (e.g., ZnO), magnesium oxide (e.g., MgO), gadolinium oxide (e.g., GdO), some other suitable group II-VI material, or any combination thereof. In some embodiments, floating gate electrode 104 may be or may comprise, for example, doped polycrystalline silicon or some other suitable material (multiple). In some embodiments, sidewall spacers 106 may be or may comprise, for example, silicon nitride, silicon dioxide, some other suitable dielectric material, or a combination thereof.

[0129] In some embodiments, the levitated gate dielectric layer 108 may include, for example, a high-k dielectric material, such as hafnium oxide (HfO) or tantalum oxide (Ta). x O y Hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), and aluminum oxide (Al) x O=), zirconium oxide (ZrO), or the like. In some embodiments, the first resistive protective layer 110, the second resistive protective layer 114, the lower oxide layer 118a, and the upper oxide layer 118b may or may contain, for example, silicon dioxide, silicon oxynitride, some other suitable oxides (multiple), or the like. In some embodiments, the insulating layer 112, the lower nitride layer 120a, and the upper nitride layer 120b may or may contain, for example, silicon nitride, some other suitable nitrides (multiple), or the like.

[0130] In some embodiments, insulating layer 112 may have a refractive index less than that of lower nitride layer 120a or upper nitride layer 120b. In some embodiments, insulating layer 112 may comprise a nitrogen-rich material more than that of lower nitride layer 120a or upper nitride layer 120b. In some embodiments, insulating layer 112 may have a refractive index range from about 1.6 to about 1.9, from about 1.6 to about 1.75, from about 1.75 to about 1.9, or some other suitable value. In some embodiments, if the refractive index of insulating layer 112 is too large (e.g., greater than 1.9), insulating layer 112 may contain charged defects, which may cause the formation of dipoles between the defect charges and the charges stored in the floating gate electrode 104, thus causing an unintended capacitive effect on the first resistive protective layer 110. In some embodiments, if the refractive index of insulating layer 112 is too small (e.g., less than 1.6), the electrical parameters of the device may deviate in an undesirable manner.

[0131] In some embodiments, the plurality of silicide layers 124 may comprise, for example, metal silicides (e.g., cobalt silicide, titanium silicide, nickel silicide, or the like) or some other suitable materials (multiple types). In some embodiments, the dielectric structure 128 may comprise, for example, nitrides (e.g., silicon nitride, silicon oxynitride), carbides (e.g., silicon carbide), oxides (e.g., silicon oxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), low-k oxides (e.g., carbon-doped oxides, SiCOH), or the like.

[0132] Figures 2A to 2B Schematic diagrams 200A and top views 200B respectively illustrate some embodiments of a memory cell including a floating gate transistor 101, a select gate transistor 201, and a capacitor 208, which are operatively coupled to store one or more data bits. Figures 3 to 4 As shown, it displays Figure 2B In some embodiments of the memory cell cross-sectional view, an insulating stack 116 covers the floating gate electrode 104 of the floating gate transistor 101 and the top capacitor plate 208a of the capacitor 208 to limit capacitive effects and improve data retention of the memory cell.

[0133] about Figure 2AIn schematic diagram 200A, the first terminal of the select gate transistor 201 is coupled to the source line SL. The first terminal of the floating gate transistor 101 is coupled to the bit line BL. The second terminal of the select gate transistor 201 is shared with the second terminal of the floating gate transistor 101. The select gate electrode (SG) 202 of the select gate transistor 201 is coupled to the select gate line SGL. The floating gate electrode (FG) 104 of the floating gate transistor 101 is coupled to the capacitor 208 through the coupling segment 210. In some embodiments, the coupling segment 210 couples the floating gate electrode 104 to the top capacitor plate 208a of the capacitor 208, and the bottom capacitor plate 208b of the capacitor is coupled to the control gate line CGL.

[0134] In some embodiments, schematic diagram 200A represents a single multi-time programmable (MTP) memory cell. In further embodiments, the IC may include multiple similar memory cells configured in multiple columns and multiple rows. In some embodiments, the memory cell may be a two-transistor-one-capacitor (2T1C) configuration. During operation of the memory cell, electrons stored in capacitor 208 (and / or floating gate electrode 104) are used to represent data bits. For example, charged floating gate electrode 104 may represent binary 0, and uncharged floating gate electrode 104 may represent binary 1. In alternative embodiments, charged floating gate electrode 104 may represent binary 1, and uncharged floating gate electrode 104 may represent binary 0. In some embodiments, charged floating gate electrode 104 causes the floating gate transistor 101 to have a higher threshold voltage than uncharged floating gate electrode 104.

[0135] In some embodiments, to program a data bit to a memory cell, a positive bias is applied to the control gate line CGL and a positive bias is applied to the bit line BL. In doing so, electrons are injected (e.g., via hot electron injection) into the floating gate electrode 104. In some embodiments, the bias applied to the control gate line CGL is greater than the bias applied to the bit line BL. In some embodiments, the capacitor 208 is in accumulation operation during the programming of the bit data.

[0136] In some embodiments, to erase data bits from a memory cell, a negative bias is applied to the control gate line CGL and a positive bias is applied to the bit line BL, allowing the source line SL to be electrically levitated. In doing so, holes are injected (e.g., via hot hole injection) into the levitated gate electrode 104. Thus, the holes are locally trapped, and some of these holes recombine with electrons in the levitated gate electrode 104 to remove charge. In some embodiments, capacitor 208 operates in reverse when erasing a single data bit.

[0137] In some embodiments, in order to read data bits from a memory cell, appropriate bias conditions are applied so that the data state of the memory cell (e.g., a threshold voltage) can be accessed by measuring the current on the bit line BL. In some embodiments, the select gate electrode 202 and the select gate line SGL allow for additional control over the operation of the memory cell and prevent eventual over-erasure failures in the memory array.

[0138] about Figure 2B A top view 200B, corresponding to schematic diagram 200A, shows a capacitor 208, a select gate electrode 202, and a floating gate electrode 104 covering a substrate 102. Individual portions 102a and 102b of the substrate 102 are separated in a first direction 214 by an isolation structure 204. The floating gate electrode 104 covers the first portion 102a of the substrate 102, and the capacitor 208 covers the second portion 102b of the substrate 102. In some embodiments, the isolation structure 204 may be a shallow trench isolation (STI) structure. The floating gate electrode 104 is connected to the top capacitor plate 208a of the capacitor 208 via a coupling segment 210. The coupling segment 210 extends in the first direction 214 from the first portion 102a of the substrate 102 above the isolation structure 204 to the second portion 102b of the substrate 102. In some embodiments, the top capacitor plate 208a of the capacitor 208 extends in a second direction 216 orthogonal to the first direction 214.

[0139] In some embodiments, a first portion 102a of substrate 102 includes a doped region 126 having a first doping type (e.g., n-type) on opposite sides of the select gate electrode 202 and the floating gate electrode 104. In some embodiments, a shared doped region 126c (e.g., a shared source / drain region) is disposed between and shared by the select gate transistor 201 and the floating gate transistor 101. The select gate transistor 201 includes the select gate electrode 202 and the doped region 126. The floating gate transistor 101 includes the floating gate electrode 104 and the doped region 126.

[0140] In some embodiments, a second portion 102b of substrate 102 includes a doped region (not shown) having a first doping type on the opposite side of capacitor 208. In some embodiments, the second portion 102b of substrate 102 includes a doped capacitor region (not shown) disposed below the top capacitor plate 208a of capacitor 208, the doped capacitor region having a first doping type that is lighter than the doped region. In some embodiments, the doped capacitor region serves as the bottom capacitor plate of capacitor 208.

[0141] The select gate electrode 202 includes a first portion extending along a first direction 214 from a first portion 102a of the substrate 102 to the isolation structure 204. The select gate electrode 202 further includes a second portion connected to the first portion, the second portion being located at a position covering the isolation structure 204 and extending over the isolation structure 204 in a second direction 216.

[0142] Multiple contacts 206 are disposed above the substrate 102 and the select gate electrode 202. A first contact 206a of the multiple contacts 206 electrically couples the source region of the doped region of the first portion 102a of the substrate 102 to an overlying source line SL. In some embodiments, the source line SL extends in a second direction 216. Second contacts 206b of the multiple contacts 206 are disposed above the drain region of the doped region of the first portion 102a of the substrate 102 and electrically coupled to an overlying bit line BL. In some embodiments, the bit line BL extends in a second direction 216.

[0143] A third contact 206c of the plurality of contacts 206 electrically couples a select gate electrode 202 to an overlying select gate line SGL. In some embodiments, the select gate line SGL extends in a first direction 214. A fourth contact 206d of the plurality of contacts 206 electrically couples one of the doped regions of a second portion 102b of the substrate 102 to an overlying control gate line CGL. In some embodiments, the control gate line CGL extends in the first direction 214.

[0144] In some embodiments, top view 200B represents a single MTP memory cell. In further embodiments, the IC may include multiple similar memory cells configured in multiple columns and multiple rows. In some embodiments, the memory cell may be configured as a 2T1C. In some embodiments, the memory cell may operate as described above. Figure 2A As stated above.

[0145] In some embodiments, the CESL structure (not shown) may extend continuously over the select gate electrode 202, the insulating stack 116, the substrate 102, and the isolation structure 204. In an alternative embodiment, sidewall spacers (not shown) may be disposed along the sidewalls of the select gate electrode 202 and the sidewalls of the floating gate electrode 104.

[0146] In some embodiments, the select gate electrode 202 may comprise, for example, doped polysilicon, a metal, or some other suitable material (multiple). In some embodiments, the isolation structure 204 may comprise, for example, silicon nitride, silicon dioxide, some other suitable dielectric material (multiple), or a combination thereof. In some embodiments, the plurality of contacts 206, source line SL, bit line BL, control gate line CGL, and / or select gate line SGL may comprise, for example, copper, iron, some other suitable conductive material (multiple), or a combination thereof. In some embodiments, the top capacitor plate 208a of the coupling segment 210 and capacitor 208 may comprise, for example, doped polysilicon, a metal, or some other suitable material (multiple).

[0147] Figure 3 A cross-section 300 of some embodiments of an IC is shown, which includes a select gate electrode 202 and an insulating stack 116 separating a floating gate electrode 104 from a CESL structure 122. In some embodiments, cross-section 300 spans... Figure 2B The line A-A' is cut off. The floating gate electrode (FG) 104 and the select gate electrode (SG) 202 are laterally separated from each other and disposed above the substrate 102. Sidewall spacers 106 and 302 are respectively disposed on the opposite sidewalls of the floating gate electrode 104 and the opposite sidewalls of the select gate electrode 202. The floating gate dielectric layer 108 separates the floating gate electrode 104 from the substrate 102. The select gate dielectric layer 304 separates the select gate electrode 202 from the substrate 102.

[0148] Multiple silicide layers 124 are disposed along the top surface of the substrate 102 and the top surface of the select gate electrode 202. A dielectric structure 128 is disposed above the CESL structure 122. Doped regions 126 of the substrate 102 are respectively disposed on opposite sides of the floating gate electrode 104 and the select gate electrode 202. The floating gate electrode 104 and the select gate electrode 202 share a common doped region 126c of the substrate 102. In some embodiments, the doped region 126 has a first doping type (e.g., n-type). The select gate transistor 201 includes the select gate electrode 202 and the doped region 126. The floating gate transistor 101 includes the floating gate electrode 104 and the doped region 126.

[0149] In some embodiments, a plurality of silicide layers 124 are disposed on a doped region 126 of substrate 102. In some embodiments, the plurality of silicide layers 124 directly contact the CESL structure 122. A plurality of contacts 206 extend vertically through the dielectric structure 128 and the CESL structure 122 to contact the plurality of silicide layers 124 disposed on the doped region 126. In some embodiments, this provides an electrical connection between the doped region 126 and the overlying source / bit line (not shown).

[0150] In some embodiments, the substrate 102 includes a doped well region 310 having a second doping type (e.g., p-type) opposite to the first doping type. In a further embodiment, a doped region 126 of the substrate 102 is disposed in the doped well region 310. In some embodiments, a bulk semiconductor layer 306 having the second doping type is disposed beneath the doped well region 310. In some embodiments, a doped buried layer 308 is disposed beneath the bulk semiconductor layer 306. In a further embodiment, the doped buried layer 308 has the first doping type.

[0151] The CESL structure 122 includes multiple oxide layers and multiple nitride layers, alternately stacked over the floating gate electrode 104 and the substrate 102. In some embodiments, there are no more than two oxide layers. In some embodiments, there are no more than two nitride layers. For example, in the illustrated embodiment, the CESL structure 122 includes a lower oxide layer 118a, a lower nitride layer 120a above the lower oxide layer 118a, an upper oxide layer 118b above the lower nitride layer 120a, and an upper nitride layer 120b above the upper oxide layer 118b. In some embodiments, the CESL structure 122 is conformally disposed on the insulating stack 116. In some embodiments, the CESL structure 122 is subjected to high stress and provides tensile stress in the channel region of the substrate 102 to improve the saturation drive current. The CESL structure 122 extends continuously over the floating gate electrode 104 and the select gate electrode 202.

[0152] The insulating stack 116 separates the CESL structure 122 from the floating gate electrode 104. The insulating stack 116 includes a first resistive protective layer 110 disposed above the floating gate electrode 104, a second resistive protective layer 114 disposed above the first resistive protective layer 110, and an insulating layer 112 separating the first resistive protective layer 110 and the second resistive protective layer 114. The first resistive protective layer 110 extends from the floating gate electrode 104 to the substrate 102 along the curved surface of the sidewall spacer 106. In some embodiments, the first resistive protective layer 110 directly covers the doped region 126 of the substrate 102. In some embodiments, the CESL structure 122 laterally separates the select gate electrode 202 from the insulating stack 116.

[0153] The first resistive protective layer 110 includes a first outer sidewall 110a and a second outer sidewall 110b, the insulating layer 112 includes a first outer sidewall 112a and a second outer sidewall 112b, and the second resistive protective layer 114 includes a first outer sidewall 114a and a second outer sidewall 114b. In some embodiments, the first outer sidewall 114a or the second outer sidewall 114b of the second resistive protective layer 114 extends below the upper surface of the insulating layer 112. In some embodiments, the first outer sidewall 112a and the second outer sidewall 112b of the insulating layer 112 are aligned with the first outer sidewall 114a and the second outer sidewall 114b of the second resistive protective layer 114 along substantially vertical axes, respectively. In some embodiments, the first outer sidewall 110a of the first resistive protective layer 110 faces the select gate electrode 202. In some embodiments, the first outer sidewall 110a of the first resistive protective layer 110 extends to a laterally outward position of the first outer sidewall 112a of the insulating layer 112. In some embodiments, the first outermost wall 110a of the first resistive protective layer 110 is the outermost wall of the resistive protective layer 110 and terminates between the edge of the select gate electrode 202 and the nearest adjacent edge of the floating gate electrode 104, without extending above the select gate electrode 202.

[0154] The insulating stack 116 has a first thickness T1 measured above the floating gate electrode 104. The CESL structure 122 has a second thickness T2 measured above the floating gate electrode 104. In some embodiments, the first thickness T1 is greater than the second thickness T2. In some embodiments, the first thickness T1 is large enough to provide sufficient separation between the floating gate electrode 104 and the CESL structure 122.

[0155] Because the floating gate electrode 104 is separated from the CESL structure 122 by an insulating stack 116 comprising multiple layers, there is a sufficient distance (e.g., a first thickness T1) between the CESL structure 122 and the floating gate electrode 104 to ensure that the unintended capacitive effect between the CESL structure 122 and the floating gate electrode 104 is reduced compared to an IC without an insulating stack. Therefore, data retention degradation of the device is reduced.

[0156] Figure 4 A cross-section 400 of some embodiments of an IC is shown, which includes an insulating stack 116 separating a capacitor 208 from a CESL structure 122. In some embodiments, the cross-section 400 spans... Figure 2B The line B-B' is cut off. The capacitor 208 is covered by the substrate 102. In some embodiments, as per [reference to...] Figure 3 The floating gate electrode 104 is connected to the top capacitor plate 208a of the capacitor 208 via the coupling section 210 (see...). Figures 2A to 2BThe doped regions 126 of the substrate 102 are respectively disposed on opposite sides of the top capacitor plate 208a of the capacitor 208. In some embodiments, the doped regions 126 have a first doping type (e.g., n-type). The doped capacitor region 402 of the substrate 102 serves as the bottom capacitor plate 208b of the capacitor 208. In a further embodiment, the doped regions 126 of the substrate 102 are disposed in the doped capacitor region 402. Sidewall spacers 406 are respectively disposed on opposite sidewalls of the top capacitor plate 208a of the capacitor 208. The capacitor dielectric layer 404 separates the top capacitor plate 208a of the capacitor 208 from the substrate 102.

[0157] In some embodiments, the substrate 102 includes a doped well region 310 having a second doping type (e.g., p-type) opposite to the first doping type. In some embodiments, a bulk semiconductor layer 306 having the second doping type is disposed beneath the doped well region 310. In some embodiments, a doped buried layer 308 is disposed beneath the bulk semiconductor layer 306. In a further embodiment, the doped buried layer 308 has the first doping type.

[0158] A dielectric structure 128 is disposed above a CESL structure 122. A plurality of silicide layers 124 are disposed on doped regions 126 of the substrate 102. In some embodiments, the plurality of silicide layers 124 directly contact the CESL structure 122. A contact 206d extends vertically through the dielectric structure 128 and the CESL structure 122 to contact one of the silicide layers 124 disposed on one of the doped regions 126. In some embodiments, this provides an electrical connection between one of the doped regions 126 and an overlying control gate line CGL.

[0159] In some embodiments, the doped capacitor region 402 has the same doping type as the doped region 126 (e.g., a first doping type). In some such embodiments, the doped capacitor region 402 is lightly doped than the doped region 126. In some embodiments, the doped capacitor region 402 is charged by applying a bias voltage to the contact 206d.

[0160] The CESL structure 122 includes multiple oxide layers and multiple nitride layers, alternately stacked above the top capacitor plate 208a and the substrate 102 of the capacitor 208. In some embodiments, the multiple oxide layers comprise no more than two layers. In some embodiments, the multiple nitride layers comprise no more than two layers. For example, in the illustrated embodiment, the CESL structure 122 includes a lower oxide layer 118a, a lower nitride layer 120a above the lower oxide layer 118a, an upper oxide layer 118b above the lower nitride layer 120a, and an upper nitride layer 120b above the upper oxide layer 118b. In some embodiments, the CESL structure 122 is conformally disposed above an insulating stack 116. The insulating stack 116 separates the CESL structure 122 from the floating gate electrode 104. The insulating stack 116 includes a first resistive protective layer 110 disposed above the top capacitor plate 208a of the capacitor 208, a second resistive protective layer 114 disposed above the first resistive protective layer 110, and an insulating layer 112 separating the first resistive protective layer 110 and the second resistive protective layer 114. The first resistive protective layer 110 extends from the top capacitor plate 208a of the capacitor 208 to the doped capacitor region 402 along the curved surface of the sidewall spacer 406. In some embodiments, the first resistive protective layer 110 directly covers the doped region 126.

[0161] The insulating stack 116 has a first thickness T1 measured above the top capacitor plate 208a of the capacitor 208. The CESL structure 122 has a second thickness T2 measured above the top capacitor plate 208a of the capacitor 208. In some embodiments, the first thickness T1 is greater than the second thickness T2. In some embodiments, the first thickness T1 is large enough to provide sufficient separation between the top capacitor plate 208a of the capacitor 208 and the CESL structure 122.

[0162] Figure 5 A graphical representation 500 of an IC data storage is shown, the IC comprising an insulating stack separating the floating gate electrode from the CESL structure. In some embodiments, the IC may be as shown with respect to Figures 2 to 500. Figure 4 Curve 502 represents data retention of a reference IC after a heat treatment process, wherein the reference IC does not contain an insulating stack separating the floating gate electrode from the CESL structure. Curve 504 represents data retention of an IC after a heat treatment process, wherein the IC contains an insulating stack separating the floating gate electrode from the CESL structure. In some embodiments, the heat treatment process may involve baking the IC at a temperature of approximately 250 degrees Celsius for approximately 24 hours.

[0163] Curve 502 has a first minimum read current C1, and curve 504 has a second minimum read current C2 that is greater than the first minimum read current C1. Since curve 502 corresponds to an IC without an insulating stack, after the baking process, the charge within the CESL structure diffuses according to the electric field generated by the floating gate electrode, resulting in an unintended capacitive effect between the floating gate electrode and the CESL structure. Therefore, the charge stored in the floating gate electrode is shielded by the CESL structure, thereby reducing the critical voltage of the memory cell in the programmed state and increasing the critical voltage of the memory cell in the erased state. This reduces the read current on the bit line and the data retention of the memory cell.

[0164] Since curve 504 corresponds to an IC containing an insulating stack, after the baking process, less charge diffuses within the CESL structure due to the electric field generated by the floating gate electrode, resulting in a reduction of the unintended capacitive effect between the floating gate electrode and the CESL structure. Therefore, the decrease in the critical voltage is smaller for memory cells in the programmed state, and the increase in the critical voltage is smaller for memory cells in the erased state. Consequently, read current on the bit lines and data retention in memory cells are improved compared to the reference IC.

[0165] Figures 6 to 24 A series of cross-sectional views 600 to 2400 illustrate some embodiments of a method for forming an IC, which includes a floating gate electrode 104, a select gate electrode 202, and an insulating stack 116 separating the floating gate electrode 104 from the CESL structure 122. In some embodiments, the IC may correspond to Figure 3 The IC described in the document.

[0166] about Figure 6 In a cross-sectional view 600, in some embodiments, a doped buried layer 308 is formed in a substrate 102 by a first doping process. A doped well region 310 is formed in the substrate 102 above the doped buried layer 308 by a second doping process. In some embodiments, the first doping process includes implanting a dopant having a first doping type (e.g., arsenic, phosphorus, or some other suitable n-type dopant) into the substrate 102. In alternative embodiments, the doped buried layer 308 may be formed by an epitaxial growth process. In some embodiments, the second doping process includes implanting a dopant having a second doping type opposite to the first doping type (e.g., boron or some other suitable p-type dopant) into the substrate 102. In some embodiments, a bulk semiconductor layer 306 is a portion of the substrate 102 that has not been doped by the first or second doping process, disposed between the doped buried layer 308 and the doped well region 310. In a further embodiment, the bulk semiconductor layer 306 has a second doping type.

[0167] about Figure 7The cross-sectional view 700 shows a gate dielectric structure 702 formed over a substrate 102. A gate electrode structure 704 is formed over the gate dielectric structure 702. In some embodiments, the gate dielectric structure 702 can be formed by a deposition process, such as, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), or some other suitable deposition process. In some embodiments, the gate electrode structure 704 can be formed by a deposition process (e.g., PVD, CVD, or the like) and / or an electroplating process (e.g., electroplating, electroless plating, or the like).

[0168] The gate dielectric structure 702 is formed to have a third thickness T3. In some embodiments, the third thickness T3 may range from about 100 angstroms to about 150 angstroms, from about 100 angstroms to about 125 angstroms, from about 125 angstroms to about 150 angstroms, or some other suitable value.

[0169] about Figure 8 In the cross-sectional view 800, the gate dielectric structure 702 and the gate electrode structure 704 are patterned by an etching process. The etching process forms a floating gate electrode (FG) 104 covering the floating gate dielectric layer 108 and a select gate electrode (SG) 202 covered by the select gate dielectric layer 304, respectively. In some embodiments, the etching process may include, for example, a wet etching process and / or a dry etching process. In various embodiments, the wet etching process includes exposing portions of the gate dielectric structure 702 and / or the gate electrode structure 704 to a wet etchant (e.g., tetramethylammonium hydroxide (TMAH)). In various embodiments, the dry etching process includes exposing portions of the gate dielectric structure 702 and / or the gate electrode structure 704 to a dry etchant (e.g., chlorine (Cl2), gaseous hydrochloric acid (HCl), or germane gas (GeH4)).

[0170] about Figure 9In a cross-sectional view 900, sidewall spacers 106 are formed on the opposite sidewalls of the floating gate electrode 104, and sidewall spacers 302 are formed on the opposite sidewalls of the select gate electrode 202. A doped region 126 is formed in the substrate 102 through a doping process. In some embodiments, the sidewall spacers 106 and 302 can be formed through a conformal deposition process (e.g., PVD, CVD, or similar) to place a conformal layer, followed by etching back to remove the side portions of the conformal layer, thereby leaving the sidewall spacers 106 and 302. In some embodiments, the doping process includes implanting a dopant having a first doping type (e.g., phosphorus, arsenic, or some other suitable n-type dopant) into the top surface of the substrate 102, such that the sidewall spacers 106 and 302, the select gate electrode 202, and the floating gate electrode 104 act as a shielding structure. In some embodiments, the doped region 126 is formed in a doped well region 310 of the substrate 102. In some embodiments, an annealing process (e.g., rapid thermal annealing or the like) may be performed to activate and / or drive the dopant in the doped region 126. In some embodiments, the floating gate electrode 104 and the select gate electrode 202 share the common doped region 126c.

[0171] about Figure 10 In a cross-sectional view 1000, a first resistive protective layer 110 is formed over the substrate 102, the select gate electrode 202, and the floating gate electrode 104. In some embodiments, the first resistive protective layer 110 is conformally formed over the select gate electrode 202, the floating gate electrode 104, and the sidewall spacers 106 and 302. In some embodiments, the first resistive protective layer 110 can be formed by a deposition process (e.g., PVD, CVD, or the like).

[0172] The first resist protective layer 110 is formed to have a fourth thickness T4. In some embodiments, the fourth thickness T4 may range from about 500 angstroms to about 1,500 angstroms, from about 500 angstroms to about 850 angstroms, from about 850 angstroms to about 1,500 angstroms, or some other suitable value.

[0173] about Figure 11 The cross-sectional view 1100 shows an insulating layer 112 formed over the first resistive protective layer 110. In some embodiments, the insulating layer 112 is conformally formed over the first resistive protective layer 110. In some embodiments, the insulating layer 112 can be formed by a deposition process (e.g., PVD, CVD, or the like).

[0174] The insulating layer 112 is formed to have a fifth thickness T5. In some embodiments, the fifth thickness T5 may range from about 100 angstroms to about 200 angstroms, from about 100 angstroms to about 175 angstroms, from about 175 angstroms to about 200 angstroms, or some other suitable value.

[0175] about Figure 12 In the cross-sectional view 1200, a second resistive protective layer 114 is formed over the insulating layer 112. In some embodiments, the second resistive protective layer 114 is conformally formed over the insulating layer 112. In some embodiments, the second resistive protective layer 114 may be formed by a deposition process (e.g., PVD, CVD, or the like).

[0176] The second resistive protective layer 114 is formed to have a sixth thickness T6. In some embodiments, the sixth thickness T6 may range from about 500 angstroms to about 1500 angstroms, from about 500 angstroms to about 850 angstroms, from about 850 angstroms to about 1500 angstroms, or some other suitable value. In some embodiments, the sixth thickness T6 is equal to the fourth thickness T4.

[0177] A first resistive protective layer 110, an insulating layer 112, and a second resistive protective layer 114 define an insulating stack 116. The insulating stack has a first thickness T1. In some embodiments, the first thickness T1 may range from about 1100 angstroms to about 3200 angstroms, from about 1875 angstroms to about 3200 angstroms, from about 1100 angstroms to about 1875 angstroms, or some other suitable value. Because the multi-layered insulating stack 116 covers the floating gate electrode 104, there is sufficient distance (e.g., the first thickness T1) between the floating gate electrode 104 and the subsequently formed CESL structure to ensure that unintended capacitive effects between the subsequently formed CESL structure and the floating gate electrode 104 are reduced. Therefore, data retention degradation of the device is reduced.

[0178] In some embodiments, if the first thickness T1 is too large (e.g., greater than about 3200 angstroms), a portion of the insulating stack 116 may be too difficult to remove in subsequent steps. In some embodiments, if the first thickness T1 is too small (e.g., less than about 1100 angstroms), the unintended capacitive effect between the subsequently formed CESL structure and the floating gate electrode 104 may not be sufficiently reduced compared to an IC without an insulating stack.

[0179] about Figure 13 In the cross-sectional view 1300, a first photoresist structure 1302 is formed above the insulating stack 116 and the floating gate electrode 104, thereby exposing a portion of the second photoresist protective layer 114. In some embodiments, the first photoresist structure 1302 is laterally separated from the select gate electrode 202. In some embodiments, the first photoresist structure 1302 is a positive photoresist.

[0180] about Figure 14A cross-sectional view 1400 shows an etching process performed to remove the exposed portion of the second resist protective layer 114. In some embodiments, the etching process may include, for example, a wet etching process and / or a dry etching process. In various embodiments, the wet etching process includes exposing the exposed portion of the second resist protective layer 114 to an isotropic wet etchant (e.g., dilute hydrofluoric acid (DHF)). In various embodiments, the dry etching process includes exposing the exposed portion of the second resist protective layer 114 to an anisotropic dry etchant (e.g., chlorine (Cl2), gaseous hydrochloric acid (HCl), or germane gas (GeH4)). The etching process defines outer sidewalls 114a, 114b of the second resist protective layer 114 and exposes a portion of the insulating layer 112. In some embodiments, one of the outer sidewalls 114a, 114b extends below the insulating layer 112.

[0181] about Figure 15 The cross-sectional view 1500 shows an etching process performed to remove the exposed portion of the insulating layer 112. In some embodiments, the etching process may include, for example, a wet etching process. In various embodiments, the wet etching process includes exposing the exposed portion of the second resist protective layer 114 to an isotropic wet etchant (e.g., peroxymonophosphate (H3PO5)). The etching process defines the outer sidewalls 112a, 112b of the insulating layer 112. In some embodiments, the outer sidewalls 112a, 112b of the insulating layer 112 are aligned with the outer sidewalls 114a, 114b of the second resist protective layer 114 along a substantially vertical axis.

[0182] about Figure 16 In the cross-sectional view 1600, a second photoresist structure 1602 is formed above the insulating stack 116 and the floating gate electrode 104, such that a portion of the first photoresist protective layer 110, which is laterally separated from the floating gate electrode 104, remains exposed. In some embodiments, the second photoresist structure 1602 completely covers the second photoresist protective layer 114 and the insulating layer 112. In some embodiments, the second photoresist structure 1602 is laterally separated from the select gate electrode 202. In some embodiments, the second photoresist structure 1602 is a positive photoresist.

[0183] about Figure 17A cross-sectional view 1700 shows an etching process performed to remove the exposed portion of the first resist protective layer 110. The etching process exposes the top surface of the selected gate electrode 202. In some embodiments, the etching process may include, for example, a wet etching process and / or a dry etching process. In various embodiments, the wet etching process includes exposing the exposed portion of the first resist protective layer 110 to an isotropic wet etchant (e.g., dilute hydrofluoric acid (DHF)). In various embodiments, the dry etching process includes exposing the exposed portion of the first resist protective layer 110 to an anisotropic dry etchant (e.g., chlorine (Cl2), gaseous hydrochloric acid (HCl), or germane gas (GeH4)). The etching process defines outer sidewalls 110a, 110b of the first resist protective layer 110. In a further embodiment, the etching process further defines a third outer sidewall 110c of the first resist protective layer 110. In some embodiments, the second outer sidewall 110b and the third outer sidewall 110c are connected by a laterally extending surface 110s of the first resistive protective layer 110.

[0184] about Figure 18 As shown in the cross-sectional view 1800, a plurality of silicide layers 124 are formed over the substrate 102 and the exposed select gate electrode 202. In some embodiments, the plurality of silicide layers 124 may be formed by a silicide process or other suitable process. In some embodiments, the plurality of silicide layers 124 are formed over the doped region 126 of the substrate 102 and along the top surface of the select gate electrode 202.

[0185] about Figure 19 In the cross-sectional view 1900, a lower oxide layer 118a of a plurality of subsequently formed oxide layers is formed over the substrate 102, the select gate electrode 202, and the insulating stack 116. In some embodiments, the lower oxide layer 118a is conformally formed over the select gate electrode 202, the insulating layer 116, and the sidewall spacers 302. In some embodiments, the lower oxide layer 118a can be formed by a deposition process (e.g., PVD, CVD, or the like).

[0186] The lower oxide layer 118a is formed to have a seventh thickness T7. In some embodiments, the seventh thickness T7 may range from about 100 angstroms to about 200 angstroms, from about 100 angstroms to about 150 angstroms, from about 150 angstroms to about 200 angstroms, or some other suitable value.

[0187] about Figure 20 In the cross-sectional view 2000, a lower nitride layer 120a of a plurality of subsequently formed nitride layers is formed above a lower oxide layer 118a. In some embodiments, the lower nitride layer 120a is conformally formed above the lower oxide layer 118a. In some embodiments, the lower nitride layer 120a can be formed by a deposition process (e.g., PVD, CVD, or the like).

[0188] The lower nitride layer 120a is formed to have an eighth thickness T8. In some embodiments, the eighth thickness T8 may range from about 100 angstroms to about 200 angstroms, from about 100 angstroms to about 175 angstroms, from about 175 angstroms to about 200 angstroms, or some other suitable value.

[0189] about Figure 21 In the cross-sectional view 2100, an upper oxide layer 118b is formed over a lower nitride layer 120a to define a plurality of oxide layers. In some embodiments, the upper oxide layer 118b is conformally formed over the lower nitride layer 120a. In some embodiments, the upper oxide layer 118b can be formed by a deposition process (e.g., PVD, CVD, or the like).

[0190] The upper oxide layer 118b is formed to have a ninth thickness T9. In some embodiments, the ninth thickness T9 may range from about 25 angstroms to about 100 angstroms, from about 25 angstroms to about 50 angstroms, from about 50 angstroms to about 100 angstroms, or some other suitable value.

[0191] about Figure 22 In cross-sectional view 2200, an upper nitride layer 120b is formed above the upper oxide layer 118b to define a plurality of nitride layers. The plurality of oxide layers and the plurality of nitride layers define the CESL structure 122. In some embodiments, the CESL structure 122 is subjected to high stress and tensile stress is provided in the channel region of the substrate 102 to improve the saturation drive current. In alternative embodiments, forming the CESL structure 122 may include performing actions such as those described above. Figure 21 and / or Figure 22 The steps are repeated once or more to increase the number of layers in the CESL structure 122. In some embodiments, the upper nitride layer 120b is conformally formed over the upper oxide layer 118b. In some embodiments, the upper nitride layer 120b can be formed by a deposition process (e.g., PVD, CVD, or the like). The upper nitride layer 120b is formed to have an eighth thickness T8. In some embodiments, the lower nitride layer 120a and / or the upper nitride layer 120b may have the same thickness as the insulating layer 112 (e.g., a fifth thickness T5, an eighth thickness T8).

[0192] about Figure 23 The cross-sectional view 2300 shows a dielectric structure 128 formed over the CESL structure 122. In some embodiments, the dielectric structure 128 may be formed by a deposition process (e.g., PVD, CVD, or the like).

[0193] about Figure 24A cross-sectional view 2400 shows a plurality of contacts 206 formed within a dielectric structure 128, extending through the dielectric structure 128 and the CESL structure 122 to contact a plurality of silicide layers 124 covering the doped region 126. In some embodiments, the plurality of contacts 206 are electrically coupled to the overlying source line SL and the overlying bit line BL. The dielectric structure 128 and the CESL structure 122 are etched to form vias and / or metal trenches. The vias and / or metal trenches are then filled with a conductive material to form the plurality of contacts 206. In some embodiments, the plurality of contacts 206 may be formed using deposition processes and / or electroplating processes (e.g., electroplating, electroless plating, etc.).

[0194] Figure 25 A flow 2500 illustrating some embodiments of a method for forming an IC includes a floating gate electrode, a select gate electrode, and an insulating stack separating the floating gate electrode from a CESL structure. In some embodiments, the method may correspond to Figures 6 to 24 The method described in [the document / document].

[0195] Although the methods disclosed in process 2500 are illustrated and described herein as a series of actions or events, it should be understood that the order of such actions or events illustrated should not be interpreted in a limiting sense. For example, some actions may occur in a different order and / or simultaneously with other actions or events other than those illustrated and / or described herein. Furthermore, not all illustrated operations require implementation of one or more of the states or embodiments described herein. Additionally, one or more operations described herein may be performed in one or more separate operations and / or phases.

[0196] In operation 2502, doped well regions are formed in the substrate. For example, see... Figure 6 .

[0197] In operation 2504, a gate dielectric structure and a gate electrode structure are formed on the substrate. For example, see... Figure 7 .

[0198] In operation 2506, the gate dielectric structure and the gate electrode structure are patterned to define the floating gate electrode covered by the floating gate dielectric layer and the select gate electrode covered by the select gate dielectric layer, respectively. For example, see Figure 8 .

[0199] In operation 2508, sidewall spacers are formed on the opposite sidewalls of the floating gate electrode and the select gate electrode, and a doped region is formed in the substrate. For example, see... Figure 9 .

[0200] In operation 2510, an insulating stack comprising a first resistive protective layer, an insulating layer, and a second resistive protective layer is formed over the substrate, the floating gate electrode, and the select gate electrode. For example, see... Figures 10 to 12 .

[0201] In operation 2512, a first photoresist structure is formed directly above the insulating stack, exposing a portion of the second photoresist protective layer that is laterally separated from the exposed floating gate electrode, and performing an etching process to remove the exposed portion of the second photoresist protective layer, exposing a portion of the insulating layer. For example, see... Figures 13 to 14 .

[0202] In operation 2514, an etching process is performed to remove the exposed portions of the insulating layer. For example, see... Figure 15 .

[0203] In operation 2516, a second photoresist structure is formed above the insulating stack, exposing a portion of the first photoresist protective layer that is laterally separated from the floating gate electrode, and an etching process is performed to remove the exposed portion of the first photoresist protective layer. For example, see... Figures 16 to 17 .

[0204] In operation 2518, multiple silicide layers are formed over the substrate and the select gate electrode. For example, see... Figure 18 .

[0205] In operation 2520, a CESL structure is formed over the insulating stack, the substrate, and the select gate electrode. For example, see... Figures 19 to 22 .

[0206] In operation 2522, a dielectric structure is formed above the CESL structure, and multiple contacts are formed extending from the dielectric structure to the doped region. For example, see... Figures 23 to 24 .

[0207] Therefore, in some embodiments, this disclosure relates to an integrated chip (IC) including a substrate, a floating gate electrode disposed above the substrate, a contact etch stop layer (CESL) structure disposed above the floating gate electrode, and an insulating stack separating the floating gate electrode from the CESL structure. The insulating stack includes a first resistive protective layer disposed above the floating gate electrode, a second resistive protective layer disposed above the first resistive protective layer, and an insulating layer separating the first resistive protective layer from the second resistive protective layer.

[0208] In some embodiments, a select gate electrode is further included, which is disposed above the substrate, wherein the CESL structure separates the select gate electrode from the insulating stack on one side upwards.

[0209] In some embodiments, the CESL structure extends continuously above the floating gate electrode and the select gate electrode.

[0210] In some embodiments, the first resistive protective layer and the second resistive protective layer comprise a first material, and the insulating layer comprises a second material different from the first material.

[0211] In some embodiments, a capacitor is further included, disposed between the substrate and the insulating stack, wherein a first portion of the substrate is separated from a second portion of the substrate by an isolation structure, wherein a floating gate electrode covers the first portion of the substrate, wherein the capacitor covers the second portion of the substrate, and wherein the floating gate electrode is connected to the capacitor by a coupling segment that extends continuously above the isolation structure.

[0212] In some embodiments, one outer wall of the second resistive protective layer extends beneath the insulating layer.

[0213] In some embodiments, an outer wall of the insulating layer is aligned with an outer wall of the second resistive protective layer along a substantially vertical axis.

[0214] In some embodiments, the CESL structure has a first thickness and the insulating stack has a second thickness, wherein the first thickness is less than the second thickness.

[0215] In some embodiments, the insulating layer has a refractive index in the range of about 1.6 to about 1.9.

[0216] In some embodiments, the insulating stack has a thickness greater than about 2000 angstroms.

[0217] In other embodiments, this disclosure relates to a method for forming an integrated chip (IC), including forming a floating gate electrode and a select gate electrode over a substrate, forming an insulating stack over the floating gate electrode and the select gate electrode, the insulating stack including a first resistive protective layer, a second resistive protective layer disposed over the first resistive protective layer, and an insulating layer separating the first resistive protective layer and the second resistive protective layer, removing a portion of the insulating stack to expose the select gate electrode, and forming a contact etch stop layer (CESL) structure over the insulating stack and the select gate electrode.

[0218] In some embodiments, it further includes the step of forming a plurality of silicide layers over the substrate and the exposed select gate electrode prior to forming the CESL structure.

[0219] In some embodiments, it further includes the step of forming a plurality of sidewall spacers along a plurality of sidewalls of the levitation gate electrode and the select gate electrode, wherein the sidewall spacers after the portion of the insulating stack is removed separate the first resist protective layer from the levitation gate electrode.

[0220] In some embodiments, the step of forming an insulating stack includes the following steps: a first resistive protective layer formed over the floating gate electrode and the select gate electrode comprises a first material; an insulating layer formed over the first resistive protective layer comprises a second material different from the first material; and a second resistive protective layer formed over the insulating layer comprises the first material.

[0221] In some embodiments, the steps of forming a floating gate electrode and a select gate electrode include the following steps: forming a gate dielectric structure above a substrate; forming a gate electrode structure above the gate dielectric structure; and patterning the gate electrode structure and the gate dielectric structure to form a floating gate electrode covered by a floating gate dielectric layer and a select gate electrode covered by a select gate dielectric layer, respectively.

[0222] In some embodiments, the step of removing a portion of the insulating stack includes the following steps: performing a first etching process to remove a portion of the second resistive protective layer that is laterally separated from the floating gate electrode, wherein the first etching process exposes a portion of the insulating layer; performing a second etching process to remove the exposed portion of the insulating layer; and performing a third etching process to remove a portion of the first resistive protective layer that is laterally separated from the floating gate electrode.

[0223] In other embodiments, this disclosure relates to an integrated chip (IC) comprising a substrate, a floating gate electrode disposed above the substrate, a first resistive protective layer having a first thickness disposed above the floating gate electrode, a contact etch stop layer (CESL) structure disposed above the floating gate electrode, wherein the CESL structure has a second thickness less than the first thickness, a second resistive protective layer having a first thickness disposed between the CESL structure and the first resistive protective layer, and an insulating layer separating the first resistive protective layer and the second resistive protective layer.

[0224] In some embodiments, it further includes a capacitor having a first capacitor plate coupled to a floating gate electrode, wherein a first resistive protective layer, an insulating layer, and a second resistive protective layer extend above the first capacitor plate.

[0225] In some embodiments, it further includes a select gate electrode disposed above the substrate; a common source / drain region disposed in the substrate between the floating gate electrode and the select gate electrode; wherein the first resistive protective layer has an outermost wall that terminates between an edge of the select gate electrode and a nearest adjacent edge of the floating gate electrode, and does not extend above the select gate electrode.

[0226] In some embodiments, the CESL structure includes a lower oxide layer, a lower nitride layer disposed above the lower oxide layer, an upper oxide layer disposed above the lower nitride layer, and an upper nitride layer disposed above the upper oxide layer, wherein the insulating layer has the same thickness as the lower nitride layer or the upper nitride layer.

[0227] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. An integrated chip, characterized in that, Include: One substrate; A floating gate electrode is disposed above the substrate; A contact etch termination layer structure is disposed above the floating gate electrode; An insulating stack separating the floating gate electrode from the contact etch stop layer structure, the insulating stack comprising: A first resistive protective layer is disposed above the floating gate electrode; A second resistive protective layer is disposed above the first resistive protective layer, wherein the lowest surface of the second resistive protective layer is above the top surface of the floating gate electrode; and An insulating layer that separates the first resistive protective layer from the second resistive protective layer; and A capacitor is disposed between a substrate and an insulating stack, wherein a first portion of the substrate is separated from a second portion of the substrate by an isolation structure, wherein a floating gate electrode covers the first portion of the substrate, wherein the capacitor covers the second portion of the substrate, and wherein the floating gate electrode is connected to the capacitor by a coupling segment that extends continuously above the isolation structure.

2. The integrated chip as described in claim 1, characterized in that, It further includes: A select gate electrode is disposed above the substrate, wherein the contact etch stop layer structure separates the select gate electrode from the insulating stack on one side upward.

3. The integrated chip as described in claim 2, characterized in that, The contact etch termination layer structure extends continuously above the floating gate electrode and the selected gate electrode.

4. The integrated chip as described in claim 1, characterized in that, The first resistive protective layer and the second resistive protective layer comprise a first material, and the insulating layer comprises a second material different from the first material.

5. The integrated chip as described in claim 1, characterized in that, The coupling segment extends in a first direction from the first portion of the substrate above the isolation structure to the second portion of the substrate.

6. The integrated chip as claimed in claim 1, characterized in that, One outer wall of the second resistive protective layer extends beneath the insulating layer.

7. The integrated wafer as claimed in claim 1, characterized in that, One outer wall of the insulating layer is aligned with one outer wall of the second resistive protective layer along a substantially vertical axis.

8. The integrated chip as claimed in claim 1, characterized in that, The contact etch-stop layer structure has a first thickness and the insulating stack has a second thickness, wherein the first thickness is less than the second thickness.

9. The integrated chip as claimed in claim 1, characterized in that, The insulating layer has a refractive index in the range of 1.6 to 1.

9.

10. The integrated chip as claimed in claim 1, characterized in that, The insulating stack has a thickness of more than 2000 angstroms.

11. A method for forming an integrated wafer, characterized in that, Includes the following steps: A floating gate electrode and a selection gate electrode are formed above a substrate; An insulating stack is formed above the floating gate electrode and the select gate electrode. The insulating stack includes a first resistive protective layer, a second resistive protective layer disposed above the first resistive protective layer, and an insulating layer separating the first resistive protective layer from the second resistive protective layer. A first portion of the insulating stack is removed such that the lowest surface of the second resist protective layer is above the top surface of the floating gate electrode to expose the select gate electrode, while leaving a second portion of the insulating stack above the floating gate electrode. The step of removing the first portion of the insulating stack includes the following steps: A first etching process is performed to remove a portion of the second resist protective layer that is laterally separated from the floating gate electrode, wherein the first etching process exposes a portion of the insulating layer; A second etching process is performed to remove the exposed portion of the insulating layer; and A third etching process is performed to remove a portion of the first resist protective layer that is laterally separated from the floating gate electrode; and A contact etch stop layer structure is formed above the second portion of the insulating stack and above the selected gate electrode.

12. The method as described in claim 11, characterized in that, It further includes the following steps: Prior to forming the contact etch-stop layer structure, multiple silicide layers are formed on the substrate and the exposed select gate electrode.

13. The method as described in claim 11, characterized in that, It further includes the following steps: Multiple sidewall spacers are formed along multiple sidewalls of the floating gate electrode and the selected gate electrode, wherein, after the first portion of the insulating stack is removed, the sidewall spacers separate the first resist protective layer from the floating gate electrode.

14. The method as described in claim 11, characterized in that: The first resist protective layer formed above the floating gate electrode and the selective gate electrode comprises a first material. The insulating layer formed above the first resistive protective layer comprises a second material different from the first material, and The second resistive protective layer formed above the insulating layer contains the first material.

15. The method as described in claim 11, characterized in that, The steps of forming the floating gate electrode and the selected gate electrode include the following steps: A gate dielectric structure is formed on the substrate; A gate electrode structure is formed above the gate dielectric structure; and The gate electrode structure and the gate dielectric structure are patterned to form a floating gate electrode covered with a floating gate dielectric layer and a selective gate electrode covered with a selective gate dielectric layer, respectively.

16. The method as described in claim 11, characterized in that, The two outer walls of the insulating layer are aligned with the two outer walls of the second resistive protective layer along the vertical axis, respectively.

17. An integrated chip, characterized in that, Include: One substrate; A floating gate electrode is disposed above the substrate; A first resistive protective layer having a first thickness is disposed above the floating gate electrode; A contact etch termination layer structure is disposed above the floating gate electrode, wherein the contact etch termination layer structure has a second thickness that is less than the first thickness; A second resistive protective layer having the first thickness is disposed between the contact etch termination layer structure and the first resistive protective layer, wherein the lowest surface of the second resistive protective layer is above the top surface of the floating gate electrode. An insulating layer that separates the first resistive protective layer from the second resistive protective layer; A select gate electrode is disposed above the substrate; and A common source / drain region is disposed in the substrate between the floating gate electrode and the select gate electrode, wherein the first resistive protective layer has an outermost wall that terminates between an edge of the select gate electrode and a nearest adjacent edge of the floating gate electrode, and does not extend above the select gate electrode.

18. The integrated wafer as claimed in claim 17, characterized in that, It further includes: A capacitor having a first capacitor plate coupled to the floating gate electrode, wherein the first resistive protective layer, the insulating layer, and the second resistive protective layer extend above the first capacitor plate.

19. The integrated chip as claimed in claim 17, characterized in that, The contact etch termination layer structure extends continuously above the floating gate electrode and the selected gate electrode.

20. The integrated chip as claimed in claim 17, characterized in that, The contact etch stop layer structure includes a lower oxide layer, a lower nitride layer disposed above the lower oxide layer, an upper oxide layer disposed above the lower nitride layer, and an upper nitride layer disposed above the upper oxide layer, wherein the insulating layer has the same thickness as the lower nitride layer or the upper nitride layer.

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