Light sensor

Abstract

Embodiments of the present disclosure relate to photosensors. The present disclosure relates to a sensor having pixels, each pixel having a photodiode each having a terminal coupled to a first node associated with the photodiode, and an amplifier having a first portion, and for each photodiode, a second portion associated with the photodiode. The first portion includes an output of the amplifier and a first MOS transistor of a differential pair. Each second portion includes a second MOS transistor of the differential pair, a gate of the second MOS transistor coupled to the first node associated with the photodiode associated with the second portion, a first switch coupling a source of the second transistor to the first portion of the amplifier, and a second switch coupling a drain of the second transistor to the first portion of the amplifier.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to European application number 21305534.6, filed on 23 April 2021, which is hereby incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates generally to electronic circuits, and more specifically to optical sensors. Background Technology

[0004] Known light sensors (e.g., ambient light sensors (ALS)) comprise multiple pixels arranged in a pixel matrix having pixel rows and pixel columns.

[0005] Among these known light sensors, those in which each pixel comprises multiple photodiodes are known. In such light sensors, the readout circuit for each pixel is typically located at the end of the row or column associated with the pixel. This results in long wires used to couple the pixel to its readout circuit, and thus wiring capacitance at the input of the readout circuit. As the capacitance of the pixel's photodiodes tends to decrease, the effect of the wiring capacitance during the pixel's readout phase becomes problematic.

[0006] For example, this is the case when the photodiode of a pixel is island-shaped (i.e., when the pixel comprises an island-shaped photodiode). In fact, the intrinsic capacitance of an island-shaped photodiode is, for example, at least ten times lower than the intrinsic capacitance of a conventional photodiode (e.g., a pinned photodiode). Island-shaped photodiodes are described, for example, in U.S. Patent 6,998,659 and U.S. Patent Applications 10,418,402 and 10,922,590.

[0007] It is necessary to overcome all or some of the shortcomings of known light sensors, such as those in known ambient light sensors. Summary of the Invention

[0008] The embodiments disclosed herein address all or some of the drawbacks of known light sensors (e.g., known ambient light sensors).

[0009] An embodiment provides a light sensor having multiple pixels, each pixel including: a first photodiode having terminals respectively coupled to a first node associated with the pixel; and a first amplifier having a first portion common to all first photodiodes and a second portion associated with each first photodiode, the first portion of the first amplifier having an output of the first amplifier and a differential pair of first MOS transistors of the first amplifier, each second portion of the first amplifier having: a second MOS transistor of the differential pair, the gate of the second transistor being coupled to the first node associated with the first photodiode associated with the second portion; a first switch coupling the source of the second transistor to the first portion of the first amplifier; and a second switch coupling the drain of the second transistor to the first portion of the amplifier.

[0010] According to one embodiment, the first amplifier for each pixel further includes a feedback loop for each first photodiode of the pixel, the feedback loop having a first end connected to a first node associated with the first photodiode, a second portion of the amplifier associated with the first photodiode having the feedback loop; and at least one third switch associated with the feedback loop, the at least one third switch coupling the second end of the feedback loop to the output of the first amplifier.

[0011] According to one embodiment, the at least one third switch includes a first third switch, which is included in the second portion of the first amplifier associated with the first photodiode.

[0012] According to one embodiment, the at least one third switch includes a second third switch included in the first portion and having a first conductive terminal connected to the output of the first amplifier, wherein the first third switch of each second portion of the first amplifier has a first conductive terminal connected to the second end of the feedback loop of the second portion, and a second conductive terminal connected to the second conductive terminal of the second third switch.

[0013] According to one embodiment, in each of the pixels, a first portion of the first amplifier includes an intermediate node of the differential pair coupled to the source of the first transistor; a first input of the first amplifier coupled to the gate of the first transistor; and a load stage of the differential pair coupled to the drain of the first transistor, a first switch of each second portion being connected between the source of the second transistor of the second portion and the intermediate node, and a second switch of each second portion being connected between the load stage and the drain of the second transistor of the second portion.

[0014] According to one embodiment, in each pixel, a first portion of the first amplifier includes a fourth switch connected between the source and an intermediate node of the first transistor, and a fifth switch connected between the drain and a load stage of the first transistor. Preferably, the fourth and fifth switches are configured to remain closed.

[0015] According to one embodiment, each pixel further includes: a second photodiode, each of the second photodiodes having a terminal coupled to a second node of the pixel, the second node being associated with the second photodiode; and a second amplifier, the second amplifier having a first portion common to all the second photodiodes, and a second portion associated with each second photodiode, the first portion of the second amplifier having an output of the second amplifier and a first MOS transistor of a differential pair of the second amplifier, and each second portion of the second amplifier having: a second MOS transistor of the differential pair of the second amplifier, the gate of the second transistor being coupled to a second node associated with the second photodiode associated with the second portion; a first switch, the first switch coupling the source of the second transistor to the first portion of the second amplifier; and a second switch, the second switch coupling the drain of the second transistor to the first portion of the second amplifier.

[0016] According to one embodiment, the second amplifier for each pixel further includes a feedback loop for each second photodiode of the pixel, the feedback loop having a first end connected to a second node associated with the second photodiode, the second portion of the second amplifier being associated with the second photodiode having the feedback loop; and at least one third switch associated with the feedback loop, the at least one third switch coupling a second end of the feedback loop to the output of the second amplifier.

[0017] According to one embodiment, the at least one third switch includes a first third switch, which is included in the second portion of the second amplifier associated with the second photodiode.

[0018] According to one embodiment, the at least one third switch includes a second third switch included in the first portion of the second amplifier and having a first conductive terminal connected to the output of the second amplifier. The first third switch of each second portion of the second amplifier has a first conductive terminal connected to the second end of the feedback loop of the second portion, and a second conductive terminal connected to the second conductive terminal of the second third switch.

[0019] According to one embodiment, in each pixel, the first portion of the second amplifier includes: an intermediate node of the differential pair of the first portion, the intermediate node being coupled to the source of the first transistor of the first portion; a first input of the second amplifier, the first input being coupled to the gate of the first transistor of the first portion; and a load stage of the differential pair of the first portion, the load stage being coupled to the drain of the first transistor of the first portion, a first switch of each second portion of the second amplifier being connected between the source of the second transistor of the second portion and the intermediate node, and a second switch of each second portion of the second amplifier being connected between the drain of the second transistor of the second portion and the load stage.

[0020] According to one embodiment, the first portion of the second amplifier includes a fourth switch connected between the source of the first transistor and an intermediate node of the first portion, and a fifth switch connected between the drain of the first transistor and a load stage of the first portion. Preferably, the fourth and fifth switches are configured to remain closed.

[0021] According to one embodiment, in each pixel, each first photodiode belongs to only one of a plurality of groups having at least one first photodiode, and each pixel includes control circuitry configured to: sequentially select each of the plurality of groups; for each first photodiode in the selected group, close a first switch and a second switch of the second portion associated with the first photodiode, and close at least one third switch associated with the feedback loop of the second portion (AMP1-21, AMP1-22, AMP1-23, AMP1-24); and for each first photodiode in the unselected group, disconnect the first switch and the second switch of the second portion associated with the first photodiode, and disconnect at least one third switch associated with the feedback loop of the second portion (AMP1-21, AMP1-22, AMP1-23, AMP1-24).

[0022] According to one embodiment, each feedback loop includes a capacitor element and a switch connected in parallel between a first end and a second end of the feedback loop.

[0023] According to one embodiment, in each pixel, the second transistor of each second portion is completely configured to be less than 50 μm away from the photodiode associated with the second portion.

[0024] Another embodiment provides a method implemented in the light sensor, wherein reading at least one first photodiode of a pixel selected from the first photodiodes of the pixels comprises: for each selected first photodiode, closing a first switch and a second switch of a second portion of a first amplifier associated with the selected first photodiode to electrically couple the second portion to the first portion of the first amplifier; and for each unselected first photodiode, disconnecting the first switch and the second switch of the second portion of the first amplifier associated with the unselected first photodiode to electrically disconnect the second portion from the first portion of the first amplifier. Attached Figure Description

[0025] To gain a more complete understanding of this disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0026] Figure 1 This is a diagram of exemplary pixels of a light sensor;

[0027] Figure 2 This is a schematic diagram of an exemplary optical sensor;

[0028] Figure 3 This is an image of exemplary pixels;

[0029] Figure 4 This is a schematic diagram of an exemplary optical sensor; and

[0030] Figure 5 This is an image of exemplary pixels. Detailed Implementation

[0031] In the various figures, similar features have been designated by similar reference numerals. Specifically, common structural or functional features in various embodiments may have the same reference numerals and may be provided with the same structure, dimensions, and material properties.

[0032] For clarity, only the operation and components used to understand the embodiments described herein have been illustrated and described in detail. Specifically, no general electronic systems and applications that may include optical sensors have been described, and the described embodiments and variations are compatible with such general systems and applications.

[0033] Unless otherwise stated, when referring to two elements connected together, this means there is no direct connection of any intermediate element other than a conductor, and when referring to two elements coupled together, this means that the two elements can be connected or they can be coupled via one or more other elements.

[0034] In the following disclosure, unless otherwise stated, reference is made to the orientation shown in the figures when referring to absolute position qualifiers (such as the terms “front,” “back,” “top,” “ground,” “left,” “right,” etc.) or relative position qualifiers (such as the terms “above,” “below,” “higher,” “lower,” etc.) or orientation qualifiers (such as “horizontal,” “vertical,” etc.).

[0035] Unless otherwise stated, the expressions “about,” “approximately,” “basically,” and “probably” indicate within 10%, and preferably within 5%.

[0036] In known light sensors having multiple pixels arranged in a matrix of pixel rows and columns, each pixel includes multiple photodiodes, and the readout circuitry for each pixel typically includes an amplifier. For example, this is the case with ambient light sensors, where each pixel includes multiple color channels, and each color channel has one or more photodiodes. Preferably, the photodiodes of different color channels are arranged relative to each other such that the different color channels have a common centroid layout to reduce the spatial sensitivity of the sensor. Within each pixel, the photodiodes of different color channels are arranged relative to each other such that the sensor is insensitive to the spatial distribution of light, the color of the light, or the orientation of the sensor (i.e., the angle of incident light).

[0037] Each amplifier in the pixel readout circuit has an input connected to a first electrode or terminal of one or more photodiodes of the pixel. Each amplifier includes an operational amplifier having one of an inverting input and a non-inverting input connected to the first electrode of one or more photodiodes. Each amplifier also includes a feedback loop connected between the output of the operational amplifier (i.e., the output of the amplifier in the readout circuit) and the first electrode of one or more photodiodes.

[0038] An operational amplifier includes a differential pair having a first transistor and a second transistor. The gate of the first transistor is the first input of the operational amplifier. The gate of the second transistor is the second input of the operational amplifier. The differential pair, together with a load stage and a bias circuit, forms, for example, the input stage of the operational amplifier. The operational amplifier also includes a gain stage that couples the differential pair to the output of the operational amplifier. The output of the operational amplifier is connected, for example, to an analog-to-digital converter (ADC).

[0039] To reduce the length of the wire connecting the first electrode of a pixel's photodiode to the input of the amplifier in the pixel's readout circuit—that is, the length of the wire connecting the first electrode of the photodiode to the gate of the first transistor in a differential pair of transistors in the amplifier—this disclosure proposes separating the differential pair such that the first transistor is positioned, for example, close to the first electrode of one or more photodiodes. Conversely, the second transistor of the differential pair can be positioned away from the photodiode.

[0040] This disclosure proposes dividing an amplifier into a first portion having a second transistor with a differential pair and a second portion having a second transistor with a differential pair. According to one embodiment, each first portion of the amplifier further includes a feedback loop for the amplifier. In addition to the second transistor with the differential pair, the first portion of the amplifier preferably includes a load stage for the differential pair, a bias circuit for the differential pair, and a gain stage for the amplifier.

[0041] This disclosure proposes providing a second portion of an amplifier for each of a plurality of photodiodes in a pixel, and selectively coupling each second portion to the same first portion of the amplifier, for example using a switch or multiplexer. In doing so, each second portion can be arranged close to the photodiode associated with it, for example, less than 50 μm away from the photodiode. Since each second portion of the amplifier includes a first transistor in a differential pair of the amplifier, the first transistor can be positioned close to the photodiode associated with the second portion, for example, less than 50 μm away from the photodiode. Therefore, the wiring capacitance between the photodiode and the corresponding first transistor in the differential pair is reduced.

[0042] Figure 1 An example of an embodiment of pixel 1 of a light sensor is shown. Although in Figure 1 Not shown, but the sensor (e.g., an ambient light sensor) includes a plurality of pixels 1, which are preferably arranged in a matrix of pixel rows and columns.

[0043] Pixel 1 comprises N photodiodes PDi (e.g., N island photodiodes PDi), where N is an integer greater than or equal to 2, and i is an integer having a value in the range from 1 to N. Figure 1 In the embodiment, N equals 2, and pixel 1 includes two photodiodes PD1 and PD2.

[0044] Each photodiode PDi of pixel 1 has an electrode or terminal coupled to nodes IN1-2i of pixel 1. In an embodiment, photodiode PD1 has a terminal (e.g., cathode) coupled (preferably connected) to nodes IN1-21 of pixel 1, and photodiode PD2 has a terminal (e.g., cathode) coupled (preferably connected) to nodes IN1-22 of pixel 1. Nodes IN1-i will be associated with photodiode PDi. In an embodiment, another terminal (e.g., anode) of each photodiode PDi is coupled (preferably connected) to node 100 configured to receive a reference potential (e.g., ground potential GND).

[0045] Pixel 1 also includes Figure 1 The amplifier AMP1 is not labeled. Amplifier AMP1 is, for example, a capacitive transimpedance amplifier CTIA. Amplifier AMP1 comprises, or more precisely is made of, the following: a first part AMP1-1, which is shared by all photodiodes PDi for pixel 1; and a second part AMP1-2i associated with each photodiode PDi. More precisely, in Figure 1 In the example, amplifier AMP1 includes a second part AMP1-21 associated with photodiode PD1 and a second part AMP1-22 associated with photodiode PD2.

[0046] In one embodiment, amplifier AMP1 includes as many second portions AMP1-2i as photodiode PDi in pixel 1, but only one portion AMP1-1. Therefore, pixel 1 includes N second portions AMP1-2i.

[0047] The first part of amplifier AMP1, AMP1-1, includes a metal-oxide-semiconductor (MOS) transistor T1. Transistor T1 is one of the two transistors in the differential pair of amplifier AMP1.

[0048] The portion AMP1-1 of amplifier AMP1 also includes the output 102 of amplifier AMP1. In the embodiment, although in Figure 1 As not shown, output 102 is coupled (e.g., connected) to the input of the analog-to-digital converter (ADC). Amplifier AMP1 and ADC are, for example, part of the readout circuitry for pixel 1.

[0049] Preferably, all the second parts AMP1-2i of the amplifier are structurally identical to each other. However, the values ​​of a given component (e.g., capacitance or dimensional values, such as channel length or width) of one of these parts AMP1-2i may differ from the values ​​of the same component in the other second part AMP1-2i of the amplifier AMP1.

[0050] In the embodiment, each second part AMP1-2i of amplifier AMP1 includes MOS transistor T2i ( Figure 1 (T21 and T22 in the diagram). The transistor T2i in each second section AMP1-2i of amplifier AMP1 is the other of the two transistors in the differential pair of amplifier AMP1. Therefore, transistors T1 and T2i are of the same type in both P-channel (PMOS) and n-channel (NMOS) types. Figure 1 In the example, transistors T1 and T2i are NMOS transistors, although in other examples not shown, transistors T1 and T2i are PMOS transistors.

[0051] In each section AMP1-2i of amplifier AMP1, the gate of transistor T2i is coupled (preferably connected) to node IN1-2i associated with the photodiode PDi associated with the second section.

[0052] Additionally, each second section AMP1-2i of amplifier AMP1 includes switch IT1i ( Figure 1 IT11, IT12) and switch IT2i Figure 1 (IT21, IT22 in the diagram). In each section AMP1-2i of amplifier AMP1, switches IT1i and IT2i are configured such that when switches IT1i and IT2i of that section AMP1-2i are closed (or, in other words, in the ON state), transistor T2i of that section AMP1-2i forms a differential pair with transistor T1 of amplifier AMP1. When switches IT1i and IT2i of that section AMP1-2i are open (i.e., in the ON state), transistor T2i does not form a differential pair with transistor T1 of amplifier AMP1. In an embodiment, each switch IT1i, IT2i is implemented by at least one MOS transistor, for example using complementary metal-oxide-semiconductor CMOS technology.

[0053] In each section AMP1-2i, switch IT1i couples the source of transistor T2i to the first section AMP1-1 of amplifier AMP1. In an embodiment, in each section AMP1-2i, switch IT1i is configured to selectively couple the source of transistor T2i to the first section AMP1-1 of amplifier AMP1. Therefore, in each section AMP1-2i, switch IT1i is connected between the source of transistor T2i and section AMP1-1 of amplifier AMP1. For example, in each section AMP1-2i of amplifier AMP1, the first conductive terminal of switch IT1i is coupled (preferably connected) to section AMP1-1 of amplifier AMP1, and the second terminal of switch IT1i is coupled (preferably connected) to the source of transistor T2i.

[0054] In each section AMP1-2i, switch IT2i couples the drain of transistor T2i to the first section AMP1-1 of amplifier AMP1. In an embodiment, in each section AMP1-2i, switch IT2i is configured to selectively couple the drain of transistor T2i to the first section AMP1-1 of amplifier AMP1. Therefore, in each section AMP1-2i, switch IT2i is connected between the drain of transistor T2i and section AMP1-1 of amplifier AMP1.

[0055] In an embodiment, in each part AMP1-2i of amplifier AMP1, the first conductive terminal of switch IT2i is coupled (preferably connected) to part AMP1-1 of amplifier AMP1, and the second terminal of switch IT2i is coupled (preferably connected) to the drain of transistor T2i.

[0056] More specifically, according to an embodiment, the first portion AMP1-1 of amplifier AMP1 includes an intermediate node 104 of the differential pair of amplifier AMP1 and a load stage LS of the differential pair of amplifier AMP1. The source of transistor T1 is coupled to node 104. The gate of transistor T1 is coupled (preferably connected) to the input IN1-1 of amplifier AMP1.

[0057] In this embodiment, the input or node IN1-1 is configured to receive a ground potential GND. The drain of transistor T1 is coupled (preferably connected) to the load stage LS, for example, to node 106 of the load stage LS. Therefore, the switch IT1i of each second section AMP1-2i of amplifier AMP1 is connected between the source of the corresponding transistor T2i and the intermediate node 104 (i.e., the source of transistor T1). Additionally, the switch IT2i of each second section AMP1-2i of amplifier AMP1 is connected between the drain of the corresponding transistor T2i and the load stage LS.

[0058] In an embodiment, the switch IT2i of each second part AMP1-2i of amplifier AMP1 is connected between the drain of the corresponding transistor T2i and node 108 of the load stage LS.

[0059] In this embodiment, the load stage LS of the differential pair of amplifier AMP1 is an active load stage LS. In this case, the load stage LS includes, for example, a current mirror having a branch connecting node 106 and node 110 configured to receive a first DC potential, and a branch connecting nodes 108 and 110.

[0060] In an embodiment, the load stage LS includes a MOS transistor T3 having a source connected to node 110 and a drain connected to node 108, as well as a gate for the transistor T3. The load stage LS also includes a MOS transistor T4 having a source connected to node 110, a drain connected to node 106, and a gate connected to the transistor T3.

[0061] exist Figure 1 In the example, transistors T1 and T2i are NMOS transistors, transistors T3 and T4 are, for example, PMOS transistors, and node 110 is configured to receive the power supply potential Vdd.

[0062] In embodiments not shown, the load level LS differs from the load level described above as an example. Specific implementations of other examples of load level LSs are within the capabilities of those skilled in the art.

[0063] In one embodiment, the intermediate node 104 of the differential pair of amplifier AMP1 is coupled to node 112, which is configured to receive a second DC potential. The difference between the potential at node 110 and the potential at node 112 corresponds to the power supply voltage of amplifier AMP1. Figure 1 In the example, transistors T1 and T2i are NMOS transistors, and node 112 is configured, for example, to receive ground potential GND.

[0064] The intermediate node 104 of the differential pair is coupled to node 112 via a bias circuit B configured to bias the differential pair. Figure 1 In the example, bias circuit B includes an NMOS transistor T5 having a source coupled (preferably connected) to node 112, a drain coupled (preferably connected) to node 104, and a gate configured to receive a control potential, although other examples of specific implementations of the bias circuit are within the capabilities of those skilled in the art.

[0065] According to the embodiments, and as Figure 1 As shown, the first part of amplifier AMP1, AMP1-1, also includes switches IT4 and IT5. Switch IT4 is connected between the source of transistor T1 and node 104. Switch IT5 is connected between the drain of transistor T1 and node 106. Switches IT4 and IT5 are configured to remain closed (i.e., dummy switches). Therefore, when switches IT1i and IT2i of part AMP1-2i are closed, the effect of these switches on the differential pair is compensated by the effect of the dummy switches IT4 and IT5 on the differential pair.

[0066] In another embodiment not shown, portion AMP1-1 of amplifier AMP1 does not include switches IT3 and IT4. In such an embodiment, the source of transistor T1 is preferably connected to node 104, and the drain of transistor T1 is preferably connected to node 106.

[0067] like Figure 1 As shown, amplifier AMP1, and more specifically, a portion of amplifier AMP1-1, includes a gain stage G configured to differentially couple amplifier AMP1 to output AMP1 at output 102. In the example where load stage LS is an active load stage with a current mirror, gain stage G couples node 106 to output 102.

[0068] As an example, the gain stage G is of the Miller type. The gain stage includes a transistor T5 having a gate coupled (preferably connected) to node 106, a drain coupled (preferably connected) to output 102, and a source coupled (preferably connected) to node 110; and a Miller capacitor Cm connected between the gate and drain of transistor T5. In this example, with node 110 receiving a potential Vdd, transistor T5 is a PMOS transistor. The gain stage G also includes a transistor T6 having a gate configured to receive a control potential, a source coupled (preferably connected) to node 112, and a drain coupled (preferably connected) to output 102. In this example, with node 112 receiving a potential GND, transistor T6 is an NMOS transistor.

[0069] Those skilled in the art can replace the gain stage G described above as an example with another gain stage G, such as the folded cascode type.

[0070] The differential pairs T1 and T2i, the load stage LS, the bias circuit B, and the load stage of amplifier AMP1 are the operational amplifier components of amplifier AMP1.

[0071] According to the embodiment, in addition to a transistor T2i, each part AMP1-2i of amplifier AMP1 includes a feedback loop FbLi of amplifier AMP1. Figure 1 (Fbl1, FbL2 in the text).

[0072] In each second section AMP1-2i of amplifier AMP1, the feedback loop FbLi has an end 116 connected to a node IN1-2i associated with the photodiode PDi associated with the second section AMP1-2i. For example, the end 116 of the feedback loop FbL1 of section AMP1-21 is connected to node IN1-21, and the end 116 of the feedback loop FbL2 of section AMP1-22 is connected to node IN1-22.

[0073] According to one embodiment, for each feedback loop FbLi, amplifier AMP1 includes a switch IT3i associated with the feedback loop FbLi. Figure 1 (IT31 and IT32 in the diagram). Switch IT3i couples the other end 118 of the feedback loop FbLi to the output 102 of amplifier AMP1.

[0074] In this embodiment, each feedback loop FbLi is associated with a switch IT3i, which is configured to selectively couple end 118 of the feedback loop FbLi to the output 102 of amplifier AMP1. Therefore, for each feedback loop FbLi, the switch IT3i associated with the feedback loop FbLi is connected between end 118 of the feedback loop FbLi and the output 102 of amplifier AMP1. For each feedback loop FbLi, the switch IT3i is configured, for example, to be in the same state (closed or open) as the switches IT1i and IT2i of the second portion AMP1-2i (which includes the feedback loop FbLi). As an example, each switch IT3i is implemented using at least one MOS transistor, for example, using CMOS technology.

[0075] According to one embodiment, such as Figure 1 As shown, for each feedback loop FbLi, switch IT3i belongs to part AMP1-2i, which includes feedback loop FbLi. For example, part AMP1-21 includes switch IT31 associated with feedback loop FbL1, and part AMP1-22 has switch IT32 associated with feedback loop FbL2.

[0076] According to one embodiment, for each feedback loop FbLi, and in addition to the switch IT3i associated with the feedback loop FbLi, amplifier AMP1 also includes a switch IT0i associated with the feedback loop FbLi. Figure 1 (IT01, IT02 in the diagram). For each feedback loop FbLi, with respect to switch IT3i, switch IT0i couples end 118 of feedback loop FbLi to output 102 of amplifier AMP1. All switches belong to part AMP1-1 of amplifier AMP1. Therefore, for each feedback loop FbLi, the corresponding switches IT3i and IT0i are connected in series between end 118 of feedback loop FbLi and output 102 of amplifier AMP1. For each feedback loop FbLi, switch IT0i associated with feedback loop FbLi is configured, for example, to be in the same state (closed or open) as switches IT1i and IT2i of part AMP2-2i of feedback loop FbLi.

[0077] In this embodiment, each switch IT0i is implemented using at least one MOS transistor, for example, using CMOS technology. An advantage of this embodiment, where each feedback loop FbLi consists of two switches IT3i and IT0i, is that when both switches IT3i and IT0i associated with a given feedback loop FbLi are disconnected, the capacitance of the wire connecting switches IT3i and IT0i is disconnected from the amplifier AMP1.

[0078] exist Figure 1 In the example, each switch IT3i of part AMP1-2i is connected to end 118 and node 120i of the feedback loop FbLi. Figure 1 Between nodes 1201 and 1202, switch IT0i is connected between node 120i and output 102 of amplifier AMP1.

[0079] In one embodiment, switch IT31 (IT32) is connected between end 118 of feedback loop FbL1 (FbL2) and node 1201 (1202), and switch IT01 (IT02) is connected between node 1201 (1202) and output 102 of amplifier AMP1.

[0080] Despite Figure 1 Not shown, but according to an alternative embodiment, each feedback loop FbLi is associated only with the switch IT3i of the portion of AMP1-2i associated with the feedback loop FbLi. In this embodiment, pixel 1 does not include switch IT0i.

[0081] Despite Figure 1 Not shown, according to another alternative embodiment, each feedback loop FbLi is associated only with a switch IT0i of a portion of the amplifier AMP1-1, with the switch IT0i connected between the end 118 of the corresponding feedback loop FbLi and the output 102 of the amplifier AMP1. In this embodiment, pixel 1 does not include a switch IT3i.

[0082] In an embodiment, each feedback loop FbLi includes a switch IT6 and a capacitor element Cfb connected in parallel between the ends 116 and 118 of the feedback loop FbLi.

[0083] According to one embodiment, pixel 1 includes a control circuit CTRL configured to control switches IT1i, IT2i, and IT3i or IT0i, and, for example, keep switches IT4 and IT5 closed. The circuit CTRL is further configured, for example, to control switch IT6.

[0084] According to one embodiment, each photodiode PDi belongs to only one group of photodiodes PDi from multiple groups of at least one photodiode PDi. Preferably, each photodiode PDi in a given group is the photodiode corresponding to a given color channel of pixel 1. Therefore, pixel 1 has multiple different color channels.

[0085] In an embodiment, one or more photodiodes PDi of a color channel are configured to receive light having wavelengths within a wavelength range, and one or more photodiodes PDi of another color channel are configured to receive light having wavelengths within another wavelength range. The circuit CTRL is configured, for example, to sequentially select each group of photodiodes PDi in the one or more photodiodes, and for each selected group, to close the switches IT1i and IT2i of portions AMP1-2i associated with each photodiode PDi in the selected group, while simultaneously opening the switches IT1i and IT2i of the other portions AMP1-2i, i.e., the switches IT1i and IT2i of each portion AMP1-2i associated with the photodiodes PDi in the unselected group of photodiodes PDi in the one or more photodiodes.

[0086] In one embodiment, N equals 2, photodiode PD1 belongs to the first color channel of pixel 1, and photodiode PD2 belongs to the second color channel of pixel 1.

[0087] In this embodiment, photodiode PD1 is configured to receive light having a wavelength within a first wavelength range, and photodiode PD2 is configured to receive light having a wavelength within a second wavelength range, the first and second wavelength ranges being different from each other. In this example, when the first color channel is selected, the circuit CTRL is configured to close switches IT11, IT21, IT31, and IT01 while opening switches IT12, IT22, IT32, and IT02; and when the second color channel is selected, the circuit CTRL is configured to close switches IT12, IT22, IT32, and IT02 while opening switches IT11, IT21, IT31, and IT01.

[0088] The advantage of this embodiment is that a portion of amplifier AMP1, AMP1-1, and the analog-to-digital converter preferably connected to the output 102 of amplifier AMP1 are shared between different color channels of pixel 1. This allows for increased matching between color channels to reduce mismatch between color channels.

[0089] According to another embodiment, all photodiodes (PDi) belong to the same color channel, and the pixels, for example, have at least one color channel not in the same color channel. Figure 1Other photodiodes shown belong to another color channel and are coupled to their own readout circuitry. For example, the circuit CTRL is configured to simultaneously close all switches IT1i, IT2i, IT3i, and IT0i.

[0090] Consider the following scenario: Pixel 1 (and more precisely, its control circuit CTRL) is configured such that switches IT1i, IT2i, IT3i, and ITOi associated with M photodiodes PDi (M being an integer greater than or equal to 2) are simultaneously closed, while switches IT1i, IT2i, IT3i, and ITOi associated with other photodiodes PDi are open. Preferably, in this case, the dimensions of the M transistors T2i associated with the M photodiodes PDi are selected such that the transistors corresponding to these M transistors T2i connected in parallel have the same dimensions as transistor T1.

[0091] Figure 2 It is shown in a very illustrative way and in the form of a box. Figure 1 An embodiment of the light sensor 2 with pixel 1. For example, sensor 2 (e.g., ambient light sensor) includes a matrix of pixels 1 arranged in rows 200 and columns 202. Figure 1 The above only partially represents three rows of 200 and three columns of 202, and... Figure 1 The above only represents a complete pixel 1.

[0092] If only for Figure 2 As shown in pixel 1 in the middle, each of the second parts of amplifier AMP1, AMP1-21, AMP1-22 ( Figure 2 (Not cited in the text) is positioned close to the photodiodes PD1 and PD2 associated with the second part. In addition, the first part AMP1-1 of amplifier AMP1 is positioned away from the photodiodes PD1 and PD2 of pixel 1, for example, at the bottom of column 202 which has pixels.

[0093] According to one embodiment, each portion AMP1-2i is positioned (preferably entirely positioned) close to the photodiode PDi. This portion AMP1-2i is associated with, for example, a photodiode PDi less than 50 μm in size, which is associated with this portion AMP1-2i.

[0094] According to one embodiment, each partial transistor T2i is configured to be close (preferably less than 50 μm) to a photodiode PDi coupled to transistor T2i.

[0095] In one embodiment, the output 102 of amplifier AMP1 is coupled (e.g., connected to) the input of analog-to-digital converter 204.

[0096] Figure 3 Another example of pixel 1 is shown. Figure 3 In the example of the embodiment, N equals 4. Therefore, with Figure 1 Compared to pixel 1, Figure 3 The pixels also include nodes IN1-23 and IN1-24, photodiodes PD3 and PD4 (the first electrode of photodiode PD3 (and PD4 respectively) is coupled (preferably connected) to nodes IN1-23 (and IN1-24 respectively)), the second part of amplifier AMP1 AMP1-23 (the second part AMP1-23 is associated with photodiode PD3 and has transistor T23), feedback loop FbL3 and switches IT13, IT23 and IT33, the second part of amplifier AMP1 AMP1-24 (the second part AMP1-24 is associated with photodiode PD4 and has transistor T24), feedback loop FbL4 and switches IT14, IT24 and IT34.

[0097] In addition, Figure 3 In the example, pixel 1 does not include switch IT0i, and node 120i is merged with the output 102 of amplifier AMP1 (not in...). Figure 3 (As cited in the text). However, those skilled in the art can enable... Figure 3 Pixel 1 is adapted to the case where pixel 1 also includes the switch IT0i, or is adapted to Figure 3 The case where pixel 1 does not include switch IT3i but includes switch IT0i.

[0098] In addition, Figure 3 In the example, part of AMP1-1 does not include switches IT4 and IT5, although those skilled in the art can understand this based on the... Figure 1 The relevant functional and structural descriptions of pixel 1 are used to add these switches.

[0099] In addition, in order to prevent Figure 3 With more loads, the feedback loop FbLi, load stage LS, bias circuit B, and gain stage G are represented in block form.

[0100] In the first example, each photodiode PDi belongs to a different color channel of pixel 1. Therefore, pixel 1 includes four different color channels.

[0101] In the second example, pixel 1 includes two different color channels, each with two photodiodes PDi. For example, the first color channel includes photodiodes PD1 and PD2, and the second color channel includes photodiodes PD3 and PD4.

[0102] In the third example, pixel 1 includes a first color channel having only one photodiode PDi (e.g., photodiode PD1) and a second color channel having other photodiodes PDi (e.g., photodiodes PD2, PD3 and PD4).

[0103] In the fourth example, pixel 1 includes a first color channel having a photodiode PDi (e.g., photodiode PD1), a second color channel having a photodiode PDi (e.g., photodiode PD2), and a third color channel having other photodiodes PDi (e.g., photodiodes PD3 and PD4).

[0104] In the fifth embodiment, pixel 1 includes four color channels having each of the photodiodes PDi.

[0105] Other examples of re-division of photodiodes PDi in at least two groups or color channels are within the capabilities of those skilled in the art.

[0106] As in Figure 1 middle, Figure 2 The advantage of pixel 1 is that a portion of amplifier AMP1, AMP1-1, is shared by all photodiodes PDi of pixel 1, and each portion AMP1-2i or at least each transistor T2i can be positioned close to the associated photodiode PDi, while the portion AMP1-1 can be positioned away from the photodiode PDi.

[0107] Figure 4 It is shown in a very illustrative way and in the form of a box. Figure 3 An embodiment of the light sensor 4 with pixel 1.

[0108] In one embodiment, sensor 4 (e.g., an ambient light sensor) comprises a matrix of pixels 1 arranged in rows and columns, although in Figure 4 The value in the middle represents only one pixel, 1.

[0109] like Figure 4 As shown, amplifier AMP1 ( Figure 4 Each second portion AMP1-2i (not cited in the text) is positioned close to the photodiode PDi associated with the second portion AMP1-2i. Additionally, the first portion AMP1-1 of amplifier AMP1 may be positioned away from the photodiode PDi of pixel 1, for example, at the bottom of the column containing pixel 1.

[0110] According to one embodiment, each portion AMP1-2i is positioned (preferably entirely positioned) close to the photodiode PDi. This portion AMP1-2i is associated with, for example, a photodiode PDi less than 50 μm in size, which is associated with this portion AMP1-2i.

[0111] According to one embodiment, each transistor T2i ( Figure 3 The photodiode (PDi) is positioned close to (preferably connected to) the transistor T2i.

[0112] As an example, the output 102 of amplifier AMP1 is coupled (e.g., connected to) to the input of analog-to-digital converter 204.

[0113] In the above embodiments and variations, those skilled in the art can change the value of N such that pixel 1 includes only one color channel with all N photodiodes PDi, or at least two different color channels, each color channel having one or more photodiodes PDi, and the number of photodiodes PDi is equal to or different from the number of photodiodes PDi in the other color channel.

[0114] Those skilled in the art can arrange the photodiodes PDi of different color channels of pixel 1 so that pixel 1 has a common centroid layout.

[0115] Figure 5 Another embodiment of pixel 5 of the light sensor is shown. Although in Figure 5 Not shown, but the sensor (e.g., an ambient light sensor) includes a plurality of pixels 5, which are preferably arranged in a matrix of pixel rows and pixel columns.

[0116] Pixel 5 includes and combines Figures 1 to 4 The description covers many common components of pixel 1, and the differences between pixel 5 and pixel 1 will be emphasized here. Specifically, as with pixel 1, pixel 5 includes N photodiodes PDi, amplifier AMP1 ( Figure 5 (not marked in the text) and therefore, the amplifier AMP1 portion AMP1-1), each associated with the corresponding photodiode PDi, N nodes IN1-2i, and each associated with the corresponding photodiode PDi and preferably associated with the control circuit CTRL, N portions AMP1-2i of the amplifier AMP1.

[0117] exist Figure 5 In the example, N equals 2, although those skilled in the art will be able to increase the value of N. Therefore, pixel 5 includes photodiodes PD1 and PD2, nodes IN1-21 and IN1-22, and portions of AMP1-21 and AMP1-22.

[0118] In addition, Figure 5In the example, part of amplifier AMP1-1 does not include switch IT0i, and node 120i is merged with the output 102 of amplifier AMP1. However, those skilled in the art can adapt pixel 5 to a situation where part of AMP1-1 includes switch IT0i, or to a situation where part of AMP1-2i does not include switch IT3i but part of AMP1-1 includes switch IT0i.

[0119] In addition, Figure 5 In the example, part of AMP1-1 does not include switches IT4 and IT5, although those skilled in the art can add these switches based on the functional and structural description of pixel 1 above.

[0120] In addition, in order to prevent Figure 5 With more loads, the feedback loop FbLi (FbL1, FbL2), load stage LS, bias circuit B, and gain stage G of amplifier AMP1 are represented in block form.

[0121] In addition to the photodiode PDi, pixel 5 includes K photodiodes PDj', where K is an integer greater than or equal to 2, and j is an integer having a value in the range from 1 to K. Preferably, the photodiodes PDj' are island-shaped photodiodes.

[0122] exist Figure 5 In the example of the embodiment, K equals 2, and pixel 5 includes two photodiodes PD1' and PD2'.

[0123] Each photodiode PDj' of pixel 5 has an electrode or terminal coupled (preferably connected) to node IN2-2j of pixel 5.

[0124] In an embodiment, photodiode PD1' has a terminal (e.g., its cathode) coupled (preferably connected) to node IN2-21, and photodiode PD2' has a terminal (e.g., its cathode) coupled (preferably connected) to node IN2-22. Node IN2-2j will be associated with photodiode PDj'.

[0125] In an embodiment, the other terminals (e.g., anodes) of each photodiode PDj' are coupled (preferably connected) to node 100.

[0126] In this embodiment, pixel 5 also includes an amplifier AMP2 ( Figure 5(Not cited in the text). Amplifier AMP2 is, for example, a capacitive transimpedance amplifier CTIA. Amplifier AMP2 comprises, or more precisely is made of, the following: a first part AMP2-1, which is shared by all photodiodes PDj'; and a second part AMP2-2j, associated with each photodiode PDj'. Therefore, pixel 5 comprises K second parts AMP2-2j. More precisely, in Figure 5 In the example, amplifier AMP2 includes a second part AMP2-21 associated with photodiode PD1' and a second part AMP2-22 associated with photodiode PD2'.

[0127] The first part AMP2-1 of amplifier AMP2 is similar to or identical to the first part AMP1-1 of amplifier AMP1. However, nodes 102, 104, 106, and 108 of part AMP1-1 correspond to the corresponding nodes 102', 104', 106', and 108' in part AMP2-1. Therefore, part AMP2-1 of amplifier AMP2 includes nodes 102', 104', 106', and 108', transistor T1, load stage LS, gain stage G, and bias circuit B. The interconnection of these components with other components is related to... Figures 1 to 4 The interconnections of the corresponding elements 102, 104, 106, 106, T1, LS, G and B in the portion of amplifier AMP1-1 described are the same.

[0128] Transistor T1 of part of AMP2-1 is one of the two transistors in the differential pair of amplifier AMP2.

[0129] Transistor T1 has a gate coupled (preferably connected) to the input IN2-1 of amplifier AMP2. Input IN2-1 is configured, for example, to receive ground potential GND.

[0130] In the embodiments, although in Figure 5 As not shown, output 102 is coupled (e.g., connected) to the input of the first analog-to-digital converter, and output 102' is coupled (e.g., connected) to the input of the second analog-to-digital converter. Amplifier AMP1 and the first converter are, for example, part of the readout circuit of photodiode PDi of pixel 5, and amplifier AMP2 and the second converter are, for example, part of the readout circuit of photodiode PDj' of pixel 5.

[0131] Preferably, all the second parts AMP2-2j of the amplifier are structurally identical to each other, although the values ​​(e.g., capacitance values) or dimensions (e.g., channel length or width) of a given component in one of these parts AMP2-2j are different from the values ​​or dimensions of the same component in another second part AMP2-2j.

[0132] Each second part of amplifier AMP2, AMP2-2j, includes a MOS transistor T2j' ( Figure 5 (T21' and T22' in the example). Transistor T2j' in each of the second parts of AMP2-2j is the other of the two transistors in the differential pair of amplifier AMP2. Therefore, transistors T1 and T2j' are of the same type in both P-channel and n-channel configurations. Figure 5 In the example shown, transistor T1 is an NMOS transistor, but in other examples not shown, transistor T1 is a PMOS transistor.

[0133] In each section AMP2-2j of amplifier AMP2, the gate of transistor T2j' is coupled (preferably connected) to node IN2-2j associated with photodiode PDj'.

[0134] Additionally, each second section AMP2-2j of amplifier AMP2 includes a switch IT1j' ( Figure 5 IT11', IT12') and switch IT2j' ( Figure 5 (IT21' and IT22' in the example). In each section AMP2-2j of amplifier AMP2, switches IT1j' and IT2j' are configured such that when switches IT1j' and IT2j' are closed, transistor T2j' forms a differential pair of amplifier AMP2 with transistor T1 of section AMP2-1. Each switch IT1j' and IT2j' is implemented, for example, by at least one MOS transistor, using CMOS technology.

[0135] In each section AMP2-2j, switch IT1j' couples the source of transistor T2j' to the first section AMP2-1 of amplifier AMP2, similar to how switch IT1i couples the source of transistor T2i to section AMP1-1 of amplifier AMP1. Therefore, in each section AMP2-2i, switch IT1j' is connected between the source of transistor T2j' and section AMP2-1 of amplifier AMP2.

[0136] In an embodiment, in each section AMP2-2j of amplifier AMP2, the first conductive terminal of switch IT1j' is coupled (preferably connected) to section AMP2-1 of amplifier AMP2, and the second terminal of switch IT1j' is coupled (preferably connected) to the source of transistor T2j'.

[0137] In each section AMP2-2j, switch IT2j' couples the drain of transistor T2j' to the first section AMP2-1 of amplifier AMP2, similar to how switch IT2i couples the drain of transistor T2i to the first section AMP1-1 of amplifier AMP1. Therefore, in each section AMP2-2j, switch IT2j' is connected between the drain of transistor T2j' and section AMP2-1.

[0138] In an embodiment, in each section AMP2-2j of amplifier AMP2, the first conductive terminal of switch IT2j' is coupled (preferably connected) to section AMP2-1 of amplifier AMP2, and the second terminal of switch IT2j' is coupled (preferably connected) to the drain of transistor T2j'.

[0139] More specifically, according to one embodiment, the switch IT1j' of each second portion AMP2-2j of amplifier AMP2 is connected between the source of the corresponding transistor T2j' and the intermediate node 104' of portion AMP2-1 of amplifier AMP2 (i.e., the source of transistor T1 of amplifier AMP2), and the switch IT2j' of each second portion AMP2-2j of amplifier AMP2 is connected between the drain of the corresponding transistor T2j' and node 108' of amplifier AMP2.

[0140] exist Figure 5 In one embodiment, the source of transistor T1 of amplifier AMP2 is connected to node 104', and the drain of transistor T1 of amplifier AMP2 is connected to node 106'.

[0141] However, in another embodiment not shown, similar to the embodiment where portion AMP1-1 of amplifier AMP1 includes switches IT4 and IT5, portion AMP2-1 of amplifier AMP2 includes a switch connected between the source of transistor T1 of portion AMP2-1 and node 104', and a switch connected between the drain of transistor T1 of portion AMP2-1 and node 106'. Both switches are configured to remain closed (i.e., dummy switches).

[0142] The load stage LS of amplifier AMP2, the bias circuit B of amplifier AMP2, the load stage LS of amplifier AMP2, and the differential pair of amplifier AMP2 are part of the operational amplifier of amplifier AMP2.

[0143] According to one embodiment, each part AMP2-2j includes a feedback loop FbLj' of amplifier AMP2. Figure 5(FbL1', FbL2' in the diagram). Although not shown, preferably, each feedback loop FbLj' is structurally identical to feedback loop FbLi. Additionally, each feedback loop FbLj' has an end 116 connected to the corresponding node IN2-2j', in a manner similar to how each feedback loop FbLi has an end 116 connected to the corresponding node IN1-2i.

[0144] According to one embodiment, for each feedback loop FbLj', amplifier AMP2 includes a switch IT3j' associated with the feedback loop FbLj'. Figure 2 (IT31' and IT32' in the diagram). Switch IT3j' couples the other end 118 of feedback loop FbLj' to the output 102' of amplifier AMP2 in a manner similar to how switch IT3i couples the end 118 of feedback loop FbLi to the output 102 of amplifier AMP1 for each feedback loop FbLi.

[0145] In this embodiment, each feedback loop FbLj' is associated with a corresponding switch IT3j'. The switch IT3j' associated with each feedback loop FbLj' is configured, for example, to be in the same state (closed or open) as the switches IT1j' and IT2j' of the second part AMP2-2j having feedback loops FbLj'.

[0146] In this embodiment, each switch IT3j' is implemented using at least one MOS transistor, for example, using CMOS technology. Each portion AMP2-2j' includes a corresponding switch IT3j'.

[0147] According to one embodiment (not shown), for each feedback loop FbLj', and in addition to switch IT3j', amplifier AMP2 includes a supplementary switch associated with feedback loop FbLj' and belonging to a portion of AMP2-1 of amplifier AMP2. For each feedback loop FbLj', this supplementary switch couples end 118 of feedback loop FbLj' to output 102' of amplifier AMP2, in a manner similar to how switch IT0i couples end 118 of feedback loop FbLi to output 102' of amplifier AMP1 for each feedback loop FbLi.

[0148] According to one embodiment, for each feedback loop FbLj', a supplementary switch is connected in series with switch IT3j' between end 118 of feedback loop FbLj' and output 102' of amplifier AMP2. For each feedback loop FbLj', the supplementary switch is configured, for example, to be in the same state as switch IT3j' (closed or open connection).

[0149] In one embodiment, each supplementary switch is implemented using at least one MOS transistor, for example, using CMOS technology. According to an alternative embodiment, pixel 5 does not include switch IT3j'.

[0150] According to one embodiment, the control circuit CTRL is further configured to control switches IT1j', IT2j' and IT3j', or to couple the feedback loop FbLj' to each supplementary switch of the output 102 of AMP2.

[0151] According to one embodiment, pixel 5 includes a first color channel having a photodiode PDi and an amplifier AMP1, and a second color channel having a photodiode PDj' and an amplifier AMP2. Compared to embodiments in which all photodiodes PDi of the first channel and all photodiodes PDj' of the second channel share the same first portion of the same amplifier, this embodiment has the advantage that the reading of the first color channel can be performed simultaneously with the reading of the second color channel.

[0152] In combination Figure 5 In the described embodiments, although pixel 5 includes only two color channels, each having its own amplifier AMP1 or AMP2, those skilled in the art can adapt pixel 5 to the following embodiments: pixel 5 includes two or more different color channels, each having an amplifier similar to amplifiers AMP1 and AMP2.

[0153] In addition, although in Figure 5 In pixel 5, each color channel includes the same number of photodiodes, but those skilled in the art can adapt pixel 5 to cases where at least two color channels of pixel 5 have different numbers of photodiodes.

[0154] In the examples above of the embodiments and variations, transistors T1 and T2i, and in Figure 5 In the embodiments described, transistors T1' and T2j' are NMOS transistors. However, those skilled in the art can apply the described embodiments and variations to cases where these transistors are PMOS transistors, for example, by replacing transistors T3 and T4 with NMOS transistors. Figure 1 ), and by permutation the potential received by nodes 110 and 112.

[0155] In the examples above of the embodiments and variations, amplifiers AMP1 and AMP2 are capacitive transimpedance amplifiers (CTIA), although the embodiments and variations are also applicable to other amplifiers with operational amplifiers, such as integrator amplifiers.

[0156] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these embodiments can be combined and other variations will readily occur to them. For example, in at least some of the feedback loops FbLi or Fblj', the capacitor element Cfb can be a capacitor element with a controllable capacitance value. Additionally, in the sensor with multiple pixels as described above, the pixels and their readout circuitry can be comprised of the same and unique semiconductor layer (i.e., the same and unique chip). Alternatively, the pixels can be comprised of a first semiconductor layer (i.e., a first chip), while the readout circuitry of these pixels (except for a second portion of the amplifiers of these readout circuitry) can be comprised of a second semiconductor layer (i.e., a second chip—which is stacked on top of the first chip).

[0157] Finally, the actual specific implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art based on the functional descriptions provided above.

[0158] Although a detailed description has been provided, it should be understood that various changes, substitutions, and alterations may be made without departing from the spirit and scope of this disclosure as defined by the appended claims. In the various figures, the same elements are designated by the same reference numerals. Furthermore, the scope of this disclosure is not intended to be limited to the specific embodiments described herein, as those skilled in the art will readily recognize from this disclosure that existing or future processes, machines, manufactures, material compositions, apparatuses, methods, or steps can perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein. Therefore, the appended claims are intended to encompass such processes, machines, manufactures, material compositions, apparatuses, methods, or steps within their scope.

[0159] Therefore, the specification and drawings should be simply regarded as illustrations of this disclosure as defined by the appended claims, and are intended to cover any and all modifications, variations, combinations or equivalents falling within the scope of this disclosure.

Claims

1. A light sensor comprising a plurality of pixels, each pixel comprising: Multiple first photodiodes, each first photodiode including a node; as well as A first amplifier, the first amplifier comprising: The first part, which is common to each of the first photodiodes, includes: The output terminal corresponds to the output terminal of the first amplifier, and The first metal-oxide-semiconductor (MOS) transistor of the differential pair of the first amplifier, and Part Two, Part Two includes: The second metal-oxide-semiconductor (MOS) transistor of the differential pair has a gate terminal coupled to a corresponding node of the corresponding first photodiode. A feedback loop circuit, the feedback loop circuit having a first end connected to a node of the corresponding first photodiode, A first switch, which couples the source terminal of the second MOS transistor to the first portion of the first amplifier. The second switch couples the drain terminal of the second MOS transistor to the first portion of the first amplifier, and A third switch couples the second end of the feedback loop circuit to the output terminal of the first amplifier. The first part includes a fourth switch, which has a first terminal coupled to the output terminal of the first amplifier and a second terminal coupled to the third switch.

2. The optical sensor according to claim 1, wherein the first part comprises: The intermediate node of the differential pair is coupled to the source terminal of the first MOS transistor, wherein the first switch of each second portion is arranged between the source terminal of the second MOS transistor and the intermediate node. The first input node is coupled to the gate terminal of the first MOS transistor; as well as The load stage of the differential pair is coupled to the drain terminal of the first MOS transistor, wherein the second switch of each second portion is arranged between the load stage and the drain terminal of the second MOS transistor.

3. The optical sensor according to claim 2, wherein the first part comprises: A fourth switch is disposed between the source terminal of the first MOS transistor and the intermediate node; as well as A fifth switch is disposed between the drain terminal of the first MOS transistor and the load stage, and the fourth and fifth switches are in the closed position.

4. The optical sensor of claim 1, wherein each first photodiode belongs to only one of several groups, each group comprising at least one photodiode, wherein each pixel includes control circuitry configured to: Select each of the aforementioned groups selectively; Close the first switch and the second switch of the second portion of the first amplifier corresponding to the first photodiode associated with the selected group; Close the third switch corresponding to the first photodiode associated with the selected group; Disconnect the first switch and the second switch of the second portion of the first amplifier corresponding to the first photodiode associated with the unselected group; as well as Disconnect the third switch corresponding to the first photodiode associated with the unselected group.

5. The optical sensor of claim 1, wherein each feedback loop circuit includes a capacitor and a switch, wherein the capacitor and the switch of the feedback loop circuit are arranged in parallel between the first end of the feedback loop circuit and the second end of the feedback loop circuit.

6. The optical sensor according to claim 1, wherein the second MOS transistor is completely disposed at a distance of less than 50µm from the corresponding first photodiode.

7. The optical sensor of claim 1, wherein each pixel further comprises: Multiple second photodiodes, each second photodiode including a second node; as well as The second amplifier includes a first part and multiple second parts. The first portion of the second amplifier is shared by each of the second photodiodes and includes: The output terminal, which is the output terminal of the second amplifier, and The first metal-oxide-semiconductor MOS transistor of the second differential pair of the second amplifier, and Each second part of the second amplifier includes: The second differential pair has a second metal-oxide-semiconductor (MOS) transistor, which has a gate terminal coupled to a corresponding node of the corresponding second photodiode. A first switch, which couples the source terminal of the second MOS transistor to the first portion of the second amplifier, and The second switch couples the drain terminal of the second MOS transistor to the first part of the second amplifier.

8. The optical sensor of claim 7, wherein each pixel further comprises: The second feedback loop circuit has a first end connected to a node of the corresponding second photodiode; as well as The third switch couples the second end of the second feedback loop circuit to the output terminal of the second amplifier.

9. The optical sensor of claim 8, wherein each second portion of the second amplifier includes the third switch.

10. The optical sensor of claim 9, wherein the first portion of the second amplifier includes a fourth switch having: a first terminal coupled to an output terminal of the second amplifier, and a second terminal coupled to the third switch of the second amplifier.

11. The optical sensor of claim 7, wherein the first portion of the second amplifier comprises: The second intermediate node of the second differential pair is coupled to the source terminal of the first MOS transistor of the second differential pair, wherein the first switch of each second part of the second amplifier is arranged between the source terminal of the second MOS transistor of the second differential pair and the second intermediate node. The first input node is coupled to the gate terminal of the first MOS transistor of the second differential pair; as well as The second load stage of the second differential pair is coupled to the drain terminal of the first MOS transistor of the second differential pair, wherein the second switch of each second portion of the second amplifier is arranged between the second load stage and the drain terminal of the second MOS transistor of the second differential pair.

12. The optical sensor of claim 11, wherein the first portion of the second amplifier comprises: A fourth switch is disposed between the source terminal of the first MOS transistor of the second differential pair and the second intermediate node; as well as A fifth switch is disposed between the drain terminal of the first MOS transistor of the second differential pair and the second load stage, wherein the fourth switch of the first portion of the second amplifier and the fifth switch of the first portion of the second amplifier are in the closed position.

13. A method for reading a first photodiode from a plurality of photodiodes in a pixel of a light sensor, the method comprising: Select the first photodiode; Close the first and second switches of the second part of the first amplifier corresponding to the selected first photodiode; The second part includes: The second metal-oxide-semiconductor (MOS) transistor of the differential pair of the first amplifier has a gate terminal coupled to a corresponding node of the corresponding first photodiode. A first switch, which couples the source terminal of the second MOS transistor to a first part of the first amplifier. The second switch couples the drain terminal of the second MOS transistor to the first portion of the first amplifier, and A feedback loop circuit, the feedback loop circuit having a first end connected to the corresponding node of the corresponding first photodiode, A third switch, wherein the third switch couples the second end of the feedback loop circuit to the output terminal of the first amplifier; The first part includes a fourth switch, the fourth switch having a first terminal coupled to the output terminal of the first amplifier and a second terminal coupled to the third switch; Close the third switch corresponding to the selected first photodiode; Disconnect the first and second switches of the second section of the amplifier corresponding to the unselected first photodiode; and Disconnect the third switch corresponding to the unselected first photodiode. The first part is shared by each of the first photodiodes and includes: The output terminal is the output terminal of the first amplifier, and The first metal-oxide-semiconductor (MOS) transistor of the differential pair of the first amplifier.

14. The method of claim 13, wherein each pixel comprises: Multiple first photodiodes, each first photodiode including a node; A first amplifier, comprising the first portion and a plurality of second portions.

15. The method of claim 14, wherein the first portion comprises: The intermediate node of the differential pair is coupled to the source terminal of the first MOS transistor, wherein the first switch of each second portion is arranged between the source terminal of the second MOS transistor and the intermediate node; The first input node is coupled to the gate terminal of the first MOS transistor; as well as The load stage of the differential pair is coupled to the drain terminal of the first MOS transistor, wherein the second switch of each second portion is arranged between the load stage and the drain terminal of the second MOS transistor.

16. A pixel, comprising: Multiple first photodiodes, each first photodiode including a node; A first amplifier, the first amplifier comprising: The first part, which is common to each of the first photodiodes, includes: The output terminal corresponds to the output terminal of the first amplifier, and The first metal-oxide-semiconductor (MOS) transistor of the differential pair of the first amplifier, and Part Two, Part Two includes: The second metal-oxide-semiconductor (MOS) transistor of the differential pair has a gate terminal coupled to a corresponding node of the corresponding first photodiode. A first switch, which couples the source terminal of the second MOS transistor to the first portion of the first amplifier, and The second switch couples the drain terminal of the second MOS transistor to the first part of the first amplifier; Feedback loop circuit, the feedback loop circuit having a first end connected to the node of the corresponding first photodiode; and A third switch, which couples the second end of the feedback loop circuit to the output terminal of the first amplifier. The first part includes a fourth switch, which has a first terminal coupled to the output terminal of the first amplifier and a second terminal coupled to the third switch.

17. The pixel of claim 16, wherein each first photodiode belongs to only one of several groups, each group comprising at least one photodiode, wherein each pixel includes control circuitry configured to: Select each of the aforementioned groups selectively; Close the first switch and the second switch of the second portion of the first amplifier corresponding to the first photodiode associated with the selected group; Close the third switch corresponding to the first photodiode associated with the selected group; Disconnect the first switch and the second switch of the second portion of the first amplifier corresponding to the first photodiode associated with the unselected group; as well as Disconnect the third switch corresponding to the first photodiode associated with the unselected group.

Images