Semiconductor device

Abstract

The present application provides a semiconductor device that is simple to manufacture and has high reliability. An FLR structure 20 is provided in an edge termination region 2 as a voltage withstanding structure. The FLR structure 20 is composed of a plurality of FLRs 101-118 that surround the periphery of the active region 2 in a concentric manner. The impurity concentration of the FLRs 101-118 is in a range of less than 1 x 10 18 / cm 3 , preferably in a range of 3 x 10 17 / cm 3 or more and 9 x 10 17 / cm 3 or less. The thickness t10 of the FLRs 101-118 is 0.7 μm or more and 1.1 μm or less. The first interval w1 between the innermost FLR 101 and the outer peripheral p + -type region 62a is in a range of 1.2 μm or less.

Description

Technical Field

[0001] This invention relates to a semiconductor device. Background Technology

[0002] Previously, power semiconductor devices that control high voltage and high current included various types such as bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors, which were used differently depending on their applications.

[0003] For example, compared to MOSFETs, bipolar transistors (BJTs) and IGBTs have higher current densities and can handle large currents, but they cannot switch at high speeds. Specifically, the operating limit for BJTs is around a few kHz, and for IGBTs it is around tens of kHz. On the other hand, compared to BJTs and IGBTs, MOSFETs have lower current densities and are difficult to operate at large currents, but they can perform high-speed switching operations at several MHz.

[0004] Furthermore, unlike IGBTs, MOSFETs have a built-in p-type base region and an n-type base region inside the semiconductor substrate (semiconductor chip). - The parasitic diode (body diode) formed by the pn junction in the drift region. A MOSFET can utilize this internal parasitic diode as a freewheeling diode for self-protection. Therefore, MOSFETs do not require an external freewheeling diode for self-protection, which is also a cost-effective consideration.

[0005] While silicon (Si) is used as a constituent material for power semiconductor devices, there is a strong market demand for power semiconductor devices that combine high current and high speed. Efforts are focused on improving IGBTs and MOSFETs, and development has now reached near material limits. Therefore, from the perspective of power semiconductor devices, alternative semiconductor materials to silicon are being explored. Silicon carbide (SiC) is attracting significant attention as a next-generation power semiconductor material capable of producing devices with low on-state voltage, high-speed characteristics, and excellent high-temperature performance.

[0006] Silicon carbide is a chemically very stable semiconductor material with a wide bandgap of up to 3 eV, and it can be used as a semiconductor with extreme stability even at high temperatures. Furthermore, the maximum electric field strength of silicon carbide is more than an order of magnitude greater than that of silicon, thus making it a promising semiconductor material for significantly reducing on-resistance. These advantages of silicon carbide are not unique to silicon carbide; they are also present in all semiconductors with a wider bandgap than silicon (hereinafter referred to as wide-bandgap semiconductors).

[0007] Furthermore, in high-voltage semiconductor devices, high voltage is applied not only to the active region where the element structure is formed, but also to the edge termination region surrounding the active region, where the electric field is concentrated. The breakdown voltage of a semiconductor device is determined by the impurity concentration, thickness, and electric field strength of the semiconductor (drift region). Due to these inherent advantages of semiconductors, the breakdown capacity is equal from the active region to the edge termination region. Therefore, it is possible to apply an electrical load exceeding the breakdown capacity to the edge termination region due to the electric field concentration, leading to breakdown at the edge termination region.

[0008] Therefore, it is known to have voltage-resistant structures such as junction termination extension (JTE) structures and field limiting ring (FLR) structures in the edge termination region to mitigate or disperse the electric field in the edge termination region, thereby improving the overall voltage withstand capability of the semiconductor device. Additionally, it is known to have structures in which a floating potential metal electrode, i.e., a field plate (FP), in contact with the FLR is placed in the edge termination region, and the charge generated in the edge termination region is released, thereby improving the reliability of the semiconductor device.

[0009] The structure of conventional silicon carbide semiconductor devices will be explained. Figure 18 This is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. Figure 18 In the diagram, FLR221 and 222 are shown with different shading lines. Figure 18 The conventional semiconductor device 230 shown is a vertical MOSFET with a trench gate structure consisting of an active region 201 through which the main current flows and an edge termination region 202 surrounding the active region 201, on a semiconductor substrate 210 made of silicon carbide. The semiconductor substrate 210 is an n-type MOSFET with a trench gate structure on a semiconductor substrate 210 made of silicon carbide. + n-type epitaxial growth is sequentially performed on the initial substrate 271. - It is formed by epitaxial layers 272 and 273 of the p-type drift region 232 and the p-type base region 234.

[0010] A portion of the edge termination region 202 of the p-type epitaxial layer 273 is removed by etching, and a step 253 is formed on the front side of the semiconductor substrate 210 in the edge termination region 202. The front side of the semiconductor substrate 210 is demarcated by the step 253, and a second surface 210b, which is further outward (on the chip end (the end of the semiconductor substrate 210)) than the inner side (the chip center (the center of the semiconductor substrate 210) side), is recessed towards the drain electrode 252. Through this step 253, the p-type epitaxial layer 273 remains in a mesa-like form on the central side of the front side of the semiconductor substrate 210 (the main surface on the p-type epitaxial layer 273 side).

[0011] The first surface 210a and the second surface 210b of the front side of the semiconductor substrate 210 are respectively composed of p-type epitaxial layers 273 and n .... - An epitaxial layer 272 is formed. In the active region 201, a trench gate MOS gate is provided on the first surface 210a side of the front side of the semiconductor substrate 210. In the edge termination region 202, a MOS gate with a trench gate structure is selectively formed in the surface region of the second surface 210b of the front side of the semiconductor substrate 210. - Multiple p inside the epitaxial layer 272 - Type region (FLR) 221 and multiple p -- The type region (FLR) 222 constitutes a spatially modulated FLR structure 220. No field plate is provided.

[0012] The spatially modulated FLR structure 220 refers to a breakdown voltage structure in which the concentration of p-type impurities per unit volume decreases progressively towards the outer edges. Specifically, multiple FLRs 221 are arranged separately from each other and concentrically surround the active region 201. The wider (normal direction) of each FLR 221 is as it is positioned outwards, and the narrower the spacing between it and its adjacent inner FLR 221. The innermost FLR 222 surrounds all the FLRs 221 and is positioned between all the adjacent FLRs 221. The innermost FLRs 221 and 222 are electrically connected to the p-type base region 234 (234a).

[0013] Multiple FLRs 222 are arranged separately from each other and concentrically surround the active region 201. The further outward an FLR 222 is positioned, the narrower its width (width in the normal direction) and the narrower the spacing between it and its adjacent inner FLRs 222. Except for the innermost FLR 222, the multiple FLRs 222 are positioned further outward than the FLR 221. -The drift region 232 surrounds all the FLRs 221 and is configured between all adjacent FLRs 221. The optimal conditions for the width and configuration of these FLRs 221 and FLR 222 have been disclosed (for example, see Patent Documents 1 and 2 below).

[0014] Symbol 203 is the intermediate region between active region 201 and edge termination region 202. Symbol 210c is the third surface (the edge of the step) connecting the first surface 210a and the second surface 210b on the front side of semiconductor substrate 210. Symbols 231, 233, 235, 236, 238, 239, 240, 240a, 241, and 281-283 represent n... + n-type drain region, n-type current diffusion region, n + Type source pole region, p ++ Type contact area, gate insulating film, gate electrode, interlayer insulating film, contact hole, metal silicide film, field oxide film, gate polysilicon wiring layer and gate metal wiring layer.

[0015] Symbols 241-245 are the metal films constituting the barrier metal 246. Symbols 248 and 249 are the plating films constituting the wiring structure on the source pad 247 and the terminal pins, respectively. Symbols 250 and 251 are protective films (passivation films). Symbols 261 and 262 are p-values ​​used to mitigate the electric field near the bottom surface of the trench 237. + Type region. Symbols 262a, 234a, and 236a are p + Type 262, p-type base region 234 and p ++ The contact region 236 is the portion extending from the active region 201 to the intermediate region 203. The symbol 223 represents n. + Type of ditch cutoff area.

[0016] Another example of the structure of a conventional silicon carbide semiconductor device will be described. Figure 19 This is a cross-sectional view showing another example of the structure of a conventional silicon carbide semiconductor device. Figure 19 The conventional semiconductor device 260 shown is Figure 18 The difference between the conventional semiconductor device 230 shown is that the voltage withstand structure of the edge termination region 202 is set to a conventional FLR structure 290 instead of the spatial modulation type FLR structure 220. Figure 19 In the conventional semiconductor device 260 shown, it is also related to Figure 18 The conventional semiconductor device 230 shown also does not have a field plate, and the second surface 210b of the front side of the semiconductor substrate 210 is covered by an insulating layer such as a field oxide film 281 and an interlayer insulating film 240.

[0017] The typical FLR structure 290 is selectively disposed on the surface region of the second surface 210b on the front side of the semiconductor substrate 210. - Multiple (18 in this case) floating potentials inside the epitaxial layer 272 - The shape area (FLR (shaded area)) 291 is formed. The innermost FLR 291 is positioned at a point larger than p. + The portion of region 262 extending from active region 201 to intermediate region 203 (hereinafter referred to as peripheral p) + The outermost position of type region 262a, and the outer periphery p + Type region 262a is separated by a predetermined width (first interval) w211. Multiple FLRs 291 are configured separately from each other and concentrically surround the active region 201 with the intermediate region 203.

[0018] All FLR 291 have a roughly rectangular cross-sectional shape with approximately the same width w210, approximately the same thickness t201, and approximately the same impurity concentration. The impurity concentration of FLR 291 is higher than that of the peripheral p... + The impurity concentration in type 262a is low; for example, when the withstand voltage is set to around 1200V or higher, the impurity concentration of FLR 291 is 5 × 10⁻⁶. 18 / cm 3 Above and below. Multiple FLR 291s are arranged at approximately equal intervals (w212). Approximately the same width, thickness, spacing, and impurity concentration (approximately equal) means identical width, thickness, spacing, and impurity concentration within permissible tolerances caused by process variations.

[0019] All FLR291 in peripheral p + The type region 262a terminates at a shallower position closer to the front side of the semiconductor substrate 210. The thickness t201 of the FLR 291, measured from the second surface 210b of the front side of the semiconductor substrate 210, is, for example, about 0.4 μm to 0.5 μm. In order to obtain the same withstand voltage as that obtained by the spatial modulation type FLR structure 220 with the conventional FLR structure 290, the length w202 of the edge termination region 202 (the length from the middle region 203 to the chip end) needs to be increased to the length w201 of the edge termination region 202 when the withstand voltage structure is set to the spatial modulation type FLR structure 220 (refer to...). Figure 18 It is about twice the size of ), for example, becoming about 300μm.

[0020] Various disclosures exist regarding JTE structures and typical FLR structures (for example, see Patent Documents 3-9 below). Patent Document 3 discloses the location and impurity concentration range when a JTE structure is constructed using two p-type regions. Patent Document 4 discloses the p-type regions constituting the JTE structure... - The base region is positioned deep away from the front side of the semiconductor substrate, thereby mitigating the electric field applied to the end corners of the p-type base region and improving the breakdown voltage. In Patent Document 5 below, by progressively thinning the thickness of the p-type silicon carbide layer extending from the active region to the edge terminal region, a JTE structure with an effective reduction in impurity concentration towards the outside is formed.

[0021] Patent Document 6 below discloses a conventional FLR structure having a field plate. In Patent Document 6, a field plate, which is disposed on each FLR constituting the conventional FLR structure and separated by an interlayer insulating film, extends from the FLR to the portion (n) between adjacent FLRs. - (Type of drift region). By making the thickness of the portion of the interlayer insulating film covering the FLR greater than the thickness of the portion covering the adjacent FLRs, n - The thinner thickness of the drift region suppresses the effect of electrostatic capacitance of the interlayer insulating film, improving reliability without optimizing the structure of the field plate.

[0022] Patent documents 7-9 disclose a conventional FLR structure without an electric field plate. Patent documents 7 and 8 disclose a p-type structure that simultaneously forms an electric field near the bottom of the trench. + Type region and FLR(p) + The scheme is a type region). Furthermore, in Patent Document 8 below, by using FLR(p)... - The type region is positioned at a deep location away from the front side of the semiconductor substrate, so that the FLR and n - The pn junction of the drift region is separated from the front side of the semiconductor substrate, thereby suppressing the increase of electric field intensity at the outermost surface of the interlayer insulating film on the front side of the semiconductor substrate and suppressing the generation of surface breakdown at the outermost surface of the interlayer insulating film.

[0023] In Patent Document 9 below, by adjusting the spacing between the p-type well region of the active region and the innermost FLR, as well as the spacing between adjacent FLRs, for the depletion layer extending outward from the active region, these adjacent p-type regions are arranged close to each other, thereby suppressing the increased electric field intensity caused by the shape effect, which is caused by the curvature of the p-type diffusion region of the FLR that forms the p-type well region. Patent Document 9 discloses that the spacing between the p-type well region of the active region and the innermost FLR is set to 0 μm or more and 1 μm or less, and the spacing between adjacent FLRs increases by 0.5 μm each as they are arranged outward.

[0024] Existing technical documents

[0025] Patent documents

[0026] Patent Document 1: Japanese Patent No. 6323570

[0027] Patent Document 2: Japanese Patent No. 6610786

[0028] Patent Document 3: Japanese Patent Application Publication No. 2006-165225

[0029] Patent Document 4: Japanese Patent Application Publication No. 2018-022851

[0030] Patent Document 5: Japanese Patent Application Publication No. 2018-082056

[0031] Patent Document 6: Japanese Patent Application Publication No. 2010-050147

[0032] Patent Document 7: Japanese Patent Application Publication No. 2016-225455

[0033] Patent Document 8: Japanese Patent Application Publication No. 2019-054087

[0034] Patent Document 9: Japanese Patent No. 5011612 Summary of the Invention

[0035] Technical issues

[0036] However, in the aforementioned conventional spatial modulation type FLR structure 220 (refer to...) Figure 18 In the ion implantation process, deviations occur in the positions and impurity concentrations of the FLRs 221 and 222 constituting the FLR structure 220 due to variations in ion implantation precision. This reduces the overall quality of the FLR structure 220, potentially decreasing the reliability of the semiconductor device 230. On the other hand, as described above, in a typical FLR structure 290 (refer to...), Figure 19 In this process, the length w202 of the edge terminal region 202 becomes longer, which is uneconomical. Furthermore, the margin (safety margin) of the spacing w212 between adjacent FLRs 291 is small (see reference). Figure 12 (As in the past), the reliability of semiconductor devices becomes lower.

[0037] In order to solve the problems of the prior art, the present invention aims to provide a semiconductor device that is simple to manufacture and highly reliable.

[0038] Technical solution

[0039] To address the aforementioned issues and achieve the objectives of this invention, the semiconductor device of this invention is a semiconductor device having an active region for the flow of main current and a terminal region surrounding the active region, and has the following characteristics: A first semiconductor region of a first conductivity type is disposed within a semiconductor substrate made of a semiconductor with a bandgap wider than silicon. A second semiconductor region of a second conductivity type is disposed in the active region between a first main surface of the semiconductor substrate and the first semiconductor region. A predetermined element structure is formed in the active region by a pn junction between the second semiconductor region and the first semiconductor region.

[0040] The first electrode is electrically connected to the second semiconductor region. The second electrode is disposed on the second main surface of the semiconductor substrate. In the terminal region, a plurality of second conductivity-type breakdown voltage regions are selectively disposed separately within the first semiconductor region on the surface region of the first main surface of the semiconductor substrate. The plurality of second conductivity-type breakdown voltage regions concentrically surround the active region. The impurity concentration of the second conductivity-type breakdown voltage regions is less than 1 × 10⁻⁶. 18 / cm 3 Within the range. The thickness of the second conductive withstand voltage region is 0.7 μm or more and 1.1 μm or less.

[0041] Furthermore, the semiconductor device of the present invention is characterized in that, in the above-described invention, the impurity concentration of the second conductivity type withstand voltage region is 3 × 10⁻⁶. 17 / cm 3 Above and 9×10 17 / cm 3 Within the following range.

[0042] Furthermore, the semiconductor device of the present invention is characterized in that, in the above-described invention, it further comprises a second high-conductivity region, which is selectively disposed between the second semiconductor region and the first semiconductor region in a manner that contacts the second semiconductor region, and surrounds the active region. The impurity concentration of the second high-conductivity region is higher than that of the second semiconductor region. The second high-conductivity region is disposed between the active region and the second high-voltage region, and is opposite to the second high-voltage region in a direction parallel to the first main surface of the semiconductor substrate.

[0043] Furthermore, the semiconductor device of the present invention is characterized in that, in the above invention, the first interval between the innermost second conductivity type withstand voltage region and the second conductivity type high concentration region is in the range of 1.2 μm or less.

[0044] Furthermore, the semiconductor device of the present invention is characterized in that, in the above invention, the innermost second conductivity type withstand voltage region is in contact with the second conductivity type high concentration region.

[0045] Furthermore, the semiconductor device of the present invention is characterized in that, in the above invention, the second interval between the innermost second conductivity type withstand voltage region and the second second conductivity type withstand voltage region measured from the inner side is in the range of 2.1 μm or less.

[0046] Furthermore, the semiconductor device of the present invention is characterized in that, in the above invention, the third interval between the second second conductivity type withstand voltage region measured from the inside and the third second conductivity type withstand voltage region measured from the inside is in the range of 3.1 μm or less.

[0047] Furthermore, the semiconductor device of the present invention is characterized in that, in the above invention, the third interval is in the range of 1.0 μm or less.

[0048] Furthermore, the semiconductor device of the present invention is characterized in that, in the above invention, the fourth interval between the third second conductivity type withstand voltage region measured from the inside and the fourth second conductivity type withstand voltage region measured from the inside is in the range of 2.0 μm or less.

[0049] Furthermore, the semiconductor device of the present invention is characterized in that, in the above invention, the spacing between adjacent second conductivity type withstand voltage regions after the fourth one from the inside is wider than the first spacing.

[0050] Furthermore, the semiconductor device of the present invention is characterized in that, in the above invention, all of the plurality of second conductivity type withstand voltage regions have the same width.

[0051] Furthermore, the semiconductor device of the present invention is characterized in that, in the above invention, the width of the second conductivity type withstand voltage region after the second one from the inside is wider than the width of the innermost second conductivity type withstand voltage region.

[0052] Furthermore, the semiconductor device of the present invention is characterized in that, in the above invention, the second conductivity-type withstand voltage region reaches the first main surface of the semiconductor substrate.

[0053] Furthermore, the semiconductor device of the present invention is characterized in that, in the above-described invention, the second conductivity-type withstand voltage region is disposed at a depth position away from the first main surface of the semiconductor substrate. The first semiconductor region is located between the first main surface of the semiconductor substrate and the second conductivity-type withstand voltage region.

[0054] Furthermore, the semiconductor device of the present invention is characterized in that, in the above invention, the second conductive voltage-resistant region has a rectangular cross-sectional shape or a barrel-shaped cross-sectional shape with a relatively wide width at the center position in the depth direction.

[0055] Furthermore, the semiconductor device of the present invention is characterized in that, in the above invention, no conductive film is provided on the first main surface of the semiconductor substrate in the terminal region.

[0056] Furthermore, the semiconductor device of the present invention is characterized in that, in the above-described invention, the first main surface of the semiconductor substrate in the terminal region is covered by an insulating layer.

[0057] According to the invention described above, the margin between adjacent second conductive voltage-resistant regions can be increased, thus improving the completeness of the voltage-resistant structure. Furthermore, by increasing the margin between adjacent second conductive voltage-resistant regions, it becomes less susceptible to adverse effects from the precision of ion implantation used to form the second conductive voltage-resistant regions, making the design of the voltage-resistant structure easier.

[0058] Technical effect

[0059] The semiconductor device according to the present invention produces the effect of providing a semiconductor device that is simple to manufacture and highly reliable. Attached Figure Description

[0060] Figure 1 This is a top view showing the layout of the semiconductor device of Embodiment 1 as viewed from the front side of the semiconductor substrate.

[0061] Figure 2 It is shown Figure 1 A cross-sectional view of the structure at the cutting line A-A'.

[0062] Figure 3 This is a cross-sectional view showing the state of the semiconductor device during the manufacturing process of Embodiment 1.

[0063] Figure 4 This is a cross-sectional view showing the state of the semiconductor device during the manufacturing process of Embodiment 1.

[0064] Figure 5 This is a cross-sectional view showing the state of the semiconductor device during the manufacturing process of Embodiment 1.

[0065] Figure 6 This is a cross-sectional view showing the state of the semiconductor device during the manufacturing process of Embodiment 1.

[0066] Figure 7 This is a cross-sectional view showing the state of the semiconductor device during the manufacturing process of Embodiment 1.

[0067] Figure 8 This is a cross-sectional view showing the state of the semiconductor device during the manufacturing process of Embodiment 1.

[0068] Figure 9 This is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 2.

[0069] Figure 10 This is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 3.

[0070] Figure 11 This is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 4.

[0071] Figure 12 This is a characteristic diagram showing the result of simulating the relationship between the first gap between the main junction and the innermost FLR of the embodiment and the withstand voltage.

[0072] Figure 13 This is a characteristic graph showing the relationship between impurity concentration and withstand voltage in a simulated FLR from an experimental example.

[0073] Figure 14 This is a characteristic graph showing the relationship between the increase in the second interval between the first and second FLRs (counting from the inside) in a simulated experimental example and the withstand voltage.

[0074] Figure 15 This is a characteristic graph showing the relationship between the increase in the third interval between the second and third FLRs (counting from the inside) in a simulated experimental example and the withstand voltage.

[0075] Figure 16 This is a characteristic graph showing the relationship between the thickness and pressure resistance of the FLR in the simulated experimental example.

[0076] Figure 17 This is a characteristic graph showing the relationship between the number of FLRs and the withstand voltage of the simulated FLR structure in the experimental example.

[0077] Figure 18 This is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device.

[0078] Figure 19 This is a cross-sectional view showing another example of the structure of a conventional silicon carbide semiconductor device.

[0079] Symbol Explanation

[0080] 1: Active region; 2: Edge termination region; 3: Intermediate region; 10: Semiconductor substrate; 10a-10c: First to third surfaces of the front side of the semiconductor substrate; 20, 120, 140, 160: FLR structure; 21: n + Type-type channel cutoff region, 30, 100a~100c: semiconductor device, 31: n + Type-32:n drain region - 33: n-type drift region, 34: p-type base region, 34a: peripheral p-type base region, 35: n-type current diffusion region +Type source polar region, 36:p ++ Type contact area, 36a: peripheral p ++ Type contact area, 37: gate trench, 38: gate insulating film, 39: gate electrode, 40: interlayer insulating film, 40a, 40b: contact holes of interlayer insulating film, 41: NiSi film, 42: first TiN film, 43: first Ti film, 44: second TiN film, 45: second Ti film, 46: barrier metal, 47: Al electrode film, 48: plating film, 49: terminal lead, 50: first protective film, 51: second protective film, 52: drain electrode, 53: step, 61, 62, 91, 93: p + Type region, 62a: peripheral p + Type region, 71:n + Type starting substrate, 72, 72a, 72b:n - 73: p-type epitaxial layer; 81: field oxide film; 82: gate polysilicon wiring layer; 83: gate metal wiring layer; 92, 94: n-type regions; 101-118, 121-138, 141-158, 161-178: FLR; X: first direction parallel to the front side of the semiconductor substrate; Y: second direction parallel to the front side of the semiconductor substrate and orthogonal to the first direction; Z: depth direction; d1: p + The depth of the region, d2: adjacent p + The distance between the n-type intervals, d3: the depth of the n-type interval, t1, t2: n - Thickness of the p-type epitaxial layer, t3: thickness of the p-type epitaxial layer, t10~t13: thickness of the FLR, t20: total thickness of the insulating layer on the front side of the semiconductor substrate (on the FLR) in the edge termination region, w1, w41: thickness of the innermost FLR and the outermost p + The first interval between the type regions, wm: the m-th interval between the (m-1)-th FLR from the inside and the m-th FLR from the inside (where m = 2 to 18), wn: the (n-40)-th interval between the (n-41)-th FLR from the inside and the (n-40)-th FLR from the inside (where n = 42 to 58), w20: the length of the edge terminal region, w21, w30, w40, w60: the width of the FLR. Detailed Implementation

[0081] Hereinafter, preferred embodiments of the semiconductor device of the present invention will be described in detail with reference to the accompanying drawings. In this specification and the drawings, layers or regions prefixed with n or p respectively indicate cases where electrons or holes are the majority carriers. Furthermore, the + and - symbols marked with n and p respectively indicate that the impurity concentration is higher and lower than that of layers or regions not marked with + and -. It should be noted that in the following description of the embodiments and the accompanying drawings, the same symbols are used for the same components, and repeated descriptions are omitted.

[0082] (Implementation Method 1)

[0083] The structure of the semiconductor device in Embodiment 1 will be described. Figure 1 This is a top view showing the layout of the semiconductor device of Embodiment 1 as viewed from the front side of the semiconductor substrate. Figure 2 It is shown Figure 1 A cross-sectional view of the structure at the cutting line A-A'. Figure 1 , Figure 2 The semiconductor device 30 of Embodiment 1 shown is a vertical MOSFET with a trench gate structure (element structure) in the active region 1 of a semiconductor substrate (semiconductor chip) 10 made of silicon carbide (SiC), and a field limiting ring (FLR) structure 20 as a voltage withstand structure in the edge terminal region 2 surrounding the active region 1.

[0084] The active region 1 is the region where the main current (drift current) flows when the MOSFET (semiconductor device 30) is turned on. In the active region 1, multiple unit cells (components of components) of the same structure of MOSFETs are arranged adjacent to each other. The active region 1 has, for example, a generally rectangular planar shape and is disposed approximately at the center (chip center) of the semiconductor substrate 10. The active region 1 is the region further inward (chip center side) than the outer sidewall (side of the interlayer insulating film 40) of the outermost contact hole 40b (chip end side). The intermediate region 3 between the active region 1 and the edge termination region 2 is adjacent to the active region 1 and surrounds the perimeter of the active region 1.

[0085] The boundary between the intermediate region 3 and the edge termination region 2 is the boundary between the first surface 10a and the third surface 10c of the semiconductor substrate 10, described later. The edge termination region 2 is the region between the active region 1 and the end (chip end) of the semiconductor substrate 10, and surrounds the active region 1 with the intermediate region 3, and has the function of mitigating the electric field on the front side (first main surface) of the semiconductor substrate 10 to maintain withstand voltage. In the edge termination region 2, an FLR structure 20 is formed on the front side of the semiconductor substrate 10 as a withstand voltage structure. Withstand voltage refers to the limiting voltage at which avalanche breakdown occurs in the pn junction, and the voltage between the source and drain does not increase further even if the current between the source and drain is increased.

[0086] In the active region 1, a MOS gate is disposed on the front side of the semiconductor substrate 10. The MOS gate consists of a p-type base region 34 and an n-type base region 35. + Source region 35, p ++ The gate contact region 36, gate trench 37, gate insulating film 38, and gate electrode 39 are combined. The outermost periphery of the gate trench 37 (the portion of the outer periphery p-type base region 34a described later) is set to not have n + The source region 35 is constructed. The semiconductor substrate 10 is made of silicon carbide. + n-type starting substrate 71 is epitaxially grown sequentially on the front side to form n-type starting substrate 71. - It is formed by epitaxial layers 72 and 73 of the p-type drift region (first semiconductor region) 32 and the p-type base region (second semiconductor region) 34.

[0087] The main surface of the p-type epitaxial layer 73 side of the semiconductor substrate 10 is set as the front side, and the n-type epitaxial layer 73 side is set as the front side. + The main surface of the type starting substrate 71 is designated as the back surface (second main surface). + Type-starting substrate 71 is n + Drain region 31. A portion of the edge termination region 2 of the p-type epitaxial layer 73 is removed by etching, and a step 53 is formed on the front side of the semiconductor substrate 10. The front side of the semiconductor substrate 10 is bounded by step 53, and the portion 10a closest to the edge termination region 2 (second side) 10b extends towards the n-type epitaxial layer 10, compared to the portion 10a of the active region 1 and the intermediate region 3. + The leak area 31 is concave on one side.

[0088] The second surface 10b of the front side of the semiconductor substrate 10 is exposed by removing the p-type epitaxial layer 73. - The exposed surface of the p-type epitaxial layer 72. On the front side of the semiconductor substrate 10, at the portion connecting the first surface 10a and the second surface 10b (third surface: the mesa edge of step 53) 10c, the active region 1 and the intermediate region 3 are formed with the edge termination region 2 as a device isolation. The side surface of the p-type epitaxial layer 73 (the peripheral p-type epitaxial layer described later) is exposed on the third surface 10c of the front side of the semiconductor substrate 10. ++ (The ends of the p-type contact region 36a and the peripheral p-type base region 34a, which will be described later).

[0089] The outer periphery p (described later) can be arranged along the third surface 10c of the front side of the semiconductor substrate 10. ++ Type contact region 36a, peripheral p-type base region 34a and peripheral p + The connection method of type area 62a is set with p + Type region (not shown). When forming step 53, the underlying n layer can also be slightly removed together with the p-type epitaxial layer 73. -The surface region of the p-type epitaxial layer 72. The gate trench 37 extends from the first surface 10a of the front side of the semiconductor substrate 10 through the p-type epitaxial layer 73 to the n-type epitaxial layer 72 in the depth direction Z. - The epitaxial layer 72 is located inside.

[0090] The gate trench 37 extends in a stripe-like pattern in a direction parallel to the front side of the semiconductor substrate 10 (here, the first direction X) to reach the intermediate region 3. A gate electrode 39 is disposed inside the gate trench 37, separated by a gate insulating film 38. The p-type base region 34 is the p-type epitaxial layer 73 excluding the n-type base region. + Source region 35 and p ++ The portion other than the p-type contact area 36. The p-type base region 34 extends outward from the active region 1 (chip end side) to the third surface 10c of the front side of the semiconductor substrate 10.

[0091] The p-type base region 34 is disposed over the entire area of ​​the active region 1 and the intermediate region 3. The outer peripheral portion of the p-type base region 34 (hereinafter referred to as the outer peripheral p-type base region) 34a surrounds the periphery of the active region 1 in a generally rectangular manner. The outer peripheral p-type base region 34a refers to the portion of the p-type base region 34 that is larger than n in the first direction X (the direction of the long side of the gate trench 37). + The outermost portion of the source region 35, and the portion further outward than the outermost gate trench 37 in the second direction Y (short side direction of the gate trench 37) which is parallel to the front side of the semiconductor substrate 10 and orthogonal to the first direction X.

[0092] n + Source region 35 and p ++ The p-type contact region 36 is selectively disposed between the first surface 10a and the p-type base region 34 on the front side of the semiconductor substrate 10, respectively, in a manner that contacts the p-type base region 34, and is exposed on the first surface 10a of the front side of the semiconductor substrate 10. Here, "exposed on the first surface 10a of the front side of the semiconductor substrate 10" means that the n-type contact region 36 is exposed on the front side of the semiconductor substrate 10. + Source region 35 and p ++ The contact area 36 is in contact with the NiSi film 41 described later in the contact hole 40a of the interlayer insulating film 40.

[0093] n + The source region 35 is in contact with the gate insulating film 38 on the sidewall of the gate trench 37. ++ Type contact area 36 is configured to be more than n + The source region 35 is further away from the gate trench 37. The p-type base region 34, n... + Source region 35 and p ++ Type contact regions 36 extend, for example, along the long side of the gate trench 37 between adjacent gate trenches 37 (not shown). ++ The contact area 36 can also be dispersed in the first direction X.

[0094] In addition, p ++ The p-type contact region 36 is disposed over the entire area between the first surface 10a on the front side of the semiconductor substrate 10 and the outer p-type base region 34a, in a manner that contacts the outer peripheral p-type base region 34a. Hereinafter, this p-type base region 34a will be described... ++ The portion of the contact area 36 between the first surface 10a of the front side of the semiconductor substrate 10 and the outer p-type base region 34a is designated as the outer p-type base region. ++ Type contact area 36a. Peripheral p ++ The contact region 36a is in contact with the gate insulating film 38 on the sidewall outside the outermost gate trench 37.

[0095] Peripheral p ++ The contact area 36a is exposed on the first surface 10a of the front side of the semiconductor substrate 10. Here, the exposure of the first surface 10a of the front side of the semiconductor substrate 10 refers to the outer periphery p ++ The contact area 36a contacts the NiSi film 41 at the outermost contact hole 40b. (Outer periphery p) ++ Contact region 36a has a feature that allows holes accumulated in edge terminal region 2 due to switching of the MOSFET to pass through the outer peripheral p when the MOSFET is turned off. + The function of the p-type base region 62a and the peripheral p-type base region 34a to extract to the source electrode.

[0096] You can also omit setting p. ++ Type contact area 36 and peripheral p ++ Type contact area 36a. In this case, instead of p ++ Type contact area 36 and peripheral p ++ The p-type contact region 36a, the p-type base region 34, and the outer peripheral p-type base region 34a are exposed on the front side of the semiconductor substrate 10. Inside the semiconductor substrate 10, the p-type base region 34 and the outer peripheral p-type base region 34a are exposed on the front side of the semiconductor substrate 10. + Type 31 (n) + Between the type starting substrate 71), n ​​are provided in such a way that they contact these regions. - Type drift zone 32.

[0097] In the p-type base region 34 and the peripheral p-type base region 34a and n - Between the n-type drift regions 32, n-type current diffusion regions 33 and first p-type current diffusion regions 33 are selectively disposed respectively. + Type 61, Second p + n-type region 62. n-type current diffusion region 33 and first p + Type 61, Second p + The lower surface of the type region 62 is positioned n times closer to the bottom surface of the gate trench 37. + The n-type drain region 31 is located deeper on the side of the second p-type current diffusion region 33. +The upper surface of the n-type region 62 contacts the p-type base region 34. The n-type current diffusion region 33 and the first p-type base region 34... + Type 61, Second p + The type region 62 extends in a straight line along the long side of the gate trench 37 with approximately the same length as the gate trench 37.

[0098] The n-type current spreading region 33 is a so-called current spreading layer (CSL) that reduces the diffusion resistance of charge carriers. The n-type current spreading region 33 is located between adjacent gate trenches 37 and the first p... + Type 61 and second p + The n-type current diffusion region 62 is contacted. The n-type current diffusion region 33 can extend from the active region 1 to the intermediate region 3. Alternatively, the n-type current diffusion region 33 can be omitted. In this case, n - The p-type drift region 32 extends on the front side of the semiconductor substrate 10 and contacts the p-type base region 34.

[0099] First p + Type 61 and second p + Type region 62 has the function of mitigating the electric field applied to the bottom surface of the gate insulating film 38 of the gate trench 37. First p + Type 61 and second p + The depth of region 62 can be set appropriately. For example, the first p + Type 61, Second p + Type region 62 can terminate inside the n-type current diffusion region 33 and be surrounded by the n-type current diffusion region 33, or it can reach a depth position approximately the same as the n-type current diffusion region 33 in the depth direction Z, or it can reach a depth position n closer to the n-type current diffusion region 33. + The leak area 31 is located deeper than n. - Type drift region 32 contact.

[0100] First p + The p-type base region 61 is disposed separately from the p-type base region 34 and faces the bottom surface of the gate trench 37 in the depth direction Z. + Type region 61 can reach the bottom surface of gate trench 37. First p + Type region 61 can be a floating potential, but it can also be achieved through the first p + Type 61 and the second p + Other p are configured at predetermined positions between type 62. + Type region (not shown) or make the first p + A portion of type region 61 extends towards the second p + The shape area 62 extends to the side and at the predetermined position with the second p + Type 62 is electrically connected and fixed at the potential of the source electrode.

[0101] Second p + Type 62 with the first p + The p-type base region 61 and the gate trench 37 are separated and disposed between adjacent gate trenches 37, and are adjacent to the p-type base region 34 in the depth direction Z. Additionally, the second p-type base region 61... + Type region 62 (and below, referred to as peripheral p) + Type region (second conductivity type high concentration region) 62a) with the first p + The p-type base region 61 and the outermost gate trench 37 are separated and disposed outside the outermost gate trench 37, and are adjacent to the outermost p-type base region 34a in the depth direction Z. + Type 62a extends outward from active region 1 and is located in the entire area of ​​intermediate region 3.

[0102] Peripheral p + Type region 62a surrounds the active region 1 in a roughly rectangular shape and is connected to all the first p + Type 61, Second p + End connection of type 62. Outer periphery p + The type region 62a extends from the middle region 3 to a position further outward than step 53, and is exposed on the second surface 10b of the front side of the semiconductor substrate 10. (Outer periphery p) + Type region 62a may also be exposed on the third surface 10c of the front side of semiconductor substrate 10. Exposure on the second surface 10b and the third surface 10c of the front side of semiconductor substrate 10 means that it is in contact with the field oxide film 81 described later on the second surface 10b and the third surface 10c.

[0103] The first p is formed simultaneously + Type 61, Second p + Type 62 (including peripheral p) + In the case of type region 62a) and FLR 101-118 described later, the first p + Type 61, Second p + Type 62 (including peripheral p) + The impurity concentration in type region 62a) is, for example, less than 1 × 10⁻⁶. 18 / cm 3 Within a range of approximately 3×10, preferably, it can be, for example, 3×10 17 / cm 3 Above and 9×10 17 / cm 3 Within the range to the left and right below. Additionally, by using the second p... + The thickness (length in the depth direction Z) of the type region 62 is set to a range of approximately 0.7 μm to 1.1 μm, for example, so that the second p + Type 62 (including peripheral p)+ Type 62a) was formed simultaneously with FLR101 to 118, which will be described later.

[0104] n - In addition to the n-type current diffusion region 33, the first p-type epitaxial layer 72 has an epitaxial layer 72. + Type 61, Second p + Type 62 (including peripheral p) + Type 62a), FLR 101-118 (described later), and n (described later) + The portion outside the cut-off zone 21 of the channel is n - Type drift region 32. n - Type drift region 32 is set in these regions and n + Between type 31 and leak zone n. - The drift region 32 extends from the active region 1 to the chip end and is exposed at the end (side of the semiconductor substrate 10).

[0105] An interlayer insulating film 40 is disposed on approximately the entire front surface of the semiconductor substrate 10, covering all gate electrodes 39. In the active region 1, contact holes 40a and 40b are provided in the interlayer insulating film 40, penetrating the interlayer insulating film 40 in the depth direction Z. n is exposed in the contact hole 40a. + Source region 35 and p ++ Type contact area 36. Contact hole 40b is configured, for example, as a roughly rectangular shape surrounding the active area 1. The outer periphery p of contact hole 40b is exposed. ++ Type contact area 36a.

[0106] In the intermediate region 3 and the edge terminal region 2, the first surface 10a to the third surface 10c of the front side of the semiconductor substrate 10 are more slender than the outer periphery p. ++ The entire outer surface of the contact area 36a is covered by an insulating layer, which is formed by sequentially stacking a field oxide film 81 and an interlayer insulating film 40. No field plate (conductive film) is provided. The first to third surfaces 10c of the front side of the semiconductor substrate 10 in the middle region 3 and the edge terminal region 2 have a smaller outer periphery p-value than the surrounding surface. ++ The outermost surface of the contact area 36a is in contact with the field oxide film 81.

[0107] In the intermediate region 3, on the field oxide film 81, at a ratio to the outer periphery p ++ Further outward from the contact region 36a, a gate polysilicon (poly-Si) wiring layer 82 and a gate metal wiring layer 83, which serve as the gate flow channel, are stacked sequentially. The gate polysilicon wiring layer 82 and the gate metal wiring layer 83 are opposite to the end of the gate trench 37 in the depth direction Z, and are electrically connected to the gate electrode 39 at the end of the gate trench 37, thereby electrically connecting the gate electrode 39 to the gate pad (not shown).

[0108] In the surface region of the second surface 10b on the front side of the semiconductor substrate 10, in n - The epitaxial layer 72 is selectively provided with multiple p-type potentials that constitute the floating potential of the FLR structure 20. - The type region (FLR (second conductivity type withstand voltage region): shaded area), selectively provided with n on its outer side in a manner separate from the FLR structure 20. + Type-shaped channel cutoff section 21. The FLR structure 20 can be composed of 16 or more FLRs (here, 18 are used, marked with symbols 101 to 118 from the inside). FLRs 101 to 118 and n + The channel cut-off region 21 is exposed on the second surface 10b of the front side of the semiconductor substrate 10.

[0109] FLR 101~118 in peripheral p + On the outer side of type region 62a, they are separately arranged on the outer periphery p + Type region 62a and n + The active region 1 is concentrically surrounded by the channel cutoff region 21 and the intermediate region 3. The innermost FLR 101 among the plurality of FLRs 101 to 118 is parallel to the outer periphery in a direction parallel to the front surface of the semiconductor substrate 10. + Type region 62a is opposite. The outermost FLR 118 among the plurality of FLRs 101 to 118 is parallel to n in a direction parallel to the front surface of the semiconductor substrate 10. + Type 21 truncated trench section is opposite.

[0110] All FLRs 101-118 are surrounded by n - The drift zone is surrounded by 32. The innermost FLR101 and the outermost p... + Between type 62a, between adjacent FLRs 101 to 118, and between the outermost FLR 118 and n + n are arranged between the cut-off sections 21 of the trench. - Type drift region 32. Through these FLR101~118 and n - The pn junction of the drift region 32 is used to bear the high voltage applied to the edge termination region 2 when the MOSFET is turned off, and to ensure the predetermined withstand voltage of the edge termination region 2.

[0111] The innermost FLR 101 and the outermost p + The first interval w1 between the type regions 62a is preferably within a range of about 1.2 μm or less. The innermost FLR 101 and the outer periphery p + The first interval w1 between type regions 62a refers to the outer periphery p + Type region 62a and n -The spacing between the pn junction (main junction) of the drift region 32 and the innermost (first from the inside) FLR 101. The lower the breakdown voltage of the semiconductor device 30, the closer the innermost FLR 101 is to the outer pn junction. + The first interval w1 between type regions 62a is set to be narrower.

[0112] The innermost FLR 101 can be set to be adjacent to the outer p + The position where the type region 62a is in contact (w1 = 0.0 μm) can also be set at the position where it is in contact with the outer periphery p. + The overlapping and contacting positions of type region 62a (w1 < 0.0 μm). For example, in the case of a semiconductor device 30 with a withstand voltage of 600V, the innermost FLR 101 is in contact with the outer periphery p. + The contact configuration is as follows: FLR 101, located on the innermost side, contacts the outer periphery p. + In the case of contact in region 62a, compared to the innermost FLR 101 and the outer p + In the case of separation of type region 62a, the second interval w2 to the 18th interval w18 between adjacent FLRs 101 to 118 are set wider.

[0113] The lower the breakdown voltage of the semiconductor device 30, the narrower the second to 18th intervals w2 to w18 between adjacent FLRs 101 to 118 are set. The second to 18th intervals w2 to w18 between adjacent FLRs 101 to 118 widen by a predetermined increment (width in the normal direction) as they are positioned further outwards. The normal direction refers to the direction from the active region 1 side (inner side) towards the chip edge. For example, when the increment is 0.1 μm, the j-th interval wj between adjacent FLRs 102 to 118 becomes a value obtained by adding 0.1 μm to the k-th interval wk between the inner adjacent FLRs 101 to 117 (j = 2 to 18, k = j-1).

[0114] At the innermost FLR 101 and the outer p + When the type region 62a is in contact, the FLRs from the innermost FLR 101 to the fourth FLR 104 counting from the inside can be configured according to the following conditions. The second interval w2 between the innermost FLR 101 and the second FLR 102 counting from the inside can be set to a range of approximately 2.1 μm or less, for example. The third interval w3 between the second FLR 102 and the third FLR 103 counting from the inside can be set to a range of approximately 3.1 μm or less, preferably, to a range of approximately 1.0 μm or less.

[0115] When the third interval w3 between the second FLR 102 (counting from the inside) and the third FLR 103 (counting from the inside) is set to approximately 1.0 μm or less, the fourth interval w4 between the third FLR 103 (counting from the inside) and the fourth FLR 104 (counting from the inside) can, for example, be set to approximately 2.0 μm or less. Between the innermost FLR 101 and the outermost p... + In the case of separation of type region 62a, the 5th interval w5 to the 18th interval w18 between the 4th and 118th FLRs from the inside can be compared with the innermost FLR 101 and the outer periphery p. + The width of the first interval w1 between type regions 62a.

[0116] All FLRs 101-118 are formed with the same structure and have approximately the same width (width in the normal direction) w21, approximately the same thickness (length in the depth direction Z) t10, and approximately the same impurity concentration. The width w21 of FLRs 101-118 is, for example, the width w210 of FLR 291 in the conventional FLR structure 290 (see reference). Figure 19 Approximately half the thickness of 1 / 2, specifically, for example, between 5μm and 15μm (1200V withstand voltage). The thickness t10 of FLR 101-118 is, for example, the thickness t201 of the conventional FLR structure 290, FLR 291 (refer to...). Figure 19 It is about twice that of ), specifically, for example, about 0.7μm above and 1.1μm below.

[0117] By making the thickness t10 of FLRs 101-118 thicker than the thickness t201 of FLR 291 in the conventional FLR structure 290, the electric field applied to FLRs 101-118 when the semiconductor device 30 is turned off can be mitigated compared to the conventional FLR structure 290. Therefore, compared to the conventional FLR structure 290, the width w21 of FLRs 101-118, the innermost FLR 101, and the outer periphery p... + The first interval w1 between type regions 62a and the second interval w2 to the 18th interval w18 between adjacent FLRs 101 to 118 become narrower.

[0118] The length of the edge termination region 2 (the length from the middle region 3 to the chip end) w20 is the length w202 of the conventional FLR structure 290 with the same number (18) of FLR 291 (see reference). Figure 19 Approximately half of the length of the edge terminal region 202 of the spatially modulated FLR structure 220 is represented by the length w201 (see reference). Figure 18The cross-sectional area of ​​each FLR 101 to 118 is approximately the same as that of the conventional FLR structure 290, and is approximately 100 μm to 200 μm in the case of a withstand voltage of 1200V.

[0119] In this way, by setting all FLRs 101 to 118 to have an elongated cross-sectional shape in the depth direction Z, even if the insulating layer (field oxide film 81, interlayer insulating film 40, and first protective film 50) on the second surface 10b of the semiconductor substrate 10 accumulates charge due to the prolonged conduction of the MOSFET, it is difficult to be adversely affected by the charge. The FLRs 102 to 118 from the second innermost FLR can also be wider than the width w21 of the innermost FLR 101. In this case, all FLRs 102 to 118 from the second innermost FLR are set to approximately the same width w21.

[0120] The adverse effects caused by the charge in the insulating layer refer to the suppression of n in the edge terminal region 2 due to the positive charge in the insulating layer when it is positively (plus) charged. - The expansion of the depletion layer within the drift region 32. Additionally, when the insulating layer is minus charged, the n in the edge termination region 2... - The potential within the drift region 32 is easily pulled outward by the negative charge in the insulation layer, thus extending outward. Because it is less susceptible to the adverse effects of the charge accumulated in the insulation layer, the withstand voltage characteristics of the FLR structure 20 can be stabilized.

[0121] The impurity concentration of FLR 101-118 is higher than that of FLR 291 (referencing the conventional FLR structure 290) which constitutes the FLR structure 290. Figure 19 The impurity concentration is low, for example, less than 1 × 10⁻⁶. 18 / cm 3 Within the range of approximately 100°C. Preferably, the impurity concentration of FLR101 to 118 can be, for example, 3 × 10⁻⁶. 17 / cm 3 Above and 9×10 17 / cm 3 Within the range to the left and right, for example, it can be 5×10 17 / cm 3 The lower the withstand voltage of the semiconductor device 30, the higher the impurity concentration of FLR 101-118 can be set.

[0122] By making the impurity concentration of FLR101-118 lower than that of FLR 291 constituting the conventional FLR structure 290, the electric field applied to FLR101-118 when the semiconductor device 30 is turned off can be mitigated compared to the conventional FLR structure 290. Therefore, compared to the conventional FLR structure 290, the width w21 of FLR101-118, the innermost FLR101, and the outer periphery p can be made more uniform. + The first interval w1 between type regions 62a and the second interval w2 to the 18th interval w18 between adjacent FLR101 to 118 become narrower.

[0123] FLR 101~118 can be compared with the first p + Type 61, Second p + Type 62 (including peripheral p) + Type 62a) forms simultaneously. FLR 101~118 can reach a level higher than the first p + Type 61, Second p + Type 62 (including peripheral p) + Type 62a) near n + The leak is located deeper on the side of type 31. In this case, it is similar to FLR101~118 at n + Leakage area 31 is located on the side of the first p + Type 61, Second p + Compared to the case where the same depth position is in type 62, the second interval w2 to the 18th interval w18 between adjacent FLR101 to 118 are set wider.

[0124] n + The channel cutoff section 21 is set separately from the FLR structure 20 on the outside of the FLR structure 20. + The channel cutoff region 21 is exposed at the end of the semiconductor substrate 10. This is achieved by setting n... + Type 21 trench cutoff zone, and no n + Compared to the case of channel cutoff region 21, it can suppress the n-channel cutoff region during MOSFET turn-off. - The depletion layer extends outward from the active region 1 within the drift region 32. No channel cutoff electrode is provided (not shown).

[0125] In replacing n + Type 21 trench cutoff zone and set p + Even with a truncated channel section (not shown), it is still possible to obtain the same result as n. + The same effect is achieved with the channel cutoff region 21. When the conditions of the FLR structure 20 are set such that even if a negative charge accumulates in the insulating layer on the second surface 10b of the semiconductor substrate 10, the MOSFET will be turned off at n... -If the depletion layer extending outward from the active region 1 within the drift region 32 does not reach the chip edge, then n may not be required. + Type 21 ditch cutoff zone.

[0126] The second surface 10b and the third surface 10c of the front side of the semiconductor substrate 10 are covered by an insulating layer formed by sequentially stacking a field oxide film 81 and an interlayer insulating film 40, as described above. This insulating layer covers FLRs 101 to 118 and n on the second surface 10b of the front side of the semiconductor substrate 10. + Type 21 channel cutoff zone, and n regions sandwiched between these zones. - Type drift region 32. The first protective film 50 (passivation film) is a surface protective film that covers the entire front side of the semiconductor substrate 10 and protects the front side of the semiconductor substrate 10.

[0127] The total thickness t20 of the field oxide film 81, the interlayer insulating film 40, and the first protective film 50 is greater than or equal to the thickness of the gate insulating film 38, and only needs to be thick enough to withstand the applied voltage. Specifically, for example, when the withstand voltage of the MOSFET is 1700V, the total thickness t20 is approximately 1.7μm or greater. The nickel silicide (NixSiy, where x and y are integers, hereinafter collectively referred to as NiSi) film 41 makes 10-ohm contact with the semiconductor substrate inside the contact holes 40a and 40b, and is in contact with n + Source region 35 and p ++ Type 36 contact area electrical connection.

[0128] NiSi film 41 is in contact hole 40b and peripheral p ++ Type 36a contact area electrical connection. Without setting p... ++ Type contact area 36 and peripheral p ++ In the case of contact area 36a, replacing p ++ Type contact area 36 and peripheral p ++ The p-type contact region 36a, the p-type base region 34, and the outer peripheral p-type base region 34a are exposed in the contact holes 40a and 40b, respectively, and are electrically connected to the NiSi film 41. A barrier metal 46 is provided along the entire surface of the interlayer insulating film 40 and the NiSi film 41 in the active region 1.

[0129] The barrier metal 46 has the function of preventing mutual reactions between the metal films of the barrier metal 46 or between the regions sandwiching opposite each other. The barrier metal 46 may, for example, have a stacked structure formed by sequentially stacking a first titanium nitride (TiN) film 42, a first titanium (Ti) film 43, a second TiN film 44, and a second Ti film 45. The first TiN film 42 covers the entire surface of the interlayer insulating film 40 in the active region 1. The first Ti film 43 is disposed on the entire surface of both the first TiN film 42 and the NiSi film 41.

[0130] A second TiN film 44 is disposed over the entire surface of the first Ti film 43. A second Ti film 45 is disposed over the entire surface of the second TiN film 44. An aluminum (Al) electrode film 47 is disposed over the entire surface of the second Ti film 45. The Al electrode film 47 is connected to the NiSi film 43 via a barrier metal 46 and a NiSi film 41. + Source region 35, p ++ Type contact area 36 and peripheral p ++ The contact area 36a is electrically connected. The Al electrode film 47 and the barrier metal 46 terminate at a position inside the gate metal wiring layer 83, which will be described later, compared to the intermediate region 3.

[0131] The Al electrode film 47 can be, for example, an Al film, an aluminum-silicon (Al-Si) film, or an aluminum-silicon-copper (Al-Si-Cu) film with a thickness of about 5 μm. The Al electrode film 47, the barrier metal 46, and the NiSi film 41 function as the source electrode (first electrode). On the Al electrode film 47, one end of the terminal pin 49 is bonded through a plating film 48 and a solder layer (not shown). The other end of the terminal pin 49 is bonded to a metal rod (not shown) disposed opposite to the front side of the semiconductor substrate 10.

[0132] Additionally, the other end of terminal pin 49 protrudes from the outside of the housing (not shown) on which the semiconductor substrate 10 is mounted, and is electrically connected to an external device (not shown). Terminal pin 49 is solder-bonded to the plating film 48 in a state that is substantially perpendicular to the front side of the semiconductor substrate 10. Terminal pin 49 is a rod-shaped (cylindrical) wiring component with a predetermined diameter corresponding to the current capability of the MOSFET, and is connected to the external ground potential (lowest potential). Terminal pin 49 is an external connection terminal for extracting the potential of the Al electrode film 47 to the outside.

[0133] The first protective film 50 and the second protective film 51 are, for example, films of highly heat-resistant organic polymer materials such as polyimide. The first protective film 50 covers the surface of the Al electrode film 47 except for the plating film 48. The first protective film 50 extends to the chip end in a manner that covers the Al electrode film 47, the interlayer insulating film 40, and the gate metal wiring layer 83, and functions as a passivation film. The portion of the Al electrode film 47 exposed at the opening of the first protective film 50 becomes the source pad. The second protective film 51 covers the boundary between the plating film 48 and the first protective film 50.

[0134] The front side of the semiconductor substrate 10 only needs to be in the edge terminal region 2 n -The epitaxial layer can be exposed on the front side of the semiconductor substrate 10, or it can be a flat surface that runs continuously from the active region 1 to the chip edge without step 53. The drain electrode (second electrode) 52 is located on the back side (n) of the semiconductor substrate 10. + The entire surface of the back side of the type-starting substrate 71 is in ohmic contact. On the drain electrode 52, for example, a drain pad (electrode pad: not shown) is provided in a stacked structure consisting of a Ti film, a nickel (Ni) film and a gold (Au) film stacked in sequence.

[0135] By bonding the terminal pins 49 to the Al electrode film 47 on the front side of the semiconductor substrate 10 and bonding the drain pads on the back side to the metal substrate of the insulating substrate, the semiconductor substrate 10 becomes a dual-sided cooling structure with cooling structures on both main surfaces. The heat generated in the semiconductor substrate 10 is dissipated from the fin portion of the cooling fins via the metal substrate bonded to the drain pads on the back side of the semiconductor substrate 10, and from the metal rod bonded to the terminal pins 49 on the front side of the semiconductor substrate 10.

[0136] The operation of the semiconductor device 30 in Embodiment 1 will be explained. When a positive voltage (forward voltage) is applied to the drain electrode 52 relative to the source electrode (Al electrode film 47), if a voltage greater than or equal to the gate threshold voltage is applied to the gate electrode 39, a channel (n-type inversion layer) is formed in the portion of the p-type base region 34 along the gate trench 37. This allows current to flow from the n-type base region 34. + Type 31 leaks towards n through the channel. + The current in the source region 35 turns the MOSFET on.

[0137] On the other hand, when a positive voltage is applied between the source and drain, and a voltage less than the gate threshold voltage is applied to the gate electrode 39, in the active region 1, the first p + Type 61, Second p + Type 62 and p-type base region 34 and n-type current diffusion region 33 and n - The pn junction of the type drift region 32 is reverse biased, thereby preventing current flow and keeping the MOSFET off. At this time, because the pn junction is reverse biased, the depletion layer extends from the pn junction, ensuring the breakdown voltage of the active region 1.

[0138] Furthermore, when the MOSFET is turned off, the depletion layer extending from the pn junction in the active region 1 is affected by the FLR 101~118 in the edge termination region 2 and n -The pn junction of the drift region 32 extends outward along the normal direction (towards the chip end) in the edge termination region 2. Corresponding to the amount by which the depletion layer extends outward in the edge termination region 2, a predetermined withstand voltage can be ensured for the silicon carbide-based insulation breakdown electric field strength and the width of the depletion layer (the width from the active region 1 toward the chip end (the normal direction of the concentrically arranged FLRs 101 to 118)).

[0139] Furthermore, when the MOSFET is turned off, a negative voltage is applied to the drain electrode 52 relative to the source electrode (Al electrode film 47), thereby enabling a positive voltage to be applied from the first p... + Type 61, Second p + Type 62 and p-type base region 34 and n-type current diffusion region 33 and n - Current flows through the parasitic diode formed by the pn junction of the drift region 32. For example, when the MOSFET is an inverter device, a parasitic diode built into the semiconductor substrate 10 can be used as a freewheeling diode to protect the MOSFET itself.

[0140] Next, the manufacturing method of the semiconductor device 30 according to Embodiment 1 will be described. Figures 3-8 This is a cross-sectional view showing the state during the manufacturing process of the semiconductor device according to Embodiment 1. Figures 3-8 The active region 1 is shown in the figure. The edge terminal region 2 and the intermediate region 3 are referenced. Figure 2 Here, we will take the case where each part of the edge terminal region 2 and the intermediate region 3 are formed simultaneously with each part of the active region 1, and the case where the same impurity concentration and depth are formed simultaneously.

[0141] First, such as Figure 3 As shown, n is prepared from silicon carbide. + Type-based starter substrate (starter wafer) 71. Next, on n + On the front side of the type-starting substrate 71, epitaxial growth is performed at a ratio of n + Type 71 starting substrate with low concentration of nitrogen doped n - Type epitaxial layer 72a(72). In the case of a withstand voltage rating of 3300V, n - The thickness t1 of the epitaxial layer 72 is, for example, about 30 μm. Under a voltage rating of 1200V, n - The thickness t1 of the epitaxial layer 72 is, for example, about 10 μm.

[0142] Next, as Figure 4 As shown, through photolithography and ion implantation of p-type impurities such as Al, n in the active region 1 - The surface region of the epitaxial layer 72 forms the first p + Type 61 and becoming the second p+ p, a part of type region 62 + Type region 91. At this time, in n - The surface region of the epitaxial layer 72, and the first p + Type 61 simultaneously forms peripheral p + Type 62a and each p that becomes part of FLR101-118 + Type 91.

[0143] Next, through photolithography and ion implantation of n-type impurities such as nitrogen (N), in n - The surface region of the epitaxial layer 72 forms an n-type region 92, which becomes part of the n-type current diffusion region 33. This is used to form the p-type current diffusion region. + Ion implantation in type regions 61 and 91 and n-type region 92 can be multi-stage ion implantation, where a predetermined dose is implanted multiple times (in multiple stages) under different conditions. Alternatively, p-type regions can be interchanged. + The formation order of type regions 61, 91 and n-type region 92.

[0144] In the active region 1, p are adjacent to each other + The distance d2 between type regions 61 and 91 is, for example, approximately 1.5 μm. Regarding p... + For regions 61 and 91, for example, the depth d1 is set to about 0.5 μm, and the impurity concentration is set to less than 1.0 × 10 as described above. 18 / cm 3 The depth d3 and impurity concentration of the n-type region 92 are, for example, approximately 0.4 μm and 1.0 × 10⁻⁶ μm, respectively. 17 / cm 3 Above and 5.0×10 18 / cm 3 Below, left and right.

[0145] Next, as Figure 5 As shown, in n - On the epitaxial layer 72a, an n-type impurity doped with nitrogen or other impurities is further epitaxially grown to a thickness t2 of approximately 0.5 μm. - Type epitaxial layer 72b(72), making n - The epitaxial layer 72 is of a predetermined thickness. - The impurity concentration of the epitaxial layer 72 (72a, 72b) is, for example, 3 × 10⁻⁶. 15 / cm 3 about.

[0146] Next, through photolithography and ion implantation of p-type impurities such as Al, in the active region 1, in n - The epitaxial layer 72b is formed as the second p + p, a part of type region 62 + Type region 93. At this time, in n- Type epitaxial layer 72b, and the p + Type 93 simultaneously forms peripheral p + Type 62a and each p that becomes part of FLR 101-118 + Type 93.

[0147] Next, through photolithography and ion implantation of n-type impurities such as nitrogen, in the n - An epitaxial layer 72b is formed as part of an n-type current diffusion region 33, forming an n-type region 94. Adjacent to the p-type region in the depth direction Z are... + Type regions 91 and 93 are connected to form the second p. + Type 62, peripheral p + Type regions 62a and FLR 101-118. Adjacent n-type regions 92 and 94 in the depth direction Z are connected to each other to form an n-type current diffusion region 33.

[0148] The thickness t10 of FLR 101–118 is set such that even after the surface area of ​​FLR 101–118 is slightly removed after the formation of step 53, the thickness t10 remains within the aforementioned range (e.g., approximately 0.7 μm to 1.1 μm). + The impurity concentration and other conditions in type 93 and n-type 94 are respectively related to p + Type 91 and n-type 92 are the same. P can also be swapped. + The formation order of type 93 and n-type region 94.

[0149] Next, as Figure 6 As shown, in n - A p-type epitaxial layer 73, doped with p-type impurities such as aluminum, is epitaxially grown on the p-type epitaxial layer 72. The thickness t3 and impurity concentration of the p-type epitaxial layer 73 are, for example, approximately 1.3 μm and 4 × 10⁻⁶ μm, respectively. 17 / cm 3 Left and right. Through the processes up to this point, the task at n is completed. + A semiconductor substrate (semiconductor wafer) 10 is obtained by sequentially stacking epitaxial layers 72 and 73 on a type starting substrate 71.

[0150] Next, by etching away the portion of the p-type epitaxial layer 73 on the edge termination region 2 side, a step 53 is formed on the front side of the semiconductor substrate 10, where the portion of the edge termination region 2 (second surface 10b) is lower than the portion of the active region 1 and the intermediate region 3 (first surface 10a). At this time, etching can be stopped by using the condition (stopper) that the FLRs 101 to 118 in the edge termination region 2 are exposed on the front side of the semiconductor substrate 10.

[0151] By stopping the etching process for forming the step 53 immediately after the FLRs 101-118 are exposed on the front side of the semiconductor substrate 10, the FLRs 101-118 can be retained at a predetermined thickness t10. Therefore, the predetermined breakdown voltage based on the design conditions of the FLR structure can be reliably obtained. - The epitaxial layer 72 is exposed in the edge terminal region 2 on the second surface 10b, which is now the front side of the semiconductor substrate 10.

[0152] The third surface 10c, which connects the first surface 10a and the second surface 10b on the front side of the semiconductor substrate 10, can be at an obtuse angle (tilted surface) relative to the first surface 10a and the second surface 10b, or it can be approximately right-angled (vertical surface) relative to the first surface 10a and the second surface 10b. The p-type epitaxial layer 73 is exposed on the third surface 10c on the front side of the semiconductor substrate 10. By etching to form this step 53, n-type epitaxial layers can be formed together with the p-type epitaxial layer 73. - The surface area of ​​the epitaxial layer 72 is slightly removed.

[0153] Next, n-type epitaxial layers 73 are selectively formed on their surface regions using photolithography and ion implantation under predetermined conditions. + Source region 35, p ++ Type contact area 36 and peripheral p ++ Type contact region 36a. Through ion implantation, in the edge termination region 2, on the second surface 10b exposed on the front side of the semiconductor substrate 10, n... - n is selectively formed on the surface region of the epitaxial layer 72. + Type 21 ditch cutoff zone.

[0154] n + Source region 35, p ++ Type contact area 36, ​​peripheral p ++ Type contact areas 36a and n + The formation order of the channel cutoff region 21 can be changed. For example, n can be formed simultaneously. + Source region 35 and n + Type 21 channel cutoff zone. n can also be formed before the formation of step 53. + Source region 35, p ++ Type contact area 36 and peripheral p ++ Type contact area 36a.

[0155] Next, a heat treatment (hereinafter referred to as activation annealing) is performed to activate the impurities implanted into the epitaxial layers 72 and 73. Activation annealing can be performed once after all diffusion regions have been formed by ion implantation, or it can be performed each time a diffusion region is formed by ion implantation. The temperature and time of activation annealing can be, for example, approximately 1700°C and approximately 2 minutes, respectively.

[0156] Through this activation annealing, all diffusion regions formed based on ion implantation (n-type current diffusion region 33, first p-type current diffusion region 34, first p-type current diffusion region 35, first p-type current diffusion region 36, first p-type current diffusion region 37, first p-type current diffusion region 38, first p-type current diffusion region 39 ... + Type 61, Second p + Type 62, peripheral p + Type 62a, n + Source region 35, p ++ Type contact area 36, ​​peripheral p ++ Type contact area 36a, n + In the channel cutoff region 21 and FLR 101-118, impurities are activated and undergo impurity diffusion according to Gaussian law, corresponding to their respective impurity concentrations and impurity diffusion coefficients.

[0157] Next, as Figure 7 As shown, through photolithography and etching, a through-hole is formed from the front side of the semiconductor substrate 10. + The n-type source region 35 and the p-type base region 34 are located inside the n-type current diffusion region 33 and are connected to the first p-type source region 35. + The gate trench 37 is opposite to the p-type region 61. The p-type base region 34 is the p-type residual portion of the p-type epitaxial layer 73 that has not been ion implanted. The step 53 can also be formed using the etching used to form the gate trench 37.

[0158] Next, as Figure 8 As shown, a gate insulating film 38 is formed along the first surface 10a of the front side of the semiconductor substrate 10 and the inner walls (sidewalls and bottom surface) of the gate trench 37. The gate insulating film 38 may be, for example, a thermal oxidation film formed by thermal oxidation of the semiconductor surface in an oxygen (O2) atmosphere at a temperature of about 1000°C, or a deposition film formed based on high-temperature oxidation (HTO).

[0159] Next, a polysilicon layer, for example, doped with phosphorus (P), is deposited (formed) on the front side of the semiconductor substrate 10 in a manner that embeds it into the gate trench 37. Then, the polysilicon layer is selectively removed, leaving only the portion that will become the gate electrode 39 inside the gate trench 37. Alternatively, a portion of the polysilicon layer may be left as both the gate electrode 39 and the gate polysilicon wiring layer 82.

[0160] When the gate electrode 39 and the gate polysilicon wiring layer 82 are formed simultaneously, a field oxide film 81 is formed on the front side of the semiconductor substrate 10 in the intermediate region 3 and the edge termination region 2 after the gate insulating film 38 is formed and before the phosphorus-doped polysilicon layer is deposited. Although in Figure 2 The diagram is omitted, but a gate insulating film 38 may remain between the front side of the semiconductor substrate 10 and the field oxide film 81.

[0161] Next, an interlayer insulating film 40, such as BPSG (Boro Phospho Silicate Glass) or PSG, is formed on the entire front side of the semiconductor substrate 10 with a thickness of, for example, 1 μm, covering the gate electrode 39 and the gate polysilicon wiring layer 82. Then, contact holes 40a and 40b, penetrating the interlayer insulating film 40 and the gate insulating film 38 in the depth direction Z, are formed by photolithography and etching.

[0162] n is exposed at contact hole 40a + Source region 35 and p ++ Type contact area 36. The outer periphery p is exposed at contact hole 40b. ++ Type contact region 36a. Additionally, while forming contact holes 40a and 40b, contact holes exposing the gate polysilicon wiring layer 82 are formed in the interlayer insulating film 40. Next, the interlayer insulating film 40 is planarized (reflow) by heat treatment.

[0163] Next, a first TiN film 42 covering only the interlayer insulating film 40 is formed in the active region 1. Then, a NiSi film 41, making ohmic contact with the front side of the semiconductor substrate 10, is formed inside the contact holes 40a and 40b. Additionally, a NiSi film making ohmic contact with the back side of the semiconductor substrate 10 is formed as the drain electrode 52. The NiSi film is formed by reacting a nickel film with the semiconductor substrate 10 using a heat treatment at, for example, a temperature of 970°C.

[0164] Next, a first Ti film 43, a second TiN film 44, and a second Ti film 45 are sequentially stacked by sputtering to cover a NiSi film 41 and a first TiN film 42, thereby forming a barrier metal 46 that covers approximately the entire surface of the active region 1. Next, an Al electrode film 47 is deposited on the second Ti film 45. Additionally, a gate pad (not shown) is formed simultaneously with the Al electrode film 47 on an interlayer insulating film 40, separate from the Al electrode film 47.

[0165] Additionally, a gate metal wiring layer 83 is formed simultaneously on the gate polysilicon wiring layer 82 and the Al electrode film 47. Next, a drain pad (not shown) is formed by sequentially stacking, for example, a Ti film, a Ni film, and a gold (Au) film on the surface of the drain electrode 52. Then, a first protective film 50 made of an organic polymer material such as polyimide is formed on the entire front side of the semiconductor substrate 10, and the first protective film 50 covers the Al electrode film 47, the gate pad, and the gate metal wiring layer 83.

[0166] Next, the Al electrode film 47 (source pad) and the gate pad are exposed at different openings formed by selectively removing the first protective film 50. Then, after a normal pre-plating treatment, a plating film 48 is formed at each opening of the first protective film 50 through a normal plating process. Next, the plating film 48 is dried by heat treatment (baking). Then, a second protective film 51, made of an organic polymer material such as polyimide, is formed to cover the boundary between the plating film 48 and the first protective film 50.

[0167] Next, the strength of the first protective film 50 and the second protective film 51 is increased by heat treatment (curing). Then, terminal leads 49 are bonded to the coated film 48 using solder layers. A wiring structure with bonded terminal leads is also formed on the gate pad (not shown), similar to that on the Al electrode film 47. Afterwards, the semiconductor substrate 10 (semiconductor wafer) is cut (slit) to monolithically form individual chips, thereby completing the process. Figure 1 , Figure 2 The MOSFET (semiconductor device 30) shown.

[0168] As explained above, according to Embodiment 1, an FLR structure is provided as a pressure-resistant structure in the edge terminal region, and the impurity concentration of the multiple FLRs constituting this FLR structure is higher than that of a conventional FLR structure (see reference). Figure 19 The impurity concentration of the FLR is low, less than 1 × 10⁻⁶. 18 / cm 3 Within this range, the thickness of the FLR is greater than that of conventional FLR structures, being 0.7 μm or more and less than 1.1 μm. This allows for a larger margin in the spacing between adjacent FLRs, resulting in a higher degree of completion in the FLR structure and improved reliability of the semiconductor device.

[0169] Furthermore, according to Embodiment 1, by reducing the impurity concentration of the FLR, the electric field applied to the FLR during turn-off is mitigated. By increasing the thickness of the FLR, the FLR extends from the front side of the semiconductor substrate to a deeper position, thus reducing its susceptibility to adverse effects from external charges accumulated in the insulating layer on the front side of the semiconductor substrate in the edge termination region. This improves the withstand voltage of the edge termination region, allowing the length of the edge termination region to be shortened to approximately half compared to conventional FLR structures.

[0170] Furthermore, according to Embodiment 1, by setting the withstand voltage structure to a conventional FLR structure, it is compared with a spatial modulation type FLR structure (see Implementation 1). Figure 18Compared to the case of a voltage-resistant FLR structure, the design of the voltage-resistant structure becomes easier and less susceptible to the effects of ion implantation accuracy. Furthermore, as mentioned above, due to the increased spacing between adjacent FLRs, it is also less affected by ion implantation accuracy compared to conventional FLR structures. Therefore, compared to spatial modulation type FLR structures and / or conventional FLR structures, the fabrication (manufacturing) of semiconductor devices becomes simpler.

[0171] (Implementation Method 2)

[0172] Next, the structure of the semiconductor device in Embodiment 2 will be described. Figure 9 This is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 2. The layout of the semiconductor device 100a according to Embodiment 2, viewed from the front side of the semiconductor substrate 10, is similar to... Figure 1 same. Figure 9 The FLR structure 120 of the semiconductor device 100a in Embodiment 2 and the FLR structure 20 of the semiconductor device 30 in Embodiment 1 (see reference) Figure 2 The difference lies in the fact that the FLR(p) constituting the FLR structure 120 - Type regions 121 to 138 are not exposed on the front side of the semiconductor substrate 10.

[0173] In embodiment 2, an n is provided between the second surface 10b on the front side of the semiconductor substrate 10 and the FLRs 121-138. - Type drift region 32. The upper end of FLR 121-138 (the end on the second surface 10b side of the front side of the semiconductor substrate 10) is separated from the second surface 10b of the front side of the semiconductor substrate 10 by, for example, 0.1 μm or more and 0.2 μm or less. Specifically, the upper end of FLR 121-138 may, for example, be located at the first p + The same depth position at the upper end of the type region 61. The impurity concentration conditions of FLR121 to 138 are the same as those of FLR101 to 118 in Embodiment 1.

[0174] FLR 121~138 of n + The depth position of the end (lower end) on the leak area 31 side is the same as that of FLR101-118 in Embodiment 1. The thickness (length in the depth direction Z) t11 and width w30 of FLR121-138 are the same as the thickness t10 and width w21 of FLR101-118 in Embodiment 1, respectively. The innermost FLR121 and the outer periphery p + The conditions for the first interval w1 between type regions 62a and the conditions for the second interval w2 to the 18th interval w18 between adjacent FLRs 121 to 138 are the same as those for FLRs 101 to 118 in Embodiment 1.

[0175] The manufacturing method of the semiconductor device 100a in Embodiment 2 is simply the same as the manufacturing method of the semiconductor device 30 in Embodiment 1, except that the first p + Similarly, in type 61 (refer to...) Figure 5 ), FLR 121~138 are formed only in n - Type epitaxial layer 72a, but not formed on the deposited n - n on the epitaxial layer 72a - The epitaxial layer 72b is sufficient. Therefore, FLRs 121-138 can be formed on the second surface 10b, which does not reach the front side of the semiconductor substrate 10. - The deep position of the surface of the epitaxial layer 72 (72a, 72b).

[0176] As explained above, according to Embodiment 2, the same effects as in Embodiment 1 can be obtained. Furthermore, according to Embodiment 2, since FLR and n... - The pn junction of the drift region is located deep away from the second side of the semiconductor substrate, so it is less susceptible to adverse effects caused by external charges accumulated in the insulating layer on the front side of the semiconductor substrate in the edge termination region. This enables the breakdown voltage characteristics of the FLR structure to be stable and improves the reliability of the semiconductor device.

[0177] (Implementation Method 3)

[0178] Next, the structure of the semiconductor device in Embodiment 3 will be described. Figure 10 This is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 3. The layout of the semiconductor device 100b according to Embodiment 3, viewed from the front side of the semiconductor substrate 10, is similar to... Figure 1 same. Figure 10 The semiconductor device 100b of Embodiment 3 and the semiconductor device 30 of Embodiment 1 (see reference) Figure 2 The difference lies in that the FLR(p) constituting the FLR structure 140 - The section 141 to 158 is defined as a barrel-shaped cross-section with a width of w40 at approximately the center position in the depth direction Z.

[0179] In embodiment 3, FLRs 141-158 are formed into a barrel-shaped cross-sectional shape, for example, by impurity diffusion based on activated annealing occurring at approximately the center position in the depth direction Z. Therefore, the impurity concentration is highest in the widest portion of FLRs 141-158, which is, for example, 1 × 10⁻⁶ of the impurity diffusion that occurs through activated annealing. 18 / cm 3Approximately. The impurity concentration of FLR 141-158, excluding the widest portion with width w40, is, for example, 1×10⁻⁶, to prevent impurity diffusion due to activation annealing. 17 / cm 3 about.

[0180] The average impurity concentration conditions for FLRs 141-158 are the same as those for FLRs 101-118 in Embodiment 1. The widest portion of the width w40 of FLRs 141-158 (the portion with the highest impurity concentration) is preferably set such that the length w20 of the edge terminal region 2 is minimized. The widest portion of the width w40 of the innermost FLR 141 is the same as the outer periphery p. + The conditions of the first interval w41 between type regions 62a and the innermost FLR 101 and the outer periphery p in embodiment 1 + The first interval w1 between type regions 62a is the same.

[0181] The conditions for the second interval w42 to the 18th interval w58 between the widest portions of the width w40 of adjacent FLRs 141 to 158 are the same as those for the second interval w2 to the 18th interval w18 between adjacent FLRs 101 to 118 in Embodiment 1. The depth positions of the two ends (upper end and lower end) of FLRs 141 to 158 in the depth direction Z are the same as those of FLRs 101 to 118 in Embodiment 1. The conditions for the thickness (length in the depth direction Z) t12 of FLRs 141 to 158 are the same as those for the thickness t10 of FLRs 101 to 118 in Embodiment 1.

[0182] The manufacturing method of semiconductor device 100b in Embodiment 3 is simply the same as the manufacturing method of semiconductor device 30 in Embodiment 1, but with the same ion implantation mask, a predetermined dose is implanted into n in multiple stages (multi-stage) under different conditions. - The epitaxial layers 72 (72a, 72b) are formed to create FLRs 141-158. For example, in the case of multi-stage ion implantation in 9 stages, two stages are performed near the upper end and two stages near the lower end of FLRs 141-158, and multi-stage ion implantation is performed at a low dose to the extent that no impurity diffusion occurs during activation annealing.

[0183] Five-stage multi-level ion implantation was performed near the approximate center location in the depth direction Z of FLRs 141–158, at a high dose to the extent that impurity diffusion would occur during activation annealing. The impurity concentration near the approximate center location in the depth direction Z of FLRs 141–158 obtained based on this five-stage multi-level ion implantation was set, for example, to 1 × 10⁻⁶. 18 / cm 3In the case of approximately 0.6 μm, the area near the approximate center position in the depth direction Z of FLR 141-158 can be relatively widened in the normal direction by about 0.3 μm to the inside and about the outside, respectively (totaling about 0.6 μm), due to impurity diffusion during activation annealing.

[0184] FLR 141-158 can be compared with the first p + Type 61, Second p + Type 62 (including peripheral p) + Type 62a) is formed simultaneously. In this case, the first p + Type 61, Second p + Type 62 (including peripheral p) + Section 62a) has a relatively wide cross-sectional shape at a depth approximately the same as the center position in the depth direction Z of FLR 141-158. FLR 141-158 and the first p can also be formed using different processes. + Type 61, Second p + Type 62 (including peripheral p) + Type 62a), so that in FLR 141~158 and the first p + Type 61, Second p + The impurity concentration distribution along the depth direction Z in region 62 is different.

[0185] As explained above, according to Embodiment 3, even when the cross-sectional shape of the FLR is modified in various ways, the same effect as Embodiment 1 can be obtained by setting the impurity concentration and depth of the FLR to the same predetermined conditions as in Embodiment 1.

[0186] (Implementation Method 4)

[0187] Next, the structure of the semiconductor device in Embodiment 4 will be described. Figure 11 This is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 4. The layout of the semiconductor device 100c according to Embodiment 4, viewed from the front side of the semiconductor substrate 10, is similar to... Figure 1 same. Figure 11 The semiconductor device 100c of Embodiment 4 shown includes an FLR structure 160, which is an FLR structure 120 of the semiconductor device 100a of Embodiment 2 (see reference). Figure 9 The configuration of the semiconductor device 100b in Embodiment 3 is applied to the FLR structure 140 (see reference). Figure 10 And thus obtained.

[0188] That is, in embodiment 4, the FLR(p) constituting the FLR structure 160 -Similar to Embodiment 3, regions 161-178 have a barrel-shaped cross-section with a width w60 that is relatively wide at approximately the center position in the depth direction Z. Furthermore, similar to Embodiment 2, an n-type cross-section is provided between the second surface 10b of the front side of the semiconductor substrate 10 and FLR 161-178. - Type drift region 32. FLR 161~178 are not exposed on the second surface 10b of the front side of the semiconductor substrate 10.

[0189] The impurity concentration conditions for FLRs 161-178 are the same as those for FLRs 141-158 in Embodiment 3. Similarly to Embodiment 3, the widest portion (the portion with the highest impurity concentration) of the width w60 of FLRs 161-178 is preferably set to minimize the length w20 of the edge terminal region 2. The widest portion of the width w60 of the innermost FLR 161 and the outer perimeter p... + The conditions of the first interval w41 between type regions 62a and the innermost FLR 101 and the outer periphery p in embodiment 1 + The first interval w1 between type regions 62a is the same.

[0190] The conditions for the second interval w42 to the 18th interval w58 between the widest portions of the width w60 of adjacent FLRs 161 to 178 are the same as those for the second interval w2 to the 18th interval w18 between adjacent FLRs 101 to 118 in Embodiment 1. The depth positions of the two ends (upper and lower ends) of FLRs 161 to 178 in the depth direction Z are the same as those for FLRs 121 to 138 in Embodiment 2. The conditions for the thickness (length in the depth direction Z) t13 of FLRs 161 to 178 are the same as those for the thickness t10 of FLRs 101 to 118 in Embodiment 1.

[0191] The manufacturing method of the semiconductor device 100c in Embodiment 4 is simply the same as the manufacturing method of the semiconductor device 100b in Embodiment 3, except that the first p + Similarly, in type 61 (refer to...) Figure 5 ), FLR 161~178 are formed only in n - Type epitaxial layer 72a, does not form on the deposited n - n on the epitaxial layer 72a - The epitaxial layer 72b is sufficient. Thus, barrel-shaped FLRs 161-178 can be formed on the second surface 10b, which does not reach the front side of the semiconductor substrate 10. - The deep position of the surface of the epitaxial layer 72 (72a, 72b).

[0192] As explained above, according to embodiment 4, the same effects as in embodiments 1 to 3 can be obtained.

[0193] (Example)

[0194] For the innermost FLR 101 (the first one counting from the inside) and the outer p + The first interval w1 between type regions 62a was verified. Figure 12 This is a characteristic graph showing the relationship between the first gap and the withstand voltage between the main junction and the innermost FLR in a simulated embodiment. The main junction refers to the outer p... + Type region 62a and n - pn junction with type 32 drift region. Figure 12 The horizontal axis is the innermost FLR101 and the outermost p + The first interval w1 between type 62a, the vertical axis is the pressure resistance.

[0195] exist Figure 12 In the case of the first interval w1 = 0.0 μm, the innermost FLR 101 is configured with respect to the outer p. + The position where type region 62a is exactly in contact. When the first interval w1 < 0.0 μm, the innermost FLR 101 is positioned with respect to the outer periphery p. + The overlapping and contacting positions of type regions 62a. When the first interval w1 > 0.0 μm, the innermost FLR101 and the outer periphery p... + Type 62a is configured separately.

[0196] Regarding the semiconductor device 30 of Embodiment 1 described above (hereinafter referred to as an embodiment, see reference 1) Figure 2 ), will compare the innermost FLR101 with the outer p + Various changes were made to the first interval w1 between type regions 62a, and the results of the pressure resistance simulation are shown below. Figure 12 .exist Figure 12 The diagram also shows a conventional semiconductor device 260 (hereinafter referred to as a conventional example, see reference 260). Figure 19 ), for the innermost FLR 291 and the peripheral p + The results of the pressure resistance were simulated by making various changes to the spacing w211 between the type regions 262a.

[0197] In the embodiment, the impurity concentration and thickness t10 of FLR 101-118 in FLR structure 20 are set to 5×10⁻⁶. 17 / cm 3 And 1μm. The width w21 of FLR 101 to 118 of FLR structure 20 and the second interval w2 to the 18th interval w18 between adjacent FLR 101 to 118 are set with a withstand voltage of 1200V. The length w20 of the edge terminal region 2 in this embodiment is 100μm.

[0198] Connect the innermost FLR 101 to the outermost p + The first interval w1 between type regions 62a is set to 1.0 μm, and the increment of the second interval w2 to the 18th interval w18 between adjacent FLRs 101 to 118 is set to 0.1 μm. That is, the second interval w2 to the 18th interval w18 between adjacent FLRs 101 to 118 are set to w2 = 1.1 μm, w3 = 1.2 μm, ..., w1 = 1.0 μm. + 0.1μm×(i-1) (where i=4~18).

[0199] In the previous example, the impurity concentration and thickness t201 of FLR 291 in FLR structure 290 were set to 1×10⁻⁶. 18 / cm 3 And 0.5μm. The width w210 of the FLR 291 of the FLR structure 290, the spacing w212 between adjacent FLR 291, etc., are set with a withstand voltage of 1200V. The multiple FLR 291 constituting the FLR structure 290 are arranged at equal intervals. The length w202 of the edge termination region 202 in the conventional example is 200μm.

[0200] according to Figure 12 The results shown confirm that, in this embodiment, compared to the conventional example, the innermost FLR 101 and the outermost p + The first interval w1 between the type regions 62a has a large margin for achieving the predetermined withstand voltage (1200V), and the withstand voltage can be improved. Furthermore, it has been confirmed that, compared to the length w202 of the edge terminal region 2 in the conventional example, the embodiment can set the length w20 of the edge terminal region 2 to half the length w202. The reason is as follows.

[0201] In previous examples, due to the high impurity concentration of FLR 291, the innermost FLR 291 and the outer p + The margin of the spacing w211 between the type regions 262a becomes smaller. In addition, due to the high impurity concentration of FLR 291 and the shallow depth (thickness t201) of FLR 291, the electric field applied to FLR 291 becomes higher. Therefore, it is necessary to ensure the spacing w212 between adjacent FLR 291 to a certain extent, and the length w202 of the edge terminal region 202 becomes longer.

[0202] In contrast, in this embodiment, the impurity concentration of FLRs 101-118 is about one order of magnitude lower than that of the conventional FLR 291, and the depth (thickness t10) of FLRs 101-118 is about twice the depth of the conventional FLR 291. Therefore, compared to the conventional example, it is possible to make the innermost FLR 101 and the outer periphery more closely connected. + The margin of the first interval w1 between type regions 62a is large enough.

[0203] Furthermore, in this embodiment, due to the low impurity concentration and deep depth of FLRs 101-118, the electric field applied to FLRs 101-118 is lower. Therefore, compared to the conventional example, the second to 18th intervals w18 between adjacent FLRs 101-118 can be narrowed. Consequently, the length w20 of the edge termination region 2 can be shortened to match the length of the spatially modulated FLR structure 220 (see reference). Figure 18 The same degree of situation.

[0204] In addition, according to Figure 12 The results shown confirm that, in the embodiment, if the innermost FLR101 and the outer p + If the first gap w1 between the type regions 62a exceeds 1.2 μm, the predetermined withstand voltage can be ensured, but the wider the first gap w1 is, the lower the withstand voltage. On the other hand, it was confirmed that even the innermost FLR 101 and the outer periphery p + Even with a 62a contact area (w1≤0.0μm), the withstand voltage will not decrease, ensuring sufficient withstand voltage.

[0205] (Experimental Example)

[0206] The other four conditions for FLR structure 20 were verified. First, as the first verification, the impurity concentrations of FLR 101–118 were verified. Figure 13 This is a characteristic graph showing the relationship between impurity concentration and withstand voltage of the simulated FLR in the experimental example. Figure 13 The vertical and horizontal axes are Figure 12 Same. Regarding the semiconductor device 30 of Embodiment 1 described above (refer to...) Figure 2 By changing the impurity concentration of FLR 101 to 118 (hereinafter referred to as Experimental Examples 1 to 3), the withstand voltage was simulated.

[0207] Regarding Experiments 1-3, the innermost FLR 101 and the outermost p will be compared. + Various modifications were made to the first interval w1 between type regions 62a, and the results of the pressure resistance simulation are shown below. Figure 13 In Experiments 1-3, the impurity concentrations of FLR 101-118 were set to 3 × 10⁻⁶.17 / cm 3 5×10 17 / cm 3 and 9×10 17 / cm 3 The composition of Experimental Examples 1-3, excluding the impurity concentrations of FLR101-118, is similar to... Figure 12 The embodiments are the same. Experimental Example 2 is equivalent to... Figure 12 Examples of implementations.

[0208] according to Figure 13 The results shown confirm that in Experiments 1-3, if the innermost FLR 101 and the peripheral p + If the first gap w1 between type regions 62a is less than 1.2 μm, the predetermined withstand voltage (1200V) can be sufficiently obtained. Therefore, by setting the impurity concentration of FLR 101~118 to 3×10 17 / cm 3 Above and 9×10 17 / cm 3 Within the following range, and with the innermost FLR 101 and the outer p + The first interval w1 between the type regions 62a is set to be within the range of 1.2 μm or less, so that the predetermined withstand pressure can be sufficiently obtained.

[0209] As a second verification, the increase in the second interval w2 between adjacent FLRs 101 and 102, and the increase in the third interval w3 between adjacent FLRs 102 and 103 were verified. Figure 14 This is a characteristic graph showing the relationship between the increase in the second interval between the first and second FLRs (counting from the inside) in a simulated experimental example and the withstand voltage. Figure 15 This is a characteristic graph showing the relationship between the increase in the third interval between the second and third FLRs (counting from the inside) in a simulated experimental example and the withstand voltage.

[0210] Figure 14 The horizontal axis represents the increase in the second interval w2 between adjacent FLRs 101 and 102 (between the innermost FLR 101 and the second FLR 102 counting from the inside), and the vertical axis represents the withstand pressure. Figure 15 The horizontal axis represents the increase in the third interval w3 between adjacent FLR102 and 103 (between the second FLR102 from the inside and the third FLR 103 from the inside), and the vertical axis represents the withstand pressure.

[0211] Regarding the semiconductor device 30 of Embodiment 1 described above (hereinafter referred to as Experimental Example 4, see reference 1) Figure 2The results of simulating the withstand voltage by varying the increase in the second interval w2 between adjacent FLR101 and 102 are shown below. Figure 14 Regarding the semiconductor device 30 of Embodiment 1 described above (hereinafter referred to as Experimental Example 5, see reference 1)... Figure 2 The results of simulating the withstand voltage by varying the increase in the third interval w3 between adjacent FLRs 102 and 103 are shown below. Figure 15 .

[0212] The increase in the second interval w2 between adjacent FLRs 101 and 102 refers to the increase between the innermost FLR 101 and the outermost p. + The increase in size between the first interval w1 in type regions 62a is (=w2-w1). The increase in size between the third interval w3 between adjacent FLRs 102 and 103 is the increase in size between the second interval w2 (=w3-w2). The configuration of Experimental Example 4, excluding the second interval w2, is... Figure 12 The embodiments are the same. The configuration of Experimental Example 5, except for the third interval w3, is the same. Figure 12 The implementation methods are the same.

[0213] according to Figure 14 , 15 The results show that as long as the increase in the second to 18th intervals w18 between adjacent FLRs 101-118 is less than 0.7 μm, even if the intervals between adjacent FLRs widen by a predetermined increase as the number of FLRs increases and they are positioned further out, it will not adversely affect the withstand voltage. It should be noted that the relationship between the increase in the fourth to 18th intervals w4 between adjacent FLRs 103-118 and the withstand voltage (not shown) also has the same... Figure 14 , 15 The same trend.

[0214] As the third verification, the thickness (depth) t10 of FLR101~118 was verified. Figure 16 This is a characteristic graph showing the results obtained from simulating the relationship between the thickness and pressure resistance of the FLR in the experimental example. Figure 16 The vertical and horizontal axes are Figure 12 Same. Regarding the semiconductor device 30 of Embodiment 1 described above (refer to...) Figure 2 The pressure resistance was simulated by changing the thickness t10 of FLR 101 to 118 (hereinafter referred to as Experimental Examples 6 to 8).

[0215] Regarding these experimental examples 6-8, the innermost FLR101 and the peripheral p will be compared. +Various changes were made to the first interval w1 between type regions 62a, and the results of the pressure resistance simulation are shown below. Figure 16 In Examples 6-8, the thickness t10 of FLR101-118 was set to 0.5 μm, 0.7 μm, and 0.9 μm, respectively. The configurations of Examples 6-8, except for the thickness t10 of FLR101-118, were similar to... Figure 12 The implementation methods are the same.

[0216] according to Figure 16 The results shown confirm that setting the impurity concentration of FLR101–118 to 5 × 10⁻⁶ is effective. 17 / cm 3 Furthermore, the thickness t10 of FLR101–118 is set to approximately 0.5 μm to 0.9 μm to adequately achieve the predetermined withstand voltage (1200V). Although the illustration is omitted, the impurity concentration of FLR101–118 is set to 3 × 10⁻⁶. 17 / cm 3 Above and 9×10 17 / cm 3 Within the following range, the relationship between the thickness t10 and the withstand voltage of FLR 101~118 also has the same characteristics as... Figure 16 The same trend.

[0217] As the fourth verification, the number of FLRs in FLR structure 20 was verified. Figure 17 This is a characteristic graph showing the relationship between the number of FLRs and the withstand voltage of the FLR structure simulating the experimental example. Figure 17 The horizontal axis represents the number of FLRs in FLR structure 20, and the vertical axis represents the pressure resistance. Figure 17 It also includes results from simulations of the external charge dependence of the FLR in FLR structure 20. External charge refers to either a positive charge that makes the insulating layer on the FLR positively (plus) or a negative charge that makes the insulating layer on the FLR negatively (minus).

[0218] Regarding the semiconductor device 30 of Embodiment 1 above (refer to...) Figure 2 The withstand voltage was simulated under the following conditions: the insulating layer (an insulating layer formed by sequentially stacking a field oxide film 81, an interlayer insulating film 40, and a first protective film 50 on the second surface 10b of the semiconductor substrate 10 in the edge terminal region 2) was uncharged (zero charge), positively charged (positive charge), and negatively charged (negative charge) (hereinafter referred to as Experimental Examples 9 to 11).

[0219] Regarding these experimental examples 9-11, the results of simulating the withstand voltage by varying the number of FLRs in the FLR structure 20 are shown below. Figure 17The configuration of Experiments 9-11, except for the number of FLRs in FLR structure 20, is similar to... Figure 12 The embodiments are the same. Experimental Example 9 is equivalent to... Figure 12 Examples of the embodiments. Experimental Example 9 is a simulation result under the condition of use in a low humidity environment (such as an indoor space where ventilation is carried out by normal air conditioning control, etc.), which is equivalent to the result obtained by a normal voltage application test based on actual use.

[0220] Experiment 10 (positively charged insulating layer) is a simulation result under high humidity conditions (such as special environments like factories), equivalent to the result obtained through THB (Temperature Humidity Bias) testing. Under high humidity conditions, the insulating layer on the second surface 10b of the semiconductor substrate 10 in the edge termination region 2 becomes positively charged, making it difficult for the depletion layer to extend outward from the active region 1, resulting in changes in breakdown voltage and leakage current. Therefore, Experiment 10 verifies the changes in breakdown voltage and leakage current under high humidity conditions.

[0221] Experiment 11 (negatively charged insulating layer) is a simulation result of applying a high voltage between the drain and source, equivalent to the result obtained through a high voltage application experiment. If the surface region of the front side of the semiconductor substrate 10 in the edge termination region 2 is depleted due to the depletion layer extending outward from the active region 1 when the MOSFET is turned off, the depleted portion becomes the same as the positively charged state. As a result, negative charge accumulates in the insulating layer on the second surface 10b of the front side of the semiconductor substrate 10 in the edge termination region 2.

[0222] If the voltage applied between the drain and source is short-term, the negative charge accumulated in the insulating layer is discharged without adverse effects. However, if a high voltage exceeding the withstand voltage (e.g., around 1400V or 1500V in the case of a withstand voltage of 1200V) is applied continuously between the drain and source for a long period (e.g., around 3000 hours), the negative charge accumulated in the insulating layer is not discharged and functions to extend the depletion layer further outward, causing changes in the withstand voltage and leakage current. Therefore, Experiment 11 verifies the changes in withstand voltage and leakage current when a high voltage is applied between the drain and source for a long time.

[0223] according to Figure 17 The results show that, regardless of the presence or absence of external charge, as long as the number of FLRs in the FLR structure 20 is 16 or more, the predetermined withstand voltage (1200V) can be sufficiently achieved. The reason for this is that, compared to previous examples (see [reference]...), [the following text is incomplete and requires further context to translate accurately]. Figure 19In contrast, the thickness t10 of the FLR is thicker, and the FLR extends from the second surface 10b of the front side of the semiconductor substrate 10 in the edge terminal region 2 to a deeper position. As a result, it is less susceptible to adverse effects from external charges accumulated in the insulating layer on the second surface 10b of the front side of the semiconductor substrate 10 in the edge terminal region 2.

[0224] Although the illustration is omitted, in the conventional example, the adverse effects caused by the external charge accumulated in the insulating layer on the second surface 210b of the front side of the semiconductor substrate 210 in the edge terminal region 202 are also similar to... Figure 17 The same trend is observed. However, the inventors have confirmed that in the prior art, compared to experimental examples 9-11, the innermost FLR 291 and the peripheral p... + The margin of the interval w211 between type regions 262a (refer to) Figure 12 Similarly, the margin of FLR291, which meets the predetermined pressure resistance of FLR structure 290, is smaller.

[0225] The present invention is not limited to the embodiments described above, and various modifications can be made without departing from the spirit of the invention. For example, in embodiments 1 and 2, the p-type electrode, which is disposed near the bottom surface of the gate trench to mitigate the electric field applied to the gate insulating film at the bottom surface of the gate trench, may be used instead. + The type region is configured as a barrel-shaped cross-section with a relatively wide width at approximately the center position in the depth direction. This invention can also be applied when a wide-bandgap semiconductor other than silicon carbide is used as the semiconductor material instead of silicon carbide. Furthermore, this invention also works even when the conductivity type (n-type, p-type) is reversed.

[0226] Industrial availability

[0227] As described above, the semiconductor device of the present invention is useful for controlling power semiconductor devices with high voltage and high current.

Claims

1. A semiconductor device, characterized in that, The semiconductor device has an active region for the flow of main current and a terminal region surrounding the active region, the semiconductor device comprising: The semiconductor substrate is made of semiconductors with a band gap wider than that of silicon; A first semiconductor region of a first conductivity type is disposed inside the semiconductor substrate; A second semiconductor region of a second conductivity type is disposed in the active region between the first main surface of the semiconductor substrate and the first semiconductor region. The predetermined component structure is formed in the active region by a pn junction of the second semiconductor region and the first semiconductor region; The first electrode is electrically connected to the second semiconductor region; The second electrode is disposed on the second main surface of the semiconductor substrate; as well as Multiple second conductivity-type withstand voltage regions are selectively disposed within the first semiconductor region, separated from each other, in the surface region of the first main surface side of the semiconductor substrate in the terminal region, and concentrically surrounding the active region. The average impurity concentration in the second conductive withstand voltage region is less than 1×10⁻⁶. 18 / cm 3 Within the range, The thickness of the second conductive withstand voltage region is 0.7 μm or more and 1.1 μm or less. The second conductive withstand voltage region has a barrel-shaped cross-sectional shape with a relatively wide width at the center position in the depth direction. Compared to other parts of the second conductive withstand voltage region, the widest part of the second conductive withstand voltage region has the highest impurity concentration.

2. The semiconductor device according to claim 1, characterized in that, The impurity concentration in the second conductive withstand voltage region is 3×10 17 / cm 3 Above and 9×10 17 / cm 3 Within the following range.

3. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a second high-conductivity region, which is selectively disposed between the second semiconductor region and the first semiconductor region in a manner that contacts the second semiconductor region, and surrounds the active region. The impurity concentration in the second high-conductivity region is higher than the impurity concentration in the second semiconductor region. The second high-concentration conductivity region is disposed between the active region and the second high-voltage conductivity region, and is opposite to the second high-voltage conductivity region in a direction parallel to the first main surface of the semiconductor substrate.

4. The semiconductor device according to claim 3, characterized in that, The first interval between the innermost second conductivity type withstand voltage region and the second conductivity type high concentration region is within the range of less than 1.2 μm.

5. The semiconductor device according to claim 3, characterized in that, The innermost second conductive type withstand voltage region is in contact with the second conductive type high concentration region.

6. The semiconductor device according to claim 5, characterized in that, The second interval between the innermost second conductive type withstand voltage region and the second second conductive type withstand voltage region counting from the inside is within the range of less than 2.1 μm.

7. The semiconductor device according to claim 5, characterized in that, The third interval between the second second conductivity type withstand voltage region, measured from the inside, and the third second conductivity type withstand voltage region, measured from the inside, is within the range of less than 3.1 μm.

8. The semiconductor device according to claim 7, characterized in that, The third interval is in the range of less than 1.0 μm.

9. The semiconductor device according to claim 8, characterized in that, The fourth interval between the third second conductive type withstand voltage region, counting from the inside, and the fourth second conductive type withstand voltage region, counting from the inside, is within the range of less than 2.0 μm.

10. The semiconductor device according to claim 4, characterized in that, The spacing between adjacent second conductive voltage-resistant regions, starting from the fourth one from the inside, is wider than the first spacing.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that, All of the multiple second-type conductive withstand voltage regions have the same width.

12. The semiconductor device according to any one of claims 1 to 10, characterized in that, The width of the second conductive voltage withstand zone from the inside out is wider than the width of the innermost second conductive voltage withstand zone.

13. The semiconductor device according to any one of claims 1 to 10, characterized in that, The second conductive voltage-resistant region reaches the first main surface of the semiconductor substrate.

14. The semiconductor device according to any one of claims 1 to 10, characterized in that, The second conductive voltage-resistant region is located at a depth position away from the first main surface of the semiconductor substrate. The first semiconductor region is located between the first main surface of the semiconductor substrate and the second conductive voltage-resistant region.

15. The semiconductor device according to any one of claims 1 to 10, characterized in that, No conductive film is provided on the first main surface of the semiconductor substrate in the terminal area.

16. The semiconductor device according to any one of claims 1 to 10, characterized in that, In the terminal region, the first main surface of the semiconductor substrate is covered by an insulating layer.

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