Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a preparation method thereof, relates to the technical field of semiconductors, and aims to solve the technical problem of insufficient channel conduction current of a semiconductor structure and its influence on performance. The semiconductor structure comprises a substrate, a source region and a drain region in the substrate, a channel layer in the substrate, and the channel layer is located between the source region and the drain region, a buried gate structure in the substrate, and the buried gate structure is located above the channel layer, and a relaxation layer at least below the channel layer. The semiconductor structure provided by the application has a relaxation layer below the channel layer, the relaxation layer can exert stress on the channel layer to improve the conduction capacity of the channel, thereby improving the mobility of the carriers and the performance of the transistor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, in order to achieve higher computing speed and larger data storage capacity, semiconductor devices are developing towards higher component density and higher integration. As a result, the size of transistors is becoming smaller and smaller, which leads to insufficient conduction current in their channels and affects the performance of transistors. Summary of the Invention

[0003] In view of the above problems, embodiments of this application provide a semiconductor structure and a method for fabricating the same, which can improve the conduction current capability of the channel and thus improve the performance of the transistor.

[0004] A first aspect of this application provides a semiconductor structure, including:

[0005] Substrate;

[0006] The source and drain regions are located in the substrate;

[0007] A channel layer is located in the substrate, and the channel layer is located between the source region and the drain region:

[0008] An embedded gate structure is located in the substrate, and the embedded gate structure is located above the channel layer;

[0009] A relaxation layer, located at least below the channel layer.

[0010] The semiconductor structure provided in this application has at least the following advantages:

[0011] The semiconductor structure provided in this application embodiment has a relaxation layer disposed below the channel layer. The relaxation layer can apply stress to the channel layer to improve the channel conduction capability (Current from Drain to Source, IDS), thereby improving the carrier mobility and thus improving the transistor performance.

[0012] In the semiconductor structure described above, the material of the relaxation layer includes GeSi or Ge. This arrangement allows the germanium material present in the channel layer to create stress due to lattice mismatch between silicon and germanium atoms, thereby increasing carrier mobility.

[0013] In the semiconductor structure described above, the relaxation layer is a GeSi layer, wherein the germanium concentration in the GeSi layer is 20-60% by mass.

[0014] In the semiconductor structure described above, the relaxation layer is a stacked structure with different germanium contents, wherein the germanium content in the stacked structure varies in a gradient.

[0015] In the semiconductor structure described above, the relaxation layer is located below the channel layer and surrounds the channel layer, with one end of the relaxation layer contacting the source region and the other end contacting the drain region.

[0016] In the semiconductor structure described above, the substrate includes a first substrate and a second substrate; the relaxation layer is located on the first substrate, and the second substrate is located on the relaxation layer and covers the surface of the relaxation layer; the channel layer and the buried gate structure are both located in the second substrate, and the source region and the drain region are respectively located in the first substrate.

[0017] The semiconductor structure described above further includes: an L-shaped buffer layer located between the buried gate structure and the drain region, and covering the surface of the drain region; the L-shaped buffer layer is also located between the buried gate structure and the source region, and covering the surface of the source region.

[0018] In the semiconductor structure described above, the L-type buffer layer is an N-type doped GeSi layer.

[0019] The semiconductor structure described above further includes a capacitor, which is connected to the drain region / source region via a capacitor contact structure formed in the L-shaped buffer layer.

[0020] The semiconductor structure described above further includes bit lines, which are connected to the source region / drain region via bit line contact structures, and the bit line contact structures are formed in the L-shaped buffer layer.

[0021] In the semiconductor structure described above, the substrate includes an active region, the top of which has a first N-type doped region to form the source region; and the top of which has a second N-type doped region to form the drain region.

[0022] In the semiconductor structure described above, the gate structure is located within the active region, and the gate structure includes:

[0023] A gate dielectric layer is located within the substrate;

[0024] The gate electrode is located above the gate dielectric layer;

[0025] A gate insulating layer is located above the gate electrode.

[0026] The second aspect of this application provides a method for fabricating a semiconductor structure, the method comprising:

[0027] Provide substrate;

[0028] A source region and a drain region are formed in the substrate;

[0029] A channel layer is formed between the source region and the drain region, the channel layer being formed in the substrate:

[0030] A buried gate structure is formed above the channel layer, and the buried gate structure is formed in the substrate;

[0031] A relaxation layer is formed at least below the channel layer.

[0032] The semiconductor structure preparation method provided in the second aspect of this application has the same advantages as the semiconductor structure involved in the first aspect, and will not be repeated here.

[0033] The semiconductor structure fabrication method described above involves forming the relaxation layer via ion implantation.

[0034] The semiconductor structure fabrication method described above provides a first substrate in which the source region and the drain region are formed;

[0035] The relaxation layer is epitaxially grown on the first substrate;

[0036] A second substrate is epitaxially grown on the relaxation layer;

[0037] The channel layer and the buried gate structure are formed in the second substrate. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of the overall semiconductor structure provided in Embodiment 1 of this application;

[0040] Figure 2 Schematic diagram of the arrangement of the relaxation layer provided in Embodiment 1 of this application Figure 1 ;

[0041] Figure 3 Schematic diagram of the arrangement of the relaxation layer provided in Embodiment 1 of this application Figure 2 ;

[0042] Figure 4 Schematic diagram of the arrangement of the relaxation layer provided in Embodiment 1 of this application Figure 3 ;

[0043] Figure 5 Schematic diagram of the arrangement of the relaxation layer provided in Embodiment 1 of this application Figure 4 ;

[0044] Figure 6 Schematic diagram of the arrangement of the relaxation layer provided in Embodiment 1 of this application Figure 5 ;

[0045] Figure 7 This is a schematic diagram showing the arrangement of the L-shaped buffer layer, bit line contact structure, and capacitor contact structure provided in Embodiment 1 of this application.

[0046] Figure 8 This is a schematic diagram of the fabrication process of the semiconductor structure provided in Embodiment 2 of this application;

[0047] Figures 9 to 14 This application provides a schematic diagram of the structure corresponding to each step in the fabrication process of the semiconductor structure for Embodiment 2.

[0048] Figure 15 This is a schematic diagram of the fabrication process of the semiconductor structure provided in Embodiment 3 of this application;

[0049] Figures 16 to 22 This is a schematic diagram of the structure corresponding to each step in the fabrication process of the semiconductor structure provided in Embodiment 3 of this application.

[0050] Explanation of reference numerals in the attached figures:

[0051] 10-Substrate;

[0052] 11-First substrate; 12-Second substrate; 13-Source region; 14-Drain region; 15-Channel layer;

[0053] 101 - Doped region; 102 - Groove structure; 103 - Gate trench;

[0054] 20-Relaxation layer;

[0055] 21-First germanium-silicon layer; 22-Second germanium-silicon layer; 23-Third germanium-silicon layer; 24-Fourth germanium-silicon layer; 25-Fifth germanium-silicon layer;

[0056] 30-Buried gate structure;

[0057] 31-Gate dielectric layer; 32-Gate electrode; 33-Gate insulating layer;

[0058] 40-L type buffer layer;

[0059] 50 - Insulating layer; 51 - Contact hole; 52 - Conductive post. Detailed Implementation

[0060] As described in the background section, semiconductor devices suffer from insufficient channel current, which affects transistor performance. The inventors discovered that this problem arises because the integration density of semiconductor devices is increasing, and transistor sizes are decreasing, leading to a smaller active region and consequently, insufficient channel current carrying capacity.

[0061] To address the aforementioned technical problems, this application provides a semiconductor structure and its fabrication method. By providing a relaxation layer within the substrate, with a portion of the relaxation layer located below the channel layer, the relaxation layer can apply compressive stress to the channel layer to enhance the channel's current-from-drain-to-source (IDS) capability, thereby increasing carrier mobility and ultimately improving transistor performance.

[0062] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0063] Example 1

[0064] like Figure 1 As shown, the semiconductor structure provided in this application embodiment includes a substrate 10; for example, the substrate 10 can be a P-type silicon substrate or an N-type silicon substrate. This application embodiment uses a P-type silicon substrate as an example for illustration.

[0065] The substrate 10 includes multiple active regions separated by a shallow trench isolation structure. Each active region has a central region and a first region and a second region located on both sides thereon. The first region is used to form the source region 13 of the semiconductor structure, and the second region is used to form the drain region 14 of the semiconductor structure.

[0066] For example, the top of the first region is N-type doped to form a first N-type doped region, which is the source in the first region. The top of the second region is N-type doped to form a second N-type doped region, which is the drain in the second region.

[0067] A gate trench is provided in the middle region of the substrate 10, and a buried gate structure 30 is provided in the gate trench, and the buried gate structure 30 is located in the second region of the substrate 10. For example, the buried gate structure 30 includes a gate dielectric layer 31, a gate electrode 32, and a gate insulating layer 33 arranged sequentially, wherein the gate dielectric layer 31 covers the inner surface of the gate trench, the gate electrode 32 covers the surface of the gate dielectric layer 31, and the gate insulating layer 33 covers the gate electrode 32, so as to isolate the buried gate structure 30 from other devices above it.

[0068] Furthermore, the substrate 10 has a channel layer 15 below the gate structure, and the channel layer 15 is located between the source region 13 and the drain region 14. When the buried gate structure 30 is connected to the turn-on voltage, the charge formed between the source and the drain can move along the channel layer 15, that is, the charge carriers move along the channel.

[0069] As the integration density of semiconductor devices increases and the size of transistors decreases, the size of their active regions also shrinks, leading to insufficient channel current conduction capability. To address this, the semiconductor structure provided in this application embodiment further includes a relaxation layer 20, which is located at least below the channel layer 15. Introducing the relaxation layer 20 into the channel layer 15 allows it to apply stress to the channel layer 15, thereby improving the channel's conduction capability, increasing carrier mobility, and ultimately enhancing transistor performance.

[0070] For example, the material of the relaxation layer 20 includes germanium-silicon (GeSi) or germanium (Ge), for instance, the relaxation layer 20 is a germanium-silicon layer, and the germanium concentration in the germanium-silicon layer is 20% to 60%, such as 25%, 30%, 40%, or 50%. With this configuration, within the aforementioned range, the introduction of germanium material into the channel layer 15 can effectively create stress due to lattice mismatch between silicon and germanium atoms, thereby improving the carrier mobility of the channel.

[0071] In this embodiment, at least a portion of the relaxation layer 20 is arranged below the channel layer 15. Different arrangements of the relaxation layer 20 are described below.

[0072] like Figure 2 As shown, in one embodiment, a partial relaxation layer 20 may be disposed below the channel layer 15, and the relaxation layer 20 includes a stacked structure with different germanium contents, wherein the germanium content varies in a gradient in the stacked structure.

[0073] For example, the relaxation layer 20 includes a first stacked structure, which includes a first germanium-silicon layer 21, a second germanium-silicon layer 22 and a third germanium-silicon layer 23 stacked sequentially. In the first stacked structure, the germanium content can gradually increase, that is, the germanium content in the first germanium-silicon layer 21 is greater than the germanium content in the second germanium-silicon layer 22, and the germanium content in the second germanium-silicon layer 22 is greater than the germanium content in the third germanium-silicon layer 23.

[0074] Alternatively, in the first stacked structure, the germanium content can be gradually decreased, i.e., the germanium content in the first germanium-silicon layer 21 is less than the germanium content in the second germanium-silicon layer 22, and the germanium content in the second germanium-silicon layer 22 is less than the germanium content in the third germanium-silicon layer 23. Preferably, in the first stacked structure, the germanium content can be gradually increased. As the germanium concentration in the germanium-silicon layer increases, the pressure exerted by the germanium-silicon layer on the channel layer 15 is greater, the carrier mobility in the channel is faster, and the transistor performance is improved more.

[0075] like Figure 3 As shown, in Figure 2 Based on the stacked structure arrangement shown, more stacked layers can be formed as needed, such as 4, 5, 8, or 10 layers, so that the stacked structure can surround the channel layer 15. For example, the relaxation layer 20 includes a second stacked structure, which includes a first germanium-silicon layer 21, a second germanium-silicon layer 22, a third germanium-silicon layer 23, a fourth germanium-silicon layer 24, and a fifth germanium-silicon layer 25 stacked sequentially. The fifth germanium-silicon layer 25 is in contact with the source region 13 and the drain region 14 of the substrate, and the germanium content in the second stacked structure can be increased or decreased sequentially, which will not be elaborated here. This arrangement can increase the distribution area of ​​the relaxation layer 20 on the substrate 10, thereby increasing the germanium content in the substrate 10, improving the conduction capability of the channel, increasing the carrier mobility, and thus improving the performance of the transistor.

[0076] It should be noted that the number of germanium-silicon layers in the first and second stacked structures described above can be multiple, and is not limited to the number of germanium-silicon layers in the stacked structures described above. The above number is for illustrative purposes only and is not limited thereto.

[0077] like Figure 4 As shown, in one embodiment, the relaxation layer 20 surrounds the channel layer 15, and a portion of the relaxation layer 20 is located below the channel layer 15. For example, the relaxation layer 20 is generally U-shaped and is disposed on the side of the gate trench 103 away from the buried gate structure 30. One end of the relaxation layer 20 extends to and contacts the source region 13; the other end of the relaxation layer 20 extends to and contacts the drain region 14. With this configuration, the relaxation layer 20 surrounds the channel layer 15, which can improve the stress distribution of the relaxation layer 20 on the channel layer 15, further improve the conduction capability of the channel, and thus improve the carrier mobility.

[0078] exist Figure 4 Based on the illustrated embodiments, as Figure 5 As shown, the relaxation layer 20 surrounding the gate trench 103 may include multiple segments spaced apart; an opening is provided between each pair of adjacent segments, wherein the portion near the source region 13 contacts the source region 13, and the portion near the drain region 14 contacts the drain region 14.

[0079] For example, the relaxation layer 20 has an opening in the middle to form two symmetrical parts on the left and right sides of the channel layer 15. These two parts can be defined as a first segment and a second segment. The first segment has one end away from the opening that contacts the source region 13 and the other end that is close to the opening. The second segment has one end away from the opening that contacts the drain region 14 and the other end that is close to the opening.

[0080] like Figure 6 As shown, in another embodiment, the substrate 10 provided in this application includes a first substrate 11 and a second substrate 12, and both the first substrate 11 and the second substrate 12 are P-type substrates. A relaxation layer 20 is disposed on the first substrate 11, surrounding the periphery of the gate trench 103, and has an overall U-shaped structure. One end of the relaxation layer 20 contacts the source region 13 disposed on the first substrate 11, and the other end contacts the drain region 14 disposed on the first substrate 11.

[0081] The second substrate 12 is disposed within the surrounding structure formed by the relaxation layer 20, and the second substrate 12 has a gate trench 103 for accommodating the buried gate structure 30. The second substrate 12 also covers the surface of the relaxation layer 20, which is the surface of the relaxation layer 20 facing the buried gate structure 30, which is disposed in the gate trench 103 of the second substrate 12.

[0082] With this configuration, the portion between the buried gate structure 30 and the channel layer 15 is separated by the relaxation layer 20 and the second substrate 12, thereby increasing the distance between the buried gate structure 30 and the channel layer 15, which improves the leakage current problem between the buried gate structure 30 and the channel layer 15, as well as the junction leak problem between the source / drain and the substrate 10.

[0083] like Figure 7 As shown, the semiconductor structure provided in this embodiment further includes an L-shaped buffer layer 40. The L-shaped buffer layer 40 is located between the buried gate structure 30 and the source region 13, and covers the surface of the source region 13.

[0084] For example, the L-shaped buffer layer 40 is an N-type doped germanium-silicon layer, which includes a horizontal portion and a vertical portion; wherein the horizontal portion covers the upper surface of the source region 13, and the vertical portion is located between the buried gate structure 30 and the source region 13. The L-shaped buffer layer 40 can provide lower contact resistance and lower leakage current. In this configuration, the vertical portion of the L-shaped buffer layer 40 increases the distance between the buried gate structure 30 and the source, thereby improving the gate-induced drain leakage (GIDL) problem.

[0085] An L-shaped buffer layer 40 is located between the buried gate structure 30 and the drain region 14, and covers the surface of the drain region 14. Exemplarily, the L-shaped buffer layer 40 is an N-type doped germanium-silicon layer, comprising a horizontal portion and a vertical portion; wherein the horizontal portion covers the upper surface of the drain region 14. This configuration raises the contact structure through the horizontal portion of the L-shaped buffer layer 40, increasing the distance between the conductive material within the contact structure and the buried gate structure 30, thereby reducing the GIDL problem.

[0086] Continue reading Figure 7 The semiconductor structure provided in this application embodiment also includes a capacitor (not shown in the figure), a bit line (not shown in the figure), and a word line, wherein the word line is connected to the buried gate structure 30, the capacitor is connected to the source or drain, and the bit line is connected to the drain or source. This application embodiment is illustrated by taking the example of the capacitor being connected to the drain and the bit line being connected to the source.

[0087] Specifically, the semiconductor structure also includes a capacitor contact structure and a bit line contact structure. The capacitor contact structure is formed in the L-shaped buffer layer 40 of the drain region 14, and the capacitor is connected to the drain region 14 through the capacitor contact structure. The bit line contact structure is formed in the L-shaped buffer layer 40 of the source region 13, and the bit line is connected to the source region 13 through the bit line contact structure.

[0088] It should be noted that each of the L-shaped buffer layers 40 covers the surfaces of the source region 13 and the drain region 14. Each L-shaped buffer layer 40 has contact holes extending from the upper surface of the buffer layer into its interior, and these holes do not contact the source region 13 and drain region 14 located below the buffer layer. This ensures that the bit line contact structure and the capacitor contact structure are both located within the buffer layer and do not contact the source region 13 and drain region 14. This increases the distance between the buried gate structure 30 and the bit line contact structure and capacitor contact structure, thereby further improving the current leakage problem between the gate and the source and drain.

[0089] Example 2

[0090] like Figure 8 As shown in the embodiments of this application, a method for fabricating a semiconductor structure is also provided, comprising the following steps:

[0091] Step S100: Provide substrate 10. Specifically, this substrate 10 can be a P-type substrate or an N-type substrate. This application embodiment does not limit this. This application embodiment uses a P-type substrate as an example for illustration.

[0092] Step S200: Form source region 13 and drain region 14 on substrate 10. Specifically, N-type doping is performed on the top of the active region of substrate 10 to form N-type doped region 101 on the top of substrate 10, as shown in the figure. Figure 9 As shown.

[0093] The active region of substrate 10 includes an intermediate region and a first region and a second region located within the intermediate region. Etching is performed in the intermediate region to form a trench structure 102, and a source region 13 is formed in the first region, and a drain region 14 is formed in the second region. This structure is as follows: Figure 10 As shown.

[0094] Step S300: A channel layer 15 is formed between the source region 13 and the drain region 14. The channel layer 15 is formed in the substrate 10. Specifically, a gate trench 103 is formed in the substrate 10 to accommodate the subsequent buried gate structure 30. The channel layer 15 can be formed around the buried gate structure 30, and one end of the channel layer 15 contacts the source region 13, while the other end of the channel layer 15 contacts the drain region 14.

[0095] Step S400: A relaxation layer 20 is formed at least below the channel layer 15; specifically, the relaxation layer 20 is formed below the channel layer 15 by ion implantation, using the gate trench 103 as a channel. For example, germanium material or germanium-silicon material is implanted below the channel layer 15 by ion implantation, using the gate trench 103 as a channel, to form a germanium layer or germanium-silicon layer below the channel layer 15.

[0096] Exemplarily, the germanium-silicon layer can be a stacked structure formed below the channel layer 15, with the percentage of germanium contained in each layer varying in a gradient. Alternatively, by adjusting the direction of ion implantation, the germanium-silicon layer can be formed to surround the gate trench 103. The germanium-silicon layer is U-shaped, with one end contacting the source region 13 and the other end contacting the drain region 14. The channel layer 15 is formed in the region between the germanium-silicon layer and the inner surface of the gate trench 103. This embodiment of the application illustrates the example of a germanium-silicon layer formed to surround the gate trench 103. This structure is as follows: Figure 11 As shown.

[0097] Step S500: A buried gate structure 30 is formed above the channel layer 15, and the buried gate structure 30 is formed in the substrate 10.

[0098] Specifically, an oxide layer 31 is formed by depositing oxide on the inner surface of the gate trench 103, as described above. Figure 12 As shown, a metal material is deposited on the surface of the gate dielectric layer 31 to form a gate electrode 32, and the gate electrode 32 fills the filling region enclosed by the gate dielectric layer 31, and the gate electrode 32 occupies a portion of the filling region. This structure is as follows. Figure 13 As shown. Further, silicon nitride is deposited on the surface of the gate electrode 32 to form a gate insulating layer 33 on the surface of the gate electrode 32, thereby forming a buried gate structure 30 within the gate trench 103, as shown. Figure 14 As shown.

[0099] In the semiconductor structure formed by the semiconductor structure preparation method provided in this application embodiment, at least a portion of the relaxation layer 20 is located below the channel layer 15. The relaxation layer 20 is introduced into the channel layer 15, and the relaxation layer 20 can apply stress to the channel layer 15 to improve the conduction capability of the channel and increase the mobility of charge carriers, thereby improving the performance of the transistor.

[0100] Example 3

[0101] like Figure 15 As shown, the substrate 10 provided in this application embodiment includes a first substrate 11 and a second substrate 12. The semiconductor fabrication method provided in this application embodiment includes the following steps:

[0102] Step S100': Provide a first substrate 11, specifically the first substrate 11 may be a P-type substrate.

[0103] Step S200': Forming source region 13 and drain region 14 on the first substrate 11. This step is the same as step S200 and will not be described again here; this structure is as follows Figure 16 As shown.

[0104] Step S300': An epitaxial relaxation layer 20 is grown on the first substrate 11; specifically, after forming the groove structure 102 on the first substrate 11, the relaxation layer 20 is epitaxially grown on the inner surface of the first substrate 11, and the surface of the relaxation layer 20 covers the inner surface of the groove structure 102 and covers the source region 13 and the drain region 14, as shown in the figure. Figure 17 As shown.

[0105] For example, the relaxation layer 20 mentioned above can be a germanium-silicon layer. Using the groove structure 102 as a channel, a selective epitaxial deposition process is employed at a temperature of 600–1100 degrees Celsius and a pressure of 1–500 Torr. The silicon source gas is SiH4, the germanium source gas is GeH4, and HCl gas and hydrogen are also included. Hydrogen is used as a carrier gas, and HCl gas is used as a selective gas to increase the selectivity of deposition, thereby forming a germanium-silicon layer on the inner surface of the first substrate 11.

[0106] Step S400': Epitaxially grow a second substrate 12 on the relaxation layer 20. Specifically, after the relaxation layer 20 is formed on the surface of the first substrate 11, the second substrate 12 can be formed on the surface of the relaxation layer 20 using an epitaxial growth process. The first substrate 11 and the second substrate 12 can be substrates of the same doping type to facilitate the formation of corresponding PMOS or NMOS devices. The second substrate 12 fills the structure enclosed by the relaxation layer 20.

[0107] It should be noted that after the second substrate 12 is epitaxially grown on the relaxation layer 20, the top of the second substrate 12 can be chemically and mechanically polished to make the upper surface of the second substrate 12 flush with the upper surface of the first substrate 11. The structure formed by this step is as follows: Figure 18 As shown.

[0108] Step S500': A trench layer 15 and a buried gate structure 30 are formed in the second substrate 12. Specifically, after the second substrate 12 is formed on the relaxation layer 20, the second substrate 12 is etched to form a gate trench 103, as shown in the figure. Figure 19 As shown. A buried gate structure 30 is further formed within the gate trench 103. This step can be referred to in step S500 and will not be repeated here. The structure formed in this step is as follows. Figure 6 As shown.

[0109] In the semiconductor structure formed by the semiconductor fabrication method provided in this application embodiment, the portion between the buried gate structure 30 and the channel layer 15 is separated by the relaxation layer 20 and the second substrate 12, so as to increase the distance between the gate and the channel. This not only improves the conduction capability of the channel carriers, but also improves the leakage current problem between the gate and the channel layer 15, as well as the leakage current problem between the source / drain and the substrate 10.

[0110] Continue reading Figure 8 and Figure 15 Based on embodiments two and three above, the method for preparing the semiconductor structure provided in this application further includes:

[0111] After forming the buried gate structure 30, the method further includes step S600: forming L-shaped buffer layers 40 on the source region 13 and the drain region 14 respectively.

[0112] Specifically, step S600 includes step S601: forming an insulating isolation layer 50 over the first substrate 11, the insulating isolation layer 50 covering the gate dielectric layer 31 and the gate insulating layer 33. For example, the insulating isolation layer 50 can be formed by depositing silicon oxide on the first substrate 11 using a chemical deposition method. The structure corresponding to this step is as follows: Figure 20 As shown.

[0113] After forming the insulating isolation layer 50 on the first substrate 11, step S600 further includes step S602: etching the insulating isolation layer 50 to form a contact hole 51. Along the thickness direction of the insulating isolation layer 50, the contact hole 51 penetrates the entire insulating isolation layer 50 and the gate dielectric layer 31 and extends to the drain region 14 and the source region 13. The structure corresponding to this step is as follows: Figure 21 As shown.

[0114] After the contact hole 51 is formed in the insulating isolation layer 50, step S600 further includes step S603: using the contact hole 51 as an injection channel, and performing N-type doping on the source region 13 and the drain region 14 to form an L-type buffer layer 40 in the source region 13 and the drain region 14, such as... Figure 22 As shown.

[0115] The L-shaped buffer layer 40 is an N-type doped germanium-silicon layer, comprising a horizontal portion and a vertical portion. The horizontal portion covers the upper surfaces of the drain region 14 and the source region 13, while the vertical portion is located between the buried gate structure 30 and the drain region 14 and the source region 13. This configuration increases the lateral distance between the buried gate structure 30 and the drain and source regions, thereby improving the GDIL leakage current problem.

[0116] Furthermore, the semiconductor fabrication method provided in this application embodiment further includes step S700: forming bit line contact structures and capacitor contact structures in the L-shaped buffer layer 40. Specifically, conductive material, such as polysilicon, is filled into the contact holes 51 opposite to the source region 13 and the contact holes 51 opposite to the drain region 14 to form conductive pillars 52. The conductive pillars 52 can serve as bit line contact structures and capacitor contact structures, with one end located within the L-shaped buffer layer 40 and the other end electrically connected to a bit line or capacitor. This step structure is as follows: Figure 7 As shown. This configuration increases the distance between the buried gate structure 30 and the bit line contact structure and capacitor contact structure, thereby further improving the current leakage problem between the gate and the source and drain.

[0117] Step S800: A conductive layer (not shown in the figure) is formed above the insulating isolation layer 50. Accordingly, the conductive layer can serve as a bit line, or a bit line or capacitor (not shown in the figure) can be formed on the conductive layer, without any particular limitation.

[0118] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0119] In the description of this specification, references to "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0120] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; The source and drain regions are located in the substrate; A channel layer is located in the substrate, and the channel layer is located between the source region and the drain region: An embedded gate structure is located in the substrate, and the embedded gate structure is located above the channel layer; A relaxation layer, located at least below the channel layer, is a stacked structure with varying germanium content. The material of the relaxation layer includes GeSi or Ge, wherein the germanium content in the stacked structure varies in a gradient.

2. The semiconductor structure according to claim 1, characterized in that, The relaxation layer is a GeSi layer, wherein the germanium concentration in the GeSi layer is 20-60% by mass.

3. The semiconductor structure according to any one of claims 1 to 2, characterized in that, The relaxation layer is located below the channel layer and surrounds the channel layer. One end of the relaxation layer contacts the source region, and the other end contacts the drain region.

4. The semiconductor structure according to any one of claims 1 to 2, characterized in that, The substrate includes a first substrate and a second substrate; The relaxation layer is located on the first substrate, and the second substrate is located on the relaxation layer and covers the surface of the relaxation layer; The channel layer and the buried gate structure are both located within the second substrate, and the source region and the drain region are respectively located within the first substrate.

5. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: An L-shaped buffer layer is located between the buried gate structure and the drain region, and covers the surface of the drain region. The L-shaped buffer layer is also located between the buried gate structure and the source region, and covers the surface of the source region.

6. The semiconductor structure according to claim 5, characterized in that, The L-shaped buffer layer is an N-type doped GeSi layer.

7. The semiconductor structure according to claim 5 or 6, characterized in that, The semiconductor structure also includes a capacitor, which is connected to the drain region / source region through a capacitor contact structure formed in the L-shaped buffer layer.

8. The semiconductor structure according to claim 5 or 6, characterized in that, The semiconductor structure further includes bit lines, which are connected to the source region / drain region via bit line contact structures, and the bit line contact structures are formed in the L-shaped buffer layer.

9. The semiconductor structure according to claim 1, characterized in that, The substrate includes an active region, the top of which has a first N-shaped doped region to form the source region; The top of the active region has a second N-type doped region to form the drain region.

10. The semiconductor structure according to claim 1 or 9, characterized in that, The gate structure is located within the active region, and the gate structure includes: A gate dielectric layer is located within the substrate; The gate electrode is located above the gate dielectric layer; A gate insulating layer is located above the gate electrode.

11. A method for fabricating a semiconductor structure, characterized in that, The method includes: Provide substrate; A source region and a drain region are formed in the substrate; A channel layer is formed between the source region and the drain region, the channel layer being formed in the substrate: A relaxation layer is formed at least below the channel layer. The relaxation layer is a stacked structure with different germanium contents. The material of the relaxation layer includes GeSi or Ge, wherein the germanium content in the stacked structure varies in a gradient. A buried gate structure is formed above the channel layer, the buried gate structure being formed in the substrate.

12. The preparation method according to claim 11, characterized in that, The relaxation layer is formed by ion implantation.

13. The preparation method according to claim 11, characterized in that, A first substrate is provided, in which the source region and the drain region are formed; The relaxation layer is epitaxially grown on the first substrate; A second substrate is epitaxially grown on the relaxation layer; The channel layer and the buried gate structure are formed in the second substrate.

Images