A nitride semiconductor structure, a method of fabricating the same, and an application thereof

Abstract

The application provides a nitride semiconductor structure, a preparation method and application thereof. The nitride semiconductor structure comprises a substrate, a mask layer, a nitride connecting layer and an epitaxial structure arranged in sequence. The epitaxial structure comprises a first epitaxial region and a second epitaxial region. The first epitaxial region comprises a first n-type nitride layer, a first nitride light-emitting layer and a first p-type nitride layer arranged in sequence. The second epitaxial region comprises a second n-type nitride layer, a second nitride light-emitting layer and a second p-type nitride layer arranged in sequence. The conductivity of the first n-type nitride layer is greater than that of the second n-type nitride layer, and / or the conductivity of the first p-type nitride layer is greater than that of the second p-type nitride layer. The first epitaxial region and the second epitaxial region with different conductivities are designed, the performance of the nitride semiconductor structure is complementary, excellent comprehensive photoelectric performance is obtained, and a semiconductor chip with excellent comprehensive performance and large size is obtained.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a nitride semiconductor structure, its preparation method, and its application. Background Technology

[0002] The research and application of gallium nitride (GaN) materials are currently at the forefront and a hot topic in semiconductor research. Along with silicon carbide and diamond, GaN is hailed as the third generation of semiconductor materials, following first-generation Ge and Si semiconductors and second-generation GaAs and InP compound semiconductors. GaN possesses characteristics such as a wide direct bandgap, high bandgap width, high critical breakdown electric field, high carrier saturation migration velocity, excellent corrosion resistance, and high thermal conductivity, making it a promising candidate for applications in high-temperature, high-frequency, high-power microelectronic devices and high-performance optoelectronic devices.

[0003] Since Group III nitrides, represented by GaN, are generally heteroepitaxially grown on heterogeneous substrates such as sapphire, the development of heteroepitaxial technology involves several key aspects. Firstly, adjustments to the epitaxial layer's growth process (e.g., thickness, doping) directly affect the layer's performance and have a significant impact on semiconductor devices. Secondly, in actual production, appropriate epitaxial processes are often required based on product performance requirements to obtain semiconductor devices with excellent overall performance. In many cases, unilateral adjustments to the epitaxial process cannot simultaneously address all performance parameters of the semiconductor device. While ensuring excellent performance in one aspect, compromises are often made on one or more other performance parameters. This can yield products that meet specific performance requirements, but the overall yield of the product is not high, which limits the application of semiconductor products in new fields. On the other hand, as the industry pursues greater production capacity to reduce the unit cost of epitaxial wafers, it has developed reaction chambers with larger sizes, as well as epitaxial wafers of larger sizes such as 4 inches, 6 inches, and even 8 inches, which poses a greater challenge to substrate peeling. Moreover, for larger epitaxial wafers, the warpage problem becomes very obvious. With similar substrate thickness, the warpage of epitaxial films grown on larger substrates at high temperatures will be more severe because larger area epitaxial wafers are more susceptible to temperature field inhomogeneity and stress accumulation in the epitaxial film.

[0004] Therefore, developing semiconductor structures and semiconductor chips with more comprehensive performance and the ability to fabricate large-size substrate epitaxial wafers is of great practical significance and is a key research focus in this field. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a nitride semiconductor structure, its fabrication method, and its application. By designing a first epitaxial region and a second epitaxial region with different conductivity properties, the performance of the nitride semiconductor structure is made complementary, combining low voltage, low leakage current, and high brightness to achieve excellent comprehensive optoelectronic performance, thereby obtaining a semiconductor chip with excellent comprehensive performance and large-size epitaxy.

[0006] To achieve this objective, the present invention employs the following technical solution:

[0007] In a first aspect, the present invention provides a nitride semiconductor structure, the nitride semiconductor structure comprising a substrate, a mask layer, a nitride interconnect layer and an epitaxial structure disposed sequentially, the epitaxial structure comprising a first epitaxial region and a second epitaxial region;

[0008] The first epitaxial region includes a first n-type nitride layer, a first nitride light-emitting layer, and a first p-type nitride layer disposed sequentially; the first n-type nitride layer is located on the side closer to the substrate;

[0009] The second epitaxial region includes a second n-type nitride layer, a second nitride light-emitting layer, and a second p-type nitride layer disposed sequentially; the second n-type nitride layer is located on the side closer to the substrate;

[0010] The conductivity of the first n-type nitride layer is greater than that of the second n-type nitride layer, and / or the conductivity of the first p-type nitride layer is greater than that of the second p-type nitride layer.

[0011] The nitride semiconductor structure provided in this application includes an epitaxial structure comprising a first epitaxial region and a second epitaxial region in contact with each other, the two epitaxial regions having different conductivity; wherein, the conductivity of the first n-type nitride layer is greater than that of the second n-type nitride layer, and / or, the conductivity of the first p-type nitride layer is greater than that of the second p-type nitride layer. The first and second epitaxial regions have different photoelectric properties, enabling complementary performance, thus giving the nitride semiconductor structure low voltage, high brightness, low leakage current, and excellent electrostatic discharge (ESD) resistance. This results in a nitride semiconductor chip containing the structure exhibiting excellent overall performance and enables the fabrication of large-size epitaxy.

[0012] Preferably, the mask layer comprises an array of mask structure units.

[0013] As a preferred embodiment of the present invention, the mask layer comprises an array of multiple mask structure units. Any two adjacent mask structure units are independent and not connected, meaning there is a mask gap between any two adjacent mask structure units. This effectively releases stress during the epitaxial growth process, preventing warping of the epitaxial nitride layer and the epitaxial structure. Furthermore, the nitride semiconductor structure containing the mask layer enables substrate stripping. Specifically, wet etching can be used to efficiently and quickly separate the substrate and nitride interconnect layer through the mask gap, thereby transferring the nitride interconnect layer and the epitaxial structure onto the terminal substrate to obtain a vertical nitride semiconductor chip. This method yields a low-cost vertical nitride semiconductor chip suitable for mass production.

[0014] Preferably, the substrate is a known heterogeneous substrate, including any one of sapphire substrate, silicon carbide substrate, gallium oxide substrate, zinc oxide substrate or diamond substrate.

[0015] Preferably, the material of the mask structure unit includes any one or a combination of at least two of nitrides, oxides, metals, or organic materials.

[0016] Preferably, the material of the mask structure unit includes any one or a combination of at least two of GaN, AlN, GaN, InGaN, AlGaN, AlInGaN, AlInN, InN, Al2O3, SiO2, Si3N4, Ga2O3, ZnO, Fe, Cu, Ag, or photoresist.

[0017] Preferably, the height of the mask structure unit is 1-5μm, for example, it can be 1.1μm, 1.3μm, 1.5μm, 1.7μm, 1.9μm, 2μm, 2.1μm, 2.3μm, 2.5μm, 2.8μm, 3μm, 3.5μm, 4μm or 4.5μm, as well as specific values ​​between the above values. Due to space limitations and for the sake of brevity, the present invention will not exhaustively list the specific values ​​included in the range, and it is further preferred to be 1-3μm.

[0018] Preferably, the width of the mask structure unit is 1-6 μm, for example, it can be 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm or 5.5 μm, as well as specific point values ​​between the above point values. Due to space limitations and for the sake of brevity, the present invention will not exhaustively list the specific point values ​​included in the range.

[0019] Preferably, the spacing between any two adjacent mask structure units is 0.1-2 μm, for example, it can be 0.3 μm, 0.5 μm, 0.7 μm, 0.9 μm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.2 μm, 2.5 μm or 2.8 μm, and specific point values ​​between the above point values. Due to space limitations and for the sake of brevity, the present invention will not exhaustively list the specific point values ​​included in the range.

[0020] Preferably, the nitride bonding layer is an n-type nitride bonding layer.

[0021] Preferably, the thickness of the nitride bonding layer is 1-5 μm, for example, it can be 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm or 4.5 μm, as well as specific values ​​between the above values. Due to space limitations and for the sake of brevity, the present invention will not exhaustively list the specific values ​​included in the range.

[0022] Preferably, the difference in photoelectric properties between the first epitaxial region and the second epitaxial region is achieved through the difference in doping concentration, that is, the doping concentration of the first n-type nitride layer is greater than that of the second n-type nitride layer, and / or, the doping concentration of the first p-type nitride layer is greater than that of the second p-type nitride layer.

[0023] Preferably, the doping concentration of the first n-type nitride layer is greater than the doping concentration of the second n-type nitride layer.

[0024] As a preferred embodiment of the present invention, the first n-type nitride layer has a high doping concentration, forming a highly conductive epitaxial layer, which helps to reduce the voltage of the first epitaxial region, but also has relatively high leakage current and low ESD resistance. The second n-type nitride layer has a low doping concentration, forming a low-conductivity epitaxial layer, which increases the voltage of the second epitaxial region, resulting in relatively low leakage current and high ESD resistance. Therefore, in the nitride semiconductor structure, the difference in doping concentration between the first n-type nitride layer and the second n-type nitride layer leads to a difference in conductivity, thereby achieving complementary performance between the two epitaxial regions and giving the nitride semiconductor structure excellent overall optoelectronic performance.

[0025] Preferably, the second n-type nitride layer includes a first n-type sublayer and a second n-type sublayer, wherein the first n-type sublayer is located on the side closer to the substrate; the conductivity of the first n-type sublayer is greater than the conductivity of the second n-type sublayer.

[0026] Preferably, the doping concentration of the first n-type sublayer is greater than the doping concentration of the second n-type sublayer.

[0027] As a preferred technical solution of the present invention, based on the first n-type nitride layer forming a highly conductive epitaxial layer through high doping and reducing the voltage of the first epitaxial region, the second n-type nitride layer with low doping includes a first n-type sublayer and a second n-type sublayer with different doping concentrations. The lower doping concentration of the second n-type sublayer forms a relatively high resistance, which has a good diffusion effect on electrons injected into the first n-type sublayer, improves the uniformity of electron injection into the nitride light-emitting layer, and thus improves the brightness of the nitride semiconductor structure and the nitride semiconductor chip containing it, effectively reduces the efficiency drop effect under high current, and realizes a nitride semiconductor chip with excellent comprehensive optoelectronic performance.

[0028] Preferably, the doping concentration of the first n-type nitride layer and the second n-type nitride layer is each independently 1×10⁻⁶. 17 -8×10 19 cm -3 For example, it can be 2×10 17 cm -3 5×10 17 cm -3 8×10 17 cm -3 1×10 18 cm -3 3×10 18 cm -3 5×10 18 cm -3 7×10 18 cm -3 9×10 18 cm -3 1×10 19 cm -3 2×10 19 cm -3 3×10 19 cm -3 4×10 19 cm -3 5×10 19 cm -3 6×10 19 cm -3 Or 7×10 19 cm -3 As well as the specific point values ​​between the above point values, due to space limitations and for the sake of brevity, this invention will not exhaustively list the specific point values ​​included in the range.

[0029] Preferably, the doping concentration of the first n-type nitride layer is 1×10⁻⁶. 19 -8×10 19 cm -3 For example, it can be 1×10 19cm -3 1.5×10 19 cm -3 2×10 19 cm -3 2.5×10 19 cm -3 3×10 19 cm -3 3.5×10 19 cm -3 4×10 19 cm -3 4.5×10 19 cm -3 5×10 19 cm -3 5.5×10 19 cm -3 6×10 19 cm -3 6.5×10 19 cm -3 7×10 19 cm -3 Or 7.5×10 19 cm -3 As well as the specific point values ​​between the above point values, due to space limitations and for the sake of brevity, this invention will not exhaustively list the specific point values ​​included in the range.

[0030] Preferably, the doping concentration of the second n-type nitride layer is 1×10⁻⁶. 17 -5×10 19 cm -3 For example, it can be 2×10 17 cm -3 5×10 17 cm -3 8×10 17 cm -3 1×10 18 cm -3 3×10 18 cm -3 5×10 18 cm -3 8×10 18 cm -3 1×10 19 cm -3 3×10 19 cm -3 Or 4×10 19 cm -3 As well as the specific point values ​​between the above point values, due to space limitations and for the sake of brevity, this invention will not exhaustively list the specific point values ​​included in the range.

[0031] Preferably, the thickness of the first n-type nitride layer and the second n-type nitride layer are each independently 0.5-2.5 μm, for example, 0.7 μm, 0.9 μm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.2 μm or 2.4 μm, as well as specific values ​​between the above values. Due to space limitations and for the sake of brevity, the present invention will not exhaustively list the specific values ​​included in the range.

[0032] Preferably, the thickness of the first n-type sublayer is 0.3-2 μm, for example, it can be 0.4 μm, 0.5 μm, 0.7 μm, 0.9 μm, 1 μm, 1.2 μm, 1.5 μm or 1.8 μm, as well as specific point values ​​between the above point values. Due to space limitations and for the sake of brevity, the present invention will not exhaustively list the specific point values ​​included in the range.

[0033] Preferably, the thickness of the second n-type sublayer is 0.2-0.5 μm, for example, it can be 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm or 0.45 μm, as well as specific values ​​between the above values. Due to space limitations and for the sake of brevity, the present invention will not exhaustively list the specific values ​​included in the range.

[0034] Preferably, the doping concentration of the first n-type sublayer is 5 × 10⁻⁶. 18 -5×10 19 cm -3 For example, it can be 6×10 18 cm -3 7×10 18 cm -3 8×10 18 cm -3 9×10 18 cm -3 1×10 19 cm -3 2×10 19 cm -3 3×10 19 cm -3 Or 4×10 19 cm -3 As well as the specific point values ​​between the above point values, due to space limitations and for the sake of brevity, this invention will not exhaustively list the specific point values ​​included in the range.

[0035] Preferably, the doping concentration of the second n-type sublayer is 1×10⁻⁶. 17 -5×10 18 cm -3 For example, it can be 2×10 17 cm -3 3×1017 cm -3 5×10 17 cm -3 7×10 17 cm -3 9×10 17 cm -3 1×10 18 cm -3 2×10 18 cm -3 Or 4×10 18 cm -3 As well as the specific point values ​​between the above point values, due to space limitations and for the sake of brevity, this invention will not exhaustively list the specific point values ​​included in the range.

[0036] Preferably, the doping concentration of the first p-type nitride layer is greater than the doping concentration of the second p-type nitride layer.

[0037] As a preferred embodiment of the present invention, the first p-type nitride layer has a high doping concentration, forming a highly conductive epitaxial layer, which can reduce the voltage of the semi-nitride semiconductor chip. However, as the doping concentration of the p-type nitride increases, the higher dopant will absorb the light emitted from the nitride light-emitting layer into the p-type nitride layer, reducing the brightness of the semiconductor device. At the same time, the high doping concentration will also lead to high defects in the p-type nitride layer, reducing leakage current and ESD performance. The second p-type nitride layer has a low doping concentration, forming a low-conductivity epitaxial layer, which reduces the absorption of light emitted from the nitride light-emitting layer into the p-type nitride layer. At the same time, the low doping concentration reduces the diffusion of dopant into the nitride light-emitting layer, improving the crystal quality of the nitride light-emitting layer and achieving high brightness of the nitride semiconductor chip. In addition, the low doping concentration forms a relatively low-conductivity epitaxial layer, which allows the holes in the p-type nitride to diffuse laterally, improving the uniformity of hole injection. The low doping concentration also reduces the defects formed in the p-type nitride layer, improving leakage current and ESD performance. Therefore, the difference in doping concentration between the first p-type nitride layer and the second p-type nitride layer in the nitride semiconductor structure results in a difference in conductivity, thereby achieving complementary performance between the two epitaxial regions and giving the nitride semiconductor structure excellent overall optoelectronic performance.

[0038] Preferably, the second p-type nitride layer includes a first p-type sublayer and a second p-type sublayer, wherein the first p-type sublayer is located on the side closer to the substrate; the conductivity of the first p-type sublayer is greater than that of the second p-type sublayer.

[0039] Preferably, the doping concentration of the first p-type sublayer is greater than the doping concentration of the second p-type sublayer.

[0040] As a preferred technical solution of the present invention, based on the formation of a highly conductive epitaxial layer by high doping of the first p-type nitride layer, the second p-type nitride layer with low doping includes a first p-type sublayer and a second p-type sublayer with different doping concentrations, and a hole concentration gradient is formed between the first p-type sublayer and the second p-type sublayer, which further improves the hole injection concentration and uniformity, and is beneficial to improving brightness and ESD performance.

[0041] Preferably, the doping concentration of the first p-type nitride layer and the second p-type nitride layer is each independently 1 × 10⁻⁶. 19 -1×10 21 cm -3 For example, it can be 2×10 19 cm -3 5×10 19 cm -3 8×10 19 cm -3 1×10 20 cm -3 3×10 20 cm -3 5×10 20 cm -3 7×10 20 cm -3 Or 9×10 20 cm -3 As well as the specific point values ​​between the above point values, due to space limitations and for the sake of brevity, this invention will not exhaustively list the specific point values ​​included in the range.

[0042] Preferably, the doping concentration of the first p-type nitride layer is 1×10⁻⁶. 20 -1×10 21 cm -3 For example, it can be 2×10 20 cm -3 3×10 20 cm -3 4×10 20 cm -3 5×10 20 cm -3 6×10 20 cm -3 7×10 20 cm -3 8×10 20 cm -3 Or 9×10 20 cm -3 As well as the specific point values ​​between the above point values, due to space limitations and for the sake of brevity, this invention will not exhaustively list the specific point values ​​included in the range.

[0043] Preferably, the doping concentration of the second p-type nitride layer is 1×10⁻⁶. 19 -5×10 20 cm -3 For example, it can be 2×10 19 cm -3 5×10 19 cm -3 7×10 19 cm -3 9×10 19 cm -3 1×10 20 cm -3 2×10 20 cm -3 3×10 20 cm -3 Or 4×10 20 cm -3 As well as the specific point values ​​between the above point values, due to space limitations and for the sake of brevity, this invention will not exhaustively list the specific point values ​​included in the range.

[0044] Preferably, the thickness of the first p-type nitride layer and the second p-type nitride layer are each independently 100-300 nm, for example, 120 nm, 150 nm, 180 nm, 200 nm, 220 nm, 250 nm or 280 nm, as well as specific values ​​between the above values. Due to space limitations and for the sake of brevity, the present invention will not exhaustively list the specific values ​​included in the range.

[0045] Preferably, the thickness of the first p-type sublayer is 20-50 nm, for example, it can be 22 nm, 25 nm, 28 nm, 30 nm, 32 nm, 35 nm, 38 nm, 40 nm, 42 nm, 45 nm or 48 nm, as well as specific values ​​between the above values. Due to space limitations and for the sake of brevity, the present invention will not exhaustively list the specific values ​​included in the range.

[0046] Preferably, the thickness of the second p-type sublayer is 80-250nm, for example, it can be 90nm, 100nm, 110nm, 130nm, 150nm, 170nm, 190nm, 200nm, 220nm or 240nm, as well as specific values ​​between the above values. Due to space limitations and for the sake of brevity, the present invention will not exhaustively list the specific values ​​included in the range.

[0047] Preferably, the doping concentration of the first p-type sublayer is 8 × 10⁻⁶. 19 -5×10 20 cm -3 For example, it can be 9×10 19cm -3 1×10 20 cm -3 1.5×10 20 cm -3 2×10 20 cm -3 2.5×10 20 cm -3 3×10 20 cm -3 3.5×10 20 cm -3 4×10 20 cm -3 Or 4.5×10 20 cm -3 As well as the specific point values ​​between the above point values, due to space limitations and for the sake of brevity, this invention will not exhaustively list the specific point values ​​included in the range.

[0048] Preferably, the doping concentration of the second p-type sublayer is 1×10⁻⁶. 19 -5×10 19 cm -3 For example, it can be 1.5 × 10 19 cm -3 2×10 19 cm -3 2.5×10 19 cm -3 3×10 19 cm -3 3.5×10 19 cm -3 4×10 19 cm -3 Or 4.5×10 19 cm -3 As well as the specific point values ​​between the above point values, due to space limitations and for the sake of brevity, this invention will not exhaustively list the specific point values ​​included in the range.

[0049] Preferably, the first nitride emitting layer and the second nitride emitting layer each independently include alternating nitride quantum well layers and nitride quantum barrier layers.

[0050] Preferably, the alternating repetition period is 3-15, for example, it can be 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 or 15.

[0051] Preferably, the thickness of the first nitride light-emitting layer and the second nitride light-emitting layer are each independently 15-200 nm, for example, 20 nm, 30 nm, 50 nm, 70 nm, 90 nm, 100 nm, 110 nm, 130 nm, 150 nm, 170 nm or 190 nm, as well as specific values ​​between the above values. Due to space limitations and for the sake of brevity, the present invention will not exhaustively list the specific values ​​included in the range.

[0052] Preferably, the ratio of the projected area of ​​the first epitaxial region on the substrate to the projected area of ​​the second epitaxial region on the substrate is 1:(4-10), for example, it can be 1:4.5, 1:5, 1:5.5, 1:6, 1:6.5, 1:7, 1:7.5, 1:8, 1:8.5, 1:9 or 1:9.5, etc.

[0053] As a preferred embodiment of the present invention, the area of ​​the first epitaxial region is smaller than the area of ​​the second epitaxial region, where "area" refers to the planar area of ​​the nitride epitaxial layer, i.e., the area relative to the plane of the substrate. A ratio of 1:(4-10) between the area of ​​the highly conductive first epitaxial region and the area of ​​the less conductive second epitaxial region enables the nitride semiconductor structure to achieve a more complete overall optoelectronic performance. If the area of ​​the first epitaxial region is too small, the complementary effect of differentiated optoelectronic performance is not obvious and cannot highlight the complementary effect; if the area of ​​the first epitaxial region is too large, the proportion of the complementary effect of differentiated optoelectronic performance will be too large, resulting in low overall optoelectronic performance and making it impossible to obtain a nitride semiconductor chip with excellent overall performance.

[0054] Preferably, the first extensional region and the second extensional region are arranged side by side or surround each other.

[0055] In this invention, the nitrides in the nitride semiconductor structure (including the nitrides in the nitride interconnect layer and the nitrides in the epitaxial structure) each independently include any one or a combination of at least two of GaN, InGaN, AlGaN, AlN, AlInGaN, AlInN, or InN.

[0056] In this invention, the n-type nitride includes Si-doped nitride, and the p-type nitride includes Mg-doped nitride.

[0057] In a second aspect, the present invention provides a method for preparing the nitride semiconductor structure described in the first aspect, the method comprising: sequentially depositing a mask layer, a nitride interconnect layer and an epitaxial structure on a substrate to obtain the nitride semiconductor structure.

[0058] Preferably, the preparation method specifically includes the following steps:

[0059] (1) A first mask dielectric layer is grown on the substrate and etched to obtain an array composed of mask structure units;

[0060] (2) After filling the mask structure units obtained in step (1) with a filling medium, a nitride bonding layer is grown;

[0061] (3) A second mask dielectric layer is grown on the nitride bonding layer obtained in step (2);

[0062] (4) Part of the second mask dielectric layer obtained in step (3) is etched, and a first n-type nitride layer, a first nitride light-emitting layer and a first p-type nitride layer are grown sequentially on the nitride interconnect layer exposed after etching to form a first epitaxial region; the remaining area of ​​the second mask dielectric layer is etched, and a second n-type nitride layer, a second nitride light-emitting layer and a second p-type nitride layer are grown sequentially on the nitride interconnect layer exposed after etching to form a second epitaxial region, thereby obtaining the nitride semiconductor structure.

[0063] Preferably, the filling medium in step (2) is made of a different material than the mask structure unit, and the filling medium is introduced to facilitate the growth of the nitride bonding layer.

[0064] Preferably, the corrosion resistance of the filling medium is less than that of the mask structure unit; the filling medium is removed after the nitride bonding layer is obtained.

[0065] Preferably, the filler medium is made of photoresist.

[0066] Thirdly, the present invention provides a nitride semiconductor chip, the nitride semiconductor chip comprising the nitride semiconductor structure as described in the first aspect, an n-type electrode and a p-type electrode, the n-type electrode and the p-type electrode being located on the same side of a substrate.

[0067] Fourthly, the present invention provides a nitride semiconductor chip, which is fabricated using the nitride semiconductor structure described in the first aspect.

[0068] The nitride semiconductor chip is a vertical nitride semiconductor chip, wherein the n-type electrode and the p-type electrode are located on different sides of the terminal substrate.

[0069] Preferably, the nitride semiconductor chip includes an n-type electrode, a terminal substrate, a semiconductor material layer, and a p-type electrode arranged sequentially; the semiconductor material layer is a nitride interconnect layer and an epitaxial structure in the nitride semiconductor structure.

[0070] In the nitride semiconductor structure provided by the first aspect of the present invention, the mask layer can be removed by wet etching, which is accompanied by the removal of the substrate, to obtain a semiconductor material layer containing a nitride interconnect layer and an epitaxial structure; then the semiconductor material layer is transferred to a terminal substrate, and n-type electrodes and p-type electrodes are respectively provided to obtain a vertical nitride semiconductor chip.

[0071] Preferably, the method for fabricating the nitride semiconductor chip includes: removing the substrate and mask layer in the nitride semiconductor structure, and setting a terminal substrate on the side of the nitride interconnect layer away from the epitaxial structure; setting an n-type electrode on the terminal substrate (on the side away from the nitride interconnect layer), and setting a p-type electrode on the first p-type nitride layer and / or the second p-type nitride layer.

[0072] Compared with the prior art, the present invention has the following beneficial effects:

[0073] (1) In the nitride semiconductor structure provided in this application, by setting a first epitaxial region and a second epitaxial region with different conductivity, differentiated performance complementarity can be achieved, so that the nitride semiconductor structure has low voltage, high brightness, low leakage current and excellent ESD resistance, effectively improving leakage current IR yield and ESD yield, thereby making the nitride semiconductor chip containing it have excellent comprehensive optoelectronic performance and improving the product yield of nitride semiconductor chip.

[0074] (2) In the nitride semiconductor structure, the mask layer can effectively release the stress of the epitaxial structure during the growth process, avoiding warping problems in the epitaxially grown nitride layer and epitaxial structure, and meeting the fabrication requirements of large-size epitaxial wafers and semiconductor chips. Simultaneously, the mask layer can be separated from the nitride interconnect layer, thereby transferring the nitride interconnect layer and epitaxial structure onto the terminal substrate to obtain a vertical nitride semiconductor chip. The vertical nitride semiconductor chip obtained by this method has low cost and is suitable for mass production. Attached Figure Description

[0075] Figure 1 This is a schematic diagram of the nitride semiconductor structure described in a specific embodiment;

[0076] Figure 2 This is a schematic diagram of the nitride semiconductor structure described in another specific embodiment;

[0077] Figure 3 This is a schematic diagram of the nitride semiconductor structure described in another specific embodiment;

[0078] Figure 4 This is a schematic diagram of the nitride semiconductor structure described in another specific embodiment;

[0079] Figure 5 This is a schematic diagram of the nitride semiconductor structure described in another specific embodiment;

[0080] Figure 6 This is a schematic diagram of the nitride semiconductor structure described in another specific embodiment;

[0081] Figure 7a This is a process diagram illustrating the fabrication method of the nitride semiconductor structure described in a specific embodiment;

[0082] Figure 7b This is a process diagram illustrating the fabrication method of the nitride semiconductor structure described in a specific embodiment;

[0083] Figure 7c This is a process diagram illustrating the fabrication method of the nitride semiconductor structure described in a specific embodiment;

[0084] Figure 7d This is a process diagram illustrating the fabrication method of the nitride semiconductor structure described in a specific embodiment;

[0085] Figure 8 This is a schematic diagram of the structure of a nitride semiconductor chip described in a specific embodiment;

[0086] Figure 9 This is a schematic diagram of the structure of the nitride semiconductor chip described in another specific embodiment;

[0087] Figure 10 This is a schematic diagram of the structure of a vertical nitride semiconductor chip in a specific embodiment.

[0088] Wherein, 10-substrate, 20-mask layer, 30-nitride interconnect layer, 40-epitaxy structure, 40A-first epitaxial region, 40B-second epitaxial region, 201-mask structure unit, 411-first n-type nitride layer, 412-first nitride light-emitting layer, 413-first p-type nitride layer, 421-second n-type nitride layer, 4211-first n-type sublayer, 4212-second n-type sublayer, 422-second nitride light-emitting layer, 423-second p-type nitride layer, 4231-first p-type sublayer, 4232-second p-type sublayer, 50-second mask dielectric layer, 60-n-type electrode, 70-p-type electrode, 80-terminal substrate. Detailed Implementation

[0089] The technical solution of the present invention will be further illustrated below through specific embodiments. Those skilled in the art should understand that the embodiments described are merely illustrative of the present invention and should not be construed as limiting the invention in any way.

[0090] The terms “comprising,” “including,” “having,” “containing,” or any other variations thereof, as used herein, are intended to cover non-exclusive inclusion. For example, a composition, step, method, article, or apparatus that includes the listed elements is not limited to those elements and may also include other elements not expressly listed or elements inherent to such composition, step, method, article, or apparatus.

[0091] "Optional" or "any one" means that the matter or event described thereafter may or may not occur, and the description includes both the possibility that the event may occur and the possibility that the event may not occur.

[0092] The indefinite articles “a” and “an” preceding an element or component of this invention do not impose any limitation on the quantity (i.e., number of times) of the element or component. Therefore, “an” or “a” should be interpreted as including one or at least one, and the singular form of an element or component also includes the plural form, unless the quantity clearly refers only to the singular form.

[0093] In this invention, features specified as "first" and "second" may explicitly or implicitly include one or more of these features, used to distinguish and describe features, without any order or emphasis. In the description of this invention, unless otherwise stated, "multiple" means two or more.

[0094] In this invention, the terms "upper," "lower," "inner," "outer," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. They should not be construed as limitations on this invention.

[0095] In this invention, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meanings of the above in this invention according to the specific circumstances.

[0096] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0097] like Figure 1 As shown, the present invention provides a nitride semiconductor structure, including a substrate 10, a mask layer 20, a nitride interconnect layer 30 and an epitaxial structure 40 arranged sequentially, wherein the epitaxial structure includes a first epitaxial region 40A and a second epitaxial region 40B.

[0098] The first epitaxial region 40A includes a first n-type nitride layer 411, a first nitride light-emitting layer 412 and a first p-type nitride layer 413 disposed sequentially; the first n-type nitride layer 411 is located on the side close to the substrate 10.

[0099] The second epitaxial region 40B includes a second n-type nitride layer 421, a second nitride light-emitting layer 422, and a second p-type nitride layer 423 disposed sequentially; the second n-type nitride layer 421 is located on the side close to the substrate 10.

[0100] The conductivity of the first n-type nitride layer 411 is greater than that of the second n-type nitride layer 421, and / or the conductivity of the first p-type nitride layer 413 is greater than that of the second p-type nitride layer 423.

[0101] In the nitride semiconductor structure provided in this application, the first epitaxial region 40A and the second epitaxial region 40B, which are in contact with each other, have different electrical conductivity, specifically including three cases:

[0102] (1) The conductivity of the first n-type nitride layer 411 is greater than that of the second n-type nitride layer 421, and the conductivity of the first p-type nitride layer 413 is the same as that of the second p-type nitride layer 423.

[0103] (2) The first n-type nitride layer 411 and the second n-type nitride layer 421 have the same conductivity, and the conductivity of the first p-type nitride layer 413 is greater than that of the second p-type nitride layer 423.

[0104] (3) The conductivity of the first n-type nitride layer 411 is greater than that of the second n-type nitride layer 421, and the conductivity of the first p-type nitride layer 413 is greater than that of the second p-type nitride layer 423.

[0105] The first and second epitaxial regions have different photoelectric properties, which enables the nitride semiconductor structure to have low voltage, high brightness, low leakage current and excellent ESD resistance. The complementary differences between the two epitaxial regions can be used to ultimately achieve the excellent performance of the nitride semiconductor chip and improve the yield of the nitride semiconductor chip. The complementary performance of the different photoelectric properties enables the nitride semiconductor structure to give the nitride semiconductor chip containing it excellent comprehensive performance and realize the fabrication of large-size epitaxy.

[0106] Preferably, the substrate 10 is a heterogeneous substrate known in the prior art, including any one of sapphire substrate, silicon carbide substrate, gallium oxide substrate, zinc oxide substrate or diamond substrate.

[0107] Preferably, the mask layer 20 comprises an array of multiple mask structure units 201. Any two adjacent mask structure units 201 are independent and not connected, meaning there is a mask gap between any two adjacent mask structure units 201. This effectively releases stress on the epitaxial structure during growth, preventing warping of the epitaxial nitride layer and epitaxial structure. Furthermore, due to the design of the mask structure units 201 and the mask gaps, the mask layer 20 (carrying the substrate 10) can be efficiently and quickly removed using wet etching. This allows the nitride interconnect layer 30 and the epitaxial structure 40 to be transferred to the terminal substrate, obtaining a vertical nitride semiconductor chip. The vertical nitride semiconductor chip obtained by this method has low cost and is suitable for mass production.

[0108] Preferably, the material of the mask structure unit 201 includes any one or a combination of at least two of nitrides, oxides, metals or organic materials, and more preferably includes any one or a combination of at least two of GaN, AlN, GaN, InGaN, AlGaN, AlInGaN, AlInN, InN, Al2O3, SiO2, Si3N4, Ga2O3, ZnO, Fe, Cu, Ag or photoresist.

[0109] Preferably, the height of the mask structure unit 201 is 1-5 μm, for example, it can be 1.1 μm, 1.3 μm, 1.5 μm, 1.7 μm, 1.9 μm, 2 μm, 2.1 μm, 2.3 μm, 2.5 μm, 2.8 μm, 3 μm, 3.5 μm, 4 μm or 4.5 μm, and more preferably 1-3 μm; the width is 1-6 μm, for example, it can be 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm or 5.5 μm.

[0110] Preferably, the spacing between any two adjacent mask structure units 201 is 0.1-2μm, for example, it can be 0.3μm, 0.5μm, 0.7μm, 0.9μm, 1μm, 1.2μm, 1.5μm, 1.8μm, 2μm, 2.2μm, 2.5μm or 2.8μm.

[0111] Preferably, the nitride bonding layer 30 is an n-type nitride bonding layer.

[0112] Preferably, the thickness of the nitride bonding layer 30 is 1-5 μm, for example, it can be 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm or 4.5 μm, etc.

[0113] Preferably, the conductivity difference between the first n-type nitride layer 411 and the second n-type nitride layer 421, and / or the conductivity difference between the first p-type nitride layer 413 and the second p-type nitride layer 423, is achieved through different doping concentrations, that is, the doping concentration of the first n-type nitride layer is greater than that of the second n-type nitride layer, and / or the doping concentration of the first p-type nitride layer is greater than that of the second p-type nitride layer. Specifically, this includes three cases:

[0114] (1) The doping concentration of the first n-type nitride layer 411 is greater than that of the second n-type nitride layer 421, and the doping concentrations of the first p-type nitride layer 413 and the second p-type nitride layer 423 are the same.

[0115] (2) The first n-type nitride layer 411 and the second n-type nitride layer 421 have the same doping concentration, and the doping concentration of the first p-type nitride layer 413 is greater than that of the second p-type nitride layer 423.

[0116] (3) The doping concentration of the first n-type nitride layer 411 is greater than the doping concentration of the second n-type nitride layer 421, and the doping concentration of the first p-type nitride layer 413 is greater than the doping concentration of the second p-type nitride layer 423.

[0117] Preferably, the doping concentration of the first n-type nitride layer 411 is greater than the doping concentration of the second n-type nitride layer 421. The higher doping concentration of the first n-type nitride layer 411 results in a highly conductive epitaxial layer, which helps reduce the voltage of the first epitaxial region, but also exhibits relatively high leakage current and low ESD resistance. Conversely, the lower doping concentration of the second n-type nitride layer 421 results in a less conductive epitaxial layer, increasing the voltage of the second epitaxial region while achieving relatively low leakage current and high ESD resistance. Therefore, in the nitride semiconductor structure, the difference in doping concentration between the first and second n-type nitride layers leads to a difference in conductivity, thereby achieving complementary performance between the two epitaxial regions and giving the nitride semiconductor structure excellent overall optoelectronic performance.

[0118] Preferably, such as Figure 2 As shown, the second n-type nitride layer 421 includes a first n-type sublayer 4211 and a second n-type sublayer 4212. The first n-type sublayer 4211 is located on the side close to the substrate 10. The conductivity of the first n-type sublayer 4211 is greater than that of the second n-type sublayer 4212.

[0119] Preferably, the difference in conductivity between the first n-type sublayer 4211 and the second n-type sublayer 4212 is achieved through the difference in doping concentration, that is, the doping concentration of the first n-type sublayer 4211 is greater than the doping concentration of the second n-type sublayer 4212.

[0120] Based on the high conductivity epitaxial layer formed by the first n-type nitride layer 411 through high doping and the reduction of the voltage of the first epitaxial region, the second n-type nitride layer 421 with low doping includes a first n-type sublayer and a second n-type sublayer with different doping concentrations. The lower doping concentration of the second n-type sublayer 4212 forms a relatively high resistance, which has a good diffusion effect on the electrons injected into the first n-type sublayer 4211, improves the uniformity of electron injection into the nitride light-emitting layer, thereby improving the brightness of the nitride semiconductor chip, reducing the efficiency drop effect under high current, and achieving excellent comprehensive optoelectronic performance.

[0121] Preferably, the thickness of the first n-type nitride layer 411 is 0.5-2.5 μm, such as 0.7 μm, 0.9 μm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.2 μm or 2.4 μm.

[0122] Preferably, the doping concentration of the first n-type nitride layer 411 is 1×10⁻⁶. 19 -8×10 19 cm -3 For example, 1×10 19 cm -3 1.5×10 19 cm -3 2×10 19 cm -3 2.5×10 19 cm -3 3×10 19 cm -3 3.5×10 19 cm -3 4×10 19 cm -3 4.5×10 19 cm -3 5×10 19 cm -3 5.5×10 19 cm -3 6×10 19 cm -3 6.5×10 19 cm -3 7×10 19 cm -3 Or 7.5×10 19 cm -3 wait.

[0123] Preferably, the second n-type nitride layer 421 is a non-molecular layer (i.e., a single-layer structure with the same doping concentration), and its doping concentration is 5 × 10⁻⁶. 18 -5×10 19 cm -3 For example, 5.5 × 10 18 cm -3 6×10 18 cm -3 6.5×10 18 cm -3 7×10 18 cm -3 7.5×10 18 cm -3 8×10 18 cm -3 8.5×10 18 cm -3 9×10 18 cm -3 9.5×10 18 cm -3 1×10 19 cm -3 3×10 19 cm -3 Or 4×10 19 cm -3 The thickness ranges from 0.5 to 2.5 μm, for example, 0.7 μm, 0.9 μm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.2 μm, or 2.4 μm.

[0124] Preferably, the second n-type nitride layer 421 includes a first n-type sublayer 4211 and a second n-type sublayer 4212, wherein the doping concentration of the first n-type sublayer 4211 is 5 × 10⁻⁶. 18 -5×10 19 cm -3 For example, 5.5 × 10 18 cm -3 6×10 18 cm -3 6.5×10 18 cm -3 7×10 18 cm -3 7.5×10 18 cm -3 8×10 18 cm -3 8.5×10 18 cm -3 9×10 18 cm -39.5×10 18 cm -3 1×10 19 cm -3 3×10 19 cm -3 Or 4×10 19 cm -3 The thickness is 0.3-2μm, for example, it can be 0.4μm, 0.5μm, 0.7μm, 0.9μm, 1μm, 1.2μm, 1.5μm or 1.8μm, etc.

[0125] Preferably, the doping concentration of the second n-type sublayer 4212 is 1×10⁻⁶. 17 -5×10 18 cm -3 For example, 2×10 17 cm -3 3×10 17 cm -3 5×10 17 cm -3 7×10 17 cm -3 9×10 17 cm -3 1×10 18 cm -3 2×10 18 cm -3 Or 4×10 18 cm -3 The thickness is 0.2-0.5μm, for example, it can be 0.25μm, 0.3μm, 0.35μm, 0.4μm or 0.45μm, etc.

[0126] Preferably, the doping concentration of the first p-type nitride layer 413 is greater than the doping concentration of the second p-type nitride layer 423. The higher doping concentration of the first p-type nitride layer 413 forms a highly conductive epitaxial layer, which can reduce the voltage of the semi-nitride semiconductor chip. However, as the doping concentration of p-type nitride increases, higher dopants will absorb light incident from the nitride light-emitting layer onto the p-type nitride layer, reducing the brightness of the semiconductor device. Simultaneously, high doping creates high defects in the p-type nitride layer, significantly reducing leakage current and ESD performance. The second p-type nitride layer... The low doping concentration of p-type nitride layer 423 forms a low-conductivity epitaxial layer, which helps reduce the absorption of light incident from the p-type nitride layer onto the p-type nitride layer. Simultaneously, the low doping reduces dopant diffusion into the p-type nitride layer, improving its crystal quality and resulting in high brightness for the nitride semiconductor chip. Furthermore, the relatively low conductivity epitaxial layer formed by low doping facilitates lateral diffusion of holes in the p-type nitride, improving hole injection uniformity. The low doping also reduces defects formed in the p-type nitride layer, effectively improving leakage current and ESD performance. The difference in doping concentration between the first and second p-type nitride layers results in differences in conductivity, thus achieving complementary performance between the two epitaxial regions and giving the nitride semiconductor structure excellent overall optoelectronic performance.

[0127] Preferably, such as Figure 3 As shown, the second p-type nitride layer 423 includes a first p-type sublayer 4231 and a second p-type sublayer 4232. The first p-type sublayer 4231 is located on the side close to the substrate 10. The conductivity of the first p-type sublayer 4231 is greater than that of the second p-type sublayer 4232.

[0128] Preferably, the difference in conductivity between the first p-type sublayer 4231 and the second p-type sublayer 4232 is achieved through a difference in doping concentration, wherein the doping concentration of the first p-type sublayer 4231 is greater than that of the second p-type sublayer 4232.

[0129] Based on the high conductivity epitaxial layer formed by high doping of the first p-type nitride layer 413, the second p-type nitride layer 423 with low doping includes a first p-type sublayer 4231 and a second p-type sublayer 4232 with different doping concentrations. This results in the first p-type sublayer 4231 and the second p-type sublayer 4232 having different hole concentrations, forming a hole concentration gradient, which further improves the hole injection concentration and uniformity, and is beneficial to improving brightness and ESD performance.

[0130] Preferably, the thickness of the first p-type nitride layer 413 is 100-300nm, such as 120nm, 150nm, 180nm, 200nm, 220nm, 250nm or 280nm.

[0131] Preferably, the doping concentration of the first p-type nitride layer 413 is 1×10⁻⁶. 20 -1×10 21 cm -3 For example, 2×10 20 cm -3 3×10 20 cm -3 4×10 20 cm -3 5×10 20 cm -3 6×10 20 cm -3 7×10 20 cm -3 8×10 20 cm -3 Or 9×10 20 cm -3 wait.

[0132] Preferably, the thickness of the second p-type nitride layer 423 is 100-300 nm, such as 120 nm, 150 nm, 180 nm, 200 nm, 220 nm, 250 nm or 280 nm.

[0133] Preferably, the second p-type nitride layer 423 is a non-molecular layer (i.e., a single-layer structure with the same doping concentration), and its doping concentration is 1×10⁻⁶. 19 -5×10 20 cm -3 For example, it can be 2×10 19 cm -3 5×10 19 cm -3 7×10 19 cm -3 9×10 19 cm -3 1×10 20 cm -3 2×10 20 cm -3 3×10 20 cm -3 Or 4×10 20 cm -3 wait.

[0134] Preferably, the second p-type nitride layer 423 includes a first p-type sublayer 4231 and a second p-type sublayer 4232; the doping concentration of the first p-type sublayer 4231 is 8 × 10⁻⁶. 19 -5×10 20 cm -3 For example, 9×10 19 cm-3 1×10 20 cm -3 1.5×10 20 cm -3 2×10 20 cm -3 2.5×10 20 cm -3 3×10 20 cm -3 3.5×10 20 cm -3 4×10 20 cm -3 Or 4.5×10 20 cm -3 The thickness ranges from 20 to 50 nm, such as 22 nm, 25 nm, 28 nm, 30 nm, 32 nm, 35 nm, 38 nm, 40 nm, 42 nm, 45 nm, or 48 nm.

[0135] Preferably, the doping concentration of the second p-type sublayer 4232 is 1×10⁻⁶. 19 -5×10 19 cm -3 For example, it can be 1.5 × 10 19 cm -3 2×10 19 cm -3 2.5×10 19 cm -3 3×10 19 cm -3 3.5×10 19 cm -3 4×10 19 cm -3 Or 4.5×10 19 cm -3 The thickness ranges from 80 to 250 nm, for example, it can be 90 nm, 100 nm, 110 nm, 130 nm, 150 nm, 170 nm, 190 nm, 200 nm, 220 nm or 240 nm, etc.

[0136] Preferably, such as Figure 4 As shown, the second n-type nitride layer 421 includes a first n-type sublayer 4211 and a second n-type sublayer 4212, and the second p-type nitride layer 423 includes a first p-type sublayer 4231 and a second p-type sublayer 4232. Figure 4 The thickness and doping concentration of each sublayer are within the same range as described above.

[0137] Preferably, Figures 1-4In this configuration, the first nitride emitting layer 412 and the second nitride emitting layer 422 each independently comprise alternating nitride quantum well layers and nitride quantum barrier layers. One stacked nitride quantum well layer and one nitride quantum barrier layer constitute one cycle, and the alternating repetition cycle is preferably 3-15, for example, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, or 15.

[0138] Preferably, the thickness of the first nitride light-emitting layer 412 and the second nitride light-emitting layer 422 is independently 15-200nm, for example, it can be 20nm, 30nm, 50nm, 70nm, 90nm, 100nm, 110nm, 130nm, 150nm, 170nm or 190nm, etc.

[0139] Preferably, the ratio of the projected area of ​​the first epitaxial region 40A on the substrate 10 to the projected area of ​​the second epitaxial region 40B on the substrate 10 is 1:(4-10), for example, 1:4.5, 1:5, 1:5.5, 1:6, 1:6.5, 1:7, 1:7.5, 1:8, 1:8.5, 1:9, or 1:9.5, etc. That is, the area of ​​the first epitaxial region is smaller than the area of ​​the second epitaxial region, and the ratio of the two is preferably 1:4-1:10, which enables the overall optoelectronic performance of the nitride semiconductor structure to reach a more perfect state. If the area of ​​the first epitaxial region is too small, the complementary effect of the differentiated optoelectronic performance will not be obvious and the complementary effect cannot be highlighted; if the area of ​​the first epitaxial region is too large, the proportion of the complementary effect of the differentiated optoelectronic performance will be too large, resulting in a low overall optoelectronic performance. In short, it is impossible to obtain a nitride semiconductor chip with excellent overall performance.

[0140] Preferably, the first extended region 40A and the second extended region 40B are arranged side by side or surround each other; wherein, a schematic diagram of the side-by-side arrangement is shown in Figure 4. Figures 1-4 As shown.

[0141] The schematic diagram of the surrounding arrangement is shown below. Figures 5-6 As shown, Figure 5 In this configuration, the second extended region 40B is disposed around the first extended region 40A; Figure 6 In this configuration, the first extended region 40A is disposed around the second extended region 40B. Figure 5 and Figure 6 The materials and structural configuration of each layer have the aforementioned characteristics. Figures 1-4 The same range.

[0142] In one specific embodiment, all nitrides in the nitride semiconductor structure (including nitrides in the nitride interconnect layer and nitrides in the epitaxial structure) independently include any one or a combination of at least two of GaN, InGaN, AlGaN, AlN, AlInGaN, AlInN, or InN.

[0143] In this invention, the n-type nitride includes Si-doped nitride, and the p-type nitride includes Mg-doped nitride.

[0144] In one specific implementation, such as Figures 7a-7d As shown, the method for preparing the nitride semiconductor structure includes the following steps:

[0145] (1) As Figure 7a As shown, a first mask dielectric layer is grown on the substrate 10 and etched to obtain an array composed of mask structure units 201;

[0146] (2) Figure 7b As shown, after filling the space between adjacent mask structure units 201 with a filling medium, a nitride bonding layer 30 is grown, and then the filling medium is removed.

[0147] (3) Figure 7c As shown, a second mask dielectric layer 50 is grown on the nitride bonding layer 30 obtained in step (2);

[0148] (4) Figure 7d As shown, the second mask dielectric layer 50 obtained in step (3) is partially etched, and a first n-type nitride layer 411, a first nitride light-emitting layer 412 and a first p-type nitride layer 413 are sequentially grown on the nitride interconnect layer exposed after etching to form a first epitaxial region.

[0149] The remaining area of ​​the second mask dielectric layer 50 is etched, and a second n-type nitride layer 421, a second nitride light-emitting layer 422, and a second p-type nitride layer 423 are sequentially grown on the exposed nitride interconnect layer after etching to form the second epitaxial region, thus obtaining... Figure 1 The nitride semiconductor structure shown.

[0150] Preferably, the etching method is photolithography.

[0151] Preferably, the filling medium in step (2) is made of a different material than the mask structure unit, and the corrosion resistance of the filling medium is less than that of the mask structure unit.

[0152] Preferably, the filler medium is made of photoresist.

[0153] like Figure 8As shown, the present invention provides a nitride semiconductor chip, including a nitride semiconductor structure as described in the first aspect, an n-type electrode 60 and a p-type electrode 70, wherein the n-type electrode 60 and the p-type electrode 70 are located on the same side of a substrate 10.

[0154] In one specific embodiment, the method for fabricating the nitride semiconductor chip includes: exposing a portion of the bottom 30 of the nitride interconnect layer by dry etching; fabricating an n-type electrode 60 on the bottom 30 of the nitride interconnect layer; fabricating a p-type electrode 70 on the first p-type nitride layer 413 and the second p-type nitride layer 423; and forming a nitride semiconductor chip with the n-type electrode and the p-type electrode on the same side of the substrate.

[0155] like Figure 9 As shown, the nitride semiconductor chip includes the aforementioned nitride semiconductor structure, an n-type electrode 60, and a p-type electrode 70, wherein the n-type electrode 60 and the p-type electrode 70 are located on the same side of the substrate 10; in the nitride semiconductor structure, a second epitaxial region 40B is disposed around the first epitaxial region 40A.

[0156] like Figure 10 As shown, the present invention provides a vertical nitride semiconductor chip, wherein the n-type electrode and the p-type electrode are located on different sides of the terminal substrate, and are fabricated by the nitride semiconductor structure as described above. The vertical nitride semiconductor chip includes an n-type electrode 60, a terminal substrate 80, a semiconductor material layer and a p-type electrode 70 arranged sequentially; the semiconductor material layer is the nitride interconnect layer 30 and the epitaxial structure 40 in the nitride semiconductor structure.

[0157] In one specific embodiment, the vertical nitride semiconductor chip is fabricated as follows: the mask structure unit 201 and the mask layer 20 are removed by wet etching, the nitride interconnect layer 30 is transferred to the terminal substrate 80, then a p-type electrode 70 is fabricated on the first p-type nitride layer 413 and the second p-type nitride layer 423, and an n-type electrode 60 is formed on the terminal substrate 80, resulting in a nitride semiconductor chip with the n-type electrode and the p-type electrode located on different sides of the terminal substrate.

[0158] The following specific embodiments illustrate the nitride semiconductor structure and its preparation method provided by the present invention.

[0159] Example 1

[0160] A nitride semiconductor structure and its fabrication method are disclosed. A schematic diagram of the nitride semiconductor structure is shown below. Figure 1As shown, the structure includes a substrate 10 (sapphire substrate), a mask layer 20, a nitride interconnect layer 30 (i.e., an n-type GaN interconnect layer 30, Si-doped GaN), and an epitaxial structure 40 arranged sequentially. The mask layer 20 includes an array of multiple mask structure units 201 (SiO2), with adjacent mask structure units 201 being independent and not connected to each other. The epitaxial structure includes a first epitaxial region 40A and a second epitaxial region 40B, with the projected area ratio (i.e., area ratio) of the first epitaxial region 40A and the second epitaxial region 40B on the substrate 10 being 1:6.

[0161] The first epitaxial region 40A includes a first n-type nitride layer 411 (i.e., a first n-type GaN layer 411, Si-doped GaN), a first nitride light-emitting layer 412 (GaN / InGaN quantum well light-emitting layer), and a first p-type nitride layer 413 (i.e., a first p-type GaN layer 413, Mg-doped GaN) sequentially disposed; the first n-type nitride layer 411 is located on the side closer to the substrate 10. The second epitaxial region 40B includes a second n-type nitride layer 421 (i.e., a second n-type GaN layer 421, Si-doped GaN), a second nitride light-emitting layer 422 (GaN / InGaN quantum well light-emitting layer), and a second p-type nitride layer 423 (i.e., a second p-type GaN layer 423, Mg-doped GaN) sequentially disposed; the second n-type nitride layer 421 is located on the side closer to the substrate 10. The conductivity (doping concentration) of the first n-type nitride layer 411 is greater than that of the second n-type nitride layer 421, and the conductivity (doping concentration) of the first p-type nitride layer 413 is greater than that of the second p-type nitride layer 423.

[0162] The method for preparing the nitride semiconductor structure includes the following steps, the preparation process as follows: Figures 7a-7d As shown:

[0163] (1) As Figure 7a As shown, a sapphire substrate is provided and placed in the reaction chamber of a PECVD (Plasma Enhanced Chemical Vapor Deposition) device. SiH4 and NO2 are introduced at a temperature of 400℃ and a pressure of 3.5 torr to grow a first SiO2 mask dielectric layer with a thickness of 1.5μm on the substrate 10. The first SiO2 mask dielectric layer is etched using photolithography to obtain an array composed of mask structure units 201, with mask gaps between adjacent mask structure units 201.

[0164] (2) Figure 7bAs shown, after filling the spaces between adjacent mask structure units 201 with a filler medium (photoresist), an n-type GaN interconnect layer 30 with a thickness of 2.5 μm is grown on the mask structure units 201 and the photoresist filler medium using MOCVD technology. The n-type doping concentration is 5 × 10⁻⁶. 18 cm -3 Then the filling medium is removed, wherein the n-type GaN interconnect layer 30 is grown at a temperature of 1085℃, a growth pressure of 150 torr, and a growth atmosphere of H2.

[0165] (3) Figure 7c As shown, a second SiO2 mask dielectric layer 50 with a thickness of 2 μm is grown on the n-type GaN interconnect layer 30 obtained in step (2), and the process is the same as in step (1);

[0166] (4) Figure 7d As shown, the second mask dielectric layer 50 obtained in step (3) is partially etched using photolithography. Then, the first n-type GaN layer 411 with a thickness of 2 μm, the first nitride light-emitting layer 412 with a thickness of 105 nm, and the first p-type GaN layer 413 with a thickness of 150 nm are sequentially grown on the exposed n-type GaN interconnect layer 30 after etching using MOCVD technology to form the first epitaxial region.

[0167] The doping concentration of the first n-type nitride layer 411 is 2 × 10⁻⁶. 19 cm -3 The growth temperature was 1095℃, the growth pressure was 200 torr, and the growth atmosphere was H2.

[0168] The first nitride luminescent layer 412 is an InGaN quantum well layer and a GaN quantum barrier layer that repeat 7 cycles periodically. The InGaN quantum well layer is 3 nm thick, with a growth temperature of 760 °C, a growth pressure of 400 torr, and a growth atmosphere of N2. The GaN quantum barrier layer is 12 nm thick, with a growth temperature of 880 °C, a growth pressure of 400 torr, and a growth atmosphere of H2.

[0169] The doping concentration of the first p-type nitride layer 413 is 2 × 10⁻⁶. 20 cm -3 Growth temperature 980℃, growth pressure 600 torr, growth atmosphere H2;

[0170] (5) The remaining area of ​​the second mask dielectric layer 50 is etched using photolithography. Then, a second n-type GaN layer 421 with a thickness of 2 μm, a second nitride emitting layer 422 with a thickness of 105 nm, and a second p-type GaN layer 423 with a thickness of 150 nm are sequentially grown on the exposed nitride interconnect layer 30 using MOCVD technology to form the second epitaxial region, thus obtaining... Figure 1 The nitride semiconductor structure shown;

[0171] The doping concentration of the second n-type GaN layer 421 is 8 × 10⁻⁶. 18 cm -3 The growth temperature was 1095℃, the growth pressure was 200 torr, and the growth atmosphere was H2.

[0172] The second nitride luminescent layer 422 is an InGaN quantum well layer and a GaN quantum barrier layer that repeat 7 cycles periodically. The InGaN quantum well layer is 3 nm thick, with a growth temperature of 760 °C, a growth pressure of 400 torr, and a growth atmosphere of N2. The GaN quantum barrier layer is 12 nm thick, with a growth temperature of 880 °C, a growth pressure of 400 torr, and a growth atmosphere of H2.

[0173] The doping concentration of the second p-type nitride layer 423 is 2 × 10⁻⁶. 20 cm -3 The growth temperature was 980℃, the growth pressure was 400 torr, and the growth atmosphere was H2.

[0174] Example 2

[0175] A nitride semiconductor structure and its fabrication method are disclosed. A schematic diagram of the nitride semiconductor structure is shown below. Figure 2 As shown, the difference between this embodiment and Embodiment 1 is only that the second n-type GaN layer 421 includes a first n-type GaN sublayer 4211 and a second n-type GaN sublayer 4212, wherein the first n-type GaN sublayer 4211 is located on the side closer to the substrate 10; and the doping concentration of the first n-type GaN sublayer 4211 is 8 × 10⁻⁶. 18 cm -3 The thickness is 1.2 μm; the doping concentration of the second n-type GaN sublayer 4212 is 2 × 10⁻⁶. 17 cm -3 The thickness is 0.3 μm; other structures, materials and preparation methods are the same as in Example 1.

[0176] Example 3

[0177] A nitride semiconductor structure and its fabrication method are disclosed. A schematic diagram of the nitride semiconductor structure is shown below. Figure 3 As shown, the difference between this embodiment and Embodiment 1 is only that the second p-type GaN layer 423 includes a first p-type GaN sublayer 4231 and a second p-type GaN sublayer 4232, wherein the first p-type GaN sublayer 4231 is located on the side closer to the substrate 10; and the doping concentration of the first p-type GaN sublayer 4231 is 1×10⁻⁶. 20 cm -3 The thickness is 25 nm; the doping concentration of the second p-type GaN sublayer 4232 is 3 × 10⁻⁶. 19 cm -3The thickness is 125 nm; other structures, materials and preparation methods are the same as in Example 1.

[0178] Example 4

[0179] A nitride semiconductor structure and its fabrication method are disclosed. A schematic diagram of the nitride semiconductor structure is shown below. Figure 4 As shown, its difference from Example 1 lies only in:

[0180] The second n-type GaN layer 421 includes a first n-type GaN sublayer 4211 and a second n-type GaN sublayer 4212. The first n-type GaN sublayer 4211 is located on the side closest to the substrate 10. The doping concentration of the first n-type GaN sublayer 4211 is 8 × 10⁻⁶. 18 cm -3 The thickness is 1.2 μm; the doping concentration of the second n-type GaN sublayer 4212 is 2 × 10⁻⁶. 17 cm -3 The thickness is 0.3 μm;

[0181] The second p-type GaN layer 423 includes a first p-type GaN sublayer 4231 and a second p-type GaN sublayer 4232. The first p-type GaN sublayer 4231 is located on the side closest to the substrate 10. The doping concentration of the first p-type GaN sublayer 4231 is 1×10⁻⁶. 20 cm -3 The thickness is 25 nm; the doping concentration of the second p-type GaN sublayer 4232 is 3 × 10⁻⁶. 19 cm -3 The thickness is 125nm;

[0182] The other structures, materials, and preparation methods are the same as in Example 1.

[0183] Example 5

[0184] A nitride semiconductor structure and its fabrication method are disclosed. A schematic diagram of the nitride semiconductor structure is shown below. Figure 1 As shown, the preparation method differs from that in Example 1 only in that the doping concentration of the first p-type nitride layer 413 is 5 × 10⁻⁶. 20 cm -3 Other structures, materials and preparation methods are the same as in Example 1.

[0185] Example 6

[0186] A nitride semiconductor structure and its fabrication method are disclosed. A schematic diagram of the nitride semiconductor structure is shown below. Figure 1 As shown, the preparation method differs from that in Example 1 only in that the doping concentration of the first n-type nitride layer 411 is 8 × 10⁻⁶. 19 cm-3 The doping concentration of the first p-type nitride layer 413 is 5 × 10⁻⁶. 20 cm -3 Other structures, materials and preparation methods are the same as in Example 1.

[0187] Comparative Example 1

[0188] A nitride semiconductor structure differs from Example 1 only in that the first n-type GaN layer 411 and the second n-type GaN layer 421 have the same doping concentration (conductivity), both being 8 × 10⁻⁶. 18 cm -3 The first p-type GaN layer 413 and the second p-type GaN layer 423 have the same doping concentration (conductivity), both being 2 × 10⁻⁶. 20 cm -3 In the method for preparing the nitride semiconductor structure, the process of setting the second mask dielectric layer 50 in step (3) is not required. The same n-type nitride layer, nitride light-emitting layer and p-type nitride layer are directly grown on the nitride interconnect layer 30 using MOCVD technology; other structures and materials are the same as in Example 1.

[0189] Comparative Example 2

[0190] A nitride semiconductor structure differs from Example 1 only in that the first n-type GaN layer 411 and the second n-type GaN layer 421 have the same doping concentration (conductivity), both being 2 × 10⁻⁶. 19 cm -3 The first p-type GaN layer 413 and the second p-type GaN layer 423 have the same doping concentration (conductivity), both being 2 × 10⁻⁶. 20 cm -3 In the method for preparing the nitride semiconductor structure, the process of setting the second mask dielectric layer 50 in step (3) is not required. The same n-type nitride layer, nitride light-emitting layer and p-type nitride layer are directly grown on the nitride interconnect layer 30 using MOCVD technology; other structures and materials are the same as in Example 1.

[0191] Comparative Example 3

[0192] A nitride semiconductor structure differs from Example 1 only in that the area ratio of the first epitaxial region 40A and the second epitaxial region 40B is 1:2; all other structures and materials are the same as in Example 1.

[0193] Performance testing:

[0194] The nitride semiconductor structures provided in Examples 1-6 and Comparative Examples 1-3 were tested using photoluminescence (PL) to determine the dominant wavelength (WLD), wavelength uniformity (std), and warpage (bow). These structures were then fabricated into LED devices using the same process. Twenty LED chips were selected for testing. Luminance (Lop) and voltage (VF) were measured at 2mA using an LED chip prober. Leakage current was measured under a reverse voltage of 15V to obtain the IR yield. ESD performance was tested under a reverse breakdown voltage of 2000V to obtain the ESD yield. The data are shown in Table 1 below.

[0195] Table 1

[0196]

[0197] According to the performance test results in Table 1, compared with the nitride semiconductor structure without partitioning in Comparative Examples 1-2, in Embodiments 1-6 of the present invention, by setting up a first epitaxial region and a second epitaxial region with different conductivity, the high conductivity of the first n-type nitride layer and / or the first p-type nitride layer compensates for the voltage of the epitaxial structure, making the performance of the nitride semiconductor structure complementary, thereby obtaining excellent comprehensive optoelectronic performance, and thus obtaining a semiconductor chip with excellent comprehensive performance and large-size epitaxy, which has lower voltage, higher brightness, lower leakage current IR yield and ESD yield.

[0198] Comparative Example 3 uses a larger area ratio (1:2) of the first region 40A and the second epitaxial region 40B. The larger area of ​​the first region 40A leads to an excessively large proportion of the complementary effect of the differentiated optoelectronic performance. Although the voltage is reduced, the brightness, leakage current and ESD performance are degraded, resulting in low overall optoelectronic performance and making it impossible to obtain a nitride semiconductor chip with excellent overall performance.

[0199] Furthermore, the data in Table 1 also shows that the bow values ​​of the epitaxial structures in Examples 1-6 of this invention are all less than 80 μm, while the industry standard is generally 100-110 μm. The warpage of this invention is significantly lower. This may be because the first and second epitaxial regions in this invention are obtained through two growth processes, which is equivalent to epitaxial growth in different regions on the epitaxial substrate. The area of ​​a single epitaxial region is small, thereby reducing the epitaxial growth stress. This is very beneficial for achieving Micro-LED epitaxial wafers with higher requirements for light emission uniformity.

[0200] The applicant declares that this invention illustrates the nitride semiconductor structure, its preparation method, and its application through the above embodiments. However, this invention is not limited to the above process steps, meaning that this invention does not necessarily rely on the above process steps to be implemented. Those skilled in the art should understand that any improvements to this invention, equivalent substitutions of the raw materials used in this invention, additions of auxiliary components, and selection of specific methods all fall within the protection and disclosure scope of this invention.

Claims

1. A nitride semiconductor structure, characterized in that, The nitride semiconductor structure includes a substrate, a mask layer, a nitride interconnect layer, and an epitaxial structure arranged sequentially. The epitaxial structure includes a first epitaxial region and a second epitaxial region. The first epitaxial region and the second epitaxial region are arranged side by side or around each other. The ratio of the projected area of ​​the first epitaxial region on the substrate to the projected area of ​​the second epitaxial region on the substrate is 1:(4-10). The first epitaxial region includes a first n-type nitride layer, a first nitride light-emitting layer, and a first p-type nitride layer disposed sequentially; the first n-type nitride layer is located on the side closer to the substrate; The second epitaxial region includes a second n-type nitride layer, a second nitride light-emitting layer, and a second p-type nitride layer disposed sequentially; the second n-type nitride layer is located on the side closer to the substrate; The conductivity of the first n-type nitride layer is greater than that of the second n-type nitride layer.

2. The nitride semiconductor structure according to claim 1, characterized in that, The conductivity of the first p-type nitride layer is greater than that of the second p-type nitride layer.

3. The nitride semiconductor structure according to claim 1, characterized in that, The mask layer comprises an array of mask structure units.

4. The nitride semiconductor structure according to claim 3, characterized in that, The material of the mask structure unit includes any one or a combination of at least two of nitrides, oxides, metals, or organic materials.

5. The nitride semiconductor structure according to claim 3, characterized in that, The material of the mask structure unit includes any one or a combination of at least two of GaN, AlN, GaN, InGaN, AlGaN, AlInGaN, AlInN, InN, Al2O3, SiO2, Si3N4, Ga2O3, ZnO, Fe, Cu, Ag, or photoresist.

6. The nitride semiconductor structure according to claim 3, characterized in that, The height of the mask structure unit is 1-5 μm.

7. The nitride semiconductor structure according to claim 6, characterized in that, The height of the mask structure unit is 1-3 μm.

8. The nitride semiconductor structure according to claim 3, characterized in that, The width of the mask structure unit is 1-6 μm.

9. The nitride semiconductor structure according to claim 3, characterized in that, The spacing between any two adjacent mask structure units is 0.1-2 μm.

10. The nitride semiconductor structure according to claim 1, characterized in that, The nitride bonding layer is an n-type nitride bonding layer.

11. The nitride semiconductor structure according to claim 1, characterized in that, The thickness of the nitride bonding layer is 1-5 μm.

12. The nitride semiconductor structure according to claim 1, characterized in that, The doping concentration of the first n-type nitride layer is greater than that of the second n-type nitride layer.

13. The nitride semiconductor structure according to claim 1, characterized in that, The second n-type nitride layer includes a first n-type sublayer and a second n-type sublayer, wherein the first n-type sublayer is located on the side closer to the substrate; the conductivity of the first n-type sublayer is greater than that of the second n-type sublayer.

14. The nitride semiconductor structure according to claim 13, characterized in that, The doping concentration of the first n-type sublayer is greater than that of the second n-type sublayer.

15. The nitride semiconductor structure according to claim 1, characterized in that, The doping concentration of the first n-type nitride layer is 1×10 19 -8×10 19 cm -3 .

16. The nitride semiconductor structure according to claim 1, characterized in that, The doping concentration of the second n-type nitride layer is 1×10 17 -5×10 19 cm -3 .

17. The nitride semiconductor structure according to claim 1, characterized in that, The thickness of the first n-type nitride layer and the second n-type nitride layer are each independently 0.5-2.5 μm.

18. The nitride semiconductor structure according to claim 1, characterized in that, The doping concentration of the first p-type nitride layer is greater than that of the second p-type nitride layer.

19. The nitride semiconductor structure according to claim 1, characterized in that, The second p-type nitride layer includes a first p-type sublayer and a second p-type sublayer, wherein the first p-type sublayer is located on the side closer to the substrate; the conductivity of the first p-type sublayer is greater than that of the second p-type sublayer.

20. The nitride semiconductor structure according to claim 19, characterized in that, The doping concentration of the first p-type sublayer is greater than that of the second p-type sublayer.

21. The nitride semiconductor structure according to claim 1, characterized in that, The doping concentration of the first p-type nitride layer is 1×10⁻⁶. 20 -1×10 21 cm -3 .

22. The nitride semiconductor structure according to claim 1, characterized in that, The doping concentration of the second p-type nitride layer is 1×10⁻⁶. 19 -5×10 20 cm -3 .

23. The nitride semiconductor structure according to claim 1, characterized in that, The thicknesses of the first p-type nitride layer and the second p-type nitride layer are each independently 100-300 nm.

24. The nitride semiconductor structure according to claim 1, characterized in that, The first nitride luminescent layer and the second nitride luminescent layer each independently include alternating nitride quantum well layers and nitride quantum barrier layers.

25. The nitride semiconductor structure according to claim 24, characterized in that, The alternating repeat cycle is 3-15.

26. The nitride semiconductor structure according to claim 1, characterized in that, The thickness of the first nitride luminescent layer and the second nitride luminescent layer are each independently 15-200 nm.

27. A method for preparing a nitride semiconductor structure as described in any one of claims 1-26, characterized in that, The fabrication method includes: sequentially depositing a mask layer, a nitride interconnect layer, and an epitaxial structure on a substrate to obtain the nitride semiconductor structure.

28. A nitride semiconductor chip, characterized in that, The nitride semiconductor chip includes a nitride semiconductor structure as described in any one of claims 1-26, an n-type electrode, and a p-type electrode, wherein the n-type electrode and the p-type electrode are located on the same side of the substrate.

29. A nitride semiconductor chip, characterized in that, The nitride semiconductor chip is fabricated using the nitride semiconductor structure as described in any one of claims 1-26.

30. The nitride semiconductor chip according to claim 29, characterized in that, The method for fabricating the nitride semiconductor chip includes: removing the substrate and mask layer in the nitride semiconductor structure, and setting a terminal substrate on the side of the nitride interconnect layer away from the epitaxial structure; setting an n-type electrode on the terminal substrate, and setting a p-type electrode on the first p-type nitride layer and / or the second p-type nitride layer.

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