Asynchronous task execution for neural processor circuitry

Abstract

Implementations relate to a neural processor circuit that includes one or more plane engine circuits that perform non-convolution operations in parallel with convolution operations performed by one or more neural engine circuits. The neural engine circuits perform convolution operations on neural input data corresponding to one or more neural engine tasks to generate neural output data. The plane engine circuits perform non-convolution operations on plane input data corresponding to one or more plane engine tasks to generate plane output data. Data processor circuits in the neural processor circuit resolve data dependencies between the one or more neural engine tasks and the one or more plane engine tasks by controlling reading of the neural output data as the plane input data by the plane engine circuits or reading of the plane output data as the neural input data by the neural engine circuits.

Description

Background Technology

[0001] 1. The technical field of this disclosure This disclosure relates to a circuit for performing operations related to neural networks, and more specifically to performing neural engine tasks and planar engine tasks asynchronously.

[0002] 2. Related technical descriptions Artificial neural networks (ANNs) are computational systems or models that use a set of connected nodes to process input data. ANNs are typically organized into layers, with different layers performing different types of transformations on their inputs. Extensions or variants of ANNs such as convolutional neural networks (CNNs), recurrent neural networks (RNNs), and deep belief networks (DBNs) have received considerable attention. These computational systems or models typically involve a wide range of computational operations, including multiplication and accumulation. For example, CNNs are a class of machine learning techniques that primarily use convolutions between input data and kernel data; convolutions can be decomposed into multiplication and accumulation operations.

[0003] These machine learning systems or models can be configured differently depending on the type of input data and the operations to be performed. Such varied configurations would include, for example, preprocessing operations, the number of channels in the input data, the kernel data to be used, the nonlinear functions to be applied to the convolution results, and the application of various post-processing operations. Instantiating and executing machine learning systems or models with various configurations using a central processing unit (CPU) and its main memory is relatively straightforward, as such systems or models can be instantiated simply by updating the code. However, relying solely on the CPU for the various operations of these machine learning systems or models would consume significant CPU bandwidth and increase overall power consumption. Summary of the Invention

[0004] The implementation scheme relates to a neural processor circuit including one or more planar engine circuits that perform non-convolution operations in parallel with convolution operations performed by the one or more neural engine circuits. The neural engine circuits perform convolution operations on neural input data corresponding to the one or more neural engine tasks to generate neural output data. The planar engine circuits perform non-convolution operations on planar input data corresponding to the one or more planar engine tasks to generate planar output data. A data processor circuit in the neural processor circuit resolves data dependencies between the one or more neural engine tasks and the one or more planar engine tasks by controlling whether the planar engine circuits read the neural output data as planar input data or vice versa.

[0005] In one or more implementations, two or more neural engine tasks in a neural engine task and one planar engine task in a planar engine task are executed in parallel, or two or more planar engine tasks in a planar engine task and one neural engine task in a neural engine task are executed in parallel.

[0006] In one or more embodiments, the data processor circuitry includes a buffer circuitry and a data control circuitry. The buffer circuitry stores at least one of neural output data or planar output data. In response to the availability of the neural output data or planar output data in the buffer circuitry, the data control circuitry selectively enables the one or more neural engines to read neural input data corresponding to the neural engine task, or enables the one or more planar engines to read planar input data corresponding to the planar engine task.

[0007] In one or more embodiments, the data processor circuitry further includes a task buffer that stores entries for configuration data corresponding to a subset of neural engine tasks and a planar engine task. The configuration data indicates the configuration of the data control circuitry for the corresponding neural engine task or the corresponding planar engine task, as well as the data dependencies between the subset of the neural engine task and the planar engine task.

[0008] In one or more embodiments, the neural processor circuitry includes a task manager circuit. The task manager circuit receives multiple task descriptors that define the configuration of the neural processor circuitry to execute corresponding neural engine tasks or corresponding planar engine tasks, extracts configuration data corresponding to the task descriptors, and sends the extracted configuration data to a data processor circuit for processing and storage. The task descriptors can be generated during the compilation process.

[0009] In one or more embodiments, the data processor circuitry discards a first portion of the configuration data for a completed neural engine task or a completed planar engine task from the task buffer, and in response to discarding the first portion of the configuration data, stores a second portion of the configuration data for a new neural engine task or a new planar engine task.

[0010] In one or more implementations, the data processor circuit resolves data hazards between one or more neural engine tasks and one or more planar engine tasks by controlling one or more neural engine circuits to write neural output data into the data processor circuit or by one or more planar engine circuits to write planar output data into the data processor circuit.

[0011] In one or more embodiments, the non-convolution operation includes at least one of operations that reduce the spatial size of the planar input data and element-wise operations on the planar input data.

[0012] In one or more embodiments, the data processor circuitry causes one or more neural engine circuitry to perform one or more neural engine tasks in a first sequence as determined by a compilation process for a neural network, and causes one or more planar engine circuitry to perform one or more planar engine tasks in a second sequence as determined by the compilation process. Attached Figure Description

[0013] Figure 1 It is a high-level diagram of an electronic device according to the implementation plan.

[0014] Figure 2 This is a block diagram illustrating components in an electronic device according to one embodiment.

[0015] Figure 3 This is a block diagram illustrating a neural processor circuit according to one embodiment.

[0016] Figure 4 This is a block diagram of a neural engine in a neural processor circuit according to one implementation scheme.

[0017] Figure 5 This is a block diagram of a planar engine in a neural processor circuit according to one implementation scheme.

[0018] Figure 6 This is a diagram illustrating the programming of the grating and data flow control circuitry, components for configuring neural processor circuitry, according to one embodiment.

[0019] Figure 7 This is a schematic block diagram illustrating a neural network represented by a task list according to one implementation scheme.

[0020] Figure 8 This is a timing diagram illustrating the execution of a task in a neural processor circuit according to one embodiment.

[0021] Figure 9 It is a block diagram of the data control circuit in a data processor circuit according to one implementation scheme.

[0022] Figure 10 This is a block diagram of a neural task manager in a neural processor circuit according to one implementation scheme.

[0023] Figure 11 This is a diagram illustrating the use of a task queue to retrieve task descriptors according to one implementation scheme.

[0024] Figure 12This is a diagram illustrating a task descriptor according to one implementation scheme.

[0025] Figure 13 This is a block diagram illustrating the acquisition queue and configuration queue according to one implementation scheme.

[0026] Figure 14 This is a flowchart illustrating a method for asynchronously processing neural engine tasks and planar engine tasks according to one implementation scheme.

[0027] For illustrative purposes only, the accompanying drawings and detailed descriptions depict various non-limiting embodiments. Detailed Implementation

[0028] Reference will now be made in detail to the embodiments, examples of which are shown in the accompanying drawings. Numerous specific details are shown in the following detailed description to provide a full understanding of the various described embodiments. However, the embodiments described may be implemented without these specific details. In other cases, well-known methods, processes, components, circuits, and networks are not described in detail so as not to unnecessarily obscure the various aspects of the embodiments.

[0029] Embodiments of this disclosure relate to asynchronously executing neural engine tasks by neural engine circuitry and planar engine tasks by planar engine circuitry within a neural processor circuit. The neural engine circuitry is efficient when performing convolution operations, while the planar engine is efficient when performing non-convolution operations. To address data dependencies between the neural engine and planar engine tasks, a data processor circuitry storing input data for processing at the neural engine and planar engine circuitries selectively enables the neural engine and planar engine circuitries to access the input data only when the data dependency requirement for either the neural engine or planar engine task is satisfied. The data processor circuitry also ensures that output data from the neural engine and planar engine circuitries to be written into the data processor circuitry does not cause data conflicts.

[0030] Exemplary electronic devices This document describes implementations of electronic devices, user interfaces for such devices, and related processes for using such devices. In some implementations, the device is a portable communication device, such as a mobile phone, that also includes other functions such as a personal digital assistant (PDA) and / or music player functionality. Exemplary implementations of portable multi-functional devices include, but are not limited to, the iPhone from Apple Inc. (Cupertino, California). ® Devices, iPod Touch ® Devices, Apple Watch ® Devices and iPads® Device. Alternatively, other portable electronic devices, such as wearable devices, laptops, or tablets, may be used. In some embodiments, the device is not a portable communication device, but a desktop computer or other computing device not designed for portable use. In some embodiments, the disclosed electronic device may include a touch-sensitive surface (e.g., a touchscreen display and / or touchpad). The following is combined with… Figure 1 The exemplary electronic device described (e.g., device 100) may include a touch-sensitive surface for receiving user input. The electronic device may also include one or more other physical user interface devices, such as a physical keyboard, mouse, and / or joystick.

[0031] Figure 1 This is a high-level diagram of an electronic device 100 according to one embodiment. Device 100 may include one or more physical buttons, such as a "home" button or a menu button 104. Menu button 104 is used, for example, to navigate to any application in a set of applications running on device 100. In some embodiments, menu button 104 includes a fingerprint sensor for recognizing a fingerprint on menu button 104. The fingerprint sensor can be used to determine whether the finger on menu button 104 has a fingerprint that matches a fingerprint stored for unlocking device 100. Alternatively, in some embodiments, menu button 104 is implemented as a soft key in a graphical user interface (GUI) displayed on a touchscreen.

[0032] In some embodiments, device 100 includes a touchscreen 150, a menu button 104, a push-button 106 for powering the device on / off and for locking the device, a volume control button 108, a subscriber identity module (SIM) card slot 110, a headset jack 112, and a docking / charging external port 124. The push-button 106 can be used to power the device on / off by pressing the button and holding it in the pressed state for a predefined time interval; to lock the device by pressing the button and releasing it before the predefined time interval has elapsed; and / or to unlock the device or initiate an unlocking process. In an alternative embodiment, device 100 also accepts voice input via microphone 113 for activating or deactivating certain functions. Device 100 includes various components, including but not limited to memory (which may include one or more computer-readable storage media), a memory controller, one or more central processing units (CPUs), peripheral interfaces, RF circuitry, audio circuitry, a speaker 111, a microphone 113, an input / output (I / O) subsystem, and other input or control devices. Device 100 may include one or more image sensors 164, one or more proximity sensors 166, and one or more accelerometers 168. Device 100 may include more than one type of image sensor 164. Each type may include more than one image sensor 164. For example, one type of image sensor 164 may be a camera, and another type of image sensor 164 may be an infrared sensor for facial recognition performed by one or more machine learning models stored in device 100. Device 100 may include Figure 1 Components not shown include, for example, an ambient light sensor, a dot projector, and a floodlight illuminator for supporting facial recognition.

[0033] Device 100 is merely one example of an electronic device, and device 100 may have more or fewer components than those listed above, some of which may be combined into a single component or have different configurations or arrangements. The various components of device 100 listed above are embodied in hardware, software, firmware, or combinations thereof, including one or more signal processing and / or application-specific integrated circuits (ASICs).

[0034] Figure 2 This is a block diagram illustrating components in device 100 according to one embodiment. Device 100 is capable of performing various operations, including implementing one or more machine learning models. For this and other purposes, device 100 may include an image sensor 202, a system-on-a-chip (SOC) component 204, system memory 230, permanent memory (e.g., flash memory) 228, a motion sensor 234, and a display 216, among other components. Figure 2 The components shown are merely illustrative. For example, device 100 may include... Figure 2Other components not shown (such as speakers or microphones). Additionally, some components (such as motion sensor 234) may be omitted from device 100.

[0035] Image sensor 202 is a component for capturing image data and can be implemented as, for example, a complementary metal-oxide-semiconductor (CMOS) active pixel sensor, camera, camcorder, or other device. Image sensor 202 generates raw image data, which is sent to SOC component 204 for further processing. In some embodiments, the image data processed by SOC component 204 is displayed on display 216, stored in system memory 230, permanent memory 228, or transmitted to a remote computing device via a network connection. The raw image data generated by image sensor 202 may be a Bayer color kernel array (CFA) pattern.

[0036] Motion sensor 234 is a component or set of components used to sense the motion of device 100. Motion sensor 234 can generate sensor signals indicating the orientation and / or acceleration of device 100. The sensor signals are sent to SOC component 204 for various operations, such as turning on device 100 or rotating an image displayed on display 216.

[0037] Display 216 is a component for displaying images generated by SOC component 204. Display 216 may include, for example, a liquid crystal display (LCD) device or an organic light-emitting diode (OLED) device. Based on data received from SOC component 204, display 216 may display various images, such as menus, selected operating parameters, images captured by image sensor 202 and processed by SOC component 204, and / or other information (not shown) received from the user interface of device 100.

[0038] System memory 230 is a component used to store instructions executed by SOC component 204 and to store data processed by SOC component 204. System memory 230 can be embodied in any type of memory, including, for example, dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) RAMBUS DRAM (RDRAM), static RAM (SRAM), or combinations thereof.

[0039] Persistent memory 228 is a component used to store data in a non-volatile manner. Even when power is unavailable, persistent memory 228 retains the data. Persistent memory 228 may be embodied as read-only memory (ROM), flash memory, or other non-volatile random access memory devices. Persistent memory 228 stores the operating system and various software applications of device 100. Persistent memory 228 may also store one or more machine learning models, such as regression models, random forest models, support vector machines (SVMs) such as kernel SVMs, and artificial neural networks (ANNs) such as convolutional networks (CNNs), recurrent networks (RNNs), autoencoders, and long short-term memory (LSTMs). Machine learning models can be standalone models that work with neural processor circuitry 218 and various software applications or sensors of device 100. Machine learning models can also be part of software applications. Machine learning models can perform various tasks, such as face recognition, image classification, object, concept and information classification, speech recognition, machine translation, voice recognition, voice command recognition, text recognition, text and context analysis, other natural language processing, prediction, and suggestion.

[0040] Various machine learning models stored in device 100 can be fully trained, untrained, or partially trained to allow device 100 to enhance or continue training the machine learning models as device 100 is used. The operation of the machine learning models includes various computations, such as training the model and using the model to determine runtime results. For example, in one scenario, device 100 captures a user's facial image and uses that image to further improve the machine learning model used to lock or unlock device 100.

[0041] SOC component 204 is embodied as one or more integrated circuit (IC) chips and performs various data processing procedures. SOC component 204 may include, among other sub-components, an image signal processor (ISP) 206, a central processing unit (CPU) 208, a network interface 210, a sensor interface 212, a display controller 214, a neural processor circuit 218, a graphics processor (GPU) 220, a memory controller 222, a video encoder 224, a memory controller 226, and a bus 232 connecting these sub-components. SOC component 204 may include... Figure 2 The sub-components shown have more or fewer sub-components.

[0042] ISP 206 is a circuit that performs each stage of the image processing pipeline. In some implementations, ISP 206 may receive raw image data from image sensor 202 and process the raw image data into a form available to other sub-components of SOC component 204 or components of device 100. ISP 206 may perform various image manipulation operations, such as image panning, horizontal and vertical scaling, color space conversion, and / or image stabilization transformations.

[0043] CPU 208 can be implemented using any suitable instruction set architecture and can be configured to execute instructions defined in that instruction set architecture. CPU 208 can be a general-purpose or embedded processor using any of a variety of instruction set architectures (ISAs), such as x86, PowerPC, SPARC, RISC, ARM, or MIPS ISA, or any other suitable ISA. Although Figure 2 A single CPU is shown, but SOC component 204 may include multiple CPUs. In a multiprocessor system, each CPU may collectively implement the same ISA, but this is not required.

[0044] The graphics processing unit (GPU) 220 is a graphics processing circuit for executing graphics data. For example, the GPU 220 may render objects to be displayed in a frame buffer (e.g., a frame buffer that includes pixel data for the entire frame). The GPU 220 may include one or more graphics processors that can execute graphics software to perform some or all of the graphics operations or hardware acceleration of some graphics operations.

[0045] Neural processor circuit 218 is a circuit that performs various machine learning operations based on computations including multiplication, addition, and accumulation. Such computations can be arranged, for example, to perform various types of tensor multiplication, such as tensor products and convolutions of input data and kernel data. Neural processor circuit 218 is a configurable circuit that performs these operations in a fast and efficient manner, while alleviating the resource-intensive operations associated with CPU 208 and neural network operations. Neural processor circuit 218 can receive input data from sensor interface 212, image signal processor 206, permanent memory 228, system memory 230, or other sources such as network interface 210 or GPU 220. The output of neural processor circuit 218 can be provided to various components of device 100, such as image signal processor 206, system memory 230, or CPU 208, for various operations. The structure and operation of neural processor circuit 218 are referenced below. Figure 3 Detailed description.

[0046] Network interface 210 is a sub-component that supports the exchange of data between device 100 and other devices via one or more networks (e.g., carrier or proxy devices). For example, video or other image data may be received from other devices via network interface 210 and stored in system memory 230 for subsequent processing (e.g., via a back-end interface to image signal processor 206) and display. Networks may include, but are not limited to, local area networks (LANs) (e.g., Ethernet or corporate networks) and wide area networks (WANs). Image data received via network interface 210 may be processed by ISP 206.

[0047] Sensor interface 212 is a circuit used to communicate with motion sensor 234. Sensor interface 212 receives sensor information from motion sensor 234 and processes the sensor information to determine the orientation or movement of device 100.

[0048] Display controller 214 is a circuit used to send image data to be displayed on display 216. Display controller 214 receives image data from ISP 206, CPU 208, graphics processor or system memory 230, and processes the image data into a format suitable for display on display 216.

[0049] The memory controller 222 is circuitry for communicating with the system memory 230. The memory controller 222 can read data from the system memory 230 for processing by the ISP 206, CPU 208, GPU 220, or other sub-components of the SOC component 204. The memory controller 222 can also write data to the system memory 230 received from various sub-components of the SOC component 204.

[0050] The video encoder 224 is hardware, software, firmware, or a combination thereof, used to encode video data into a format suitable for storage in permanent memory 128 or to pass data to network interface 210 for transmission over a network to another device.

[0051] In some implementations, one or more sub-components of SOC component 204, or some functions of these sub-components, may be executed by software components that run on neural processor circuitry 218, ISP 206, CPU 208, or GPU 220. Such software components may be stored in system memory 230, permanent memory 228, or in another device that communicates with device 100 via network interface 210.

[0052] Exemplary neural processor circuit The neural processor circuit 218 is a programmable circuit that performs machine learning operations on the input data of the neural processor circuit 218. The machine learning operations may include different computations for training a machine learning model and for performing inference or prediction based on the trained machine learning model.

[0053] Taking a CNN as an example of a machine learning model, CNN training can include forward propagation and backward propagation. A neural network can include an input layer, an output layer, and one or more intermediate layers, which may be called hidden layers. Each layer can include one or more nodes, which may be fully or partially connected to other nodes in adjacent layers. In forward propagation, the neural network performs computations in the forward direction based on the output of the previous layer. The operations of a node can be defined by one or more functions. Functions defining node operations can include various computational operations, such as data convolution using one or more kernels, layer pooling, tensor multiplication, etc. Functions can also include activation functions that adjust the weights of the node's output. Nodes in different layers can be associated with different functions. For example, a CNN may include one or more convolutional layers mixed with pooling layers and followed by one or more fully connected layers.

[0054] Each function (including the kernel) in a machine learning model can be associated with different coefficients that can be adjusted during training. Additionally, individual nodes in a neural network can also be associated with activation functions that determine the weights of the node's output during forward propagation. Common activation functions include step functions, linear functions, sigmoid functions, hyperbolic tangent functions (tanh), and rectified linear unit functions (ReLU). After a batch of training sample data passes through the neural network in forward propagation, the result is compared to the training labels of the training samples to calculate the network's loss function, which represents the network's performance. Furthermore, the neural network performs backpropagation by adjusting the coefficients in the individual functions using coordinate descent techniques such as stochastic coordinate descent (SGD) to improve the value of the loss function.

[0055] During training, device 100 may use neural processor circuitry 218 to perform all or some of the operations in forward and backward propagation. Multiple rounds of forward and backward propagation may be performed by neural processor circuitry 218 alone or in coordination with other processors such as CPU 208, GPU 220, and ISP 206. Training may be completed when the loss function no longer improves (e.g., the machine learning model has converged) or after a predetermined number of rounds for a specific training sample. While using device 100, it may continue to collect additional training samples for the neural network.

[0056] To make predictions or inferences, device 100 may receive one or more input samples. Neural processor circuitry 218 may take the input samples and perform forward propagation to determine one or more results. Input samples may be images, speech, text files, sensor data, or other data.

[0057] In machine learning, data and functions (e.g., input data, kernels, functions, layer outputs, gradient data) can be stored and represented by one or more tensors. Common operations related to the training and runtime of machine learning models can include tensor product, tensor transpose, element-wise tensor operations, convolution, application of activation functions, automatic differentiation to determine gradients of values ​​in tensors, statistics and aggregations (e.g., mean, variance, standard deviation), tensor rank and size manipulation, etc.

[0058] While the training and runtime of neural networks have been discussed as examples, the neural processor circuit 218 can also be used to operate other types of machine learning models, such as kernel SVMs.

[0059] See Figure 3 The exemplary neural processor circuitry 218 may, among other components, include a neural task manager 310, a plurality of neural engines 314A to 314N (collectively referred to below as "a plurality of neural engines 314" and also individually as "neural engine 314"), kernel direct memory access (DMA) 324, data processor circuitry 318, data processor DMA 320, planar engine 340, and neural processor (NP) controller 350. The neural processor circuitry 218 may include... Figure 3 The fewer components shown may include Figure 3 Additional components not shown.

[0060] Each neural engine in neural engine 314 performs machine learning computational operations in parallel. Depending on the workload, the entire group of neural engines 314 may be operating, or only a subset of neural engines 314 may be operating, while the remaining neural engines 314 are placed in a power-saving mode to conserve power. Each neural engine in neural engine 314 includes components for storing one or more kernels, for performing multiplication and accumulation operations, and for post-processing to generate output data 328, as described below. Figure 4 Detailed description. The Neural Engine 314 is specifically designed to perform computationally intensive operations, such as convolution and tensor product operations. Convolution operations can include different types of convolution, such as cross-channel convolution (convolution that sums values ​​from different channels), communication-by-communication convolution, and transposed convolution.

[0061] Planar engine 340 can specialize in performing simpler computational operations, the speed of which may depend primarily on the input and output (I / O) speed of data transfer rather than the computational speed within planar engine 340. These computational operations may be referred to as I / O-constrained computations and are also referred to herein as “non-convolutional operations.” In contrast, neural engine 314 can focus on complex computations, such as convolutional operations, the speed of which may depend primarily on the computational speed within each neural engine 314. For example, planar engine 340 is efficient for performing operations within a single channel, while neural engine 314 is efficient for performing operations across multiple channels that may involve heavy accumulation of data. Computations with I / O constraints using neural engine 314 cannot be efficient in both speed and power consumption. In one implementation, the input data may be a tensor with a rank greater than three (e.g., having three or more dimensions). One set of dimensions (two or more) in the tensor may be referred to as a plane, and another dimension may be referred to as a channel. Neural engine 314 may utilize kernels to convolve the data in the planes of the tensor and accumulate the results of convolutions in different planes across different channels. On the other hand, the planar engine 340 can be dedicated to operations within a plane.

[0062] The circuitry of the planar engine 340 can be programmed to operate in one of several modes, including pooling mode, element-wise mode, and shrinking mode. In pooling mode, the planar engine 340 shrinks the spatial size of the input data. In element-wise mode, the planar engine 340 generates the output derived from element-wise operations on one or more inputs. In shrinking mode, the planar engine 340 shrinks the rank of a tensor. For example, a rank-5 tensor can be shrunk to a rank-2 tensor, or a rank-3 tensor can be shrunk to a rank-0 tensor (e.g., a scalar). See below for reference. Figure 5 The operation of the planar engine 340 will be discussed in further detail.

[0063] The neural task manager 310 manages the overall operation of the neural processor circuitry 218. The neural task manager 310 may receive a list of tasks from a compiler executed by the CPU 208, store tasks in its task queue, select tasks to be executed, and send task commands to other components of the neural processor circuitry 218 for executing the selected tasks. Data may be associated with task commands indicating the type of operation to be performed on the data. The data of the neural processor circuitry 218 includes input data transferred from another source, such as system memory 230, and data generated by the neural processor circuitry 218 in previous operating cycles. Each dataset may be associated with a task command specifying the type of operation to be performed on the data. The neural task manager 310 may also perform task switching upon detecting events such as receiving instructions from the CPU 208. In one or more embodiments, the neural task manager 310 sends raster information to components of the neural processor circuitry 218 to enable each of these components to track, retrieve, or process appropriate portions of the input data and kernel data. For example, the neural task manager 310 may include registers storing information about the size and rank of the datasets for processing by the neural processor circuitry 218. Although in Figure 3 The neural task manager 310 is shown as part of the neural processor circuitry 218, but the neural task manager 310 may be a component external to the neural processor circuitry 218.

[0064] Kernel DMA 324 is a read circuit that retrieves kernel data from a source (e.g., system memory 230) and sends kernel data 326A to 326N to each neural engine in neural engine 314. Kernel data represents information from which kernel elements can be extracted. In one embodiment, the kernel data may be a compressed format that is decompressed at each neural engine in neural engine 314. Although in some cases the kernel data provided to each neural engine in neural engine 314 may be the same, in most cases the kernel data provided to each neural engine in neural engine 314 is different. In one embodiment, the direct memory access nature of kernel DMA 324 allows kernel DMA 324 to directly retrieve and write data from the source without the involvement of CPU 208.

[0065] Data processor circuitry 318 manages the data flow and task performance of neural processor circuitry 218. Data processor circuitry 318 may include data control circuitry 332 and buffer 334. Buffer 334 is a temporary storage device used to store: data associated with the operation of neural processor circuitry 218, such as input data transferred from system memory 230 (e.g., data from a machine learning model); and other data generated within neural processor circuitry 218. Input data can be transferred from system memory 230. The data stored in data processor circuitry 318 may include different subsets, which are sent to various downstream components, such as neural engine 314 and planar engine 340.

[0066] In one embodiment, buffer 334 is implemented as a non-transitory memory accessible to neural engine 314 and planar engine 340. Buffer 334 may store: input data 322A to 322N (also referred to herein as “neural input data”) for feeding to the corresponding neural engines 314A to 314N and input data 342 (also referred to herein as “planar input data”) for feeding to the planar engine 340; and output data 328A to 328N (also referred to herein as “neural output data”) from each neural engine 314A to 314N and output data 344 from the planar engine 340 (also referred to herein as “planar output data”) for feeding back to one or more neural engines 314 or planar engine 340 or to a target circuit (e.g., system memory 230). Buffer 334 may also store input data 342 and output data 344 of the planar engine 340 and allows data exchange between neural engine 314 and planar engine 340. For example, one or more output data 328A to 328N of neural engine 314 can be used as planar input data 342 to planar engine 340. Similarly, planar output data 344 of planar engine 340 can be used as input data 322A to 322N of neural engine 314. The input to neural engine 314 or planar engine 340 can be any data stored in buffer 334. For example, in each operation loop, the source dataset from which one of the engines obtains input can be different. The input to an engine can be the output of the same engine in a previous loop, the output of a different engine, or any other suitable source dataset stored in buffer 334. Furthermore, the dataset in buffer 334 can be partitioned and sent to different engines for different operations in the next operation loop. Two datasets in buffer 334 can also be combined for the next operation.

[0067] The data control circuit 332 of the data processor circuit 318 controls the data exchange between the neural engine 314 and the planar engine 340. The operation of the data processor circuit 318 and other components of the neural processor circuit 218 is coordinated so that input data and intermediate data stored in the data processor circuit 318 can be reused across multiple operations at the neural engine 314 and the planar engine 340, thereby reducing the data transfer to and from the system memory 230. Data control circuitry 332 may perform one or more of the following operations: (i) monitor the size and rank of the data being processed by neural engine 314 and planar engine 340 (e.g., the data may be one or more tensors), (ii) determine which subsets of data are transmitted to neural engine 314 or planar engine 340 based on task commands associated with different subsets of data, (iii) determine the manner in which data is transmitted to neural engine 314 and planar engine 340 (e.g., data processor circuitry 318 may operate in broadcast mode, where the same data is fed to multiple input channels of neural engine 314 such that multiple or all neural engines 314 receive the same data, or may operate in unicast mode, where different neural engines 314 receive different data), and (iv) transmit configuration commands to planar engine 340 to instruct planar engine 340 to program itself for operation in one of multiple operating modes. References below... Figure 9 Describe the details of the data control circuit 332.

[0068] The data stored in the neural processor circuit 218 in the buffer 334 may be a portion of image data, histograms of orientation gradient (HOG) data, audio data, metadata, output data 328 of the previous loop of the neural engine 314, and other processed data received from other components of the SOC component 204.

[0069] The data processor DMA 320 includes read circuitry that receives segments of input data from a source (e.g., system memory 230) for storage in a buffer 334, and write circuitry that forwards the data from the buffer 334 to a target component (e.g., system memory). In one embodiment, the direct memory access nature of the data processor DMA 320 allows the data processor DMA 320 to directly acquire and write data from a source (e.g., system memory 230) without the involvement of the CPU 208. The buffer 334 may be a direct memory access buffer that stores data of the machine learning model of device 100 without the involvement of the CPU 208.

[0070] The neural processor (NP) controller 350 is a control circuit that performs various operations to control the overall operation of the neural processor circuit 218. The NP controller 350 can connect to the CPU 208 and the program unit of the neural processor circuit 218 and perform stewardship operations by setting registers in its components. The NP controller 350 can also initialize the components in the neural processor circuit 218 when the neural processor circuit 218 is turned on.

[0071] Exemplary Neural Engine Architecture Figure 4 This is a block diagram of a neural engine 314 according to one embodiment. The neural engine 314 is a circuit that performs various operations to facilitate machine learning, such as convolution, tensor product, and other operations that may involve large computational loads. To this end, the neural engine 314 receives input data 322, performs a multiplication-accumulation operation (e.g., a convolution operation) on the input data 322 based on stored kernel data, performs further post-processing operations on the result of the multiplication-accumulation operation, and generates output data 328. The input data 322 and / or output data 328 of the neural engine 314 can be a single channel or span multiple channels.

[0072] The neural engine 314 may include, among other components, an input buffer circuit 402, a computational core 416, a neural engine (NE) control 418, a kernel extraction circuit 432, an accumulator 414, and an output circuit 424. The neural engine 314 may include... Figure 4 The fewer components shown may include Figure 4 Other components not shown.

[0073] Input buffer circuit 402 is a circuit that stores a subset of data received from a source when a subset of data for neural processor circuit 218 is received. The source may be data processor circuit 318, planar engine 340, or another suitable component. Input buffer circuit 402 sends an appropriate segment 408 of data for the current task or processing loop to computation core 416 for processing. Input buffer circuit 402 may include a shifter 410 that shifts the read position of input buffer circuit 402 to change the segment 408 of data sent to computation core 416. By changing the segment of input data provided to computation core 416 via shifting, neural engine 314 can perform multiplication and accumulation on different segments of input data based on a smaller number of read operations. In one or more embodiments, the data for neural processor circuit 218 includes differential convolution groups and / or input channel data.

[0074] Kernel extraction circuit 432 is a circuit that receives kernel data 326 from kernel DMA 324 and extracts kernel coefficients 422. In one embodiment, kernel extraction circuit 432 references a lookup table (LUT) and uses a mask to reconstruct the kernel from compressed kernel data 326 based on the LUT. The mask indicates the locations of unfilled zeros and the remaining locations of unfilled numbers in the reconstructed kernel. The kernel coefficients 422 of the reconstructed kernel are sent to compute core 416 to populate registers in the multiply-accumulate (MAD) circuitry of compute core 416. In other embodiments, kernel extraction circuit 432 receives kernel data in uncompressed format and determines the kernel coefficients without referencing a LUT or using a mask.

[0075] The computational core 416 is a programmable circuit that performs computational operations. For this purpose, the computational core 416 may include MAD circuits MAD0 to MADN and a post-processor 428. Each of the MAD circuits MAD0 to MADN may store an input value in a segment 408 of input data and a corresponding kernel coefficient in kernel coefficient 422. In each of the MAD circuits, the input value and the corresponding kernel coefficient are multiplied to generate a processed value 412.

[0076] Accumulator 414 is a memory circuit that receives and stores processed values ​​412 from the MAD circuit. The processed values ​​stored in accumulator 414 can be sent back as feedback information 419 for further multiplication and addition operations at the MAD circuit, or sent to post-processor 428 for post-processing. Accumulator 414, combined with the MAD circuit, forms multiplication accumulator (MAC) 404. In one or more embodiments, accumulator 414 may have sub-units, each of which sends data to a different component of neural engine 314. For example, during a processing cycle, data stored in a first sub-unit of accumulator 414 is sent to the MAC circuit, while data stored in a second sub-unit of accumulator 414 is sent to post-processor 428.

[0077] Postprocessor 428 is circuitry that performs further processing on the value 412 received from accumulator 414. Postprocessor 428 may perform operations including, but not limited to, applying linear functions (e.g., rectified linear unit (ReLU)), normalizing cross-correlation (NCC), combining the results of neural operations on 8-bit data into 16-bit data, and local response normalization (LRN). The result of such operations is output from postprocessor 428 as a processed value 417 to output circuitry 424. In some embodiments, processing at postprocessor 428 is bypassed. For example, data in accumulator 414 may be sent directly to output circuitry 424 for access by other components of neural processor circuitry 218.

[0078] The NE control 418 controls the operation of other components of the neural engine 314 based on the operating mode and parameters of the neural processor circuit 218. Depending on different operating modes (e.g., group convolution mode or non-group convolution mode) or parameters (e.g., the number of input channels and the number of output channels), the neural engine 314 can operate on different input data in different sequences, return different values ​​from the accumulator 414 to the MAC circuit, and perform different types of post-processing operations at the post-processor 428. To configure the components of the neural engine 314 to operate in a desired manner, the NE control 418 sends task commands, which can be included in the information 419, to the components of the neural engine 314. The NE control 418 may include a raster 430 that tracks the current task or processing loop being processed at the neural engine 314.

[0079] Input data is typically divided into smaller data slices for parallel processing across multiple neural engines 314 or between neural engine 314 and planar engine 340. A set of data used for convolution operations may be called a convolution group, which can be divided into multiple smaller units. The hierarchical structure of these smaller units (slices) can be convolution groups, slices, blocks, working units, output channel groups, input channels (Cin), sub-Cin for input strides, etc. For example, a convolution group can be divided into slices; slices can be divided into blocks; blocks can be divided into working units; and so on. In the context of neural engine 314, a working unit can be a slice of input data, such as data processed by planar engine 340 or data processed in a previous loop of neural engine 314, having a size that generates the output value of accumulator 414 suitable for neural engine 314 during a single loop of computation kernel 416. In one case, the size of each working unit is 256 bytes. In such implementations, for example, a working unit may be shaped into one of a 16×16, 32×8, 64×4, 128×2, or 256×1 dataset. In the context of the planar engine 340, a working unit may be (i) a fragment of input data, (ii) data from the neural engine 314, or (iii) data from a previous loop of the planar engine 340, which may be processed simultaneously at the planar engine 340.

[0080] Rasterizer 430 performs operations associated with dividing input data into smaller units (segments) and regulates the processing of these smaller units via MAC 404 and accumulator 414. Rasterizer 430 keeps track of the size and rank (e.g., group, working unit, input channel, output channel) of the input / output data segments and instructs components of neural processor circuitry 218 to correctly process the segments of input data. For example, rasterizer 430 operates shifter 410 in input buffer circuitry 402 to forward the correct segment 408 of input data to MAC 404 and send the completed output data 328 to data buffer 334. Other components of neural processor circuitry 218 (e.g., kernel DMA 324, data processor DMA 320, data buffer 334, planar engine 340) may also have corresponding rasterizers for monitoring the division of input data and the parallel computation of the various segments of input data in different components.

[0081] The output circuit 424 receives the processed value 417 from the post-processor 428 and interacts with the data processor circuit 318 to store the processed value 417 in the data processor circuit 318. For this purpose, the output circuit 424 may issue output data 328 in an order or format different from the order or format in which the processed value 417 is processed in the post-processor 428.

[0082] Components in the Neural Engine 314 can be configured by the NE control 418 and the Neural Task Manager 310 during the configuration cycle. To this end, the Neural Task Manager 310 sends configuration information to the Neural Engine 314 during the configuration cycle. Configurable parameters and modes may include, but are not limited to, the mapping between input data elements and kernel elements, the number of input channels, the number of output channels, the execution of output strides, and enabling / selecting post-processing operations at the post-processor 428.

[0083] Exemplary planar engine architecture Figure 5This is a block diagram of a planar engine 340 according to one embodiment. The planar engine 340 is a separate circuit from the neural engine 314 and can be programmed to perform in different operating modes. For example, the planar engine 340 can operate in pooling mode, shrinking mode, gain-biased mode, and element-wise mode. Pooling mode shrinks the spatial size of the data, shrinking mode shrinks the rank of the tensor, gain-biased mode provides a one-way addition of bias and scaling by a scaling factor, and element-wise mode includes element-wise operations. For this purpose, the planar engine 340 may include, among other components, a first format converter 502, a first filter 506 (also referred to herein as "multimode horizontal filter 506"), a line buffer 510, a second filter 514 (also referred to herein as "multimode vertical filter 514"), a post-processor 518, a second format converter 522, and a planar engine (PE) control 530 (including a rasterizer 540). The planar engine 340 may include fewer components or may include... Figure 5 Other components not shown. Each component in the planar engine 340 may be implemented as a circuit or a circuit combined with firmware or software.

[0084] Input data 342 for the planar engine 340 can be obtained from one or more source datasets stored in the data processor circuitry 318. If the dataset to be processed by the planar engine 340 is larger than the working unit of data that the planar engine 340 can process simultaneously, such a dataset can be segmented into multiple working units for use as input data 342 to be read into the planar engine 340. Depending on the mode of the planar engine 340, the input data 342 may include data from one or more source datasets. The source datasets described herein refer to different data stored in the neural processor circuitry 218 for processing. Different components of the neural processor circuitry 218 can generate or transfer data stored in the data processor circuitry 318. For example, the neural engine 314, the planar engine 340 (which generated data in a previous operating loop), and the system memory 230 can generate or transfer different datasets stored in different memory locations of the data processor circuitry 318. Each source dataset can represent a different tensor. During the operating loop of the planar engine 340, different source datasets can be acquired together as input data 342. For example, in element-wise mode involving the addition of two different tensors to derive the tensor, input data 342 may include data from two different source datasets, each providing a separate tensor. In other modes, a single source dataset may provide input data 342. For example, in pooling mode, input data 342 may be obtained from a single source dataset.

[0085] The first format converter 502 is a circuit that performs one or more format conversions on input data 342 in one format (e.g., a format for use in the buffer 334) to another form for processing in subsequent parts of the planar engine 340. Such format conversions may include, etc., applying a ReLU function to one or more values ​​of input data 342, converting one or more values ​​of input data 342 to their absolute values, transposing a tensor included in the source, applying a gain to one or more values ​​of input data 342, biasing one or more values ​​of input data 342, normalizing or denormalizing one or more values ​​of input data 342, converting floating-point numbers to signed or unsigned numbers (or vice versa), logarithmicizing, and changing the size of a tensor, such as by broadcasting the tensor's values ​​in one or more dimensions to expand the tensor's rank. The converted input data 342 and the unconverted input data 342 to the planar engine 340 are collectively referred to herein as "versions of input data".

[0086] The first filter 506 is a circuit that performs a filtering operation in one direction. For this purpose, the first filter 506 may include an adder, a comparator, and a multiplier, among other components. The filtering performed by the first filter 506 may be, for example, averaging, selecting a maximum value, or selecting a minimum value. When averaging, an adder is used to sum the values ​​of the input data 342, and a weighting factor may be applied using a multiplier to the sum to obtain an average value. When selecting a maximum or minimum value, a comparator may be used instead of an adder and a multiplier to select the value.

[0087] Row buffer 510 is a memory circuit for storing results, such as one or more intermediate data obtained from the first filter 506 or the second filter 514. Row buffer 510 can store values ​​from different rows and allows access from the second filter 514 or other downstream components to obtain intermediate data for further processing. In some modes, row buffer 510 is bypassed. Row buffer 510 may also include logic circuitry for performing additional operations beyond simply storing intermediate data. For example, row buffer 510 includes adder circuitry 512, which, combined with memory components, enables row buffer 510 to act as an accumulator that aggregates data generated from the results of the first filter 506 or the second filter 514 to store aggregated data in a separate, non-reduced dimension.

[0088] Similar to the first filter 506, the second filter 514 performs filtering operations, but in a different direction than the first filter 506. For this purpose, the second filter 514 may include adders, comparators, and multipliers, among other components. In pooling mode, the first filter 506 performs filtering operations in the first dimension, while the second filter 514 performs filtering operations in the second dimension. In other modes, the first filter 506 and the second filter 514 may operate differently. In reduction mode, for example, the first filter 506 performs element-wise operations, while the second filter 514 acts as a reduction tree to aggregate data values.

[0089] Postprocessor 518 is circuitry that performs further processing on values ​​obtained from other upstream components. Postprocessor 518 may include dedicated circuitry that is efficient for performing certain types of mathematical calculations that might be inefficient using general-purpose computing circuitry. The operations performed by postprocessor 518 may include, among others, performing square root operations and reciprocals of values ​​in reduction mode. Postprocessor 518 may be bypassed in other operating modes.

[0090] The second format converter 522 is circuitry that converts the results of previous components in the planar engine 340 from one format to another format for output data 344. Such format conversions may include, for example, applying a ReLU function to the results, transposing the resulting tensor, normalizing or denormalizing one or more values ​​of the results, and other digital format conversions. Output data 344 may be stored in the data processor circuitry 318 as output of the neural processor circuitry 218 or as input to other components of the neural processor circuitry 218 (e.g., the neural engine 314).

[0091] The PE control 530 is a circuit that controls the operation of other components in the planar engine 340 based on the operating modes of the planar engine 340. Depending on the operating mode, the PE control 530 programs registers associated with different components in the planar engine 340, causing the programmed components to operate in a certain way. The pipeline of connections between components or between components in the planar engine 340 can also be reconfigured. In pooling mode, for example, data processed by the first filter 506 can be stored in the row buffer 510 and then read by the second filter 514 for further filtering. However, in shrinking mode, data is processed by the first filter 506, then by the second filter 514, and then accumulated in the row buffer 510, which is programmed as an accumulator. In element-wise mode, the row buffer 510 can be bypassed.

[0092] The PE control 530 also includes a rasterizer 540 that tracks the current task or processing loop being processed at the planar engine 340. The rasterizer 540 is circuitry that tracks units or segments of input data and / or loops used to process input data in the planar engine 340. The rasterizer 540 controls the acquisition of segments to the planar engine 340 in each operating cycle and monitors the size and rank of each segment processed by the planar engine 340. For example, smaller segments of the dataset may be acquired as input data 342 in rasterizer order for processing at the planar engine 340 until all segments of the source dataset have been processed. While acquiring segments, the rasterizer 540 monitors the coordinates of the segments in the dataset. The way the dataset is segmented into input data 342 for processing at the planar engine 340 can be different from how the dataset is segmented into input data 328 for processing at the neural engine 314.

[0093] The dataset to be processed at the planar engine 340 may be larger than the capacity of the planar engine 340, which can process data in a single operation loop. In this case, the planar engine 340 acquires different segments of the dataset as input data 342 in multiple operation loops. The acquired segments may partially overlap with previously acquired segments and / or the next segment to be acquired. In one embodiment, portions of the overlapping data are acquired only once and reused to reduce the time and power consumption costs of the planar engine 340 in acquiring data.

[0094] Exemplary Neural Task Manager and Task List Compilation Figure 6 This diagram illustrates the programming of rasterizers 614, 622, 624 and data control circuitry 332 in components 314, 318, 322, 340 of a neural processor circuitry 218 according to one embodiment. To perform their functions, rasterizers 614, 622, 624 and data control circuitry 332 receive configuration data 610 instructing how input data and / or kernel data are segmented and processed by each component of the neural processor circuitry 218. This task information includes details about the current layer (e.g., the dimensions of the input and output data, the dimensions of the associated kernel, and the type of padding at input data boundaries). Rasterizers 614, 622, 624 and data control circuitry 332 may also receive constraints on their operation (e.g., whether tile widths are allowed or not allowed to exceed a threshold). The configuration data 610 sent to the data control circuit 332 may further include information about data dependencies and data conflicts, enabling the data control circuit 332 to coordinate the reading of input data from the data processor circuit 318 to the neural engine 314 and the planar engine 340, and to coordinate the writing of output data from the neural engine 314 and the planar engine 340 to the data processor circuit 318.

[0095] By providing rasterizers in different components of the neural processor circuit 218, the overhead of data transfer between components of the neural processor circuit 218 can be reduced. If a single central rasterizer were provided to control the different components of the neural processor circuit 218, kernel data, input data, and output data might need to be transferred between these components to identify associated locations in the task loop, such as convolutional groups, tiles, slices, working units, input channels, and output channels. By using distributed rasterizers, separate metadata is not required to transfer kernel data, input data, and output data between components of the neural processor circuit 218.

[0096] The neural network may include network layers or sublayers that are instantiated or implemented as a series of tasks performed by the neural processor circuit 218. Figure 7 This is a schematic block diagram illustrating a neural network 700 represented by a task list 704 according to one embodiment. The neural network 700 includes network layers (or sublayers) including convolutional layers C1, C2, and C3 (including sublayer C3). 00 C3 10 C3 11 C3 20 and C3 21 The neural network 700 consists of C4 and non-convolutional layers (e.g., pooling layers) P1, P2, P3, and P4. The neural network 700 is an example of a neural network architecture that can be instantiated by the neural processor circuit 218. That is, when the neural network 700 is transformed into a task list 704 to become executable by the neural processor circuit 218. Other types of neural network architectures with different types of network layers or network hierarchical order can also be instantiated by the neural processor circuit 218.

[0097] Neural network 700 is transformed into task list 704 through a compiler process, for example, executed by CPU 208. This task list 904 includes a series of tasks, including neural engine tasks TC1 to TC4 (corresponding to convolutional layers C1 to C4) and planar engine tasks P1 to P5 (corresponding to pooling layers P1 to P5). Neural engine task TC3 is further divided into smaller neural engine tasks TC3. 00 To TC3 21 (corresponding to sublayer C3) 00 To C3 21Although listed as a linearly linked task chain, the neural engine tasks and the planar engine tasks do not need to be executed in this sequence. Instead, to increase the efficiency of the neural processor circuit 218, it is desirable to execute the planar engine tasks in parallel with the neural engine tasks, provided that data dependencies and data conflicts are resolved. In one or more implementations, the task sequence between neural engine tasks and the task sequence between planar engine tasks are maintained as determined during the compiler process, but the sequence between planar engine tasks and neural engine tasks can be switched.

[0098] Each task is associated with a task descriptor, which defines the configuration of the neural processor circuitry 218 to perform the task. Each task may correspond to a single network layer of the neural network 900, a portion of the network layers of the neural network 900, or multiple network layers of the neural network 900. The neural processor circuitry 218 instantiates the neural network 900 by executing tasks from the task list 904 under the control of the neural task manager 310.

[0099] Asynchronous execution of neural engine tasks and planar engine tasks Figure 8 This is a timing diagram illustrating the execution of a task in a neural processor circuit 218 according to one embodiment. In this example, the task begins in the sequence TC1, TP1, TC2, TC3, TP2, TP3, TP4, TP5, and TC4. This sequence is not related to... Figure 7 The task sequence in task list 704 is consistent. Because task TC3 is a long neural engine task, and planar engine 340 can perform operations in parallel with neural engine 314, planar engine tasks TP2 to TP4 are executed simultaneously with neural engine task TC3. By processing tasks TP2 to TP4 in parallel with task TC3, the data for task TP5 can be obtained faster than by executing the process in the sequence of task list 704.

[0100] although Figure 8 Adjacent neural engine tasks and adjacent planar engine tasks are illustrated as being separated by a time difference to facilitate interpretation; however, in practice, the execution times of adjacent neural engine tasks and adjacent planar engine tasks can overlap. Neural engine 314 and planar engine 340 can employ a pipelined processing architecture, where they can receive input data for one task while simultaneously producing output data for a previous task. Neural engine 314 and planar engine 340 can operate on data from different tasks simultaneously. For example, neural engine 314 can begin task TC3 before task TC2 is completed, and planar engine 340 can begin task TP3 before task TP2 is completed.

[0101] To address the data dependency issue, data control circuitry 332 controls the timing of sending neural input data and planar input data to neural engine 314 and planar engine 340, respectively. For this purpose, data control circuitry 332 may include, for example... Figure 9 Other components shown include the access enable circuit 910, the raster 920, and the task buffer 930. The data control circuit 332 may include... Figure 9 Other components not shown.

[0102] Task buffer 930 is a memory circuit that stores entries of task information (or configuration information) 942A to 942X. Each entry 942 of the task information corresponds to a neural engine task or a planar engine task. Task information entries for completed tasks can be discarded from task buffer 930 and replaced with new task entries for new tasks. Some task information entries may include data dependency information 950 for pending tasks, indicating that output data is used for one or more tasks by which the neural engine 314 or planar engine 340 performs the pending task. Task information entries may also include data conflict information indicating whether the data source or target of the corresponding task's data conflicts with the data source or target of a previous task.

[0103] Access enable circuit 910 is a programmable circuit that selectively grants access to read data from or write data to buffer 334 of data processor circuit 318. Neural engine 314 and planar engine 340 can be configured such that their circuitry and components do not produce output data until input data is provided. Therefore, access enable circuit 910 can postpone the pending tasks of neural engine 314 or planar engine 340 by preventing neural engine 314 or planar engine 340 from accessing input data in buffer 334 until all dependent data for pending tasks in buffer 334 is available. Access enable circuit 910 can determine the data dependencies of a task by reading and analyzing dependency information 950 contained in task information entries corresponding to the task, and by referring to the state of the task tracked by rasterizer 920 to determine whether all dependent data is available in buffer 334. In this way, access enable circuit 910 can prevent the start of the next task, which depends on the output data of the previous task, until the output data of the previous task is stored in buffer 334 and available in the buffer.

[0104] Access enable circuitry 910 also prevents output data (generated by neural engine 314 and planar engine 340) from being written to buffer 334 or from being read from input data to resolve data conflict issues. For this purpose, access enable circuitry 910 may reference the state of operation indicated by rasterizer 920. Based on the indicated state, access enable circuitry 910 may prevent neural engine 314 or planar engine 340 from writing output data to buffer 334 until another operation or task is completed, or prevent neural engine 314 or planar engine 340 from reading input data from buffer 344 for the current task until at least a portion of the output data from the previous task is stored in buffer 334.

[0105] The rasterizer 920 is a circuit that tracks the current task or process cycle being processed at the data processor circuit 318. The function and operation of the rasterizer 920 are essentially the same as described in the reference above. Figure 4 and Figure 6 The same applies to the rasterizers described in detail. In one or more embodiments, at a given time, rasterizer 920 may track a task different from the task being tracked by other rasterizers (e.g., rasterizer 620 and rasterizer 622).

[0106] Example Task Management Figure 10 This is a block diagram illustrating a neural task manager 310 according to one embodiment. The neural task manager 310 manages tasks executed by neural processor circuitry 218 for one or more neural networks 900. Among other components, the neural task manager 310 may include a task arbitrator 1002, task queues 1004A to 1004N (collectively referred to hereinafter as “multiple task queues 1004” and also individually as “task queue 1004”), a task manager direct memory access (DMA) 1006, a fetch queue 1008, and a configuration queue 1010. The neural task manager 310 may include... Figure 10 Other components not shown.

[0107] Task arbiter 1002 is a circuit or combination of circuitry and firmware that selects tasks from task queue 1004 for execution by neural processor circuitry 218. Task arbiter 1002 dequeues tasks from task queue 1004 and places them in configuration queue 1010. While a task is in the configuration queue, it is submitted for execution, and the neural processor circuitry performs prefetching of input data and kernel data before the task is executed by other components of neural processor circuitry 218. For example, task arbiter 1002 may perform fixed-priority arbitration among multiple task queues 1004 and select a task from the task queue 1004 with the highest priority for retrieving task descriptor 1012 from system memory 230 by task manager DMA 1006.

[0108] The neural task manager 310 may include one or more task queues 1004. Each task queue 1004 is coupled to the CPU 208 and the task arbiter 1002. Each task queue 1004 receives from the CPU 208 an index to a task list 904 of tasks that instantiate the neural network 900 when executed by the neural processor circuitry 218. The indexes stored in each task queue 1004 may include a set of pointers and counters pointing to the task list 904 in the task descriptors 1012 in system memory 230. Each task queue 1004 may also be associated with a priority parameter that defines the relative priority of the task queue 1004. The task descriptor 1012 of the task specifies the configuration of the neural processor circuitry 218 used to execute the task.

[0109] Task Manager DMA 1006 is coupled to Task Arbiter 1002, System Memory 230, and Acquisition Queue 1008. Task Manager DMA 1006 includes read circuitry that receives task descriptors 1012 from a source (e.g., System Memory 230) for storage in Acquisition Queue 1008. For example, Task Arbiter 1002 selects Task Queue 1004 based on its priority and controls Task Manager DMA 1006 to select task descriptors 1012 using a task list 904 indexed by the selected Task Queue 1004.

[0110] The fetch queue 1008 is a single entry queue that stores task descriptors 1012 of pending submissions for execution. The fetch queue 1008 is coupled to the task manager DMA 1006 to receive task descriptors 1012 from system memory 230 and to provide task descriptors 1012 to the configuration queue 1010, or to provide configuration data 1014 extracted from task descriptors 1012 to the configuration queue 1010.

[0111] Configuration queue 1010 holds configuration data 1014 submitted for execution of multiple tasks. While a task is in configuration queue 1010, kernel DMA 324 may retrieve kernel data from system memory 230 to store in kernel fetch circuitry 432 of neural engine 314, and data processor DMA 320 may retrieve input data from system memory 230 to store in data processor circuitry 318. To execute a task, kernel fetch circuitry 432 provides prefetched kernel data to MAC 404 of neural engine 314, and data buffer 318 provides prefetched input data to MAC 404 of neural engine 314. Planar engine 340 also accesses data processor circuitry 318 to read its input data 342. In some embodiments, configuration queue 1010 may include multiple queues holding configuration data 1014 fetched from submitted task descriptors 1012. Figure 13 In more detail, configuration queue 1010 is further coupled to other components of neural processor circuit 218 to configure neural processor circuit 218 according to configuration data 1014.

[0112] Figure 11 This diagram illustrates the retrieval of task descriptor 1012 using task queue 1004 according to one embodiment. Task queue 1004 includes indexes, such as a set of pointers, for task descriptors 1012A to 1012N stored in system memory 230. For this purpose, task queue 1004 may include memory storing header parameters 1102, network identifier (ID) 1104, base address index 1106, tail parameters 1108, count parameters 1110, and priority parameters 1112. Header parameter 1102 is a pointer to the location in system memory 230 where task descriptor 1012A is stored at the head of task queue 1004. Network ID 1104 identifies the neural network 900 of task descriptor 1012 at the head of task queue 1004, and base address index 1106 is an index of base address table 1114 of network ID 1104, which marks task descriptor 1012A, at the head of task queue 1004. The count parameter 1110 limits the number of task descriptors 1012 in task queue 1004. The priority parameter 1112 limits the priority of task queue 1004, and the task arbitrator 1002 uses the priority of the task queue to select among multiple task queues 1004.

[0113] When a specific task queue 1004 is selected (e.g., based on priority parameter 1112), the task arbiter 1002 indexes header parameters 1102, network ID 1104, base address index 1106, and base address table 1114 to retrieve task descriptor 1012 from system memory 230 and places task descriptor 1012 into the fetch queue 1008 to initiate a commitment to execute the task. In each configuration cycle, the task arbiter 1002 may continue to place task descriptor 1012 into the fetch queue 1008 according to the order of tasks defined by the task list 904 of task queue 1004 (e.g., by retrieving the next task descriptor 1012B).

[0114] Figure 12 This is a diagram illustrating a task descriptor 1012 according to one embodiment. A task arbitrator 1002 places the task descriptor 1012 from system memory 230 into an acquisition queue 1008 and then transfers it to a configuration queue 1010. The highest priority (e.g., advanced) task descriptor 1012 in the configuration queue 1010 is used to configure the neural processor circuitry 218 for execution during a configuration cycle. The task descriptor 1012 includes configuration data 1014, which includes a task descriptor header 1202 and address data 1204A to 1204N (hereinafter referred to as "address data 1204"). The task descriptor header 1202 includes configuration data 1014 configuring various operations of the neural task manager 310, including operations related to task selection and task switching. For example, the task descriptor header 1202 may be parsed by the task arbitrator 1002 to extract configuration data 1014 for programming the neural task manager 310 and other components of the neural processing circuitry 218. The task descriptor header 1202 may include a task identifier (ID) 1206 that identifies the task, a neural network identifier (ID) 1208 that identifies the neural network 700 instantiated by the task, a task switch parameter 1210 that limits whether the neural task manager 310 should initiate a task switch (e.g., execute tasks from different task queues 1004) after the task is executed, an input surface parameter 1212 that limits whether input data for the task should be retrieved from system memory 230 or data processor circuitry 318, an output surface parameter 1214 that limits whether output data for the task should be stored in system memory 230 or data processor circuitry 318, various pointers (e.g., base addresses) 1216 that facilitate programming of the neural processor circuitry 218, and one or more debug / exception parameters 1218 that control events, exceptions, or debug logs.

[0115] Each instance of address data 1204A through 1204N (collectively or individually referred to as "address data 1204") defines an address and data payload pair for programming components of neural processor circuitry 218. The data payload may include input data and kernel data for performing a task. For example, each instance of address data 1204 includes register data defining the data payload, a register address defining the destination memory location of neural processing circuitry 218 for receiving the register data, and a register count defining the number of consecutive memory locations (e.g., registers) to which the register data to be written. In some embodiments, the register address is combined with a base address stored in header 1202 to define the full address of each memory location. If task descriptors 1116 are generated at compile time, the actual runtime addresses may be unknown. Using base address table 1114 avoids copying or updating all task descriptors with dynamically allocated addresses.

[0116] In one or more embodiments, address data 1204A is used to program data processor circuitry 318. Address data 1204A includes data dependency information 950, as referenced above. Figure 9 As described, data dependency information 950 is included as part of configuration data 1014C sent to data processor circuitry 318.

[0117] Figure 13This is a block diagram illustrating an acquire queue 1008 and a configuration queue 1010 according to one embodiment. The configuration queue 1010 is coupled to the acquire queue 1008, which is coupled to system memory 230 via a task manager DMA 1006. The configuration queue 1010 is further coupled to a raster 540 of a planar engine 340, a raster 714 of one or more neural engines 314, a data control circuit 332 of a data processor circuit 318, a raster 720 of a data processor DMA 320, and a raster 722 of a kernel DMA 324. The acquire queue 1008 stores task descriptors 1012 (e.g., including a task descriptor header 1202 and address data 1204A to 1204N) for pending tasks that are not submitted for execution. The acquire queue 1008 reduces the latency of reading the next task descriptor 1012 from system memory 230 into the configuration queue 1010. The acquire queue 1008 stores the highest priority task descriptor 1012 determined by the task arbitrator 1002. If a higher-priority task descriptor 1012 has already been enqueued (e.g., enqueued from a higher-priority task queue 1004), the task arbitrator 1002 can replace the task descriptor 1012 stored in the fetch queue 1008. The task descriptor 1012 in the fetch queue 1008 does not initiate input data or kernel prefetching and does not affect task queue priorities, pointers, or counters. Thus, by writing the higher-priority task descriptor 1012 into the fetch queue 1008, the task descriptor 1012 in the fetch queue 1008 can be easily replaced by the higher-priority task descriptor 1012. When the task descriptor 1012 stored in the configuration queue 1010 is executed by the neural processor circuitry 218, the task descriptor 1012 stored in the fetch queue 1008 is transferred to the configuration queue 1010, and another task descriptor 1012 for a subsequent task can be stored in the fetch queue 1008.

[0118] Configuration queue 1010 stores task descriptors 1012 submitted for tasks to be executed by neural processor circuitry 218. In some embodiments, configuration queue 1010 includes multiple separate queues 1310, each storing a portion of configuration data 1014 (including configuration data 1014A to 1014F) extracted from task descriptors 1012. Furthermore, each queue 1310 is coupled to a corresponding component of neural processor circuitry 218 for programming the component with the configuration data 1014. Through the operation of configuration queue 1010, neural task manager 310 programs rasterizers 540, 714, 720, 722 and data control circuitry 332 to perform the tasks described above. Figures 3 to 5The functions discussed herein. For example, queue 1310A is coupled to raster 540 of planar engine 340 to provide configuration data 1014A for controlling operating modes and parameters, while queue 1310B is coupled to raster 714 of neural engine 314 to provide configuration data 1014B, which controls the operation of shifter 410 in input buffer circuit 402 to forward the correct portion 408 of input data to MAC 404 and to send completed output data 328 to data processor circuit 318. Queue 1310C is coupled to data control circuit 332 of data processor circuit 318 to provide configuration data 1014C to fill task buffer 930 and segment buffer 334 to receive output data 344, 328 and send input data 322, 342 for processing by neural engine 314 and planar engine 340. Queue 1310D is a rasterizer 720 coupled to the data processor DMA 320 to provide a read queue for configuration data 1014D, which controls the data processor DMA 320 to retrieve input data (e.g., tiles) from system memory 230 and store the input data in data buffer 318. Queue 1310E is a rasterizer 720 coupled to the data processor DMA 320 to provide a write queue for configuration data 1014E, which controls the data processor DMA 320 to store output data in system memory 230. Queue 1310F is a rasterizer 722 coupled to the kernel DMA 322 to provide configuration data 1014F, which controls which kernels to receive and allocate to the neural engine 314.

[0119] Exemplary process at the neural task manager architecture Figure 14 This is a flowchart illustrating a method for asynchronously processing neural engine tasks and planar engine tasks according to one embodiment. The method may include different and / or additional steps, or these steps may have a different order.

[0120] Data processor circuit 318 controls 1410 to read neural output data as planar input data from planar engine 340, or controls neural engine 314 to read planar output data as neural input data, to prevent data dependency problems associated with neural output data or planar output data. In one or more embodiments, data processor circuit 318 controls the reading of neural output data or planar output data by disallowing planar engine 340 or neural engine 314 to access neural output data or planar output data stored in buffer 334.

[0121] When the data processor circuit 318 allows the neural engine 314 to read neural input data from the buffer 334, the neural engine 314 performs 1420 convolution operations on the neural input data to perform neural engine tasks and other operations. Operations other than convolution (e.g., ReLU) can also be performed by the neural engine. Therefore, neural output data is generated by the neural engine 314.

[0122] Furthermore, while the data processor circuit 318 allows the planar engine 314 to read planar input data from the buffer 334, the planar engine 340 performs 1430 convolution operations on the planar input data to perform planar engine tasks and other operations. Non-convolution operations include pooling of the planar input data, performing element-wise operations on one or more planar inputs, and reducing the spatial size of the planar input data.

[0123] During or after performing a planar engine task or a neural engine task, the data processor circuit 318 controls 1440 to write output data generated by the neural engine 314 and the planar engine 340 into the buffer 334. The data processor circuit 318 can determine whether any data conflict will occur by writing neural output data or planar output data into the buffer 334, and if the write operation does not cause a data conflict, it allows the neural engine 314 and the planar engine 340 to write output data into the buffer.

[0124] While specific implementations and applications have been described and illustrated, it should be understood that the invention is not limited to the precise constructions and components disclosed herein, and that various modifications, alterations, and variations that will be apparent to those skilled in the art may be made to the arrangement, operation, and details of the methods and apparatus disclosed herein without departing from the spirit and scope of this disclosure.

Claims

1. A neural processor circuit, comprising: One or more neural engine circuits, the one or more neural engine circuits being configured to perform convolution operations on neural input data corresponding to one or more neural engine tasks to generate neural output data; One or more planar engine circuits, the one or more planar engine circuits being configured to perform non-convolution operations on planar input data corresponding to one or more planar engine tasks to generate planar output data, the one or more planar engine circuits being configured to perform the non-convolution operations in parallel with the convolution operations performed by the one or more neural engine circuits; and A data processor circuit coupled to the one or more neural engine circuits and the one or more planar engine circuits, the data processor circuit including a buffer circuit and a data control circuit coupled to the buffer circuit, the buffer circuit being configured to store at least one of the neural output data or the planar output data, and the data control circuit being configured to resolve data dependencies between the one or more neural engine tasks and the one or more planar engine tasks by selectively causing the buffer circuit to perform the following operations: In response to the planar output data dependent on the neural engine task being available in the buffer circuit, the one or more neural engine circuits allow access to the planar output data in the buffer circuit to read the planar output data as the neural input data corresponding to the neural engine task; or In response to the availability of neural output data dependent on the planar engine task in the buffer circuit, the one or more planar engine circuits allow access to the neural output data in the buffer circuit to read the neural output data as the planar input data corresponding to the planar engine task.

2. The neural processor circuit of claim 1, wherein (i) two or more neural engine tasks in the neural engine task are executed in parallel with one of the planar engine tasks, or (ii) two or more planar engine tasks in the planar engine task are executed in parallel with one of the neural engine tasks.

3. The neural processor circuit of claim 1, wherein the data processor circuit further includes a task buffer coupled to the data control circuit, the task buffer being configured to store entries of configuration data corresponding to a subset of the neural engine tasks and the planar engine tasks, the configuration data indicating: The configuration of the data control circuitry for the corresponding neural engine task or the corresponding planar engine task, and Data dependencies between the subset of the neural engine task and the planar engine task.

4. The neural processor circuit according to claim 3, further comprising a task manager circuit, wherein the task manager circuit is configured to: The system receives multiple task descriptors, each task descriptor defining the configuration of the neural processor circuitry to execute a corresponding neural engine task or a corresponding planar engine task. Extract the configuration data corresponding to the task descriptor, and The extracted configuration data is sent to the data processor circuit for processing and storage.

5. The neural processor circuit according to claim 4, wherein the task descriptor is generated through a compilation process.

6. The neural processor circuit of claim 3, wherein the data processor circuit is further configured to: The first portion of the configuration data for the completed neural engine task or the completed planar engine task is discarded from the task buffer, and In response to discarding the first portion of the configuration data, a second portion of the configuration data is stored for a new neural engine task or a new planar engine task.

7. The neural processor circuit of claim 1, wherein the data processor circuit is further configured to resolve data conflicts between the one or more neural engine tasks and the one or more planar engine tasks by controlling the writing of the neural output data or the planar output data into the data processor circuit.

8. The neural processor circuit of claim 1, wherein the non-convolution operation includes at least one of an operation to reduce the spatial size of the planar input data or an element-wise operation on the planar input data.

9. The neural processor circuit of claim 1, wherein the data processor circuit causes: The one or more neural engine circuits execute the one or more neural engine tasks in a first sequence as determined by a compilation process for neural networks, and The one or more planar engine circuits execute the one or more planar engine tasks in a second sequence as determined by the compilation process.

10. A method for performing neural processing operations, the method comprising: At least one of neural output data or planar output data is stored in the buffer circuit of the data processor circuit; The data control circuitry is configured to resolve data dependencies between one or more neural engine tasks and one or more planar engine tasks by selectively causing the buffer circuitry to perform the following operations: In response to the planar output data dependent on the neural engine task being available in the buffer circuit, the one or more neural engine circuits allow access to the planar output data in the buffer circuit to read the planar output data as neural input data corresponding to the neural engine task. or In response to the availability of the neural output data dependent on the planar engine task in the buffer circuit, the one or more planar engine circuits allow access to the neural output data in the buffer circuit to read the neural output data as planar input data corresponding to the planar engine task. The data control circuit is included in the data processor circuit and coupled to the buffer circuit; The neural output data is generated by performing a convolution operation on the neural input data corresponding to the one or more neural engine tasks by the one or more neural engine circuits. as well as The planar output data is generated by the one or more planar engine circuits performing non-convolution operations in parallel with the convolution operations on the planar input data corresponding to the one or more planar engine tasks.

11. The method of claim 10, wherein (i) two or more neural engine tasks in the neural engine task are executed in parallel with one of the planar engine tasks, or (ii) two or more planar engine tasks in the planar engine task are executed in parallel with one of the neural engine tasks.

12. The method of claim 10, further comprising storing in a task buffer of the data processor circuit entries an entry for configuration data corresponding to a subset of the neural engine task and the planar engine task, the configuration data indicating: The configuration of the data control circuitry for the corresponding neural engine task or the corresponding planar engine task, and Data dependencies between the subset of the neural engine task and the planar engine task.

13. The method of claim 12, further comprising: Multiple task descriptors are received via a task manager circuit. Each task descriptor defines the configuration of the neural processor circuitry to execute a corresponding neural engine task or a corresponding planar engine task. The configuration data corresponding to the task descriptor is extracted through the task manager circuit, and The extracted configuration data is sent from the task manager circuit to the data processor circuit for processing and storage.

14. The method of claim 12, further comprising: The first portion of the configuration data for the completed neural engine task or the completed planar engine task is discarded from the task buffer, and In response to discarding the first portion of the configuration data, a second portion of the configuration data is stored for a new neural engine task or a new planar engine task.

15. The method of claim 10, further comprising controlling the neural output data to be written into the data processor circuit by the one or more neural engine circuits or the planar output data to be written into the data processor circuit by the one or more planar engine circuits.

16. The method of claim 10, wherein the non-convolution operation includes at least one of an operation to reduce the spatial size of the planar input data or an element-wise operation on the planar input data.

17. The method of claim 10, wherein the one or more neural engine tasks are performed in a first sequence as determined by a compilation process for a neural network, and the one or more planar engine tasks are performed in a second sequence as determined by the compilation process.

18. An electronic device comprising: One or more neural engine circuits, the one or more neural engine circuits being configured to perform convolution operations on neural input data corresponding to one or more neural engine tasks to generate neural output data; One or more planar engine circuits, the one or more planar engine circuits being configured to perform non-convolutional operations on planar input data corresponding to one or more planar engine tasks to generate planar output data, the one or more planar engine circuits being configured to perform the non-convolutional operations in parallel with the convolutional operations performed by the one or more neural engines; and A data processor circuit coupled to the one or more neural engine circuits and the one or more planar engine circuits, the data processor circuit including a buffer circuit and a data control circuit coupled to the buffer circuit, the buffer circuit being configured to store at least one of the neural output data or the planar output data, and the data control circuit being configured to resolve data dependencies between the one or more neural engine tasks and the one or more planar engine tasks by selectively causing the buffer circuit to perform the following operations: In response to the planar output data depending on the neural engine task being available in the buffer circuit, the one or more neural engines are allowed to access the planar output data in the buffer circuit to read the planar output data as the neural input data corresponding to the neural engine task; or In response to the availability of neural output data dependent on the planar engine task in the buffer circuit, the one or more planar engines allow access to the neural output data in the buffer circuit to read the neural output data as the planar input data corresponding to the planar engine task.

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