Linear transimpedance amplifier dual regulator architecture and tuning

Abstract

A system includes: a transimpedance amplifier disposed on a chip, having a front-end section and a back-end section; an on-chip linear regulator located on the chip and arranged to power the front-end section; and an off-chip switching regulator located off-chip and arranged to power the back-end section. This arrangement provides a low-noise power supply to the front-end section while providing a more energy-efficient switching regulator to power the back-end section. The output voltage of the on-chip linear regulator and the output voltage of the off-chip switching regulator are controlled to be the same.

Description

Technical Field

[0001] This disclosure relates to a method of supplying power to an integrated circuit (e.g., a transimpedance amplifier). Background Technology

[0002] Optical links are replacing electrical interconnects in data center infrastructure. Optical links support much higher data rates compared to electrical links. They also consume only a fraction of the power of traditional electrical links. The latest push is to transmit at least 100 Gbps over a single wavelength of light. At such rates, the bandwidth of popular binary NRZ (non-return-to-zero) signaling schemes is too large to be supported by electro-optical and opto-optical interfaces. Advanced modulation techniques help reduce bandwidth. One such technique is pulse amplitude modulation (PAM-4) with four levels. Two bits are encoded in one of the four levels. As a result, the symbol rate (baud rate) is half that of NRZ signaling, and the bandwidth requirement is reduced. However, one aspect of this approach is that the signal processing circuitry must be linear. This is a challenge in low-voltage complementary metal-oxide-semiconductor (CMOS) processes. Fine-linewidth CMOS processes provide very high-speed transistors, but the operating voltage is typically 1V or lower. To maintain clearly distinguishable and equally spaced four levels, the signal processing circuitry should exhibit high linearity and low noise.

[0003] Transimpedance amplifiers (TIAs) are components used to convert optical signals into electrical signals. High-bandwidth linear TIAs are typically implemented using indium phosphide (InP) or silicon germanium (SiGe) BiCMOS (double complementary metal-oxide-semiconductor) technology, where bipolar transistors provide high speed, low noise, and maintain high voltage. However, the signal processing and logic requirements of monolithic transceiver integrated circuits (ICs) are best met using CMOS technology. Due to limited supply voltage, linear TIAs designed using fine-line CMOS processes may face major technical challenges in signal compression. Furthermore, in high-speed optical links, TIAs can significantly contribute to overall chip power consumption. Attached Figure Description

[0004] Figure 1 This is a block diagram depicting an optical transceiver including a transimpedance amplifier powered by an on-chip linear regulator and an off-chip switching regulator, according to an example embodiment.

[0005] Figure 2 This is a high-level block diagram of a transimpedance amplifier, including the boundary between a front-end portion and a back-end portion, according to an example embodiment.

[0006] Figure 3 This is a schematic diagram of a transimpedance amplifier including the boundary between a front-end portion and a back-end portion according to an example embodiment.

[0007] Figure 4This is a schematic diagram illustrating the implementation of an on-chip linear regulator for implementing dynamic voltage scaling for the front end of a transimpedance amplifier, and an off-chip switching regulator for powering the back end of the transimpedance amplifier, according to an example embodiment.

[0008] Figure 5 This is a high-level block diagram illustrating, according to an example embodiment, that the front-end and rear-end portions of a transimpedance amplifier are powered by an on-chip linear regulator and an off-chip switching regulator, respectively.

[0009] Figure 6 This is a high-level block diagram depicting a voltage measurement and feedback block for controlling the voltage of an off-chip regulator, according to an example embodiment.

[0010] Figure 7 This is a high-level block diagram illustrating the use of a corresponding process and temperature monitor, according to an example embodiment, to provide control feedback to an on-chip linear regulator and an off-chip switching regulator.

[0011] Figure 8 This is a high-level block diagram illustrating the use of a single process and temperature monitor, according to an example embodiment, to provide control feedback to on-chip linear regulators and off-chip switching regulators.

[0012] Figure 9 This is a flowchart depicting a series of operations for operating a transimpedance amplifier system according to an example embodiment. Detailed Implementation

[0013] Overview

[0014] In one embodiment, a system includes: a transimpedance amplifier disposed on a chip, having a front-end portion and a back-end portion; an on-chip linear regulator located on the chip and arranged to power the front-end portion; and an off-chip switching regulator located off-chip and arranged to power the back-end portion. This arrangement provides a low-noise power supply to the front-end portion while providing a more energy-efficient switching regulator to power the back-end portion. The output voltage of the on-chip linear regulator and the output voltage of the off-chip switching regulator are controlled to be the same.

[0015] In another embodiment, a method is provided. The method includes: receiving power from an on-chip linear regulator at a front end of an on-chip transimpedance amplifier; receiving power from an off-chip switching regulator at a rear end of the transimpedance amplifier; monitoring the output voltage of the on-chip linear regulator and the output voltage of the off-chip switching regulator; and making the output voltage of the off-chip switching regulator the same as the output voltage of the on-chip linear regulator.

[0016] Example Implementation

[0017] Building high-speed linear transimpedance amplifiers (TIAs) using low-voltage CMOS processes presents several challenges. One consideration is the low signal swing resulting from the low supply voltages available. As the signal swing increases, distortion increases rapidly. Negative feedback cannot be used to improve linearity because the loop gain is very low at the frequencies of interest (~30 GHz). Adding to this challenge is the wide dynamic range of the input. At low input levels, the signal-to-noise ratio (SNR) is limited by the noise generated by the TIA. Even after achieving low input reference noise, the TIA output should be large enough to overcome the quantization noise of subsequent A / D converters in the chain. Large swings in low-voltage techniques using conventional methods would be highly nonlinear. The nonlinearity worsens as the input signal becomes larger. Therefore, low-noise, wide dynamic range, high gain bandwidth, and linear TIAs are highly desirable. TIAs optimized for power consumption are also very valuable.

[0018] Figure 1 This is a block diagram depicting an optical transceiver including a transimpedance amplifier powered by an on-chip linear regulator and an off-chip switching regulator, according to an example embodiment. The optical transceiver is merely one example using a linear TIA according to embodiments presented herein. The optical transceiver 100 includes an optical integrated circuit (IC) 102 coupled to one or more optical fibers (lines). Figure 1 The illustrated optical path includes an output line 104-1 configured to forward optical signals from optical IC 102 and an input line 104-2 configured to forward optical signals to optical IC 102. Optical IC 102 includes an electro-optic modulator 106 and a photodiode 108. In one embodiment, the electro-optic modulator 106 may be a Mach-Zehnder modulator that outputs, for example, a 53.125 GBd PAM-4 optical signal. The photodiode 108 is configured to convert the PAM-4 optical signal into a current signal.

[0019] The optical transceiver 100 also includes an electrical IC 110 coupled to the optical IC 102. At the transmitting end, the electrical IC 110 includes a host serializer / deserializer (SERDES) 116 configured to receive NRZ signals from a host 120. The output of the SERDES is provided to a PAM encoder 114. The output of the PAM encoder 114 is provided to an electro-optic interferometer driver 112 configured to drive an electro-optic modulator 106. In one example, the electro-optic interferometer driver 112 may be a Mach-Zehnder interferometer (MZI) driver. At the receiving end, the electrical IC 110 includes a TIA 122, a clock and data recovery (CDR) circuit 124, and a PAM decoder 126. The TIA 122 is a linear TIA configured to convert the current signal received from the photodiode 108 into a voltage signal and amplify the voltage signal. In one embodiment, the TIA 122, manufactured using a CMOS process, can increase THD (Total Harmonic Distortion) by less than 5% to generate four equally spaced levels in a PAM-4 100Gbps / λ link. As will be explained further below, the TIA 122 is powered by two different voltage regulators: an on-chip linear regulator 180 and an off-chip switching regulator 190.

[0020] In one embodiment, the optical transceiver 100 is a transceiver system-in-package (SiP) that includes an electrical IC 110 having a monolithically integrated TIA flip-chip mounted on the optical IC 102.

[0021] Figure 2 This is a high-level block diagram of a transimpedance amplifier 122, including a boundary between a front-end portion and a back-end portion, according to an example embodiment. As shown, the TIA 122 includes a transimpedance front-end 202, a single-to-differential converter 204, a programmable gain amplifier (PGA) portion 206, and an output buffer portion 208. The transimpedance front-end 202 of the TIA 122 may be a current-to-voltage (I / V) converter. The front-end 202 is configured to receive a photodiode 108 ( Figure 1 The current output of the photodiode is converted into a voltage signal. Because the photodiode current is inherently single-ended, the output of the transimpedance front end 202 is also single-ended. Therefore, in some embodiments, the single-to-differential converter 204 is used to receive the voltage signal VAM from the transimpedance front end 202 and generate a complementary signal VAP. The PGA section 206 is configured to receive and amplify the complementary voltage signals VAM and VAP. The output buffer section 208 is configured to be coupled to the PGA section 206 to receive the amplified voltage signals and provide output for the voltage signals VOP and VOM to the CDR 124 ( Figure 1 The desired impedance of the analog-to-digital converter (ADC) in ).

[0022] In some embodiments, the TIA 122 may further include a first (DC) feedback circuit 210 and a second (DC) feedback circuit 212. The first feedback circuit 210 is coupled between the current source 214 of the TIA 122 and the output of the single-to-differential converter 204. The first feedback circuit 210 is configured to subtract the average value of the photodiode current received from the photodiode 108. The second feedback circuit 212 is coupled between the output of the output buffer section 208 and the first stage of the PGA section 206. The second feedback circuit 212 is configured to minimize random mismatch effects and prevent gain stage saturation in the TIA 122.

[0023] like Figure 2 As further illustrated, the TIA 122 can be viewed as having a front-end section 240 and a back-end section 250, separated by a dashed dividing line 245. The front-end section 240 includes, for example, a transimpedance front-end 202, a single-to-differential converter 204, and a first feedback circuit 210. The back-end section 250 includes, for example, a PGA section 206, an output buffer section 208, and a second feedback circuit 212. By using different regulator types to power the front-end section 240 and the back-end section 250, significant power can be saved in the back-end section 250 while still retaining the benefits of low power supply noise in the front-end section 240. In one embodiment, the front-end section 240 is powered by an on-chip linear regulator 180, while the back-end section 250 is powered by an off-chip switching regulator 190. As used herein, "on-chip" means on the same silicon die as, for example, the transimpedance front-end 202 and the single-to-differential converter 204, and "off-chip" means not on the same die as, for example, the transimpedance front-end 202 and the single-to-differential converter 204; that is, "off-chip" refers to a different silicon die.

[0024] Figure 3 This is a schematic diagram of TIA122, including a boundary line 245 between a front-end portion 240 and a rear-end portion 250, according to an example embodiment. In one embodiment, the transimpedance front-end 202 includes a parallel feedback inverter 304. The parallel feedback inverter 304 powers a photodetector (e.g., Figure 1 The current output I of the photodiode 108 in the middle in The signal is converted to voltage. The resistive component in the feedback loop of the transimpedance front-end 202 can be a MOS device 306 operating in the transistor region (ohmic mode) to reduce parasitics and achieve higher bandwidth compared to programmable polysilicon resistors. The MOS device 306 also saves valuable real-world space on the chip. The output of the transimpedance front-end 202 is a voltage signal VAM, which is a single-ended voltage signal. Since the analog-to-digital converter (ADC) uses differential (or balanced) inputs, the single-ended signal can be converted to differential or balanced form.

[0025] A single-ended voltage signal VAM is fed to a single-to-differential converter 204. The single-to-differential converter 204 is a complementary signal generator configured to generate a complementary signal VAP from the voltage signal VAM. In terms of linearity, single-to-differential converters are perhaps the most challenging blocks to work with. Existing single-to-differential converters typically use differential pairs, where the output of the I / V converter is applied to one of the inputs of the differential pair, while the other input is connected to AC ground (a suitable DC voltage). Such circuits only produce balanced differential outputs if the tail current source is ideal (infinite impedance) and the input is small enough that the differential pair cannot completely channel the tail current to one side or the other. For the practical range of signals from the I / V converter, the differential output can be highly nonlinear. Source degradation techniques will not work properly when the inputs of the differential pair are single-ended. Furthermore, tail current sources are far from ideal. Techniques such as simple cascading or gain-enhancing cascading are only effective at low frequencies. Therefore, the current source has a relatively low impedance, especially at high frequencies. This causes the current value to vary depending on the input signal. The effect of having a bias current that depends on the signal is that the output is non-linear.

[0026] To solve these problems, such as Figure 3 As shown, in one form, the single-to-differential converter 204 includes a first inverter INV1 series-coupled to a second inverter INV2, the second inverter INV2 having a short-circuit connection from its output to its input. The first inverter INV1 acts as a driver for the load of the short-circuited second inverter INV2 to generate a complementary signal VAP. The first inverter INV1 has an input coupled to a transimpedance front end 202 and an output coupled to the input of the second inverter INV2. The second inverter INV2 has an output coupled to a PGA section 206. The amplitude of the complementary signal VAP is determined by the ratio of the size of the driver (INV1) inverter to the size of the load (INV2) inverter, and can therefore be very tightly controlled. In one embodiment, the sizes of the first inverter INV1 and the second inverter INV2 can be similar or the same. In another embodiment, the size of the load inverter INV2 is smaller than the size of the driver inverter INV1 to achieve unity gain. The single-to-differential converter 204 is configured to generate a 180-degree out-of-phase signal VAP from the input signal VAM. Any additional phase shift from the complementary paths is very small because the pole frequencies are close to the device's propagation frequency (f). TBecause the gain of the single-to-differential converter 204 is primarily affected by the ratio of the transconductance of the drive inverter INV1 to the transconductance of the load inverter INV2, the gain is independent of process and temperature variations. This single-ended to differential arrangement is accurate because the amplitude and phase of the signal have no resistor dependence, since the single-to-differential converter 204 does not include resistors. However, other forms of the single-to-differential converter 204 can be employed, such as a transadmittance-transresistance (TAS-TIS) circuit that includes resistor components.

[0027] PGA section 206 includes a first signal path 312 and a second signal path 314 that receive complementary voltage signals VAM and VAP, respectively. Each of the first signal path 312 and the second signal path 314 has multiple inverters connected in series without resistors between them. The first signal path 312 is directly coupled after the transimpedance front end 202, while the second signal path 314 is directly coupled after the single-to-differential converter 204. For example, each of the first signal path 312 and the second signal path 314 may include three cascaded coarse (e.g., 0 or 5 dB) programmable gain stages (PGA-C) and fine gain stages (PGA-F) with, for example, a 0.5 dB step. However, the number of connected PGAs is not limited to this, and other numbers of PGA-Cs and PGA-Fs may be used.

[0028] Still referencing Figure 3 The first signal path 312 and the second signal path 314 are cross-coupled to each other through multiple inverters 332. These inverters 332 between the complementary signal paths 312 and 314 minimize any amplitude and phase mismatch applied to the inputs of the complementary signal paths 312 and 314.

[0029] Output buffer section 208 is coupled after PGA section 206. Specifically, first signal path 312 and second signal path 314 are coupled to output buffers 334-1 and 334-2, respectively. In some embodiments, the output buffer topology can be used as a voltage-mode driver, providing a controlled output impedance such as 50Ω, and providing good bandwidth and linearity in the serial transceiver block (SERDES). The function of output buffers 334-1 and 334-2 is to provide a large linear output swing and a well-controlled output impedance.

[0030] like Figure 3As shown, the entire signal path from the transimpedance front end 202 to the output buffer section 208 consists of DC-coupled inverters operating in the linear region. Using multiple unit-sized inverters can eliminate system skew. In some embodiments, each section from the I / V converter to the output buffer section 208 is constructed using basic CMOS inverters. Any number of basic CMOS inverters can be used in each section, such that only the number of inverters can vary within each section. For example, in the single-to-differential converter 204, the driver INV1 can have nine units of basic inverters connected in parallel, and the load INV2 can have eight units connected in parallel.

[0031] In some embodiments, TIA 122 further includes a first feedback circuit (DCFB1) 210 coupled between current source 342 and the output of second inverter INV2 of single-to-differential converter 204. The first feedback circuit 210 includes a first resistor 344, a first inverter 346, a first short-circuit inverter 348, a second resistor 350, and a final-stage inverter 352 with capacitive feedback, all connected in series. The first feedback circuit 210 is configured to subtract the average value of the photodiode current at the input. TIA 122 also includes two second feedback circuits (DCFB2) 212(1) and 212(2), one on each of the first signal path 312 and the second signal path 314. Each of the second feedback circuits 212(1) and 212(2) is coupled between the output of output buffer 334-1 or 334-2 and the first stage of PGA section 206 (i.e., the first coarse PGA (PGA-C) in the signal path). The components of the second feedback circuits 212(1) and 212(2) are similar to those of the first feedback circuit 210, and therefore will not be described again. The second feedback circuits 212(1) and 212(2) are configured to minimize random mismatch effects and prevent gain stage saturation. The DC feedback loop also uses a unit-size inverter and provides a high-pass angle frequency of less than 100kHz for the signal. Automatic gain control (AGC) provided to the TIA122 is via firmware through monitoring clock and data recovery (CDR) block 124 (…). Figure 1 This is achieved through the output of the A / D converter (ADC) in the ().

[0032] Those skilled in the art will understand that Figure 3 Several components described herein and represented as part of front-end section 240 are powered by on-chip linear regulator 180, and Figure 3 Several components described herein and represented as part of back-end section 250 may be powered by off-chip switch regulator 190.

[0033] Figure 4This is a schematic diagram depicting an implementation of an on-chip linear regulator 180 for providing power supply noise suppression and implementing dynamic voltage scaling for the front-end portion 240 of a transimpedance amplifier 122, and an off-chip switching regulator 190 for powering the rear-end portion 250 of the transimpedance amplifier 122, according to an example embodiment. As shown, circuit 400 includes a TIA 122, an on-chip linear regulator 180 (programmable), a process and temperature monitor 404, and a frequency comparator 406. The on-chip linear regulator 180 is configured to provide appropriate power to the front-end portion 240 of the TIA 122 and to the process and temperature monitor 404. The on-chip linear regulator 180 includes a programmable reference 410, an operational amplifier 412, a replicated load 414, two transistors 416 and 418, and a capacitor 419 to regulate the output voltage VREG to between 0.75V and 1.25V. Programmable reference 410 outputs a control signal to operational amplifier 412 based on process and temperature data received from frequency comparator 406. Operational amplifier 412 compares the control signal from programmable reference 410 with a signal from replica load 414 and outputs adjustment signals to transistors 416 and 418 to adjust the voltage supplied to the front end portion 240 of TIA 122. Capacitor 419 is disposed between the adjustment output and ground, further improving immunity to substrate noise.

[0034] The regulated voltage adapts to process and temperature variations, thereby tightly controlling the bandwidth and peak value of the TIA 122. An on-chip linear regulator 180 uses process and temperature data to regulate the voltage. The process and temperature data represent process and temperature variations affecting the TIA 122. A process and temperature monitor 404 is configured to monitor these variations. The process and temperature monitor 404 includes a ring oscillator (RO) 420 and two transistors, MPT and MNT, to protect the RO 420 from overvoltage.

[0035] For example, the regulated voltage range is 0.75 to 1.25V across process, voltage, and temperature (PVT) variations. In this example, the voltage between any two terminals of the transistor must not exceed 0.9V. RO 420 is made from an inverter of the same unit size as the inverter in TIA 122 and serves as a PVT variation sensor. RO 420 serves as a process and temperature sensor and has a delay stage constructed from multiple (e.g., 2) unit inverters. Therefore, there is a high correlation between the components in TIA 122 and RO 420. Thus, the regulated supply voltage can be precisely tuned to a range of millivolts to obtain optimal gain and bandwidth across all process and temperature ranges. Although the voltage swing in TIA 122 is much lower than rail-to-rail, the swing of the ring oscillator is rail-to-rail. Therefore, MOS devices, MPT, and MNT in the transistor region are added to prevent overvoltage. The frequency 422 of RO 420, affected by process and temperature variations, is compared with an external reference clock 424 at frequency comparator 406. Therefore, the digital output of frequency comparator 406 represents the process angle and temperature of the TIA 122. The on-chip linear regulator 180 is programmed via a firmware feedback loop to achieve the target RO frequency. An example control algorithm for regulating the voltage output to the TIA 122 is shown below:

[0036] • VTT = 0.91V during reset;

[0037] • The target output of the frequency comparator is 1F1(h) (programmable);

[0038] • The regulator input increases / decreases by 1 LSB (8 mV) based on the output of the frequency comparator;

[0039] • Repeat the above steps until the output is within the target count (1F1±3) of the desired value (software programmable);

[0040] • The resolution / range of the comparator can be programmed (the required counter value is appropriately scaled from 1F1).

[0041] The regulated supply voltage VREG is automatically adjusted for different process corners and temperatures to maximize bandwidth and minimize any in-band peaks for the TIA 122. In one embodiment, all transistors in the inverter stage are biased in the saturation region, and circuit 400 adjusts their bias points to compensate for variations in mobility and threshold voltage. Therefore, using circuit 400, the transconductance of all devices in the TIA 122 is tightly controlled across process, voltage, and temperature (PVT) variations. Similarly, front-end section 240 ( Figure 3 The output conductance of the transistor device in the feedback path is also closely tied to similar schemes.

[0042] Since TIA performance cannot be fully determined at the wafer stage, the absence of process and temperature tuning can significantly reduce module yield. The cost of discarding assembled modules due to any performance defects is extremely high. Tuning schemes can also be used to fine-tune the quality of the received data eyes. Based on the techniques disclosed above, TIA parameter yields are expected to be very high because process and temperature variations are automatically compensated for to keep critical performance parameters within very tight ranges.

[0043] As mentioned above, the TIA 122 consumes a significant amount of power. For example, a single TIA 122 on a die driven by a 1.8V supply may draw approximately 40mA of current, thus consuming 72mW. Moreover, a single die may carry eight TIAs, resulting in a total power consumption of approximately 576mW. Power savings can be achieved by using an on-chip linear regulator 180 to power the front-end section 240 of the TIA 122 and using a more efficient off-chip switching regulator 190 to power the back-end section 250 of the TIA 122.

[0044] The off-chip switching regulator 190 can be configured according to any known circuit topology. Switching regulators are inherently more power-efficient than linear regulators. However, they are noisier than linear regulators. Since the back-end section 250 of the TIA 122 is fully differential, any power supply noise will appear as a common-mode signal and will not affect the differential output of the TIA 122.

[0045] Figure 5 This is a high-level block diagram illustrating that the front-end portion 240 and the back-end portion 250 of a TIA 122 according to an example embodiment are powered by an on-chip linear regulator 180 and an off-chip switching regulator 190, respectively. In one embodiment, the TIA 122 and the on-chip linear regulator 180 are disposed on the same chip 510 (i.e., die), and the chip 510 and the off-chip switching regulator 190 (e.g., a separate IC) may be located on the same circuit board 520.

[0046] In one example implementation, the front-end section 240 draws 15mA from a 1.8V supply, consuming 27mW. The back-end section 250 may draw 25mA from an off-chip switching regulator 190 (regulated to 1V), assuming a regulator efficiency of 90%, for a total of 28mW. For eight TIAs on a single die, the total power consumption is 440mW. If the entire TIA is powered by a linear regulator, the power consumption would be (15mA + 25mA) * 1.8 * 8 = 576mW. Therefore, the dual-regulator scheme would save 176mW, or nearly 24% of the power. However, to ensure proper performance of the TIA 122, regulators 180 and 190 should be properly tuned or synchronized to avoid unintended distortion, bias, or even saturation, especially in the context of PAM-4 technology.

[0047] Figure 6 This is a high-level block diagram depicting a voltage measurement and feedback block 610 for setting the voltage of an off-chip switching regulator 190 according to an example embodiment. As shown in the figure, Figure 6 Similar to Figure 5 It also includes an on-chip process and temperature monitor 404, a frequency comparator 406, an external reference clock 424, and a voltage measurement and feedback block 610. As previously described, the process and temperature monitor 404 is configured to monitor process and temperature changes and provide feedback to control the output voltage of the on-chip linear regulator 180 sensed by the process and temperature monitor 404. The voltage measurement and feedback block 610 also monitors the output of the on-chip linear regulator 180 and further monitors the output voltage of the off-chip switching regulator 190, then forces the output of the off-chip switching regulator 190 to be the same as the output voltage of the on-chip linear regulator 180. In this way, the outputs of the two power supplies are tuned or synchronized together, thereby avoiding power supply mismatch between the front-end section 240 and the back-end section 250.

[0048] Figure 7 This is a high-level block diagram illustrating corresponding process and temperature monitors 404(1) and 404(2) used to provide control feedback to the on-chip linear regulator 180 and the off-chip switching regulator 190, respectively, according to an example embodiment. As shown, the first process and temperature monitor 404(1) is used to monitor the output of the on-chip linear regulator 180, and the second process and temperature monitor 404(2) is used to monitor the output of the off-chip switching regulator. The outputs of the process and temperature monitors 404(1) and 404(2) are fed back to the frequency comparator 406 via a multiplexer or switch 710. Switch 710 selects one of the outputs at a time to compare with an external reference clock 424. The output of the frequency comparator 406 is then transmitted via a demultiplexer or switch 712 to provide control signals to the appropriate power supply, i.e., the on-chip linear regulator 180 or the off-chip switching regulator 190, to tune or synchronize the output voltages of the two regulators 180, 190. Switch 712 can be replaced by a firmware loop. However, Figure 7 The tuning method described herein may suffer from a mismatch between the first process and temperature monitor 404(1) and the second process and temperature monitor 404(2). Such a mismatch can be addressed through... Figure 8 The illustrated embodiment addresses this issue.

[0049] Figure 8 This is a high-level block diagram illustrating a single process and temperature monitor 810 used to provide control feedback to an on-chip linear regulator 180 and an off-chip switching regulator 190, according to an example embodiment. More specifically, not as... Figure 7 The diagram shows two separate process and temperature monitors to feed the frequency comparator 406 separately, instead of... Figure 8In this embodiment, a single process and temperature monitor 810 is used to monitor the output of each of the on-chip linear regulator 180 and the off-chip switching regulator 190 individually by selectively switching on or off switches MPT1 820 or MPT2 822. Thus, the same process and temperature monitor 810 is used to monitor the output voltage. A frequency comparator 406 is switched via a demultiplexer or switch 830 to provide appropriate control feedback to each of the on-chip linear regulator 180 and the off-chip switching regulator 190. Switch 830 can be replaced by firmware cycling. Therefore, the output voltages of the on-chip linear regulator 180 and the off-chip switching regulator 190 are tuned or synchronized with each other.

[0050] Figure 8 The embodiments provide the low noise advantage of the on-chip linear regulator 180, the power efficiency of the off-chip switching regulator 190, and the accuracy of the common process and temperature monitor 810 for both regulators.

[0051] Figure 9 This is a flowchart depicting a series of operations for operating a transimpedance amplifier system according to an example embodiment. At 902, the system receives power from an on-chip linear regulator at the front end of the transimpedance amplifier. At 904, the system receives power from an off-chip switching regulator at the rear end of the transimpedance amplifier. At 906, the system monitors the output voltage of the on-chip linear regulator and the output voltage of the off-chip switching regulator. At 908, the system makes the output voltage of the off-chip switching regulator the same as the output voltage of the on-chip linear regulator.

[0052] In summary, in one aspect, a system is provided. The system includes: a transimpedance amplifier disposed on a chip and having a front-end portion and a back-end portion; an on-chip linear regulator located on the chip and arranged to power the front-end portion; and an off-chip switching regulator located off-chip and arranged to power the back-end portion.

[0053] The front-end section may include a transimpedance front-end, a single-to-differential converter, and a first feedback circuit.

[0054] The back-end section may include a programmable gain amplifier section, an output buffer, and a second feedback circuit.

[0055] The system may also include a voltage measurement and feedback block that communicates with an off-chip switching regulator and is configured to monitor the output voltage of the on-chip linear regulator, monitor the output voltage of the off-chip switching regulator, and tune the output voltage of the off-chip switching regulator to the output voltage of the on-chip linear regulator.

[0056] The system may also include process and temperature monitoring circuitry, which is arranged to monitor the output of the on-chip linear regulator.

[0057] The system may include: a first process and temperature monitoring circuit, configured to monitor the output of an on-chip linear regulator; and a second process and temperature monitoring circuit, configured to monitor the output of an off-chip switching regulator.

[0058] The system may also include a frequency comparator and a multiplexer communicating with the frequency comparator, wherein the outputs of the first process and temperature monitoring circuit and the second process and temperature monitoring circuit are selectively provided to the frequency comparator via the multiplexer.

[0059] In one embodiment, the frequency comparator communicates with the on-chip linear regulator and the off-chip switching regulator via a demultiplexer, and the output of the frequency comparator is selectively provided to the on-chip linear regulator and the off-chip switching regulator via the demultiplexer.

[0060] The system may include process and temperature monitoring circuitry configured to independently monitor the outputs of the on-chip linear regulator and the off-chip switching regulator.

[0061] In one embodiment, the process and temperature monitoring circuitry may include a first switch that communicates with the output of an on-chip linear regulator and a second switch that communicates with the output of an off-chip switching regulator.

[0062] The system may include a frequency comparator, to which the output of the process and temperature monitoring circuitry is provided.

[0063] In one embodiment, the frequency comparator communicates with the on-chip linear regulator and the off-chip switching regulator via a demultiplexer, and the output of the frequency comparator is selectively provided to the on-chip linear regulator and the off-chip switching regulator via the demultiplexer.

[0064] In another embodiment, a device is provided comprising: a transimpedance amplifier disposed on a chip and having a front-end portion and a back-end portion; an on-chip linear regulator located on the chip and arranged to power the front-end portion; and process and temperature monitoring circuitry configured to independently monitor the outputs of the on-chip linear regulator and an off-chip switching regulator powering the back-end portion.

[0065] In this device, the process and temperature monitoring circuitry may include a first switch that communicates with the output of an on-chip linear regulator and a second switch that communicates with the output of an off-chip switching regulator.

[0066] The device may also include a frequency comparator, to which the output of the process and temperature monitoring circuitry is provided.

[0067] In this device, the frequency comparator can communicate with the on-chip linear regulator and the off-chip switching regulator via a demultiplexer, and the output of the frequency comparator is selectively provided to the on-chip linear regulator and the off-chip switching regulator via the demultiplexer.

[0068] In another embodiment, a method includes: receiving power from an on-chip linear regulator at a front end portion of an on-chip transimpedance amplifier; receiving power from an off-chip switching regulator at a rear end portion of the transimpedance amplifier; monitoring the output voltage of the on-chip linear regulator and the output voltage of the off-chip switching regulator; and making the output voltage of the off-chip switching regulator the same as or equal to the output voltage of the on-chip linear regulator.

[0069] In this method, the front-end portion may include a transimpedance front-end, a single-to-differential converter, and a first feedback circuit.

[0070] In this method, the back-end section may include a programmable gain amplifier section, an output buffer, and a second feedback circuit.

[0071] The method may also include using a single process and temperature monitoring circuit to monitor the output voltage of the on-chip linear regulator and the output voltage of the off-chip switching regulator.

[0072] The above description is intended only as an example. Various modifications and structural changes may be made therein without departing from the scope of the concepts described herein and within the scope of the equivalents of the claims.

Claims

1. A power supply system, comprising: A transimpedance amplifier, wherein the transimpedance amplifier is disposed on a chip, and the transimpedance amplifier has a front end portion and a rear end portion; An on-chip linear regulator, located on the chip, is arranged to power the front-end portion; as well as An off-chip switch regulator, located outside the chip, is configured to supply power to the back-end portion. The output voltage of the on-chip linear regulator and the output voltage of the off-chip switching regulator are controlled to be the same.

2. The system according to claim 1, wherein, The front-end section includes a transimpedance front-end, a single-to-differential converter, and a first feedback circuit.

3. The system according to claim 1 or 2, wherein, The back-end section includes a programmable gain amplifier section, an output buffer, and a second feedback circuit.

4. The system of claim 1 further includes a voltage measurement and feedback block, the voltage measurement and feedback block communicating with the off-chip switching regulator and configured to monitor the output voltage of the on-chip linear regulator, monitor the output voltage of the off-chip switching regulator, and synchronize the output voltage of the off-chip switching regulator with the output voltage of the on-chip linear regulator.

5. The system of claim 1 further includes process and temperature monitoring circuitry, the process and temperature monitoring circuitry being arranged to monitor the output of the on-chip linear regulator.

6. The system according to claim 1, further comprising: A first process and temperature monitoring circuit is arranged to monitor the output of the on-chip linear regulator. And a second process and temperature monitoring circuit, which is arranged to monitor the output voltage of the off-chip switching regulator.

7. The system of claim 6 further includes a frequency comparator and a multiplexer communicating with the frequency comparator, wherein, The outputs of the first process and temperature monitoring circuit and the second process and temperature monitoring circuit are selectively provided to the frequency comparator via the multiplexer.

8. The system according to claim 7, wherein, The frequency comparator communicates with the on-chip linear regulator and the off-chip switching regulator via a demultiplexer, and the output of the frequency comparator is selectively provided to the on-chip linear regulator and the off-chip switching regulator via the demultiplexer.

9. The system according to claim 1, further comprising: A process and temperature monitoring circuit is configured to independently monitor the outputs of the on-chip linear regulator and the off-chip switching regulator.

10. The system according to claim 9, wherein, The process and temperature monitoring circuit includes a first switch that communicates with the output of the on-chip linear regulator and a second switch that communicates with the output of the off-chip switching regulator.

11. The system of claim 9, further comprising a frequency comparator, wherein, The output of the process and temperature monitoring circuit is provided to the frequency comparator.

12. The system according to claim 11, wherein, The frequency comparator communicates with the on-chip linear regulator and the off-chip switching regulator via a demultiplexer, and the output of the frequency comparator is selectively provided to the on-chip linear regulator and the off-chip switching regulator via a second demultiplexer.

13. A power supply device, comprising: A transimpedance amplifier, wherein the transimpedance amplifier is disposed on a chip, and the transimpedance amplifier has a front end portion and a rear end portion; An on-chip linear regulator, located on the chip, is arranged to power the front-end portion; as well as A process and temperature monitoring circuit is configured to independently monitor the outputs of the on-chip linear regulator and the off-chip switching regulator that powers the back-end section. The output voltage of the on-chip linear regulator and the output voltage of the off-chip switching regulator are controlled to be the same.

14. The device according to claim 13, wherein, The process and temperature monitoring circuit includes a first switch that communicates with the output of the on-chip linear regulator and a second switch that communicates with the output of the off-chip switching regulator.

15. The device according to claim 13 or 14, further comprising a frequency comparator, wherein, The output of the process and temperature monitoring circuit is provided to the frequency comparator.

16. The device according to claim 15, wherein, The frequency comparator communicates with the on-chip linear regulator and the off-chip switching regulator via a demultiplexer, and the output of the frequency comparator is selectively provided to the on-chip linear regulator and the off-chip switching regulator via the demultiplexer.

17. A power supply method, comprising: Power is received at the front end of the transimpedance amplifier located on the chip from an on-chip linear regulator located on the chip; Power is received from an off-chip switching regulator at the rear end of the transimpedance amplifier. Monitor the output voltage of the on-chip linear regulator and the output voltage of the off-chip switching regulator; as well as Make the output voltage of the off-chip switching regulator the same as the output voltage of the on-chip linear regulator.

18. The method according to claim 17, wherein, The front-end section includes a transimpedance front-end, a single-to-differential converter, and a first feedback circuit.

19. The method according to claim 17 or 18, wherein, The back-end section includes a programmable gain amplifier section, an output buffer, and a second feedback circuit.

20. The method of claim 17, further comprising: The output voltage of the on-chip linear regulator and the output voltage of the off-chip switching regulator are monitored using a single process and temperature monitoring circuit.

Images