High speed peripheral component interconnect (PCIE) interface system and operating method thereof

Abstract

The present application relates to a Peripheral Component Interconnect Express (PCIe) interface system including a PCIe interface device, a host, and a Non-Volatile Memory Express (NVMe) device connected to the host through the PCIe interface device. The host includes a host memory configured to store information about a command to be executed on the NVMe device and a command that has been executed on the NVMe device, and an NVMe driver configured to transmit the command to be executed on the NVMe device to the host memory and output a doorbell signal to the NVMe device, the doorbell signal indicating that the command to be executed on the NVMe device has been stored in the host memory. The NVMe device requests the host memory to register a Lightweight Notification (LN) indicating a location where the command to be executed on the NVMe device is stored.

Description

[0001] Cross-reference to related applications

[0002] This patent document claims priority and benefit to Korean patent application No. 10-2021-0048080, filed on April 13, 2021, and Korean patent application No. 10-2021-0070686, filed on June 1, 2021, both of which are incorporated herein by reference in their entirety. Technical Field

[0003] The technology and implementation scheme disclosed in this patent document relate to an electronic device, and more specifically, to a PCIe interface system and its operation method. Background Technology

[0004] High-speed peripheral component interconnect (PCIe) is a serial interface architecture used for data communication. PCIe-based storage devices support multiple ports and multiple functions. PCIe-based storage devices can be virtualized or non-virtualized, and can implement Quality of Service (QoS) for host I / O commands through one or more PCIe functions.

[0005] A storage device is a means of storing data under the control of a host device such as a computer or smartphone. A storage device may include a memory device for storing data and a memory controller for controlling the memory device. Memory devices are classified as volatile memory devices and non-volatile memory devices.

[0006] Volatile memory devices are devices that store data only when powered on and lose the stored data when power is cut off. Volatile memory devices include static random access memory (SRAM) and dynamic random access memory (DRAM).

[0007] Non-volatile memory devices are devices that retain data even when power is cut off. Non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, etc. Summary of the Invention

[0008] Various embodiments of the disclosed technology provide a PCIe interface system and its operation method, which reduces the time to obtain commands by registering PCIe Lightweight Notifications (LNs) and pre-fetching commands.

[0009] According to embodiments of this disclosure, a high-speed peripheral component interconnect (PCIe) interface system may include a PCIe interface device, a host, and a high-speed non-volatile memory (NVMe) device connected to the host via the PCIe interface device. The host may include: host memory configured to store information about commands to be executed on the NVMe device and commands already executed on the NVMe device; and an NVMe drive configured to send commands to be executed on the NVMe device to the host memory and output a doorbell signal to the NVMe device indicating that commands to be executed on the NVMe device have been stored in the host memory. The NVMe device is configured to request the host memory to register a lightweight notification (LN) register indicating the location where commands to be executed on the NVMe device are stored.

[0010] According to embodiments of this disclosure, an operating system method may include: requesting a high-speed peripheral component interconnect (PCIe) lightweight notification (LN) register by a system, the system including a host having host memory and a high-speed non-volatile memory (NVMe) device connected to the host via a PCIe interface device, the LN register indicating a location within the host memory included in the system where a command to be executed on the NVMe device is stored; registering the LN; and storing the command to be executed on the NVMe device in the host memory.

[0011] According to this technology, a PCIe interface system and its operation method are provided, which reduces the time to obtain commands by registering PCIe Lightweight Notifications (LN) and pre-fetching commands. Attached Figure Description

[0012] Figure 1 This is an example of a block diagram illustrating a high-speed peripheral component interconnect (PCIe) interface system based on some implementations of the disclosed technology.

[0013] Figure 2 This is an example of a diagram illustrating packet transmission between configurations included in a PCIe interface device based on some embodiments of the disclosed technology.

[0014] Figure 3 This is a diagram illustrating examples of command processing in NVMe based on some implementations of the disclosed technology.

[0015] Figure 4 It is shown Figure 3 A diagram illustrating an example of command processing.

[0016] Figure 5 This is a diagram illustrating examples of command processing executed via LN based on some implementations of the disclosed technology.

[0017] Figure 6 This is a diagram illustrating examples of LN implementations based on the disclosed technology.

[0018] Figure 7 This is a diagram illustrating examples of LN registers based on some implementations of the disclosed technology.

[0019] Figure 8 This is an example illustrating command prefetching and command fetching after an LN register based on some implementations of the disclosed technology.

[0020] Figure 9 This is a diagram illustrating the delay at the end of a low-power state in some embodiments based on the disclosed technology.

[0021] Figure 10 This is a diagram illustrating the termination of a low-power state via an LN register based on some embodiments of the disclosed technology.

[0022] Figure 11 This is a diagram illustrating the operation of a PCIe interface system based on some implementations of the disclosed technology.

[0023] Figure 12 This is a diagram illustrating the operation of a PCIe interface system based on some implementations of the disclosed technology.

[0024] Figure 13 This is a diagram illustrating the operation of a PCIe interface system based on some implementations of the disclosed technology. Detailed Implementation

[0025] Figure 1 This is a block diagram illustrating a high-speed peripheral component interconnect (PCIe) interface system.

[0026] Reference Figure 1 , Figure 1 The PCIe interface device 100 may include a central processing unit 110, a root union 120, a memory 130, a switch 140, PCIe endpoints 150_1 and 150_2, and traditional endpoints 160_1 and 160_2. Additionally, Figure 1 The host 300 may include host internal structure 310, host processor 320, host memory 330 and NVMe drive 340.

[0027] exist Figure 1 In this configuration, root consortium 120 can be connected to switch 140 via a link. Additionally, switch 140 can be connected via links to each of PCIe endpoints 150_1 and 150_2, and legacy endpoints 160_1 and 160_2. Each link can be configured with at least one channel.

[0028] In this embodiment, root union 120 can connect central processing unit 110 and memory 130 to the I / O hierarchy. Root union 120 can support PCIe ports. Therefore, root union 120 can support root ports that can be connected to input / output (I / O) devices.

[0029] Additionally, root federation 120 can support routing between each configured tier included in the PCIe interface device 100. Routing can include the operation of selecting a path from the sending side to the receiving side in data communication. Routing can be performed based on any of the methods either pre-configured paths from the sending side to the receiving side or by selecting the most efficient path based on the state of the system or network.

[0030] In some implementations, root union 120 may support input / output requests. Root union 120 needs to support generating configuration requests. Root union 120 is not allowed to support locking semantics as a completer. Root union 120 may act as a requester to request the generation of lock requests.

[0031] In this embodiment, root union 120 may divide data packets transmitted between tiers into smaller units during routing. Additionally, root union 120 may generate input / output requests.

[0032] In this embodiment, switch 140 may be configured with two or more logical PCI-to-PCI bridges. Each of the two or more logical PCI-to-PCI bridges may be connected to an upstream port or a downstream port.

[0033] Switch 140 can use the PCI bridge mechanism (address-based multicast method) to transmit transactions. In this case, switch 140 needs to be able to transmit all types of Transaction Layer Packets (TLPs) through upstream and downstream ports. Additionally, switch 140 needs to support locking requests. Each port of the enabled switch 140 must be able to support flow control. When contention occurs in the same virtual channel, switch 140 can arbitrate using either round-robin or weighted round-robin methods.

[0034] In this embodiment, unlike root federation 120, switch 140 may not divide data packets transmitted between tiers into smaller units.

[0035] In this embodiment, PCIe endpoints 150_1 and 150_2, and traditional endpoints 160_1 and 160_2, can be used as requesters or completers of PCIe transactions. TLPs sent and received by PCIe endpoints 150_1 and 150_2, and traditional endpoints 160_1 and 160_2, must include a configuration space header. Additionally, PCIe endpoints 150_1 and 150_2, and traditional endpoints 160_1 and 160_2, must provide configuration requests as completers.

[0036] In this embodiment, PCIe endpoints 150_1 and 150_2, and traditional endpoints 160_1 and 160_2, can be distinguished based on the size of the memory transaction. For example, when the memory transaction is likely to exceed 4GB, the endpoints may be PCIe endpoints 150_1 and 150_2; when the memory transaction is unlikely to exceed 4GB, the endpoints may be traditional endpoints 160_1 and 160_2. PCIe endpoints 150_1 and 150_2 may not generate I / O requests, but traditional endpoints 160_1 and 160_2 may provide or generate I / O requests.

[0037] In the embodiment, PCIe endpoints 150_1 and 150_2 or traditional endpoints 160_1 and 160_2 can send TLPs to and receive TLPs from switch 140.

[0038] In one embodiment, switch 140 can send TLPs received from PCIe endpoints 150_1 and 150_2 or traditional endpoints 160_1 and 160_2 to root union 120.

[0039] In this embodiment, root federation 120 can send TLPs to and receive TLPs from PCIe endpoints 150_1 and 150_2 or traditional endpoints 160_1 and 160_2 via switch 140. Root federation 120 can then send TLPs received from PCIe endpoints 150_1 and 150_2 or traditional endpoints 160_1 and 160_2 to central processing unit 110 or memory 130.

[0040] In an embodiment, the host processor 320 and host memory 330 included in the host 300 can be connected to the root union 120 through the host internal structure 310.

[0041] In this embodiment, the host processor 320 can control write or read operations to be performed on a high-speed non-volatile memory (NVMe) device connected to each of PCIe endpoints 150_1 and 150_2 or traditional endpoints 160_1 and 160_2. In some embodiments, the NVMe device may be a solid-state drive (SSD) or include a solid-state drive (SSD). Additionally, the host processor 320 may store information required to control the write or read operations to be performed on the NVMe device in host memory 330.

[0042] In one embodiment, the NVMe drive 340 can be connected to the central processing unit 110 and allow the host 300 to control the NVMe device through the PCIe interface device 100.

[0043] Figure 2 This is a diagram illustrating the data packet transmission between configurations included in a PCIe interface device.

[0044] Reference Figure 1 and Figure 2 , Figure 2 PCI components PCI COMPONENT 1 and 2 can be Figure 1 Any of the root union 120, switch 140, PCIe endpoints 150_1 and 150_2, and legacy endpoints 160_1 and 160_2. Figure 2 PCI components 1 and 2 can be either of the components connected via a link. The link can be configured with at least one channel.

[0045] In this embodiment, PCI components PCI COMPONENT 1 and 2 can send and receive data packets via a link LINK. Each of PCI components PCI COMPONENT 1 and 2 can operate as a transmitter (TX) for sending data packets or a receiver (RX) for receiving data packets.

[0046] In an embodiment, a data packet (PACKET) may be an information transmission unit that includes a selective TLP prefix, a header, and a data payload.

[0047] In this embodiment, packets that do not need to be cached are not monitored, thereby reducing latency. When there are no dependencies between transactions, the performance of packet operations can be improved by changing the ordering. Additionally, the performance of packet operations can be improved by changing the ID-based ordering.

[0048] Figure 3 This is a diagram illustrating command processing in NVMe.

[0049] Reference Figure 1 and Figure 3 , Figure 3 It shows the way Figure 1 The process of running commands on an NVMe device connected to each of PCIe endpoints 150_1 and 150_2 or legacy endpoints 160_1 and 160_2, including an NVMe drive 340 and host memory 330 in host 300. The NVMe device may include an NVMe controller 500. Figure 3 In this context, the host memory 330 may include a submission queue (SQ) and a completion queue (CQ).

[0050] In one embodiment, the NVMe drive 340 can send a command COMMAND, which is to be executed on the NVMe device, to a submission queue. The submission queue can then queue commands received from the NVMe drive 340. For example, the host memory 330 can queue the received commands sequentially from the head to the tail of the submission queue.

[0051] When the command COMMAND is queued in the commit queue, the NVMe drive 340 can output a commit queue tail doorbell signal to the NVMe controller 500. The NVMe controller 500 can receive the commit queue tail doorbell signal and store a commit queue tail entry pointer in a register. Here, the commit queue tail entry pointer can be an indicator that indicates a command queued at the tail of the commit queue. The NVMe controller 500 can store the commit queue tail entry pointer in a register to identify new commands output from the host memory 330.

[0052] Subsequently, the NVMe controller 500 can retrieve commands from the host memory 330. The NVMe controller 500 can receive commands queued in the submission queue. The NVMe controller 500 can execute operations corresponding to the received commands.

[0053] In this embodiment, after the NVMe controller 500 executes an operation corresponding to a command, a completion queue entry can be sent to the host memory 330. The completion queue entry may include information about commands recently executed by the NVMe controller 500. The host memory 330 may queue the received completion queue entries in a completion queue. For example, the host memory 330 may queue the received completion queue entries sequentially from the front to the back of the completion queue.

[0054] Subsequently, the NVMe controller 500 can output an interrupt signal to the NVMe driver 340. The interrupt signal can be a signal indicating that a completion queue entry has been queued in the completion queue.

[0055] Upon receiving an interrupt signal, the NVMe driver 340 can perform an operation based on the completion queue entry in the completion queue. When the NVMe driver 340 completes the operation, it can output a completion queue head-of-line doorbell signal to the NVMe controller 500. The NVMe controller 500 can receive the completion queue head-of-line doorbell signal and store a completion queue head-of-line entry pointer in a register. Here, the completion queue head-of-line entry pointer can be an indicator that points to the entry queued at the head of the completion queue. The NVMe controller 500 can store the completion queue head-of-line entry pointer in a register to identify commands indicating that the corresponding operation has been completed.

[0056] Figure 4 It is shown Figure 3 A diagram illustrating command processing.

[0057] Figure 4 The operation of the NVMe drive 340, host memory 330, and SSD is illustrated. The SSD corresponds to the connection... Figure 3 One of the NVMe devices with PCIe endpoints 150_1 and 150_2 or traditional endpoints 160_1 and 160_2.

[0058] exist Figure 4 In this context, non-DMA (Non-Direct Access Memory) operations can be directed to... Figure 1 The operations performed by the central processing unit 110, DMA (Direct Access Memory) operations can refer to operations performed without... Figure 1 Operations performed independently without intervention from the central processing unit 110.

[0059] In this embodiment, the NVMe drive 340 outputs the command COMMAND to be executed on the SSD to the host memory 330, and the host memory 330 can queue the received commands sequentially from the head to the tail of the submission queue.

[0060] Afterwards, the NVMe drive 340 can output an SQ doorbell signal to the SSD. The SQ doorbell signal can be... Figure 3 The same signal as the doorbell signal at the end of the submission queue. In other words, the NVMe drive 340 can output an SQ doorbell signal to the SSD to identify new commands output from the host memory 330.

[0061] In this embodiment, the SSD can retrieve commands from the host memory 330. That is, the SSD can receive commands queued in the submission queue from the host memory 330 and execute the operations corresponding to the received commands. When the SSD completes the operation corresponding to the command received from the host memory 330, the SSD can output a completion signal to the host memory 330.

[0062] After that, NVMe drives 340 and SSDs can be used without Figure 1 DMA operations can be performed independently without intervention from the central processing unit 110.

[0063] In this embodiment, after the SSD performs the operation corresponding to the command, the completion queue of the host memory 330 can be updated (Completion Queue Update, CQ UPDATE). That is, after the SSD performs the operation corresponding to the command, completion queue entries can be sent to the host memory 330, and the host memory 330 can queue the received completion queue entries sequentially from the front to the back of the completion queue.

[0064] After this, the SSD can output an interrupt signal to the NVMe drive 340. The interrupt signal can be a signal indicating that a completion queue entry is being queued in the completion queue.

[0065] In this embodiment, when the NVMe drive 340 completes an operation based on a completion queue entry in the completion queue, the NVMe drive 340 can output a CQ doorbell signal to the SSD. The CQ doorbell signal can be... Figure 3 The NVMe drive 340 outputs a CQ doorbell signal to the SSD to identify the completion of the operation.

[0066] Subsequently, the NVMe drive 340 can output the new command COMMAND, which is to be run on the SSD, to the host memory 330, and output the SQ doorbell signal to the SSD to recognize the new command output from the host memory 330.

[0067] Of the operations described above, those other than DMA operations can be non-DMA operations. (See reference...) Figure 4 It should be noted that non-DMA operations take longer to process than DMA operations. Since processing non-DMA operations requires more time, an implementation scheme is needed to reduce the time spent processing them. To reduce the time consumed by non-DMA operations, a method for performing non-DMA operations using lightweight notifications (LNs) will be discussed below.

[0068] Figure 5 This is a diagram illustrating the processing of commands executed via LN.

[0069] Figure 5 It shows Figure 4 The NVMe drive 340, host memory 330, and SSD operate based on PCIe Lightweight Notification (LN). The LN can indicate a specific address of the host memory 330 and can be included in the header of a Transaction Layer Packet (TLP). Additionally, the LN can be registered... Figure 1 The root union 120 is in the cache line.

[0070] exist Figure 5 In this context, non-DMA operations refer to operations performed by... Figure 1 The operations performed by the central processing unit 110, DMA operations can refer to operations performed without... Figure 1 Operations performed independently without intervention from the central processing unit 110.

[0071] In this embodiment, the SSD can register the LN. Figure 1 The LN is located in the cache line of the root union 120 and in the host memory 330. At this time, the LN can indicate the position where the command is queued in the host memory 330.

[0072] When LN is registered Figure 1 When the NVMe drive 340 is in the cache line of the root union 120 and the host memory 330, the NVMe drive 340 can output commands waiting to run on the SSD to the host memory 330, and the host memory 330 can queue the received commands sequentially from the head to the tail of the submission queue.

[0073] In this embodiment, when the command COMMAND is queued in the host memory 330, the host memory 330 can output an LN message to the SSD. The LN message can indicate the position of the command COMMAND in the host memory 330 queue. When the position of the command COMMAND in the queue changes, the host memory 330 can output the changed position to the SSD through the LN message.

[0074] In this embodiment, the SSD can pre-fetch commands (command pre-fetch). For example, the SSD can receive commands queued in the submission queue from the host memory 330. Commands queued in the submission queue can be updated before the NVMe drive 340 outputs the SQ doorbell signal, and the host memory 330 can output an LN message to the SSD before the SQ doorbell signal is output. Therefore, the SSD can prepare for command execution in advance by pre-fetching commands. Furthermore, since the command information is stored in... Figure 1 The root union 120 is cached in the high-speed line, so commands can be quickly retrieved to improve the operating speed of the SSD.

[0075] Afterwards, the NVMe drive 340 can output an SQ doorbell signal to the SSD. The SQ doorbell signal can be... Figure 3 The SQ doorbell signal is the same as the tail doorbell signal in the submission queue. The NVMe drive 340 can output the SQ doorbell signal to the SSD to identify new commands output from the host memory 330. The SSD can then perform an operation corresponding to the pre-fetched command based on the SQ doorbell signal.

[0076] Upon receiving the SQ doorbell signal, the SSD can fetch a command from the host memory 330 (command fetch, COMMAND FETCH). When the SSD fetches a command, it can release the LN register. The SSD can then perform operations based on a comparison between the pre-fetched command and the fetched command.

[0077] For example, if the pre-fetched command and the fetched command are the same, the SSD can continue to execute the operation corresponding to the pre-fetched command. However, if the pre-fetched command and the fetched command are different, the SSD can stop the operation corresponding to the pre-fetched command and execute the operation corresponding to the fetched command.

[0078] When the SSD completes the operation corresponding to the command received from the host memory 330, the SSD can output a completion signal to the host memory 330.

[0079] In this embodiment, the operation of the SSD retrieving commands from the host memory 330 and the operation of outputting a completion signal to the host memory 330 can be performed via... Figure 1 The central processing unit 110 performs non-DMA operations. Since these non-DMA operations are performed between DMA operations, the randomness of data input / output can be improved. Input / output randomness can mean the randomness of data of a specific size for each command.

[0080] After this, the SSD can register instructions for the next command. Figure 1 The LN of the cache line of the root union 120 and the queued location in the host memory 330.

[0081] In this embodiment, after the SSD performs the operation corresponding to the command, the completion queue of the host memory 330 can be updated (CQ update). After the CQ update, the SSD can output an interrupt signal to the NVMe drive 340 indicating that a completion queue entry has been queued in the completion queue. When the operation performed by the NVMe drive 340 in response to the interrupt signal based on the completion queue entry is completed, the NVMe drive 340 can output a CQ doorbell signal to the SSD.

[0082] In one embodiment, the NVMe drive 340 may further perform the operation of outputting the command COMMAND, which is to be run on the SSD, to the host memory 330.

[0083] Therefore, by registering the LN in the host memory 330 and pre-fetching commands, the command fetching time can be shortened and the input / output random performance of the SSD can be improved.

[0084] Figure 6 This is a diagram showing LN.

[0085] Figure 6 This shows a portion of the TLP header.

[0086] In an embodiment, the TLP header may include 0 to 3 bytes (BYTE), and each BYTE may include 0 to 8 bits (BIT). The 0 to 3 BYTEs of the TLP header may include various information.

[0087] In an embodiment, the 0BYTE of the TLP header may include format (FMT) information indicating the TLP format and type (TYPE) information indicating the TLP type. For example, the FMT information may be included in bits 7 to 5 of the 0BYTE, and the TYPE information may be included in bits 4 to 0 of the 0BYTE.

[0088] In this embodiment, LN information may be included in the 1-bit of a 1-byte TLP header. The LN may be a protocol that supports hardware-based notification of endpoints when cache lines are updated. When the 1-bit of a 1-byte is "1", the LN information can indicate that the operation is complete.

[0089] Reference Figure 5 Before the NVMe drive 340 outputs a command to the host memory 330, the LN can be registered in the host memory 330. At this time, the 1-bit of the 1-byte TLP header can be set to "1". That is, before the NVMe drive 340 outputs the SQ doorbell signal to the SSD, the command queue position can be registered in LN. When the SSD receives the LN message, the SSD can prefetch the commands queued in the host memory 330.

[0090] Subsequently, when the NVMe drive 340 outputs the SQ doorbell signal to the SSD, and the SSD retrieves the command again, the 1-bit of the 1-byte in the TLP header can be set to "0", and the LN register can be released.

[0091] Figure 7 This is a diagram showing the LN register.

[0092] Figure 7 It shows Figure 1The system includes a host 300, a central processing unit 110, a root federation 120, a switch 140, and an NVMe device 150 connected to any one of PCIe endpoints 150_1 and 150_2 and legacy endpoints 160_1 and 160_2. In some implementations, the NVMe device 150 may be an SSD.

[0093] In this embodiment, when the host 300 sends a command to the NVMe device 150, the host 300 can store the command information. Figure 1 The SQ doorbell signal is then stored in the host memory 330 and sent to the NVMe device 150. At this time, the command information is stored... Figure 1 The address in the host memory 330 can be fixed. In some embodiments of the disclosed technology, this address can be registered in LN. Figure 1 The cache lines (LN registers) of host 300 and root union 120.

[0094] In this embodiment, the LN can be registered before the host 300 sends a command to the NVMe device 150. When the LN is registered, the host 300 can store the command information. Figure 1 The host 300 stores the LN message in the host memory 330 and simultaneously outputs the LN message to the NVMe device 150. Therefore, the host 300 can notify the NVMe device 150 of command information via the LN message. Figure 1 The host memory 330 is updated. Afterwards, the host 300 can output an SQ doorbell signal to the NVMe device 150.

[0095] Therefore, by outputting an LN message before the host 300 outputs an SQ doorbell signal to the NVMe device 150, the NVMe device 150 can pre-check for the occurrence of a new command.

[0096] Figure 8 This is a diagram showing command prefetching and command fetching after LN register.

[0097] Figure 8 It shows that in such Figure 7 The discussion concerns the operations following the output of LN messages from host 300 to NVMe device 150.

[0098] In this embodiment, the NVMe device 150 can pre-fetch data stored in memory before receiving the SQ doorbell signal. Figure 1 Commands in host memory 330. Specifically, NVMe device 150 can be accessed via... Figure 1The root union 120 uses a cache line (CACHELINE) to prefetch commands. The NVMe device 150 can check for new commands based on LN messages and prefetch commands stored in the cache before receiving the SQ doorbell signal. Figure 1 Commands in host memory 330.

[0099] In this embodiment, the data is pre-fetched and stored in the database. Figure 1 Commands stored in host memory 330 can be retrieved, reducing the time spent fetching commands. Therefore, input / output randomness can be improved. Input / output randomness can refer to the randomness of data of a specific size for each command.

[0100] Additionally, in this scenario, after receiving the SQ doorbell signal, the NVMe device 150 can again access the data stored in the memory. Figure 1 Commands in host memory 330 (command fetch, COMMAND FETCH).

[0101] In this embodiment, when the pre-fetched command and the acquired command are the same, the NVMe device 150 can perform the pre-fetch and continue executing the operation corresponding to the currently running command. However, when the pre-fetched command and the acquired command are different, the NVMe device 150 can stop the operation corresponding to the pre-fetched command and execute the operation corresponding to the newly acquired command.

[0102] Figure 9 This is a diagram showing the delay at the end of the low-power state.

[0103] Figure 9 It shows Figure 3 The operation of the NVMe drive 340, host memory 330, and SSD is shown. The SSD corresponds to the connection to... Figure 1 The downstream port DOWNSTREAM PORT of switch 140 and one of the NVMe devices of PCIe endpoints 150_1 and 150_2 or traditional endpoints 160_1 and 160_2. Here, the downstream port DOWNSTREAM PORT may be a port that is relatively farther from the root union 120 compared to the upstream port of switch 140.

[0104] exist Figure 9 In this context, an SSD can be in an L1.2 state. The L1.2 state can signify a low-power state. To prevent excessive power consumption, an SSD can be in an L1.2 state.

[0105] exist Figure 9In this context, the L0 state can be a state where power can be managed, and it can also be a state where data and control packets can be sent and received normally. For example, in the L0 state, Transaction Layer Packets (TLPs) and Data Link Layer Packets (DLLPs) can be sent and received. An SSD can stop operating in the L1.2 state and resume operation in the L0 state.

[0106] In this embodiment, the NVMe drive 340 can output a COMMAND command to the host memory 330, which can then queue the received command. Subsequently, the NVMe drive 340 can output an SQ doorbell signal, indicating that a new command is being queued in the SSD, via the downstream port DOWNSTREAM PORT.

[0107] However, since the SSD is initially in the L1.2 state, a wake-up signal can be output to the SSD from the downstream DOWNSTREAM PORT. Based on the wake-up signal, the SSD can transition from the L1.2 state to the L0 state (LOW POWEREXIT), and the SSD can then be in a state where it can resume operations. At this point, a latency (LATENCY) may occur before the SSD transitions from the L1.2 state to the L0 state.

[0108] When the SSD is in an operational state, the SQ doorbell signal received from the NVMe drive 340 can be output to the SSD from the downstream port DOWNSTREAM PORT.

[0109] Subsequently, in L0 state, the SSD can retrieve commands from the host memory 330. The SSD can receive commands queued in the submission queue from the host memory 330 and execute the operations corresponding to the received commands.

[0110] In order to minimize the latency of LATENCY before the SSD transitions from L1.2 to L0, some implementations of the disclosed technology propose a method to terminate the low-power state by registering the location of the command storage in LN.

[0111] Figure 10 This is a diagram illustrating the termination of the low-power state via the LN register.

[0112] Figure 10 It shows Figure 3 The operation of the NVMe drive 340 and host memory 330, as well as the operation of the SSD, are shown. The SSD corresponds to the connection to... Figure 1The downstream port of switch 140 is a DOWNSTREAM PORT, and one of the NVMe devices at PCIe endpoints 150_1 and 150_2 or traditional endpoints 160_1 and 160_2. Here, the downstream port can be a port that is relatively farther from the root union 120 compared to the upstream port of switch 140.

[0113] exist Figure 10 In this context, an SSD can be in an L1.2 state. The L1.2 state can signify a low-power state. To prevent excessive power consumption, an SSD can be in an L1.2 state.

[0114] exist Figure 10 In this context, the L0 state can be a state where power can be managed, and it can also be a state where data and control packets can be sent and received normally. For example, in the L0 state, Transaction Layer Packets (TLPs) and Data Link Layer Packets (DLLPs) can be sent and received. An SSD can stop operating in the L1.2 state and resume operation in the L0 state.

[0115] However, with Figure 9 The difference lies in Figure 10 In this process, by registering LN in the host memory 330, the state of the SSD can change from L1.2 state to L0 state.

[0116] In this embodiment, before the NVMe driver 340 sends a command to the NVMe device 150, the LN can be registered in the host memory 330 in the L0 state (LN register, LN REGISTER). At this time, the LN can indicate the address where the command information is stored in the host memory 330.

[0117] When an LN is registered, in L1.2 state, the NVMe driver 340 can store command information in the host memory 330 and simultaneously output an LN message from the host memory 330 to the downstream port DOWNSTREAM PORT. Therefore, an LN message can be output to notify the downstream port DOWNSTREAM PORT that new commands are queued in the host memory 330.

[0118] In this embodiment, a wake-up signal can be output from the downstream port DOWNSTREAM PORT to the SSD based on an LN message. According to the wake-up signal, the SSD can transition from the L1.2 state to the L0 state (low power exit), allowing the SSD to be in a state capable of resuming operation.

[0119] At this point, since the wake-up signal is output based on the LN message before the SQ doorbell signal is output, the time it takes for the SSD to change its state from L1.2 to L0 can be reduced.

[0120] Subsequently, when the SSD is in a recoverable state, the SQ doorbell signal received from the NVMe drive 340 can be output to the SSD from the downstream port DOWNSTREAM PORT. In L0 state, the SSD can retrieve commands from the host memory 330.

[0121] Figure 11 This is a diagram illustrating the operation of a PCIe interface system based on some implementations of the disclosed technology.

[0122] Reference Figure 11 In step S1101, the host may register an LN. The LN may indicate an address corresponding to the location in the host memory where the command information is stored.

[0123] In step S1103, the host may store commands to be executed on the SSD. For example, the host may queue the commands sequentially in the host memory from the front to the back of the submission queue.

[0124] In step S1105, the host can send an LN message to the SSD. That is, the host can indicate the queued position of a new command in the host memory. In other words, when the command queued position changes, the host can output the changed position to the SSD via an LN message.

[0125] In step S1107, the SSD can prefetch commands queued in the host memory. When the SSD receives an LN message, it can prepare to execute commands in advance through command prefetching.

[0126] In step S1109, the host can send an SQ doorbell signal to the SSD. Therefore, the host can output the SQ doorbell signal to the SSD to identify a new command output from the host memory. The SSD can then execute an operation corresponding to the pre-acquired command based on the SQ doorbell signal.

[0127] In step S1111, the SSD may re-fetch commands queued in host memory. For example, when the SSD executes an operation corresponding to a pre-fetched command, it may re-fetch commands queued in host memory. The SSD may execute operations based on a comparison between the pre-fetched command and the fetched command.

[0128] Figure 12 This is a diagram illustrating the operation of a PCIe interface system based on some implementations of the disclosed technology.

[0129] Figure 12 It shows Figure 11 The steps following step S1111.

[0130] In step S1201, the SSD can determine whether the pre-fetched command and the fetched command are the same. When executing the operation corresponding to the pre-fetched command, the SSD can fetch the command again and compare the pre-fetched command with the fetched command.

[0131] When the command to be fetched is the same as the command to be fetched (yes), the operation can proceed to step S1203, and the SSD can then execute the operation corresponding to the command in progress.

[0132] However, when the pre-fetched command and the fetched command are different (no), the operation can proceed to step S1205, where the SSD can stop the operation corresponding to the ongoing command and execute the operation corresponding to the newly fetched command.

[0133] Figure 13 This is a diagram illustrating the operation of a PCIe interface system based on some implementations of the disclosed technology.

[0134] Reference Figure 13 In step S1301, the host can register an LN. The LN can indicate the address where command information is stored in the host memory included in the host. At this time, the SSD can be in the L0 state. The L0 state can be a power-manageable state, and can also be a state for normally sending and receiving data and control packets.

[0135] In step S1303, the host can store commands to be executed on the SSD. For example, the host can queue commands sequentially in the host memory from the front to the back of the submission queue. At this time, the SSD can be in the L1.2 state, i.e., the low-power state.

[0136] In step S1305, the host can send an LN message to the SSD via a downstream port. An LN message can be output to notify the downstream port that a new command is being queued in the host memory. Here, the downstream port can be a port of a switch located relatively further from the root federation within the configuration of the PCIe interface device.

[0137] In step S1307, a wake-up signal output from the downstream port can be sent to the SSD. To change the SSD's state from L1.2 to L0, i.e., a state where operation can be performed, a wake-up signal can be output from the downstream port. Based on the wake-up signal, the SSD can change from L1.2 to L0 (low power exit), and the SSD can be in a state where it can perform operation again.

[0138] In step S1309, the host can send an SQ doorbell signal to the SSD via a downstream port. When the SSD is in an operational state, the host can output the SQ doorbell signal to the SSD to identify new commands output from the host memory.

[0139] In step S1311, the SSD can retrieve commands queued in the host memory. The SSD can retrieve the commands and execute the operations corresponding to the retrieved commands.

[0140] Examples of embodiments of the disclosed technology for a system having a host and one or more memory devices, and an interface between the host and the memory devices, are described. Variations and modifications may be made to the disclosed embodiments and other embodiments based on the descriptions or illustrations herein.

Claims

1. A high-speed peripheral component interconnect interface system, namely a PCIe interface system, the PCIe interface system comprising a PCIe interface device, a host, and a high-speed non-volatile memory device, namely an NVMe device, connected to the host via the PCIe interface device. The host includes: Host memory stores information about commands to be executed on the NVMe device and commands that have already been executed on the NVMe device; as well as The NVMe drive sends commands to be executed on the NVMe device to the host memory and outputs a doorbell signal to the NVMe device, indicating that the commands to be executed on the NVMe device have been stored in the host memory. The NVMe device requests the host memory to register a Lightweight Notification (LN), the LN indicating the location where a command to be executed on the NVMe device is stored, and receives an LN message from the host memory before the doorbell signal, the LN message indicating that the command to be executed on the NVMe device is stored in the host memory.

2. The PCIe interface system of claim 1, wherein after the LN is registered in the host memory, the commands received from the NVMe driver are queued in a submission queue.

3. The PCIe interface system according to claim 1, wherein the NVMe device pre-acquires commands to be executed on the NVMe device and performs operations corresponding to the pre-acquired commands.

4. The PCIe interface system of claim 3, wherein the NVMe device further receives the doorbell signal from the NVMe driver, and upon receiving the doorbell signal, retrieves a command to be executed on the NVMe device from the host memory.

5. The PCIe interface system of claim 4, wherein the NVMe device further performs operations based on a comparison between the pre-fetched command and the fetched command.

6. The PCIe interface system of claim 5, wherein the NVMe device further responds to a comparison result indicating that the pre-fetched command and the fetched command are the same, and performs an operation corresponding to the pre-fetched command.

7. The PCIe interface system of claim 5, wherein the NVMe device further responds to a comparison result indicating that the pre-fetched command and the acquired command are different, stops the operation corresponding to the pre-fetched command and executes the operation corresponding to the acquired command.

8. The PCIe interface system of claim 1, wherein in response to a low-power state of the NVMe device, the host memory further sends the LN message to a downstream port of a switch included in the PCIe interface device.

9. The PCIe interface system of claim 8, wherein the switch further sends a wake-up signal to the NVMe device to end the low-power state based on the LN message, and The NVMe device further receives the wake-up signal and changes the state of the NVMe device from the low power state.

10. The PCIe interface system of claim 9, wherein the NVMe driver further outputs the doorbell signal to the NVMe device through the downstream port, and The NVMe device further retrieves commands from the host memory to be executed on the NVMe device.

11. A method for operating a system, the method comprising: The system requests a high-speed peripheral component interconnect lightweight notification register, i.e., a PCIe LN register. The system includes a host with host memory and a high-speed non-volatile memory device, i.e., an NVMe device, connected to the host via a PCIe interface device. The LN register indicates the location within the host memory included in the system where a command to be executed on the NVMe device is stored. Register the LN; as well as The commands to be executed on the NVMe device are stored in the host memory; as well as Before a doorbell signal indicating that a command to be executed on the NVMe device is stored in the host memory, an LN message is output to the NVMe device, the LN message indicating that a command to be executed on the NVMe device is stored in the host memory.

12. The method of claim 11, wherein storing commands includes queuing commands to be executed on the NVMe device in a submission queue included in the host memory.

13. The method of claim 11, further comprising: Prefetch commands to be executed on the NVMe device; as well as Execute the operation corresponding to the pre-fetched command.

14. The method of claim 13, further comprising: When the doorbell signal is output, a command to be executed on the NVMe device is retrieved from the host memory, and the doorbell signal output during the operation corresponds to the pre-retrieved command.

15. The method of claim 14, wherein performing the operation corresponding to the pre-fetched command includes performing the operation corresponding to the pre-fetched command in response to a comparison result between the pre-fetched command and the acquired command, the result indicating that the pre-fetched command and the acquired command are the same.

16. The method of claim 14, wherein performing the operation corresponding to the pre-fetched command includes, in response to a comparison result between the pre-fetched command and the acquired command, stopping the operation corresponding to the pre-fetched command and performing the operation corresponding to the acquired command, the result indicating that the pre-fetched command and the acquired command are different.

17. The method of claim 11, further comprising responding to a low-power state of the NVMe device: The LN message is sent to a downstream port of a switch included in the interface device, the LN message indicating that a command to be executed on the NVMe device has been stored; and Based on the LN message, a wake-up signal is sent to the NVMe device to end the low-power state.

18. The method of claim 17, further comprising: The doorbell signal is output to the NVMe device; as well as The command to be executed on the NVMe device is retrieved from the host memory based on the doorbell signal.

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