A voltage divider RRAM array structure

Abstract

This invention discloses a voltage divider type RRAM array structure, including a 1T1R unit and another 1T unit. 1T refers to a MOSFET, and 1R refers to an RRAM unit. The MOSFET is connected to the RRAM unit to form a 1T1R unit; multiple 1T1R units are connected in parallel to form a 1T1R array; the other 1T unit is a MOSFET, one end of which is connected to the SL terminal of the 1T1R unit, and the other end is connected to a high-level voltage V. HI By connecting the resistors R of the N MOS transistors in another 1T unit in parallel, R is formed. N This structure, consisting of a 1T1R array and another 1T cell, is called a pseudo-1T1R RRAM array structure. This structure can effectively reduce the array area and fully utilize array resources while implementing a voltage divider RRAM array, and simultaneously introduces a gate voltage sensing scheme to reduce read interference.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a voltage divider type RRAM (Resistive Random Access Memory) array structure. Background Technology

[0002] With the rapid development of the information age, storage technology is constantly being updated, and flash memory based on traditional semiconductor processes has encountered bottlenecks. Memristors, with their advantages of non-volatility, low power consumption, and compatibility with CMOS processes, have enormous potential in non-volatile memories, large-scale integrated circuits, and artificial neural networks. In artificial neural network applications, vector-matrix multiplication is the core of AI operations, and RRAM arrays can complete this operation in one step. Binary neural networks, due to their simple structure, exhibit good performance under limited memory conditions; however, because the resistance of RRAM itself is all greater than zero, it cannot effectively binarize the weights.

[0003] The existing solution is to use a pair of RRAM cells to represent one weight. However, using a pair of RRAM cells to represent one weight does not fully utilize array resources to some extent and increases the array area. Summary of the Invention

[0004] The purpose of this invention is to provide a voltage divider RRAM array structure that can effectively reduce the array area and make full use of array resources while implementing a voltage divider RRAM array, and at the same time introduce a gate voltage sensing scheme to reduce read interference.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] A voltage divider type RRAM array structure, the RRAM array structure including 1T1R cell and another 1T cell, wherein:

[0007] 1T refers to a MOSFET, and 1R refers to an RRAM cell. The MOSFET and the RRAM cell are connected to form a 1T1R cell.

[0008] Multiple 1T1R units are connected in parallel to form a 1T1R array. In this 1T1R array, the terminals of each MOS transistor are connected to form the SL terminal, and the terminals of each RRAM unit are connected to ground (GND), forming a parallel structure of the array. The gate terminal of each MOS transistor, i.e., WLs, serves as the input terminal.

[0009] The other 1T unit is a MOSFET. One end of the MOSFET is connected to the SL terminal of the 1T1R unit, and the other end is connected to a high-level voltage V. HI ;

[0010] The RRAM cells in the 1T1R unit have different configurations, where HRS represents the high-resistance state of the RRAM cell and LRS represents the low-resistance state of the RRAM cell. Specifically: HRS and the MOS transistor in another 1T unit form a positive weight; LRS and the MOS transistor in another 1T unit form a negative weight; and ground GND and power supply VDD are used as inputs applied to the gate terminal WLs of each MOS transistor.

[0011] By connecting the resistors R of the N MOS transistors in another 1T unit in parallel, R is formed. N This structure, consisting of a 1T1R array and another 1T unit, is called a pseudo-1T1R RRAM array structure.

[0012] The RRAM array structure, through voltage division between resistors, eliminates the need for a current-to-voltage conversion circuit during output readout. Instead, a voltage-type detection amplifier VSA directly reads the output result V from the SL terminal. OUT .

[0013] As can be seen from the technical solution provided by the present invention, the above structure can effectively reduce the array area and make full use of array resources while implementing a voltage divider RRAM array, and at the same time introduce a gate voltage sensing scheme to reduce read interference. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the structure of a voltage divider RRAM array provided in an embodiment of the present invention;

[0016] Figure 2 As described in the embodiments of the present invention, in N WL A schematic diagram showing the results of the multiplicative summation value (MACV) for different resistance values ​​of the MOSFET when the resistance is 9.

[0017] Figure 3 As described in this embodiment of the invention, the resistor of the MOSFET is fixed at R6, N WL V of MACV from 1 to 9 OUT A schematic diagram of the voltage distribution;

[0018] Figure 4 This is the sensing and control solution described in the embodiments of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments, and do not constitute a limitation of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0020] like Figure 1 The diagram shown is a schematic of a voltage divider RRAM array provided in an embodiment of the present invention. The RRAM array structure includes a 1T1R unit and another 1T unit (in the diagram, the MOS transistor is only used as a switch, and its equivalent resistance is taken as R), wherein:

[0021] 1T refers to a MOSFET, and 1R refers to an RRAM cell. The MOSFET and the RRAM cell are connected to form a 1T1R cell.

[0022] Multiple 1T1R units are connected in parallel to form a 1T1R array. In this 1T1R array, the terminals of each MOS transistor are connected to form the SL terminal, and the terminals of each RRAM unit are connected to ground (GND), forming a parallel structure of the array. The gate terminal of each MOS transistor, i.e., WLs, serves as the input terminal.

[0023] The other 1T unit is a MOSFET. One end of the MOSFET is connected to the SL terminal of the 1T1R unit, and the other end is connected to a high-level voltage V. HI ;

[0024] The RRAM cells in the 1T1R unit have different configurations, where HRS represents the high-resistance state of the RRAM cell and LRS represents the low-resistance state of the RRAM cell. The neural network, as a computational model, is composed of a large number of neurons directly interconnected. The connection strength between neurons is represented by weights, and the magnitude of the weights represents the probability. Specifically: HRS and the MOS transistor in another 1T unit form a positive weight (+1); LRS and the MOS transistor in another 1T unit form a negative weight (-1); ground GND (0) and power supply VDD (1) are used as inputs applied to the gate WLs of each MOS transistor.

[0025] By connecting the resistors R of the N MOS transistors in another 1T unit in parallel, R is formed. N This structure, consisting of a 1T1R array and another 1T unit, is called a pseudo-1T1R RRAM array structure.

[0026] The RRAM array structure, through voltage division between resistors, eliminates the need for a current-to-voltage conversion circuit during output readout. The output result V can be directly read from the SL terminal using a voltage-type detection amplifier VSA. OUT .

[0027] like Figure 1 As shown, the MOSFET and RRAM serve as voltage divider units, corresponding to different multiplication and accumulation values ​​of the OUT terminal voltage of MACV, which is determined by the high level V. HI The voltage division process between GND and the output V determines the output result. OUT It is derived from the following formula:

[0028]

[0029] Among them, R NWL This refers to the parallel equivalent resistance of the RRAM cell when the gate terminals WL of N MOS transistors are turned on; R N This refers to the resistance value of N MOSFETs connected in parallel.

[0030] like Figure 2 The figure shown is an embodiment of the present invention described in N. WL A schematic diagram showing the results of the multiplication accumulation value MACV for different resistance values ​​of the MOSFET when N = 9. WL N refers to the number of gate terminals WL of the MOSFET that are turned on, where V HI Set to 1.2V, LRS = 10kΩ, HRS = 200kΩ, resistance ratio is 20;

[0031] When selecting a MOSFET as the voltage divider unit, the curve with the steepest slope near the bit count value (±1) is chosen. A steeper slope indicates a larger range of adjacent MACV results, allowing for better separation of the reference voltage of the analog-to-digital converter (ADC). Taking MOSFET strengths ranging from R1 to R10 as an example... Figure 2 Simulation curves were performed on MOSFETs of different strengths. Based on the simulation results, MOSFETs of corresponding strengths were selected as voltage dividers. For example, the MOSFET with the largest slope of the simulation curve can be selected. The equivalent resistance of this MOSFET is R.

[0032] like Figure 3 The figure shows the embodiment of the present invention where the MOSFET resistor is fixed at R6 (the slope of the simulation curve is the largest), N WL V of MACV from 1 to 9 OUT A schematic diagram of the voltage distribution, from Figure 3 It can be seen that when N WL The smaller the value, the more likely the output MACV will be greater than 0.6V, which may cause read interference.

[0033] like Figure 4 The diagram illustrates the sensing control solution described in an embodiment of the present invention. During the calculation process using the RRAM array structure:

[0034] When the input DIN is sent to the gate control (WL Drive) of the MOS transistor to enable the 1T1R array to perform parallel multiplication and accumulation (MAC) operation, the input DIN is simultaneously sent to the counter circuit (1'S Counter).

[0035] The counter circuit will generate different N values ​​based on the number of high-level inputs in DIN. WL N WL N refers to the number of gate terminals (WL) of the MOSFET that are turned on. WL It will be transmitted to the gate voltage control circuit (i.e., V). WL Controller);

[0036] The gate voltage control circuit will be based on N WL Different gate voltage signals are generated, and these gate voltage signals are transmitted to the gate terminal of another 1T cell; through N WL The resistance R of another 1T unit MOSFET is changed differently (the resistance is different depending on the gate voltage of the MOSFET), so that the value of resistance R is the same as that of N. WL Size-related;

[0037] In another 1T cell, the resistance R of the MOSFET satisfies the following condition:

[0038] The output results all showed good performance.

[0039] It is worth noting that the contents not described in detail in the embodiments of the present invention belong to the prior art known to those skilled in the art.

[0040] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims. The information disclosed in the background section is intended only to enhance the understanding of the overall background technology of the present invention and should not be construed as an admission or implication in any way that such information constitutes prior art known to those skilled in the art.

Claims

1. A voltage divider type RRAM array structure, characterized in that, The RRAM array structure includes a 1T1R cell and another 1T cell, wherein: 1T refers to a MOSFET, and 1R refers to an RRAM cell. The MOSFET and the RRAM cell are connected to form a 1T1R cell. Multiple 1T1R units are connected in parallel to form a 1T1R array. In this 1T1R array, the terminals of each MOS transistor are connected to form the SL terminal, and the terminals of each RRAM unit are connected to ground (GND), forming a parallel structure of the array. The gate terminal of each MOS transistor, i.e., WLs, serves as the input terminal. The other 1T unit is a MOSFET. One end of the MOSFET is connected to the SL terminal of the 1T1R unit, and the other end is connected to a high-level voltage V. HI ; The RRAM cells in the 1T1R unit have different configurations, where HRS represents the high-resistance state of the RRAM cell and LRS represents the low-resistance state of the RRAM cell. Specifically: HRS and the MOS transistor in another 1T unit form a positive weight; LRS and the MOS transistor in another 1T unit form a negative weight; and ground GND and power supply VDD are used as inputs applied to the gate terminal WLs of each MOS transistor. By connecting the resistors R of multiple MOSFETs from another 1T unit in parallel, R is formed. N This structure, consisting of a 1T1R array and multiple other 1T units, is called a pseudo-1T1R RRAM array structure. The RRAM array structure, through voltage division between resistors, eliminates the need for a current-to-voltage conversion circuit during output readout. Instead, a voltage-type detection amplifier VSA directly reads the output result V from the SL terminal. OUT .

2. The voltage divider RRAM array structure according to claim 1, characterized in that, In the RRAM array structure: Another 1T unit uses a MOS transistor and an RRAM unit as a voltage divider, corresponding to the OUT terminal voltage of MACV for different multiplication and accumulation values, controlled by a high level V. HI The voltage division process between GND and the output V determines the output result. OUT It is derived from the following formula: ； Among them, R NWL This refers to the parallel equivalent resistance of the RRAM cells when the gate terminals WLs of the N MOS transistors in the 1T1R array are turned on; R N This refers to the resistance value of the N MOS transistors connected in parallel in a 1T1R array.

3. The voltage divider RRAM array structure according to claim 2, characterized in that, In the process of selecting another 1T unit MOSFET as the voltage divider unit, simulation curves were performed on MOSFETs of different strengths, and the MOSFET of the corresponding strength was selected as the voltage divider based on the simulation results. Specifically, select the MOSFET with the largest slope of the simulation curve corresponding to the strength, and the equivalent resistance of the MOSFET is R.

4. The voltage divider RRAM array structure according to claim 1, characterized in that, During the calculation process using the aforementioned RRAM array structure: When the input DIN is sent to the gate terminal of the MOS transistor of another 1T cell to control the 1T1R array to perform parallel multiplication and accumulation MAC operation, the input DIN is simultaneously sent to the counter circuit. The counter circuit will generate different N values ​​based on the number of high-level inputs in DIN. WL N WL N refers to the number N of the gate terminals WLs of the MOSFET that are turned on. WL It will be transmitted to the gate voltage control circuit; The gate voltage control circuit is based on N WL Different gate voltage signals are generated and transmitted to the gate terminal of another 1T cell, via N. WL The resistance R of the MOS transistor in another 1T cell is changed differently, so that the value of resistance R is the same as that of N. WL Size-related; In another 1T cell, the resistance R of the MOSFET satisfies the following condition: 。

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