Power mode control in multi-memory devices

Abstract

This application is directed to power mode control in multi-memory devices. An apparatus can include a non-volatile memory and a volatile memory. The apparatus can operate the volatile memory in a first power mode and the non-volatile memory in a second power mode. The apparatus can transition the volatile memory from the first power mode to a third power mode based on a power mode command from a host device. The apparatus can transition the non-volatile memory from the second power mode to a fourth power mode that consumes less power than the second power mode, and independent of the command from the host device, based on a number of queued commands for the non-volatile memory being less than a threshold number.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 585,298, filed January 26, 2022, entitled "Power Mode Control in a Multi-Memory Device," filed by Song et al., and U.S. Provisional Patent Application No. 63 / 181,065, filed April 28, 2021, entitled "Power Mode Control in a Multi-Memory Device," both of which are assigned to this assignee and are expressly incorporated herein by reference in their entirety. Technical Field

[0003] The technical field relates to power mode control in multi-memory devices. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, often represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write states into the memory device or program states.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, and chalcogenide memory technology. Memory cells can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logic state for a long time, even without external power. Volatile memory devices (such as DRAM) may lose their stored state when disconnected from external power. Summary of the Invention

[0006] Describe a device. The device may include non-volatile memory; volatile memory configured to serve as a cache for the non-volatile memory; and an interface controller coupled to the non-volatile memory and the volatile memory. The interface controller may be operable such that the device performs the following operations: determining whether the number of queued commands for the non-volatile memory is less than a threshold number, wherein the number of queued commands includes pending commands for the non-volatile memory and commands sent to the non-volatile memory; and, at least in part based on the determination that the number of queued commands for the non-volatile memory is less than the threshold number, switching the non-volatile memory from a first power mode to a second power mode that consumes less power compared to the first power mode.

[0007] Describe a device. The device may include non-volatile memory; volatile memory configured to serve as a cache for the non-volatile memory; and an interface controller coupled to the non-volatile memory and the volatile memory. The interface controller may be operable such that the device performs the following operations: operating the volatile memory in a first power mode and operating the non-volatile memory in a second power mode; switching the volatile memory from the first power mode to a third power mode based at least in part on a command from a host device, the command indicating the third power mode; and switching the non-volatile memory from the second power mode to a fourth power mode that consumes less power compared to the second power mode, independent of the command from the host device and based at least in part on the number of queued commands for the non-volatile memory being less than a threshold number.

[0008] A method performed by a memory device is described. The method may include operating volatile memory in a first power mode and operating non-volatile memory in a second power mode; switching the volatile memory from the first power mode to a third power mode based at least in part on a command from a host device coupled to the memory device, the command indicating the third power mode; and switching the non-volatile memory from the second power mode to a fourth power mode that consumes less power compared to the second power mode, independent of the command from the host device and based at least in part on a queued number of commands for the non-volatile memory being less than a threshold number. Attached Figure Description

[0009] Figure 1 This document describes examples of systems that support power mode control in multi-memory devices, based on the examples disclosed herein.

[0010] Figure 2This document describes an example of a memory subsystem that supports power mode control in a multi-memory device, based on the examples disclosed herein.

[0011] Figure 3 This document describes examples of devices that support power mode control in multi-memory devices, based on the examples disclosed herein.

[0012] Figure 4 This document describes an example of a process flow that supports power mode control in a multi-memory device, based on the examples disclosed herein.

[0013] Figure 5 A block diagram of a memory device supporting power mode control in a multi-memory device, according to an example disclosed herein, is shown.

[0014] Figure 6 and 7 A flowchart illustrating one or more methods for supporting power mode control in a multi-memory device according to the examples disclosed herein is shown. Detailed Implementation

[0015] For example, an electronic device may include non-volatile memory (e.g., main memory for storing information during other operations) and volatile memory (e.g., secondary memory) that can be used as a cache for non-volatile memory. This configuration allows the device to benefit from the advantages of non-volatile memory (e.g., non-volatile persistent storage, high storage capacity, low power consumption) while maintaining compatibility with the host device and other aspects through volatile memory. In some instances, volatile and non-volatile memory may support different power modes that provide different levels of functionality, consume different amounts of power, or have different exit latency, and other differences. The host device can control the volatile and non-volatile memory's respective power modes holistically by issuing commands to the device to operate the volatile and non-volatile memory in the same specific power mode. However, operating volatile and non-volatile memory in the same specific power mode can waste power (e.g., when the memory has different business or access expectations) and has other disadvantages.

[0016] According to the techniques described herein, a device can save power and other advantages by selecting the power mode of a first memory, such as non-volatile memory, in a manner independent of the power mode of a second memory, such as volatile memory, and vice versa. For example, the device can select the power mode of volatile memory based on or in response to one or more power mode commands from a host device, and can select the power mode of non-volatile memory based on or in response to the number of commands queued for non-volatile memory, among other factors or instances. In some instances, if the number of queued commands is less than a threshold number (e.g., zero, a value less than the threshold number), the device can change the power mode of non-volatile memory from a relatively high power mode to a lower power mode. In some instances, after detecting the presence of a queued command for non-volatile memory (or after detecting a threshold number of queued commands), the device can immediately switch the non-volatile memory from a lower power mode to a relatively high power mode. Therefore, the power mode of non-volatile memory can be controlled independently of the power mode of volatile memory, which allows the device to save power and operate more dynamically, among other advantages.

[0017] First, as referenced Figure 1 and 2 The features of this disclosure are described in the context of the system and memory subsystem described herein. (See references...) Figure 3 The described apparatus and as referenced Figure 4 and 5 The features of this disclosure are described in the context of the described process flow. (This is achieved through references to...) Figure 6 and 7 The device diagrams and flowcharts of the dynamic intermediate result scratchpad for the cache described herein further illustrate and describe these and other features of this disclosure with reference to the device diagrams and flowcharts.

[0018] Figure 1This document describes an example of a system 100 supporting power mode control in a multi-memory device, based on the examples disclosed herein. System 100 may be contained in an electronic device, such as a computer or telephone. System 100 may include a host device 105 and a memory subsystem 110. Host device 105 may be a processor or system-on-a-chip (SoC) that interfaces with interface controller 115, as well as other components of the electronic device containing system 100. Memory subsystem 110 may store electronic information (e.g., digital information, data) for host device 105 and provide access to said electronic information. Memory subsystem 110 may include interface controller 115, volatile memory 120, and non-volatile memory 125. In some instances, interface controller 115, volatile memory 120, and non-volatile memory 125 may be contained in the same physical package, such as package 130. However, interface controller 115, volatile memory 120, and non-volatile memory 125 may be disposed on different corresponding dies (e.g., silicon dies).

[0019] The devices in system 100 can be coupled via various wires (e.g., traces, printed circuit board (PCB) wiring, redistribution layer (RDL) wiring) that enable the transmission of information (e.g., commands, addresses, data) between the devices. These wires can form channels, data buses, command buses, address buses, etc.

[0020] The memory subsystem 110 can be configured to provide the benefits of non-volatile memory 125 while maintaining compatibility with host device 105 that supports protocols for different types of memory, such as volatile memory 120, and other instances. For example, non-volatile memory 125 can provide (e.g., relative to volatile memory 120) benefits such as non-volatility, higher capacity, or lower power consumption. However, host device 105 may be configured incompatible with or inefficiently configured with various aspects of non-volatile memory 125. For example, host device 105 may support voltages, access latency, protocols, page sizes, etc., that are incompatible with non-volatile memory 125. To compensate for the incompatibility between host device 105 and non-volatile memory 125, memory subsystem 110 can be configured to have volatile memory 120 that is compatible with host device 105 and acts as a cache for non-volatile memory 125. Therefore, host device 105 can use the protocols supported by volatile memory 120 while also benefiting from the advantages of non-volatile memory 125.

[0021] In some instances, system 100 may be contained in, or coupled to, a computing device, electronic device, mobile computing device, or wireless device. The device may be a portable electronic device. For example, the device may be a computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, etc. In some instances, the device may be configured for bidirectional wireless communication via a base station or access point. In some instances, the device associated with system 100 may be capable of machine-type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication. In some instances, the device associated with system 100 may be referred to as a user equipment (UE), station (STA), mobile terminal, etc.

[0022] Host device 105 may be configured to interface with memory subsystem 110 using a first protocol (e.g., Low Power Double Data Rate (LPDDR)) supported by interface controller 115. Therefore, in some instances, host device 105 may interface directly with interface controller 115 and indirectly with non-volatile memory 125 and volatile memory 120. In alternative instances, host device 105 may interface directly with non-volatile memory 125 and volatile memory 120. Host device 105 may also interface with other components of the electronic device comprising system 100. Host device 105 may be or include a SoC, a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations of these types of components. In some instances, host device 105 may be referred to as a host.

[0023] Interface controller 115 can be configured (e.g., based on or in response to one or more commands or requests issued by host device 105) to interface with volatile memory 120 and non-volatile memory 125 on behalf of host device 105. For example, interface controller 115 can facilitate the retrieval and storage of data in volatile memory 120 and non-volatile memory 125 on behalf of host device 105. Therefore, interface controller 115 can facilitate data transfer between various sub-components, such as data transfer between at least some of host device 105, volatile memory 120, or non-volatile memory 125. Interface controller 115 can interface with host device 105 and volatile memory 120 using a first protocol, and can interface with non-volatile memory 125 using a second protocol supported by non-volatile memory 125.

[0024] Non-volatile memory 125 may be configured to store digital information (e.g., data) for use in electronic devices including system 100. Therefore, non-volatile memory 125 may include one or more memory cell arrays and a local memory controller configured to operate the memory cell arrays. In some instances, the memory cells may be or include FeRAM cells (e.g., non-volatile memory 125 may be FeRAM). Non-volatile memory 125 may be configured to interface with interface controller 115 using a second protocol different from the first protocol used between interface controller 115 and host device 105. In some instances, non-volatile memory 125 may have a longer access operation latency than volatile memory 120. For example, retrieving data from non-volatile memory 125 may take longer than retrieving data from volatile memory 120. Similarly, writing data to non-volatile memory 125 may take longer than writing data to volatile memory 120. In some instances, as described herein, non-volatile memory 125 may have a smaller page size than volatile memory 120.

[0025] Volatile memory 120 may be configured to serve as a cache for one or more components (e.g., non-volatile memory 125). For example, volatile memory 120 may store information (e.g., data) for use in an electronic device containing system 100. Therefore, volatile memory 120 may include one or more memory cell arrays and a local memory controller configured to operate the memory cell arrays. In some instances, the memory cells may be or include DRAM cells (e.g., the volatile memory may be DRAM). Non-volatile memory 125 may be configured to interface with interface controller 115 using a first protocol used between interface controller 115 and host device 105.

[0026] In some instances, volatile memory 120 may have shorter access operation latency than non-volatile memory 125. For example, retrieving data from volatile memory 120 may take less time compared to retrieving data from non-volatile memory 125. Similarly, writing data to volatile memory 120 may take less time than writing data to non-volatile memory 125. In some instances, volatile memory 120 may have a larger page size than non-volatile memory 125. For example, the page size of volatile memory 120 may be 2 kilobytes (2kB) and the page size of non-volatile memory 125 may be 64 bytes (64B) or 128 bytes (128B).

[0027] While non-volatile memory 125 may be a higher-density memory than volatile memory 120, accessing non-volatile memory 125 may take longer than accessing volatile memory 120 (e.g., due to different architectures and protocols, and other reasons). Therefore, using volatile memory 120 as a cache can reduce latency in system 100. As an example, by retrieving data from volatile memory 120 instead of from non-volatile memory 125, access requests for data from host device 105 can be satisfied relatively quickly. To facilitate the operation of volatile memory 120 as a cache, interface controller 115 may include multiple buffers 135. Buffers 135 may be located on the same die as interface controller 115 and may be configured to temporarily store data for transfer between volatile memory 120, non-volatile memory 125, or host device 105 (or any combination thereof) during one or more access operations (e.g., store and retrieve operations).

[0028] Access operations, also referred to as access procedures or access routines, may involve one or more sub-operations performed by one or more components of the memory subsystem 110. Examples of access operations may include: a store operation in which data provided by the host device 105 is stored (e.g., written to) volatile memory 120 or non-volatile memory 125 (or both); and a retrieval operation in which data requested by the host device 105 is obtained (e.g., read) from volatile memory 120 or non-volatile memory 125 and returned to the host device 105.

[0029] To store data in memory subsystem 110, host device 105 can initiate a storage operation (or “stored procedure”) by sending a storage command (also referred to as a storage request, write command, or write request) to interface controller 115. The storage command can target a set of non-volatile memory cells in non-volatile memory 125. In some instances, the set of memory cells may also be referred to as a portion of memory. Host device 105 can also provide data to be written to the set of non-volatile memory cells to interface controller 115. Interface controller 115 can temporarily store the data in buffer 135-a. After storing the data in buffer 135-a, interface controller 115 can transfer the data from buffer 135-a to volatile memory 120 or non-volatile memory 125, or both. In write-through mode, interface controller 115 can transfer data to both volatile memory 120 and non-volatile memory 125. In write-back mode, the interface controller 115 may transfer data only to the volatile memory 120 (wherein data is transferred to the non-volatile memory 125 during a later eviction process).

[0030] In any mode, interface controller 115 can identify an appropriate set of one or more volatile memory cells in volatile memory 120 for storing data associated with a store command. To this end, interface controller 115 can implement set-association mapping, where each set of one or more non-volatile memory cells in non-volatile memory 125 can be mapped to multiple sets (e.g., rows) of volatile memory cells in volatile memory 120. For example, interface controller 115 can implement an n-way associative mapping, which allows data from a set of non-volatile memory cells to be stored in one of n sets of volatile memory cells in volatile memory 120. Therefore, interface controller 115 can manage volatile memory 120 as a cache for non-volatile memory 125 by referencing n sets of volatile memory cells associated with a target set of non-volatile memory cells. As used herein, unless otherwise described or mentioned, a “set” of objects can refer to one or more objects. Although the reference set associative mapping is described, the interface controller 115 can manage the volatile memory 120 as a cache by implementing one or more other types of mapping (such as direct mapping or associative mapping, and other instances).

[0031] After determining which n volatile memory cell sets are associated with the target non-volatile memory cell set, the interface controller 115 can store the data in one or more of the n volatile memory cell sets. Therefore, by retrieving data from the lower-latency volatile memory 120 instead of the higher-latency non-volatile memory 125, subsequent retrieval commands for data from the host device 105 can be efficiently satisfied. The interface controller 115 can determine which of the n sets of volatile memory 120 to store data based on or in response to one or more parameters associated with the data stored in the n sets of volatile memory 120 (such as data validity, newness, or modification status). Therefore, storage commands from the host device 105 can be satisfied fully (e.g., in write-back mode) or partially (e.g., in write-through mode) by storing the data in the volatile memory 120. In order to track data stored in volatile memory 120, interface controller 115 can store tag addresses for one or more sets of volatile memory cells (e.g., each set of volatile memory cells), the tag addresses indicating to non-volatile memory cells data stored in a given set of volatile memory cells.

[0032] To retrieve data from memory subsystem 110, host device 105 can initiate a retrieval operation (also referred to as a retrieval process) by sending a retrieval command (also referred to as a retrieval request, read command, or read request) to interface controller 115. The retrieval command can target one or more sets of non-volatile memory cells in non-volatile memory 125. Upon receiving the retrieval command, interface controller 115 can examine the requested data in volatile memory 120. For example, interface controller 115 can examine the requested data in n sets of volatile memory cells associated with the target set of non-volatile memory cells. If the requested data is stored in one of the n sets of volatile memory cells (e.g., data is stored for the target set of non-volatile memory cells), then interface controller 115 can transfer the data from volatile memory 120 to buffer 135-a (e.g., in response to determining that the requested data is stored in one of the n sets of volatile memory cells, such as...). Figure 4 and 5 (as described in the text) enables it to be transmitted to the host device 105.

[0033] Generally, the term "hit" can be used to refer to a scenario where volatile memory 120 stores data targeted by host device 105. If a set of n sets of one or more volatile memory cells does not store the requested data (e.g., the set of n volatile memory cells stores data for a non-volatile memory cell set other than the target non-volatile memory cell set), then interface controller 115 may transfer the requested data from non-volatile memory 125 to buffer 135-a (e.g., in response to determining that the set of n volatile memory cells does not store the requested data, as referenced). Figure 4 and 5 (as described) so that it can be transmitted to host device 105. Generally, the term "miss" can be used to refer to a situation in which the volatile memory 120 does not store data that has been targeted by host device 105.

[0034] More specifically, a write hit may refer to a situation in which data in volatile memory 120 is associated with a non-volatile memory address targeted by a write command from the host device (e.g., matching data stored at a non-volatile memory address targeted by a write command from the host device); while a write miss may refer to a situation in which no data associated with a non-volatile memory address exists in volatile memory 120.

[0035] In a miss scenario, after transferring the requested data to buffer 135-a, interface controller 115 may transfer the requested data from buffer 135-a to volatile memory 120, so that subsequent read requests for the data can be satisfied through volatile memory 120 instead of non-volatile memory 125. For example, interface controller 115 may store data in one of n sets of volatile memory cells associated with a target set of non-volatile memory cells. However, the n sets of volatile memory cells may already be storing data for other sets of non-volatile memory cells. Therefore, to retain this other data, interface controller 115 may transfer the other data to buffer 135-b so that the data can be transferred to non-volatile memory 125 for storage. This process can be called "eviction," and the data transferred from volatile memory 120 to buffer 135-b can be called "victimized" data. In some cases, interface controller 115 may transfer a subset of the victimized data from buffer 135-b to non-volatile memory 125. For example, interface controller 115 can transmit one or more subsets of compromised data that have changed since the data was initially stored in non-volatile memory 125. Data that is inconsistent between volatile memory 120 and non-volatile memory 125 (e.g., due to an update in one memory but not in another) can in some cases be referred to as "modified" or "dirty" data. In some instances (e.g., when the interface controller is operating in a mode such as write-back mode), dirty data can be data that exists in volatile memory 120 but not in non-volatile memory 125.

[0036] Therefore, if volatile memory 120 is full, interface controller 115 can execute an eviction procedure to save data from volatile memory 120 to non-volatile memory 125 (e.g., to make room for new data in volatile memory 120). In some instances, interface controller 115 can execute a "filling" procedure in which data from non-volatile memory 125 is saved to volatile memory 120. Interface controller 115 can execute a filling procedure in the event of a miss (e.g., filling volatile memory 120 with relevant data). For example, in the event of a read miss when a read command from host device 105 targets data that is not present in volatile memory 120, interface controller 115 can retrieve the data requested by the read command and, in addition to returning the data to the host device, also store the data in volatile memory 120 (e.g., so that the data can be quickly retrieved in the future).

[0037] Therefore, the memory subsystem 110 may satisfy (or “fulfill”) the request using volatile memory 120 or non-volatile memory 125, depending on the hit or miss status of the request (e.g., a read command, a write command) from the host device 105. For example, in the case of a read miss, non-volatile memory 125 may satisfy the read command from the host device 105, meaning that the data returned from the host device 105 may originate from non-volatile memory 125. And in the case of a read hit, volatile memory 120 may satisfy the read command from the host device 105, meaning that the data returned from the host device 105 may originate from volatile memory 120. In some instances, the hit-to-miss ratio (“hit-miss ratio”) may be relatively high (e.g., the hit percentage may be approximately 85%, and the miss percentage may be approximately 15%).

[0038] Volatile memory 120 and non-volatile memory 125 may support different power modes, which provide different levels of functionality, consume different amounts of power, or have different exit delays, and other differences. For example, volatile memory 120 may support an active mode, during which volatile memory 120 executes commands in response to functional commands from host device 105. Active mode consumes the most power compared to other power modes of volatile memory 120. Volatile memory 120 may also support one or more standby (or "idle") modes, during which volatile memory 120 is partially powered down and awaits commands from host device 105. Standby mode consumes moderate power compared to other power modes of volatile memory 120. In addition, volatile memory 120 may support a low-power mode (or "deep sleep" mode), during which volatile memory 120 is mostly or completely powered down. The low-power mode consumes the least power compared to other power modes of the volatile memory 120. The non-volatile memory 125 can support similar power modes that can be adjusted as needed. Other power modes for both volatile and non-volatile memory 125 are also covered.

[0039] In some instances, using different techniques, host device 105 can control the power modes of volatile memory 120 and non-volatile memory 125 holistically based on host device 105's service or access expectations. For example, if host device 105 does not expect to access memory subsystem 110 for a threshold duration, host device 105 can instruct memory subsystem 110 to operate both volatile memory 120 and non-volatile memory 125 in a low-power mode to save power. However, in situations where non-volatile memory 125 is ready to enter low-power mode before host device 105 recognizes a service or access interruption, using different techniques that depend on host device 105 to switch non-volatile memory 125 to low-power mode can waste power. In other words, using different techniques to control the power mode of memory holistically and solely based on host device 105's service or access expectations can cause non-volatile memory 125 to switch to low-power mode too late, resulting in unnecessary power consumption.

[0040] As another example, when host device 105 expects immediate access to memory, using different techniques, host device 105 may instruct memory subsystem 110 to operate volatile memory 120 and non-volatile memory 125 in standby mode, enabling the memory to quickly provide access immediately after receiving a functional command (e.g., activation command, precharge command, read command, write command) from host device 105. However, in scenarios where non-volatile memory 125 is not accessed for a period of time (e.g., because standby mode consumes more power than other modes supported by the memory, such as low-power modes), relying on host device 105 to use different techniques to switch non-volatile memory 125 to standby mode can waste power. In other words, using different techniques to control the power mode of memory holistically and solely based on the service or access expectations of host device 105 can cause non-volatile memory 125 to prematurely transition from a lower-power mode to standby mode, resulting in unnecessary power consumption. In systems with a high hit-miss ratio, the described power consumption problem may be particularly exacerbated.

[0041] In contrast, according to the described technique, memory subsystem 110 can reduce power consumption by controlling the power modes of the memory in a manner independent of each other. To ensure that volatile memory 120 can provide access in the manner expected by host device 105, memory subsystem 110 can control the power mode of the first memory (e.g., volatile memory 120) based on (e.g., in response to) a power mode command from host device 105. A power mode command can refer to a command indicating the power mode to be used. To prevent a second memory, such as non-volatile memory 125, from entering a power mode too late or too early, memory subsystem 110 can control the power mode of the second memory, such as non-volatile memory 125, based on or in response to the presence or absence of a queuing command for the second memory, such as non-volatile memory 125 (and independent of the power mode of the first memory, such as volatile memory 120), and other factors. For example, a second memory, such as non-volatile memory 125, may transition to a low-power mode without any commands queued for it, and may transition to a standby mode (or other higher-power mode) with one or more commands queued for it. Although described as different types of memory, in some instances, the first and second memories may be the same type of memory (e.g., both may be volatile or both may be non-volatile).

[0042] System 100 may include any number of non-transitory computer-readable media supporting power mode control as described herein. For example, host device 105, interface controller 115, volatile memory 120, or non-volatile memory 125 may include or otherwise access one or more non-transitory computer-readable media storing instructions (e.g., firmware) for performing the functions described herein that pertain to host device 105, interface controller 115, volatile memory 120, or non-volatile memory 125. For example, such instructions, when executed by host device 105 (e.g., host device controller), interface controller 115, volatile memory 120 (e.g., local controller), or non-volatile memory 125 (e.g., local controller), may cause host device 105, interface controller 115, volatile memory 120, or non-volatile memory 125 to perform the associated functions described herein.

[0043] Figure 2 This document describes an example of a memory subsystem 200 supporting power-mode control in a multi-memory device, based on the examples disclosed herein. The memory subsystem 200 may be used as a reference. Figure 1 An example of the described memory subsystem 110. Therefore, the memory subsystem 200 can be compared with, as in the reference... Figure 1 The host device interaction is described. The memory subsystem 200 may include an interface controller 202, volatile memory 204, and non-volatile memory 206, which may be as described in reference... Figure 1 The described interface controller 115, volatile memory 120, and non-volatile memory 125 are examples. Therefore, the interface controller 202 can represent, as referenced... Figure 1 The described host device interfaces with volatile memory 204 and non-volatile memory 206. For example, the interface controller 202 can use volatile memory 204 as a cache for non-volatile memory 206. Using volatile memory 204 as a cache allows the subsystem to provide the benefits of non-volatile memory 206 (e.g., non-volatile, high-density storage) while maintaining compatibility with host devices that support protocols different from those of non-volatile memory 206.

[0044] exist Figure 2 In this diagram, dashed lines between components represent data flows or data transmission paths, while solid lines between components represent command flows or command transmission paths. In some cases, the memory subsystem 200 is one of several similar or identical subsystems that may be included in an electronic device. In some instances, each subsystem may be referred to as a slice and may be associated with a corresponding channel of the host device.

[0045] Non-volatile memory 206 can be configured to be used as main memory for a host device (e.g., memory for long-term data storage). In some cases, non-volatile memory 206 may comprise one or more arrays of FeRAM cells. Each FeRAM cell may include a select element and a ferroelectric capacitor and can be accessed by applying appropriate voltages to one or more access lines, such as word lines, board lines, and digital lines. In some instances, a subset of FeRAM cells coupled to an active word line may be sensed, for example, in parallel or simultaneously, without having to sense all FeRAM cells coupled to an active word line. Therefore, the page size of the FeRAM array may be different from (e.g., smaller than) the DRAM page size. In the context of a memory device, a page may refer to a row of memory cells (e.g., a group of memory cells with a common row address), and the page size may refer to the number of memory cells or column addresses in a row, or the number of column addresses accessed during an access operation. Alternatively, the page size may refer to the size of data handled by various interfaces, or the amount of data that a row can store. In some cases, different memory device types may have different page sizes. For example, a DRAM page size (e.g., 2kB) can be a superset of a non-volatile memory (e.g., FeRAM) page size (e.g., 64B).

[0046] The smaller page size of FeRAM arrays offers various efficiency benefits because a single FeRAM cell may require more power to read or write compared to a single DRAM cell. For example, the smaller page size used for FeRAM arrays facilitates efficient energy use because a smaller number of FeRAM cells can be activated at minute intervals of associated changes in information. In some instances, depending on the nature of the data and commands utilizing FeRAM operations, the page size of the FeRAM cell array can, for example, change dynamically (e.g., during operation of the FeRAM cell array).

[0047] Although an individual FeRAM cell may require more power to read or write compared to an individual DRAM cell, a FeRAM cell can maintain its stored logic state for a longer period of time in the absence of an external power supply because the ferroelectric material in the FeRAM cell can maintain a non-zero polarization in the absence of an electric field. Therefore, including an FeRAM array in the non-volatile memory 206 can provide power and efficiency benefits relative to volatile memory cells (e.g., DRAM cells in volatile memory 204) because it reduces or eliminates the need to perform refresh operations.

[0048] Volatile memory 204 can be configured to function as a cache for non-volatile memory 206. In some cases, volatile memory 204 may comprise one or more arrays of DRAM cells. Each DRAM cell may include a capacitor containing dielectric material to store charge representing a programmable state. The memory cells of volatile memory 204 may be logically grouped or arranged into one or more memory groups (as referred to herein as “groups”). For example, volatile memory 204 may comprise sixteen groups. The memory cells of a group may be arranged in a grid or an array of intersecting columns and rows, and each memory cell can be accessed or refreshed by applying appropriate voltages to the digital lines (e.g., column lines) and word lines (e.g., row lines) for the memory cell. A row of a group may be referred to as a page, and the page size may refer to the number of columns or the number of memory cells in a row (and therefore, the amount of data that a row can store). As mentioned, the page size of volatile memory 204 may be different from (e.g., larger than) the page size of non-volatile memory 206.

[0049] Interface controller 202 may include various circuitry for interfacing (e.g., communicating) with other devices such as host devices, volatile memory 204, and non-volatile memory 206. For example, interface controller 202 may include a data (DA) bus interface 208, a command and address (C / A) bus interface 210, a data bus interface 212, a C / A bus interface 214, a data bus interface 216, and a C / A bus interface 264. The data bus interfaces may support the use of one or more communication protocols to transmit information. For example, data bus interface 208, C / A bus interface 210, data bus interface 216, and C / A bus interface 264 may support information transmitted using a first protocol (e.g., LPDDR signaling), while data bus interface 212 and C / A bus interface 214 may support information transmitted using a second protocol. Therefore, the various bus interfaces coupled to interface controller 202 may support different data volumes or data rates.

[0050] Data bus interface 208 can be coupled to data bus 260, transaction bus 222, and buffer circuitry 224. Data bus interface 208 can be configured to transmit and receive data on data bus 260 and to transmit and receive control information (e.g., acknowledge / negative acknowledge) or metadata on transaction bus 222. Data bus interface 208 can also be configured to transfer data between data bus 260 and buffer circuitry 224. Data bus 260 and transaction bus 222 can be coupled to interface controller 202 and host device, such that a conductive path is established between interface controller 202 and host device. In some instances, the pin of transaction bus 222 may be referred to as a Data Mask Inversion (DMI) pin. Although shown as having one data bus 260 and one transaction bus 222, any number of data buses 260 and any number of transaction buses 222 may be coupled to one or more data bus interfaces 208.

[0051] C / A bus interface 210 can be coupled to C / A bus 226 and decoder 228. C / A bus interface 210 can be configured to transmit and receive commands and addresses via C / A bus 226. Commands and addresses received via C / A bus 226 can be associated with data received or transmitted via data bus 260. C / A bus interface 210 can also be configured to transmit commands and addresses to decoder 228, such that decoder 228 can decode the commands and forward the decoded commands and associated addresses to command circuitry system 230.

[0052] Data bus interface 212 can be coupled to data bus 232 and memory interface circuitry 234. Data bus interface 212 can be configured to transmit and receive data on data bus 232, which can be coupled to non-volatile memory 206. Data bus interface 212 can also be configured to transfer data between data bus 232 and memory interface circuitry 234. C / A bus interface 214 can be coupled to C / A bus 236 and memory interface circuitry 234. C / A bus interface 214 can be configured to receive commands and addresses from memory interface circuitry 234 and forward commands and addresses on C / A bus 236 to non-volatile memory 206 (e.g., to a local controller of non-volatile memory 206). Commands and addresses transmitted via C / A bus 236 can be associated with data received or transmitted via data bus 232. The data bus 232 and the C / A bus 236 can be coupled to the interface controller 202 and the non-volatile memory 206 to establish a conductive path between the interface controller 202 and the non-volatile memory 206.

[0053] Data bus interface 216 may be coupled to data bus 238 (e.g., data bus 238-a, data bus 238-b) and memory interface circuitry 240. Data bus interface 216 may be configured to transmit and receive data via data bus 238, which may be coupled to volatile memory 204. Data bus interface 216 may also be configured to transfer data between data bus 238 and memory interface circuitry 240. C / A bus interface 264 may be coupled to C / A bus 242 and memory interface circuitry 240. C / A bus interface 264 may be configured to receive commands and addresses from memory interface circuitry 240 and forward commands and addresses on C / A bus 242 to non-volatile memory 204 (e.g., to a local controller of non-volatile memory 204). Commands and addresses transmitted via C / A bus 242 may be associated with data received or transmitted via data bus 238. The data bus 238 and the C / A bus 242 can be coupled to the interface controller 202 and the volatile memory 204 to establish a conductive path between the interface controller 202 and the volatile memory 204.

[0054] In addition to the bus and bus interface for communicating with the coupled device, the interface controller 202 may also include circuitry for using non-volatile memory 206 as main memory and volatile memory 204 as a cache. For example, the interface controller 202 may include command circuitry 230, buffer circuitry 224, cache management circuitry 244, one or more engines 246, and one or more schedulers 248.

[0055] Command circuitry system 230 may be coupled to buffer circuitry system 224, decoder 228, cache management circuitry system 244, scheduler 248, and other components. Command circuitry system 230 may be configured to receive command and address information from decoder 228 and store the command and address information in queue 250. Command circuitry system 230 may include logic 262 that processes command information (e.g., from a host device) and stores information from other components (e.g., cache management circuitry system 244, buffer circuitry system 224) and uses the information to generate one or more commands for scheduler 248. Command circuitry system 230 may also be configured to pass address information (e.g., address bits) to cache management circuitry system 244. In some instances, logic 262 may be circuitry configured to function as a finite state machine (FSM).

[0056] Buffer circuitry system 224 may be coupled to data bus interface 208, command circuitry system 230, memory interface circuitry system 234, and memory interface circuitry system 234. Buffer circuitry system 224 may include sets of one or more buffer circuits for at least some groups (if not every group) of volatile memory 204. Buffer circuitry system 224 may also include components for accessing the buffer circuits (e.g., a memory controller). In one example, volatile memory 204 may contain sixteen groups and buffer circuitry system 224 may contain sixteen sets of buffer circuits. Each set of buffer circuitry may be configured to store data from or for a corresponding group of volatile memory 204 (or both). As an example, the buffer circuit set for group 0 (BK0) can be configured to store data from the first group of volatile memory 204 or to store data for the first group of volatile memory 204 (or both), and the buffer circuit for group 15 (BK15) can be configured to store data from the sixteenth group of volatile memory 204 or to store data for the sixteenth group of volatile memory 204 (or both).

[0057] Each set of buffer circuits in buffer circuit system 224 may include a pair of buffers. The pair of buffers may include: one buffer (e.g., an Open Page Data (OPD) buffer) configured to store data targeted by an access command (e.g., a write command or read command) from the host device; and another buffer (e.g., a Victim Page Data (VPD) buffer) configured to store data for use in an eviction process triggered by an access command. For example, the set of buffer circuits for BK0 may include buffers 218 and 220, which may be instances of buffers 135-a and 135-b, respectively. Buffer 218 may be configured to store BK0 data targeted by an access command from the host device. And buffer 220 may be configured to store data transferred from BK0 as part of a eviction process triggered by an access command. Each buffer in the set of buffer circuits may be configured with a size (e.g., storage capacity) corresponding to the page size of volatile memory 204. For example, if the page size of volatile memory 204 is 2kB, then the size of each buffer can be 2kB. Therefore, in some instances, the size of the buffer can be equal to the page size of volatile memory 204.

[0058] Cache management circuitry system 244 may be coupled to command circuitry system 230, engine 246, scheduler 248, and other components. Cache management circuitry system 244 may include one or more sets of cache management circuitry for volatile memory (e.g., each set). As an example, cache management circuitry system 244 may include sixteen sets of cache management circuitry for BK0 through BK15. Each set of cache management circuitry may include two memory arrays configured to store storage information for volatile memory 204. As an example, the cache management circuitry set for BK0 may include memory array 252 (e.g., a cache DRAM (CDRAM) tag array (CDT-TA)) and memory array 254 (e.g., a CDRAM active (CDT-V) array), configured to store storage information for BK0. In some instances, the memory array may also be referred to as an array or buffer. In some cases, the memory array may be or contain volatile memory cells, such as static RAM (SRAM) cells.

[0059] Storage information (or “metadata”) may include content information, validity information, and / or dirty information (or any combination thereof) associated with volatile memory 204, as well as other instances. Content information (which may also be referred to as tag information or address information) indicates which data is stored in the set of volatile memory cells. For example, the content information (e.g., tag address) of a row in volatile memory 204 may indicate which set of one or more non-volatile memory cells currently contains data stored in that row. As mentioned, validity information may indicate whether the data stored in the set of volatile memory cells is actual data (e.g., data with an expected order or form) or placeholder data (e.g., random or dummy data without an expected or important order). Dirty information may indicate whether the data stored in the set of one or more volatile memory cells in volatile memory 204 differs from the corresponding data stored in the set of one or more non-volatile memory cells in non-volatile memory 206. For example, dirty information may indicate whether the data stored in the set of volatile memory cells has been updated relative to the data stored in non-volatile memory 206.

[0060] Memory array 252 may include memory cells that store storage information (e.g., tag information, validity information, dirty information) of an associated group (e.g., BK0) of volatile memory 204. Storage information may be stored on a row-by-row basis (e.g., each row of an associated non-volatile memory group may have corresponding storage information). Interface controller 202 can examine requested data in volatile memory 204 by referring to the storage information in memory array 252. For example, interface controller 202 may receive a retrieval command from a host device for data in a set of non-volatile memory cells in non-volatile memory 206. Interface controller 202 may use a set of one or more address bits (e.g., a set of row address bits) targeted by the access request to refer to the storage information in memory array 252. For example, using set-association mapping, interface controller 202 may refer to content information in memory array 252 to determine which set of volatile memory cells (if present) stores the requested data.

[0061] In addition to storing content information for the volatile memory cells, memory array 252 may also store validity information indicating whether data in the volatile memory cell set is actual data (also called valid data) or random data (also called invalid data). For example, volatile memory cells in volatile memory 204 may initially store random data and continue to do so until data is written to the volatile memory cell from a host device or non-volatile memory 206. To track which data is valid, memory array 252 may be configured to set a bit for each volatile memory cell set (e.g., row) when actual data is stored in that volatile memory cell set. This bit may be called a validity bit or validity flag. Like content information, validity information stored in memory array 252 may be stored on a row-by-row basis. Thus, in some instances, each validity bit may indicate the validity of data stored in the associated row.

[0062] In some instances, memory array 252 may store dirty information indicating whether a set of volatile memory cells (e.g., rows) stores any dirty data. Similar to validity information, the dirty information stored in memory array 252 may be stored on a row-by-row basis.

[0063] Memory array 254 may be similar to memory array 252 and may also include memory cells that store storage information for a group (e.g., BK0) of volatile memory 204 associated with memory array 252. For example, memory array 254 may store validity information and dirt information for the group of volatile memory 204. However, the storage information stored in memory array 254 may be stored on a sub-block basis rather than on a row-by-row basis. For example, validity information stored in the memory cells of memory array 254 may indicate the validity of data for a subset of volatile memory cells in a row of volatile memory 204.

[0064] As an example, validity information in memory array 254 can indicate the validity of each subset of data (e.g., 32B or 64B) stored in a row of BK0 in volatile memory 204. Similarly, dirty information stored in memory cells of memory array 254 can indicate which subset of volatile memory cells in a row of volatile memory 204 stores dirty data. For example, dirty information in memory array 254 can indicate the dirty state of each subset of data (e.g., 32B or 64B) stored in a row of BK0 in volatile memory 204. Storing storage information (e.g., tag information, validity information) on a row-by-row basis in memory array 252 allows interface controller 202 to determine whether data in volatile memory 204 has a hit or a miss. Storing storage information (e.g., validity information, dirty information) in memory array 254 on a sub-block basis allows interface controller 202 to determine which subsets of data are returned to the host device (e.g., during a retrieval process) and which subsets of data are retained in non-volatile memory 206 (e.g., during an eviction process).

[0065] Each cache management circuitry may also include a corresponding pair of registers coupled to command circuitry 230, engine 246, memory interface circuitry 234, memory interface circuitry 240, and the memory array for the cache management circuitry, as well as other components. For example, the cache management circuitry may include a first register (e.g., register 256, which may be an Open Page Tag (OPT) register) configured to receive storage information (e.g., tag information, validity information, dirty information, other information, or any combination of bits) from memory array 252 or scheduler 248-b, or both. The cache management circuitry may also include a second register (e.g., register 258, which may be a Victim Page Tag (VPT) register) configured to receive storage information (e.g., validity information and / or dirty information, or both) from memory array 254 and scheduler 248-a, or both. The information in registers 256 and 258 can be passed to command circuitry 230 and engine 246 to enable decisions to be made by these components. For example, the command circuitry 230 may issue a command to read non-volatile memory 206 or volatile memory 204 based on or in response to stored information in register 256 and / or register 258 or both.

[0066] Engine 246-a can be coupled to registers 256 and 258 and scheduler 248. Engine 246-a can be configured to receive stored information from various components and issue commands to scheduler 248 based on the stored information. For example, if interface controller 202 is in a first mode, such as write-through mode, then engine 246-a can issue commands to scheduler 248-b, and in response, scheduler 248-b initiates or facilitates data transfers from buffer 218 to both volatile memory 204 and non-volatile memory 206. Alternatively, if interface controller 202 is in a second mode, such as write-back mode, then engine 246-a can issue commands to scheduler 248-b, and in response, scheduler 248-b initiates or facilitates data transfers from buffer 218 to volatile memory 204. In the case of a write-back operation, the data stored in volatile memory 204 can eventually be transferred to non-volatile memory 206 during a subsequent (e.g., later) eviction process.

[0067] Engine 246-b may be coupled to register 258 and scheduler 248-a. Engine 246-b may be configured to receive stored information from register 258 and issue commands to scheduler 248-a based on the stored information. For example, engine 246-b may issue commands to scheduler 248-a to initiate or facilitate the transfer of dirty data from buffer 220 to non-volatile memory 206 (e.g., as part of a retrieval process). If buffer 220 holds a dataset (e.g., victim data) transferred from volatile memory 204, engine 246-b may indicate which one or more subsets (e.g., which 64Bs) of the dataset in buffer 220 should be transferred to non-volatile memory 206.

[0068] Scheduler 248-a may be coupled to various components of interface controller 202 and may facilitate access to non-volatile memory 206 by issuing commands to memory interface circuitry 234. Commands issued by scheduler 248-a may be based on commands from command circuitry 230, engine 246-a, engine 246-b, or a combination of these components. Similarly, scheduler 248-b may be coupled to various components of interface controller 202 and may facilitate access to volatile memory 204 by issuing commands to memory interface circuitry 240. Commands issued by scheduler 248-b may be based on or in response to commands from command circuitry 230 or engine 246-a, or both.

[0069] The memory interface circuitry 234 can communicate with the non-volatile memory 206 via one or more of the data bus interface 212 and the C / A bus interface 214. For example, the memory interface circuitry 234 can prompt the C / A bus interface 214 to forward commands issued by the memory interface circuitry 234 to a local controller in the non-volatile memory 206 on the C / A bus 236. Furthermore, the memory interface circuitry 234 can transmit data to or receive data from the non-volatile memory 206 via the data bus 232. In some instances, commands issued by the memory interface circuitry 234 may be supported by the non-volatile memory 206 rather than the non-volatile memory 204 (e.g., commands issued by the memory interface circuitry 234 may differ from commands issued by the memory interface circuitry 240).

[0070] Memory interface circuitry 240 can communicate with volatile memory 204 via one or more of data bus interface 216 and C / A bus interface 264. For example, memory interface circuitry 240 can prompt C / A bus interface 264 to forward commands issued by memory interface circuitry 240 on C / A bus 242 to the local controller of volatile memory 204. Furthermore, memory interface circuitry 240 can transmit data to or receive data from volatile memory 204 on one or more data buses 238. In some instances, commands issued by memory interface circuitry 240 may be supported by volatile memory 204 instead of non-volatile memory 206 (e.g., commands issued by memory interface circuitry 240 may differ from commands issued by memory interface circuitry 234).

[0071] In summary, the components of interface controller 202 can use non-volatile memory 206 as main memory and volatile memory 204 as a cache. This operation can be prompted by one or more access commands (e.g., read / retrieve command / request and write / store command / request) received from the host device.

[0072] In some instances, interface controller 202 may receive a storage command from the host device. The storage command may be received via C / A bus 226 and transmitted to command circuitry 230 via one or more of C / A bus interface 210 and decoder 228. The storage command may include or be accompanied by address bits targeting a memory address of non-volatile memory 206. Data to be stored may be received via data bus 260 and transmitted to buffer 218 via data bus interface 208. In write-through mode, interface controller 202 may transmit data to both non-volatile memory 206 and volatile memory 204. In write-back mode, in some instances, interface controller 202 may transmit data only to volatile memory 204.

[0073] In either mode, the interface controller 202 may first check whether the volatile memory 204 still has space available for storing data in its memory cells. To achieve this, the command circuitry 230 may refer to the memory array 252 (e.g., using a set of memory address bits) to determine whether one or more of the n sets (e.g., rows) of volatile memory cells associated with a memory address are empty (e.g., storing random or invalid data) or whether one or more of the n sets (e.g., rows) of volatile memory cells associated with a memory address are full (e.g., storing valid data). For example, the command circuitry 230 may determine whether one or more of the n sets (e.g., rows) of volatile memory cells are available (or unavailable) based on tag information and validity information stored in the memory array 252. In some cases, the set of volatile memory cells in the volatile memory 204 may be referred to as a line, cache line, or row.

[0074] If one of the n associated volatile memory cell sets is available for storing information, the interface controller 202 can transfer data from buffer 218 to volatile memory 204 for storage in said volatile memory cell set. However, if the associated volatile memory cell set is not empty, the interface controller 202 can initiate an eviction process to free up space for data in volatile memory 204. The eviction process may involve transferring compromised data from one of the n associated sets of volatile memory cells to buffer 220. Dirty information for the compromised data can be transferred from memory array 254 to register 258 for identification of a dirty subset of the compromised data. After the compromised data is stored in buffer 220, new data can be transferred from buffer 218 to volatile memory 204, and compromised data can be transferred from buffer 220 to non-volatile memory 206. In some cases, a dirty subset of old data can be transferred to non-volatile memory 206 and a clean subset (e.g., an unmodified subset) can be discarded. Engine 246-b can identify a dirty subset based on or in response to dirty information transferred from memory array 254 to register 258 during the eviction process.

[0075] In another example, interface controller 202 may receive commands, such as retrieval commands, from a host device. Retrieval commands may be received via C / A bus 226 and transmitted to command circuitry 230 via one or more of C / A bus interface 210 and decoder 228. The retrieval command may include address bits targeting a memory address of non-volatile memory 206. Before attempting to access the target memory address of non-volatile memory 206, interface controller 202 may perform a check to determine whether volatile memory 204 stores data. To achieve this, command circuitry 230 may reference memory array 252 (e.g., using a set of memory address bits) to determine whether one or more of n sets (e.g., rows) of volatile memory cells associated with the memory address store the requested data (e.g., whether one or more of the n sets of volatile memory cells associated with the memory address store the requested data or alternatively, not store the requested data). If the requested data is stored in volatile memory 204, the interface controller 202 can transfer the requested data to buffer 218 for transmission to the host device via data bus 260.

[0076] If the requested data is not stored in volatile memory 204 (e.g., the requested data may be stored in non-volatile memory 206 or another location), then interface controller 202 may retrieve the data from non-volatile memory 206 and transfer the data to buffer 218 for transmission to the host device via data bus 260. Alternatively, interface controller 202 may transfer the requested data from buffer 218 to volatile memory 204 for lower latency access during subsequent retrieval operations. However, before transferring the requested data, interface controller 202 may first determine whether one or more of the n associated sets of volatile memory cells are available to store the requested data (e.g., whether one or more of the n associated sets of volatile memory cells are empty or full). Interface controller 202 may determine the availability of the n associated volatile memory cell sets by communicating with the associated cache management circuitry. If the associated volatile memory cell sets are available, interface controller 202 may transfer the data in buffer 218 to volatile memory 204 without performing a eviction process. Otherwise, the interface controller 202 may transfer the data from the buffer 218 to the volatile memory 204 after the recovery process.

[0077] The memory subsystem 200 can be implemented in one or more configurations, including single-chip and multi-chip versions. The multi-chip version may include one or more components of the memory subsystem 200, including interface controller 202, volatile memory 204, and non-volatile memory 206 (and other components or combinations thereof), on a separate chip from the chip containing one or more other components of the memory subsystem 200. For example, in a multi-chip version, the respective separate chip may contain each of interface controller 202, volatile memory 204, and non-volatile memory 206. In contrast, the single-chip version may include interface controller 202, volatile memory 204, and non-volatile memory 206 on a single chip.

[0078] To ensure efficient power transitions between power modes, interface controller 202 can control the power mode of volatile memory 204 separately from the power mode of non-volatile memory 206. Because volatile memory 204 is expected to fulfill more commands than non-volatile memory 206 (given a high hit-miss ratio for memory subsystem 200), interface controller 202 can control the power mode of volatile memory 204 based on the host device's expectations (e.g., based on or in response to a power mode command from the host device). However, because the host device is unaware of non-volatile memory 206, interface controller 202 can control the power mode of non-volatile memory 206 based on or in response to its own access needs and other instances (e.g., based on or in response to the number of queued commands for non-volatile memory 206, and other factors).

[0079] Figure 3 This document describes an example of a system 300 supporting multi-memory power mode control, based on the examples disclosed herein. System 300 may include a host device 305 and a memory subsystem 310, and may be used as a reference. Figure 1 An example of the described system 100. The memory subsystem 310 may include an interface controller 315, volatile memory 320, and non-volatile memory 325, which may be coupled to each other via one or more transmit lines, buses, or both. The interface controller 315 may include a power mode controller 330 and one or more command buffers 335. As described herein, the interface controller 315 may control the power modes of the volatile memory 320 and non-volatile memory 325 in a manner independent of each other. For example, the interface controller 315 may control the power mode of the volatile memory 320 based on (e.g., in response to) a power mode command from the host device 305 and other factors, and control the power mode of the non-volatile memory 325 based on or in response to the number of commands queued for the non-volatile memory 325 in the buffers 335 and other factors.

[0080] Interface controller 315 may receive one or more commands from host device 305, including function (or "access") commands and power mode commands, as well as other commands. Function commands may refer to commands that cause access to memory, such as activation commands, precharge commands, read commands, write commands, etc. Power mode commands may refer to commands that indicate a power mode. Interface controller 315 may also issue one or more commands to volatile memory 320 and non-volatile memory 325, said one or more commands including function commands, power mode commands, and other commands. Interface controller 315 may include a power mode controller 330, a pending command (PC) buffer 335-a, a pending command buffer 335-b, and an issued command buffer 335-c, as well as other components.

[0081] The power mode controller 340 can be configured to manage the power mode of the volatile memory 320. The power mode controller 340 can change the power mode of the volatile memory 320 based on (e.g., in response to) a power mode command from the host device 305. For example, after receiving a power mode command from the host device 305, the power mode controller 340 can immediately switch the volatile memory 320 from one power mode to the power mode indicated by the power mode command (e.g., by sending a command or indication, such as a new power mode command, to the volatile memory 320 via the power mode controller 340).

[0082] The power mode controller 330 can be configured to manage the power mode of the non-volatile memory 325. The power mode controller 330 can be coupled to and exchange signaling with pending command buffers 335-a, 335-b, and issuing command buffer 335-c, as well as other components. For example, the power mode controller 330 can receive one or more commands from buffers 335 and an indication of the number of commands queued (or “buffered” or “stored” and other suitable terms) in buffers 335. The power mode controller 330 can use the number of queued commands as a basis for controlling the power mode of the non-volatile memory 325 and other factors.

[0083] The pending command buffer 335-a may store commands (e.g., function commands) for the non-volatile memory 325. In some instances, the pending command buffer 335-a is included in or coupled to the scheduling component of the memory interface circuitry 234.

[0084] Pending command buffer 335-b may be a smaller buffer (relative to pending command buffer 335-a) storing commands from pending command buffer 335-a. Pending command buffer 335-b may be configured to ensure that various parameters (e.g., timing parameters) for non-volatile memory 325 are satisfied. Therefore, commands ready for use in non-volatile memory 325 from pending command buffer 335-a can be transferred from pending command buffer 335-a to pending command buffer 335-b so that pending command buffer 335-a can appropriately transfer the commands to non-volatile memory 325 (or intermediate components).

[0085] In some instances, pending command buffers 335-a and 335-b may be combined into a single buffer. In some instances, pending command buffer 335-a may be referred to as a scheduling buffer, and pending command buffer 335-b may be referred to as an input queue. Pending command buffers 335-a and 335-b may be configured (e.g., to power mode controller 330) to indicate the number of commands stored in the buffers for non-volatile memory 325.

[0086] The command buffer 335-c can store commands that have been sent to the non-volatile memory 325 but have not yet been satisfied (e.g., commands that the non-volatile memory 325 is currently satisfying or executing). The power mode controller 330 can refer to the command buffer 335-c to determine whether the non-volatile memory 325 is busy (e.g., performing one or more operations) or idle (e.g., not performing one or more operations), which allows the power mode controller 330 to avoid changing the power mode of the non-volatile memory 325 at inappropriate times (e.g., when the non-volatile memory 325 is in the middle of a task). In some instances, the command buffer 335-c may be referred to as a read-response buffer.

[0087] In response to receiving a power mode command from the host device 305, the interface controller 315 may (e.g., via the power mode controller 340) change the power mode of the volatile memory 320 (e.g., change it to the power mode indicated by the power mode command). For example, the power mode controller 340 may issue a command, such as a new power mode command, or send an indication to the volatile memory 320 to achieve the power mode change. Therefore, the volatile memory 320 may be in the power mode expected by the host device 305 for subsequent commands (e.g., function commands).

[0088] In some instances, the power mode controller 330 may maintain the current power mode of the non-volatile memory 325 regardless of power mode commands from the host device 305 (and regardless of changes in the power mode of the volatile memory 320). For example, the power mode controller 330 may keep the non-volatile memory 325 in standby (or active) mode regardless of power mode commands indicating a low power mode. In other instances, the power mode controller 330 may comply with power commands after a delay. For example, in response to a power command indicating a higher power mode, the power mode controller 330 may delay transitioning the non-volatile memory 325 from a low power mode to a higher power mode until a threshold number of commands are queued for the non-volatile memory 325.

[0089] Therefore, the power mode controller 330 can use the number of queued commands for the non-volatile memory 325 as the basis for changing the power mode of the non-volatile memory. The power mode controller 330 can determine the number of queued commands for the non-volatile memory 325 based on or in response to the number of commands in the pending command buffer 335-a, the number of commands in the pending command buffer 335-b, the number of commands in the issuing command buffer 335-c, or a combination thereof.

[0090] If the number of queued commands is less than a threshold number (e.g., if the number of queued commands is zero), then the power mode controller 330 may transition the non-volatile memory 325 from a higher power mode (e.g., standby mode, active mode) to a lower power mode. This type of technique reduces the power consumption of the non-volatile memory 325 by allowing it to transition to a lower power mode in the event of an interruption in access to the non-volatile memory 325. If the number of queued commands meets a threshold number (e.g., if the number of queued commands is one or more), then the power mode controller 330 may transition the non-volatile memory from a lower power mode to a higher power mode (e.g., standby mode, active mode). This type of technique reduces the power consumption of the non-volatile memory 325 by allowing, in some instances, a delayed transition to a higher power mode until the non-volatile memory 325 needs to be accessed (e.g., in the event of a miss). In other words, the non-volatile memory 325 can switch to a higher power mode as one or more function commands associated with one or more misses are being added to the pending command buffer 335-a.

[0091] In some instances, the power mode controller 330 may delay power mode transitions until a duration (e.g., relative to a transition trigger) has expired. For example, after detecting that a certain number of commands (e.g., zero commands) are queued for non-volatile memory 325, the power mode controller 330 may wait for a configurable delay before transitioning the non-volatile memory 325 from a first power mode to a second power mode (e.g., from a higher power mode to a lower power mode). This type of technique prevents the power mode controller 330 from immediately re-transitioning the power mode of the non-volatile memory 325 in the event of another triggering event, which could waste power, increase latency, or both, and have other disadvantages. In some instances, the duration may be indicated by a register included in the interface controller 315 (e.g., coupled to the power mode controller 330). In some instances, the register may indicate the duration of different combinations of power mode transitions (defined with respect to power mode exit and power mode entry). For example, the register may indicate a first duration for transitioning from standby mode to low power mode and a second duration for transitioning from active mode to low power mode (and so on for other transition combinations). The delay indicated by the register may be set by the user, by the host device 305, by the interface controller 315 (e.g., based on the access mode of the non-volatile memory 325, the power level of the memory subsystem 310), or a combination thereof.

[0092] Figure 4 This describes an example of a process flow 400 supporting multi-memory power mode control, based on the examples disclosed herein. Process flow 400 can be found in the reference... Figure 1 The described memory subsystem 110 or interface controller 115, reference Figure 2 The described memory subsystem 200 or interface controller 202 or reference Figure 3 The described memory subsystem 310 or interface controller 315 is implemented. However, other types of devices or components may implement process flow 400. Process flow 400 may describe the operation of a device that changes the power mode of volatile memory independently of the power mode of non-volatile memory, and vice versa.

[0093] For ease of reference, the process flow 400 is described using reference devices. For example, aspects of the process flow 400 may be implemented by means including volatile memory and non-volatile memory. Alternatively, aspects of the process flow 400 may be implemented as instructions stored in memory (e.g., firmware stored in volatile memory 120 or non-volatile memory 125, or both). For example, if the instructions are executed by a controller, then the controller may perform the operation of the process flow 400.

[0094] At 405, a command, such as a power mode command, may be received. For example, interface controller 315 may receive a power mode command from host device 305. The power mode command may indicate a low power mode requested by host device 305. At 410, the power mode of volatile memory 320 may be changed based on (e.g., in response to) the power mode command. For example, interface controller 315 may change the power mode of volatile memory 320 from a first power mode, such as a higher power mode (e.g., active mode, standby mode), to a second power mode, such as a low power mode, one or both of which may be indicated by the power mode command. Therefore, after 410, volatile memory 320 may operate in a low power mode (at least until another power mode command is received or some other power mode transition event occurs). However, the power mode of non-volatile memory 325 may be maintained (e.g., maintained in the current power mode) regardless of power mode command 405.

[0095] At 415, it can be determined whether the number of queued commands is less than a threshold number (e.g., one). For example, interface controller 315 can determine whether the number of queued commands for non-volatile memory 325 is less than a threshold number (e.g., zero). The number of queued commands can be determined based on or in response to the number of pending commands stored (or “queued”) in pending command buffer 335-a, based on or in response to the number of pending commands stored in pending command buffer 335-b, based on or in response to the number of issued commands stored in issued command buffer 335-c, or based on or in response to a combination of two or more of these numbers. In some instances, the number of queued commands can be determined based on or in response to an indication of the number received from buffer 335.

[0096] If at 415 it is determined that the number of queued commands is less than a threshold number (e.g., the number of queued commands is zero), then the device may proceed to 420 and maintain the power mode of the non-volatile memory 325 as it is before returning to 415. If at 415 it is determined that the number of queued commands is not less than a threshold number (e.g., the number of queued commands is one or more), then the device may proceed to 425.

[0097] At 425, it can be determined whether a new command has been queued (e.g., added to one of the buffers 335) for nonvolatile memory 325 during the determined delay duration relative to 415. For example, interface controller 315 can determine whether a new command has been queued for nonvolatile memory 325 in pending command buffer 335-a. The delay duration can be indicated by a register configured to indicate the delay duration. The delay duration can be set (or updated) by a user (in this case, the delay duration may be referred to as based on or in response to user input), set (or updated) by host device 305, set (or updated) by interface controller 315, or a combination thereof. In some instances, interface controller 315 can set the delay duration based on or in response to the access mode (e.g., access history) of nonvolatile memory 325. In some instances, interface controller 315 can set the delay duration based on or in response to the power level of nonvolatile memory 325. In some instances, the interface controller 315 may determine whether to use a delay duration based on or in response to the last one or more commands sent to the non-volatile memory 325.

[0098] If at 425 it is determined that a new command has been queued for non-volatile memory 325 during the delay duration, then interface controller 315 may proceed to 420 and maintain the current power mode of non-volatile memory 325. If at 425 it is determined that no new command has been queued for non-volatile memory 325 during the delay duration, then interface controller 315 may proceed to 430.

[0099] At 430, the power mode of the non-volatile memory 325 can be changed. For example, the interface controller 315 can switch the non-volatile memory 325 from a higher power mode to a lower power mode. The switch to a lower power mode can be based on or in response to determinations at 415 and 420 and is independent of a power command received at 405.

[0100] At 435, it can be determined whether the number of queued commands meets (e.g., is greater than or equal to) a threshold number. For example, interface controller 315 can determine whether the number of queued commands for non-volatile memory 325 meets the threshold number (e.g., by comparing the number of queued commands for non-volatile memory 325 with a threshold number that can be stored or otherwise calculated or obtained).

[0101] If at 435 it is determined that the number of queued commands does not meet the threshold number (e.g., the number of queued commands is zero), then the device may proceed to 440 and maintain the power mode of the non-volatile memory 325 as it is before returning to 435. If at 435 it is determined that the number of queued commands meets the threshold number (e.g., the number of queued commands is one or more), then the device may proceed to 445.

[0102] At 445, the power mode of the non-volatile memory 325 can be changed. For example, the interface controller 315 can transition the non-volatile memory 325 from a low power mode to a higher power mode. The transition to a higher power mode may be based on or in response to a determination at 435. In some instances, the transition to a higher power mode is additionally based on or in response to a power mode command indicating a higher power mode (e.g., received before 435). If transitioning from a low power mode to a higher power mode, the device may not use a delay duration to postpone the transition because doing so could increase the latency of the non-volatile memory 325 used for access operations.

[0103] Although shown as occurring before the operation at 415, in some instances, the operations at 405 and 410 may occur after the operation at 430. Therefore, in some instances, the power mode of the non-volatile memory 325 changes to a low-power mode before the power mode of the volatile memory 320 changes to a low-power mode.

[0104] Therefore, the device can change the power mode of volatile memory independently of the power mode of non-volatile memory, and vice versa.

[0105] Alternative instances of the above can be implemented, in which some operations are performed in a different order than described, in parallel, or not at all. In some cases, operations may include additional features not mentioned below, or additional operations may be added. Furthermore, some operations may be performed multiple times, or combinations of operations may be repeated or cyclical.

[0106] Figure 5 A block diagram 500 illustrates a memory device 520 supporting power mode control in a multi-memory device according to an example disclosed herein. The memory device 520 may be as described in reference... Figures 1 to 4 Examples of aspects of the described memory device. Memory device 520 or its various components may be examples of means for performing various aspects of power mode control in a multi-memory device as described herein. For example, memory device 520 may include controller 525, volatile memory (VM) controller 530, non-volatile memory (NVM) controller 535, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0107] Controller 525 may be or includes logic, circuitry, a processor, a controller, or other components capable of performing the functions described herein. In some instances, controller 525 is an instance of an interface controller as described herein. VM controller 530 may be or includes logic, circuitry, a processor, a controller, or other components capable of performing the functions described herein. In some instances, VM controller 530 is a reference... Figure 3 An example of the described power mode controller 340. The NVM controller 535 may be or includes logic, circuitry, a processor, a controller, or other components capable of performing the functions described herein. In some instances, the NVM controller 535 is a reference... Figure 3 An example of the described power mode controller 330.

[0108] Controller 525 may be configured or otherwise support means for operating volatile memory in a first power mode and non-volatile memory in a second power mode. VM controller 530 may be configured or otherwise support means for switching the volatile memory from the first power mode to a third power mode, at least in part based on (e.g., in response to) a command from a host device coupled to the memory device, the command indicating the third power mode. NVM controller 535 may be configured or otherwise support means for switching the non-volatile memory from the second power mode to a fourth power mode that consumes less power than the second power mode, independent of the command from the host device and at least in part based on (e.g., in response to) a queued number of commands for the non-volatile memory being less than a threshold number.

[0109] In some instances, the NVM controller 535 may be configured or otherwise supported to include means for determining whether the number of queued commands for the non-volatile memory is less than the threshold number. In some instances, the NVM controller 535 may be configured or otherwise supported to include means for issuing a command indicating the fourth power mode to the non-volatile memory, at least in part based on determining that the number of queued commands is less than the threshold number, wherein the non-volatile memory is switched to the fourth power mode based at least in part on issuing the command indicating the fourth power mode.

[0110] In some instances, the NVM controller 535 may be configured or otherwise supported to support means for determining a first number of pending commands for the non-volatile memory stored in a first buffer, wherein the queued command number includes the first number of pending commands. In some instances, the NVM controller 535 may be configured or otherwise supported to support means for determining a second number of issued commands for the non-volatile memory stored in a second buffer, wherein the queued command number includes the second number of issued commands.

[0111] In some instances, the NVM controller 535 may be configured or otherwise supported to provide means for determining a third number of pending commands stored in a third buffer for the non-volatile memory, wherein the number of queued commands includes the third number of pending commands.

[0112] In some instances, the NVM controller 535 may be configured or otherwise supported to determine whether the number of queued commands for the non-volatile memory meets the threshold number after the non-volatile memory has been switched to the fourth power mode. In some instances, the NVM controller 535 may be configured or otherwise supported to switch the non-volatile memory from the fourth power mode to a different power mode that consumes more power than the fourth power mode, at least in part based on the determination that the number of queued commands for the non-volatile memory meets the threshold number.

[0113] In some instances, the NVM controller 535 may be configured or otherwise support means for determining, at least in part, the duration between a delay in transitioning the non-volatile memory from the second power mode to the fourth power mode, based on user input, the access mode of the non-volatile memory, or a combination thereof, wherein the non-volatile memory is transitioned after the duration.

[0114] In some instances, the NVM controller 535 may be configured or otherwise supported to include means for determining whether the number of queued commands for the non-volatile memory is less than a threshold number, wherein the number of queued commands includes pending commands for the non-volatile memory and commands sent to the non-volatile memory. In some instances, the NVM controller 535 may be configured or otherwise supported to include means for switching the non-volatile memory from a first power mode to a second power mode that consumes less power compared to the first power mode, at least in part based on (e.g., in response to) determining that the number of queued commands for the non-volatile memory is less than the threshold number.

[0115] In some instances, the NVM controller 535 may be configured or otherwise supported to determine whether the number of queued commands for the non-volatile memory meets the threshold number after the non-volatile memory is switched to the second power mode. In some instances, the NVM controller 535 may be configured or otherwise supported to switch the non-volatile memory from the second power mode to a different power mode that consumes more power than the second power mode, at least in part based on the determination that the number of queued commands for the non-volatile memory meets the threshold number.

[0116] In some instances, the NVM controller 535 may be configured or otherwise supported to delay the duration between determining that the number of queued commands is less than the threshold number and transitioning the non-volatile memory from the first power mode to the second power mode, wherein the delay is based at least in part on user input, the access mode of the non-volatile memory, or a combination thereof.

[0117] In some instances, VM controller 530 may be configured or otherwise supported to support means for receiving commands from a host device indicating the power mode of the volatile memory. In some instances, NVM controller 535 may be configured or otherwise supported to support means for maintaining the power mode of the non-volatile memory independently of receiving commands indicating the power mode of the volatile memory.

[0118] Figure 6 A flowchart illustrating a method 600 for supporting power mode control in a multi-memory device according to an example disclosed herein is shown. Operation of method 600 may be implemented by the memory device or its components described herein. For example, operation of method 600 may be provided by reference to... Figures 1 to 5 The described memory device performs the functions described. In some instances, the memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0119] At 605, the method may include operating the volatile memory in a first power mode and operating the non-volatile memory in a second power mode. The operation at 605 may be performed according to the examples disclosed herein. In some instances, it may be provided by reference... Figure 5 The controller 525 described performs the operation of 605.

[0120] At 610, the method may include, at least in part, based on a command from a host device coupled to the memory device, transitioning the volatile memory from a first power mode to a third power mode, the command indicating the third power mode. Operation 610 may be performed according to the examples disclosed herein. In some instances, it may be provided by reference... Figure 5 The VM controller 530 described performs the operations of 610.

[0121] At 615, the method may include, independently of the commands from the host device and at least in part based on the fact that the number of queued commands for the non-volatile memory is less than a threshold number, switching the non-volatile memory from the second power mode to a fourth power mode that consumes less power compared to the second power mode. The operation at 615 may be performed according to the examples disclosed herein. In some instances, it may be performed by reference to... Figure 5 The NVM controller 535 described performs the operations of 615.

[0122] In some instances, the device as described herein may perform one or more methods, such as method 600. The device may include features, circuitry, logic, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: operating volatile memory in a first power mode and operating non-volatile memory in a second power mode; switching the volatile memory from the first power mode to a third power mode based at least in part on a command from a host device coupled to the memory device, the command indicating the third power mode; and switching the non-volatile memory from the second power mode to a fourth power mode that consumes less power compared to the second power mode, independent of the command from the host device and based at least in part on a queue of commands for the non-volatile memory being less than a threshold number.

[0123] Some examples of the method 600 and apparatus described herein may additionally include operations, features, circuit systems, logic, means, or instructions for: determining whether the number of queued commands for the non-volatile memory is less than a threshold number; and, based at least in part on determining that the number of queued commands is less than the threshold number, transmitting a command indicating the fourth power mode to the non-volatile memory, wherein the non-volatile memory may be switched to the fourth power mode based at least in part on transmitting the command indicating the fourth power mode.

[0124] Some examples of the method 600 and apparatus described herein may additionally include operations, features, circuit systems, logic, means, or instructions for: determining a first number of pending commands for the non-volatile memory stored in a first buffer, wherein the queued command number includes the first number of pending commands; and determining a second number of issued commands for the non-volatile memory stored in a second buffer, wherein the queued command number includes the second number of issued commands.

[0125] Some examples of the method 600 and apparatus described herein may additionally include operations, features, circuit systems, logic, means, or instructions for determining a third number of pending commands stored in a third buffer for the non-volatile memory, wherein the number of queued commands includes the third number of pending commands.

[0126] Some examples of the method 600 and apparatus described herein may additionally include operations, features, circuit systems, logic, means, or instructions for: determining whether the number of queued commands for the non-volatile memory meets the threshold number after switching the non-volatile memory to the fourth power mode; and switching the non-volatile memory from the fourth power mode to a different power mode that consumes more power compared to the fourth power mode, based at least in part on the determination that the number of queued commands for the non-volatile memory meets the threshold number.

[0127] Some examples of the method 600 and apparatus described herein may additionally include operations, features, circuit systems, logic, means, or instructions for determining, at least in part, the duration between delaying the transition of the non-volatile memory from the second power mode to the fourth power mode, based on user input, the access mode of the non-volatile memory, or a combination thereof, wherein the non-volatile memory may be transitioned after the duration.

[0128] Figure 7 A flowchart illustrating a method 700 for supporting power mode control in a multi-memory device according to an example disclosed herein is shown. Operation of method 700 may be implemented by a memory device or its components as described herein. For example, operation of method 700 may be performed by reference to... Figures 1 to 5 The described memory device performs the functions described. In some instances, the memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0129] At 705, the method may include determining whether the number of queued commands for the non-volatile memory is less than a threshold number, wherein the number of queued commands includes commands pending for the non-volatile memory and commands sent to the non-volatile memory. The operation at 705 may be performed according to the examples disclosed herein. In some instances, it may be referenced... Figure 5 The NVM controller 535 described performs the operation of 705.

[0130] At 710, the method may include, at least in part, switching the non-volatile memory from a first power mode to a second power mode that consumes less power compared to the first power mode, based on determining that the number of queued commands for the non-volatile memory is less than the threshold number. The operation at 710 may be performed according to the examples disclosed herein. In some instances, it may be provided by reference... Figure 5 The NVM controller 535 described performs the operations of 710.

[0131] In some instances, the device as described herein may perform one or more methods, such as method 700. The device may include features, circuitry, logic, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: determining whether the number of queued commands for the non-volatile memory is less than a threshold number, wherein the number of queued commands includes pending commands for the non-volatile memory and commands sent to the non-volatile memory; and, at least in part based on the determination that the number of queued commands for the non-volatile memory is less than the threshold number, switching the non-volatile memory from a first power mode to a second power mode that consumes less power compared to the first power mode.

[0132] Some examples of the method 700 and apparatus described herein may additionally include operations, features, circuit systems, logic, means, or instructions for: determining, after switching the non-volatile memory to the second power mode, whether the number of queued commands for the non-volatile memory meets the threshold number; and switching the non-volatile memory from the second power mode to a different power mode that consumes more power compared to the second power mode, based at least in part on the determination that the number of queued commands for the non-volatile memory meets the threshold number.

[0133] Some examples of the method 700 and apparatus described herein may additionally include operations, features, circuit systems, logic, devices, or instructions for delaying the determination that the number of queued commands may be less than the threshold number and the duration between transitioning the non-volatile memory from the first power mode to the second power mode, wherein the delay may be based at least in part on user input, the access mode of the non-volatile memory, or a combination thereof.

[0134] Some examples of the method 700 and apparatus described herein may additionally include operations, features, circuit systems, logic, means, or instructions for: receiving a command from a host device indicating a power mode of the volatile memory; and maintaining the power mode of the non-volatile memory independently of receiving the command indicating the power mode of the volatile memory.

[0135] It should be noted that the methods described herein describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0136] Describe a device. The device may include non-volatile memory; volatile memory configured to serve as a cache for the non-volatile memory; and an interface controller coupled to the non-volatile memory and the volatile memory, the interface controller being operable such that the device performs the following operations: determining whether the number of queued commands for the non-volatile memory is less than a threshold number, wherein the number of queued commands includes pending commands for the non-volatile memory and commands sent to the non-volatile memory; and at least in part based on the determination that the number of queued commands for the non-volatile memory is less than the threshold number, switching the non-volatile memory from a first power mode to a second power mode that consumes less power compared to the first power mode.

[0137] In some instances, the device may include a first buffer, located within the interface controller, configured to store pending commands for the non-volatile memory, wherein the interface controller is operable such that the device determines the number of queued commands at least in part based on the pending commands stored in the first buffer; and a second buffer, located within the interface controller, configured to store issued commands for the non-volatile memory, wherein the interface controller is operable such that the device determines the number of queued commands at least in part based on the issued commands stored in the second buffer.

[0138] In some instances, the device may include a third buffer within the interface controller, configured to store a set of pending commands from the first buffer, wherein the interface controller may be operable such that the device determines the number of queued commands at least in part based on the pending commands stored in the third buffer.

[0139] In some instances, the device may include, after switching the non-volatile memory to the second power mode, determining whether the number of queued commands for the non-volatile memory meets the threshold number; and, at least in part based on determining that the number of queued commands for the non-volatile memory meets the threshold number, switching the non-volatile memory from the second power mode to a different power mode that consumes more power than the second power mode.

[0140] In some instances, the device may include a delay between determining that the number of queued commands may be less than the threshold number and the duration between transitioning the non-volatile memory from the first power mode to the second power mode, wherein the delay may be based at least in part on user input, the access mode of the non-volatile memory, or a combination thereof.

[0141] In some instances, the device may include a register within the interface controller, configured to instruct the interface controller to delay the duration between determining that the number of queued commands may be less than the threshold number and transferring the non-volatile memory.

[0142] In some instances, the device may include receiving a command from a host device indicative of a power mode for the volatile memory; and maintaining the power mode of the non-volatile memory independently of receiving the command indicative of the power mode for the volatile memory. In some instances of the device, the number of thresholds may be one and the number of queued commands may be zero.

[0143] Describe another device. The device may include non-volatile memory; volatile memory configured to serve as a cache for the non-volatile memory; and an interface controller coupled to the non-volatile memory and the volatile memory, the interface controller being operable such that the device performs the following operations: operating the volatile memory in a first power mode and operating the non-volatile memory in a second power mode; switching the volatile memory from the first power mode to a third power mode, at least in part based on a command from a host device, the command indicating the third power mode; and switching the non-volatile memory from the second power mode to a fourth power mode that consumes less power compared to the second power mode, independent of the command from the host device and at least in part based on the number of queued commands for the non-volatile memory being less than a threshold number.

[0144] In some instances, the device may include determining whether the number of queued commands for the non-volatile memory is less than a threshold number; and, based at least in part on determining that the number of queued commands is less than the threshold number, transmitting a command indicating the fourth power mode to the non-volatile memory, wherein the non-volatile memory may be switched to the fourth power mode based at least in part on transmitting the command indicating the fourth power mode.

[0145] In some instances, the device may include determining a first number of pending commands for the non-volatile memory stored in a first buffer, wherein the number of queued commands may be determined at least in part based on the first number of pending commands; and determining a second number of issued commands for the non-volatile memory stored in a second buffer, wherein the number of queued commands may be determined at least in part based on the second number of issued commands.

[0146] In some instances, the device may include determining a third number of pending commands stored in a third buffer for the non-volatile memory, wherein the number of queued commands may be determined at least in part based on the third number of pending commands.

[0147] In some instances, the device may include, after switching the non-volatile memory to the fourth power mode, determining whether the number of queued commands for the non-volatile memory meets the threshold number; and, at least in part based on determining that the number of queued commands for the non-volatile memory meets the threshold number, switching the non-volatile memory from the fourth power mode to a different power mode that consumes more power compared to the fourth power mode.

[0148] In some instances, the device may include determining, at least in part, the duration between delaying the transition of the non-volatile memory from the second power mode to the fourth power mode based on user input, the access mode of the non-volatile memory, or a combination thereof, wherein the non-volatile memory may be transitioned after the duration.

[0149] In some instances of the device, the volatile memory may be switched to the third power mode after the non-volatile memory has been switched to the fourth power mode. In some instances of the device, the volatile memory and the non-volatile memory may be switched in parallel. In some instances of the device, the device may include receiving the command from the host device after switching the non-volatile memory to the fourth power mode. In some instances of the device, the threshold number may be one and the queued command number may be zero.

[0150] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods can be combined.

[0151] When used to describe conditional actions or processes, the terms "if...then...", "when...", "based on...", "at least in part based on...", and "in response to..." are interchangeable.

[0152] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate signaling as a single signal; however, those skilled in the art will understand that a signal can represent a bus of signals, where the bus can have various bit widths.

[0153] A protocol can define one or more communication procedures and one or more communication parameters that support use by a device or component. For example, a protocol can define various operations, the timing and frequency of those operations, the meaning of various commands or signals or both, one or more addressing schemes for one or more memories, the type of communication where pins are reserved, the size of data processed at various components of an interface, the data rate supported by various components of an interface, or the bandwidth supported by various components of an interface, and other parameters and metrics, or any combination thereof. The use of shared protocols enables interaction between devices because each device can operate in a way that another device expects, recognizes, and understands. For example, two devices supporting the same protocol can interact according to the policies, procedures, and parameters defined by the protocol, while two devices supporting different protocols may be incompatible.

[0154] To illustrate, two devices supporting different protocols may be incompatible because the protocols define different addressing schemes (e.g., different numbers of address bits). As another illustration, two devices supporting different protocols can be incompatible because the protocols define different transmission procedures for responding to a single command (e.g., the batch length or number of bytes allowed in response to a command may be different). Simply translating a command into an action should not be interpreted as the use of two different protocols. In fact, protocols can be considered different if the corresponding procedures or parameters defined by the two protocols change. For example, if a device supports different addressing schemes or different transmission procedures for responding to commands, the device can be said to support two different protocols.

[0155] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if any conductive path exists between them that can support the flow of signals between them at any given time. At any given time, based on (e.g., in response to) the operation of a device containing the connected components, the conductive path between components that are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) can be an open circuit or a closed circuit. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path between connected components that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0156] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. When a component, such as a controller, couples other components together, it initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0157] The term "isolation" refers to the relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller separates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0158] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0159] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped, for example, degenerate, semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority of the carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of the carriers are holes), then the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "started." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "de-started."

[0160] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0161] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0162] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0163] As used herein, the term “generally” means that the modified feature (e.g., a verb or adjective modified by the term “generally”) need not be absolute but must be close enough to obtain the advantage of the feature. As used herein, the term “in parallel” means that the described actions or phenomena occur during a period of time that are at least partially overlapping in time, can be substantially simultaneous, or are offset in time.

[0164] The various illustrative blocks and modules described herein can be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0165] The functionality described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functionality described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality may also be physically located in various locations, including distributed implementations such that portions of the functionality are implemented in different physical locations. And, as used herein, the word “or” used in the list of items included in the claims (e.g., a list of items beginning with phrases such as “at least one of” or “one or more of”) indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase “based on” should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as “based on condition A” may be based on both condition A and condition B. In other words, as used herein, the phrase “based on” should also be interpreted as the phrase “at least partially based on”.

[0166] Computer-readable media includes both non-transitory computer storage media and communication media that include any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), compressed optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital video discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0167] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: Non-volatile memory; A volatile memory configured to function as a cache for the non-volatile memory; and An interface controller, coupled to the non-volatile memory and the volatile memory, is operable to cause the device to perform the following operations: Determine whether the number of queued commands for the non-volatile memory is less than a threshold number, wherein the number of queued commands includes commands pending for the non-volatile memory and commands sent to the non-volatile memory; and Regardless of the power mode of the volatile memory and based at least in part on determining that the number of queued commands for the non-volatile memory is less than the threshold number, the non-volatile memory is switched from a first power mode to a second power mode that consumes less power compared to the first power mode.

2. The device according to claim 1, further comprising: A first buffer, located in the interface controller, is configured to store pending commands for the non-volatile memory, wherein the interface controller is operable such that the device determines the number of queued commands based at least in part on the pending commands stored in the first buffer. and A second buffer, located in the interface controller, is configured to store issued commands for the non-volatile memory, wherein the interface controller is operable such that the device determines the number of queued commands at least in part based on the issued commands stored in the second buffer.

3. The device according to claim 2, further comprising: A third buffer, located within the interface controller, is configured to store a set of pending commands from the first buffer, wherein the interface controller is operable such that the device determines the number of queued commands based at least in part on the pending commands stored in the third buffer.

4. The device of claim 1, wherein the interface controller is further operable to cause the device to perform the following operations: After switching the non-volatile memory to the second power mode, it is determined whether the number of queued commands for the non-volatile memory meets the threshold number; and The non-volatile memory is switched from the second power mode to a different power mode that consumes more power than the second power mode, based at least in part on determining that the number of queued commands for the non-volatile memory meets the threshold number.

5. The device of claim 1, wherein the interface controller is further operable to cause the device to perform the following operations: The delay determines the duration between the number of queued commands being less than the threshold number and the transition of the non-volatile memory from the first power mode to the second power mode, wherein the delay is based at least in part on user input, the access mode of the non-volatile memory, or a combination thereof.

6. The device according to claim 5, further comprising: A register, located in the interface controller, is configured to instruct the interface controller to delay the duration between determining that the number of queued commands is less than the threshold number and transferring the non-volatile memory.

7. The device of claim 1, wherein the interface controller is further operable to cause the device to perform the following operations: Receive a command from the host device instructing the power mode of the volatile memory; and Maintaining the power mode of the non-volatile memory is independent of receiving the command instructing the power mode of the volatile memory.

8. The device of claim 1, wherein the number of thresholds is one and the number of queuing commands is zero.

9. An apparatus comprising: Non-volatile memory; A volatile memory configured to function as a cache for the non-volatile memory; and An interface controller, coupled to the non-volatile memory and the volatile memory, is operable to cause the device to perform the following operations: The volatile memory operates in a first power mode and the non-volatile memory operates in a second power mode; The volatile memory is switched from a first power mode to a third power mode based at least in part on a command from the host device, the command indicating the third power mode; and The non-volatile memory is switched from the second power mode to a fourth power mode that consumes less power compared to the second power mode, independently of the commands from the host device and at least in part based on the fact that the number of queued commands for the non-volatile memory is less than a threshold number.

10. The device of claim 9, wherein the interface controller is further operable to cause the device to perform the following operations: Determine whether the number of queued commands for the non-volatile memory is less than the threshold number; and At least in part based on determining that the number of queued commands is less than the threshold number, a command indicating the fourth power mode is sent to the non-volatile memory, wherein the non-volatile memory is switched to the fourth power mode at least in part based on sending the command indicating the fourth power mode.

11. The device of claim 9, wherein the interface controller is further operable to cause the device to perform the following operations: Determine a first number of pending commands stored in a first buffer for the non-volatile memory, wherein the number of queued commands is determined at least in part based on the first number of pending commands; and A second number of commands to be issued for the non-volatile memory is determined in a second buffer, wherein the number of queued commands is determined at least in part based on the second number of commands to be issued.

12. The device of claim 11, wherein the interface controller is further operable to cause the device to perform the following operations: A third number of pending commands for the non-volatile memory is determined in a third buffer, wherein the number of queued commands is determined at least in part based on the third number of pending commands.

13. The device of claim 9, wherein the interface controller is further operable to cause the device to perform the following operations: After switching the non-volatile memory to the fourth power mode, it is determined whether the number of queued commands for the non-volatile memory meets the threshold number; and The non-volatile memory is switched from the fourth power mode to a different power mode that consumes more power compared to the fourth power mode, based at least in part on determining that the number of queued commands for the non-volatile memory meets the threshold number.

14. The device of claim 9, wherein the interface controller is further operable to cause the device to perform the following operations: The duration between the delay of switching the non-volatile memory from the second power mode to the fourth power mode is determined at least in part based on user input, the access mode of the non-volatile memory, or a combination thereof, wherein the non-volatile memory is switched after the duration.

15. The device of claim 9, wherein the volatile memory is switched to the third power mode after the non-volatile memory is switched to the fourth power mode.

16. The device of claim 9, wherein the volatile memory and the non-volatile memory are switched in parallel.

17. The device of claim 9, wherein the interface controller is further operable to cause the device to perform the following operations: The command is received from the host device after the non-volatile memory is switched to the fourth power mode.

18. The device of claim 9, wherein the number of thresholds is one and the number of queuing commands is zero.

19. A method executed by a memory device, comprising: The volatile memory operates in a first power mode and the non-volatile memory operates in a second power mode. The volatile memory is switched from a first power mode to a third power mode based at least in part on a command from a host device coupled to the memory device, the command indicating the third power mode; and The non-volatile memory is switched from the second power mode to a fourth power mode that consumes less power compared to the second power mode, independently of the commands from the host device and at least in part based on the fact that the number of queued commands for the non-volatile memory is less than a threshold number.

20. The method of claim 19, further comprising: Determine whether the number of queued commands for the non-volatile memory is less than the threshold number; and At least in part based on determining that the number of queued commands is less than the threshold number, a command indicating the fourth power mode is sent to the non-volatile memory, wherein the non-volatile memory is switched to the fourth power mode at least in part based on sending the command indicating the fourth power mode.

21. The method of claim 19, further comprising: Determine a first number of pending commands stored in a first buffer for the non-volatile memory, wherein the number of queued commands includes the first number of pending commands; and Determine a second number of commands to be issued for the non-volatile memory stored in a second buffer, wherein the number of queued commands includes the second number of commands to be issued.

22. The method of claim 21, further comprising: A third number of pending commands for the non-volatile memory is determined and stored in a third buffer, wherein the number of queued commands includes the third number of pending commands.

23. The method of claim 19, further comprising: After switching the non-volatile memory to the fourth power mode, it is determined whether the number of queued commands for the non-volatile memory meets the threshold number. and The non-volatile memory is switched from the fourth power mode to a different power mode that consumes more power compared to the fourth power mode, based at least in part on determining that the number of queued commands for the non-volatile memory meets the threshold number.

24. The method of claim 19, further comprising: The duration between the delay of switching the non-volatile memory from the second power mode to the fourth power mode is determined at least in part based on user input, the access mode of the non-volatile memory, or a combination thereof, wherein the non-volatile memory is switched after the duration.

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