Method of fabricating a semiconductor structure

Abstract

This invention discloses a method for fabricating a semiconductor structure, comprising providing a substrate, forming a first gate structure and a second gate structure on the substrate, wherein the height of the first gate structure is greater than the height of the second gate structure, depositing a first dielectric layer, wherein the thickness of the first dielectric layer is greater than the height of the first gate structure, depositing a second dielectric layer on the first dielectric layer, removing a portion of the first dielectric layer and the second dielectric layer, and forming a third dielectric layer and a fourth dielectric layer on the second dielectric layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing processes, and in particular to a method for depositing material layers on semiconductor structures with different gate heights. Background Technology

[0002] In semiconductor manufacturing processes, various material layers are often deposited onto a substrate or target layer to form a stack of material layers.

[0003] For target layers on substrates where electronic components have already been formed, the shape characteristics of these electronic components, such as height, width, and depth, must be considered during the deposition of the material layer to avoid defects such as voids after deposition. These defects are more likely to occur, especially when the electronic components are taller or when the semiconductor substrate contains different electronic components with significantly different heights. Summary of the Invention

[0004] The method provided by this invention relates to a method for depositing a material layer on a semiconductor substrate, wherein gate structures of varying heights already exist on the semiconductor substrate. This invention provides a method for fabricating a semiconductor structure that can reduce the probability of defects occurring during deposition.

[0005] The present invention provides a method for fabricating a semiconductor structure, comprising providing a substrate, forming a first gate structure and a second gate structure on the substrate, wherein the height of the first gate structure is greater than the height of the second gate structure, depositing a first dielectric layer, wherein the thickness of the first dielectric layer is greater than the height of the first gate structure, depositing a second dielectric layer on the first dielectric layer, removing a portion of the first dielectric layer and the second dielectric layer, and forming a third dielectric layer and a fourth dielectric layer on the second dielectric layer.

[0006] The present invention is characterized by the presence of gate structures of varying heights already existing on the semiconductor substrate. For example, the gate heights within the logic region and memory region of a memory element may differ, causing difficulties during deposition. In this invention, the deposition height of the first dielectric layer is controlled to be greater than that of the tallest gate structure, thus reducing the likelihood of voids in this step. Furthermore, the thickness of other material layers can be controlled in subsequent steps, resulting in a semiconductor structure with a lower overall thickness compared to existing technologies. This also facilitates the formation of subsequent contact structures and improves the yield of the semiconductor fabrication process. Attached Figure Description

[0007] Figures 1 to 4 This is a cross-sectional schematic diagram of the semiconductor structure fabricated for this invention.

[0008] Explanation of key component symbols:

[0009] 10: Base

[0010] 12: First gate structure

[0011] 14: Second gate structure

[0012] 22: First dielectric layer

[0013] 24: Second dielectric layer

[0014] 26: Third dielectric layer

[0015] 28: Fourth dielectric layer

[0016] CG: Control Gate

[0017] FG: Dummy Gate

[0018] P1: Flattening steps

[0019] P2: Etching Back Step

[0020] R1: First Region

[0021] R2: Second Region

[0022] R3: Third Region

[0023] X1: Distance

[0024] X2: Distance

[0025] X3: Distance Detailed Implementation

[0026] To enable those skilled in the art to further understand the present invention, preferred embodiments of the present invention are described below, and the composition and desired effects of the present invention are explained in detail with reference to the accompanying drawings.

[0027] For ease of explanation, the accompanying drawings are merely illustrative to facilitate understanding of the invention, and their detailed proportions can be adjusted according to design requirements. The vertical relationships between relative elements in the drawings described herein should be understood by those skilled in the art to refer to the relative positions of objects; therefore, all can be flipped to present the same components, and this should all fall within the scope of this specification, as stated herein.

[0028] Figures 1 to 4 A cross-sectional schematic diagram of the semiconductor structure fabricated according to the present invention is shown. Firstly, as follows... Figure 1As shown, a substrate 10 includes gate structures of different heights, such as a first gate structure 12 and a second gate structure 14. The region where the first gate structure 12 is located is defined as the first region R1, and the region where the second gate structure 14 is located is defined as the second region R2. In addition, another third region R3 can be defined, located next to the second region R2, and the third region R3 does not contain a gate structure.

[0029] In this embodiment, the first region R1 is, for example, a flash memory region in a semiconductor memory element, the second region R2 is, for example, a logic region in a semiconductor memory element, and the third region R3 is, for example, an unused region (ISO region). The first gate structure 12 may include a stacked structure of a dummy gate (FG) and a control gate (CG), so its height is greater than that of the second gate structure 14 within the second region R2. For example, in this embodiment, the height of the first gate structure 12 is, for example, 1700 angstroms or less, while the height of the second gate structure 14 is approximately 800 angstroms or less. However, the invention is not limited to this, and the height of the gate elements may be changed according to actual needs.

[0030] As described in the previous technical paragraphs, the significant height difference between the gate structures in different regions can easily lead to defects in the deposition process. For example, in existing deposition processes, when depositing a material layer of average thickness (e.g., 850 angstroms) on the first gate structure 12 and the second gate structure, the material layer may fail to completely fill the gap between the two gate structures, resulting in voids between them. To avoid this situation, such as... Figure 1 As shown, the method proposed in this invention deposits a first dielectric layer 22 on the first gate structure 12 and the second gate structure 14, wherein the thickness of the first dielectric layer 22 is greater than the height of the higher gate structure (i.e., the height of the first gate structure 12). In this way, it is easier to fill the gap between the two gate structures, that is, it is less likely to generate voids between the two gate structures.

[0031] Then refer to Figure 1 Since the first dielectric layer 22 is deposited along the contours of the first gate structure 12 and the second gate structure 14, a height difference may occur on the top surface. That is, the top surface heights of the first dielectric layer 22 in the first region R1, the second region R2, and the third region R3 are different. Then, the second dielectric layer 24 is deposited on the first dielectric layer 22. Since the second dielectric layer 24 is thicker (approximately 5000 angstroms or more), the above-mentioned top surface height difference becomes less noticeable.

[0032] Then as Figure 2As shown, in a planarization step P1, such as a chemical mechanical polishing (CMP) step, a portion of the second dielectric layer 24 is removed, such that the top surfaces of the second dielectric layers 24 in the first region R1, the second region R2, and the third region R3 are aligned. Additionally, in this embodiment, after the planarization step, the distance from the second dielectric layer 24 to the highest point of the first dielectric layer 22 within the first region R1 (…) Figure 2 The distance X1 in the middle still has about 600 angstroms. This left distance X1 is used as a reserve material layer thickness for subsequent back etch steps to improve the thickness uniformity of wafer-to-wafer (WTW) or in-wafer (WiW).

[0033] In this embodiment, the first dielectric layer 22 is made of, for example, sub-atmospheric undoped-silicon glass (SAUSG), and the second dielectric layer 24 is made of, for example, tetraethoxysilane (TEOS). The etch selectivity between the two is low enough that they can be removed simultaneously in a single etch step.

[0034] like Figure 3 As shown, an etch-back step P2 is performed to remove portions of the first dielectric layer 22 and the second dielectric layer 24. This etch-back step is, for example, a dry etching step. After the etch-back step P2 is completed, the distance from the first gate structure 12 to the top surface of the first dielectric layer 22 within the first region R1 is ( Figure 3 The distance X2 in the second region R2 is approximately 500 angstroms, while the distance from the second gate structure 14 to the top surface of the first dielectric layer 22 within the second region R2 is approximately 500 angstroms. Figure 3 The distance (X3) in the third region is approximately 1400 angstroms. In addition, a portion of the second dielectric layer 24 remains on the first dielectric layer 22 in the third region. The thickness of the first dielectric layer 22 in the third region is approximately 1800 angstroms, while the thickness of the remaining second dielectric layer 24 is approximately 400 angstroms, but not limited to this.

[0035] like Figure 4 As shown, a third dielectric layer 26 and a fourth dielectric layer 28 are formed, for example, a third dielectric layer 26 with a thickness of approximately 500 angstroms and a fourth dielectric layer 28 with a thickness of approximately 700 angstroms, respectively. In this embodiment, the third dielectric layer 26 is, for example, phosphosilicate glass (PSG), and the material of the fourth dielectric layer 28 is, for example, tetraethoxysilane (TEOS).

[0036] It is worth noting that the first dielectric layer 22, the second dielectric layer 24, the third dielectric layer 26, and the fourth dielectric layer 28 in this invention are preferably used as interlayer dielectric layers (ILDs). That is, unlike the intermetallic interlayer dielectric layers (IMDs) that form subsequent metal wiring, the first dielectric layer 22, the second dielectric layer 24, the third dielectric layer 26, and the fourth dielectric layer 28 may only contain contact structures such as transistors (not shown) and do not contain metal conductive lines or metal via structures. However, this invention is not limited to this.

[0037] After the stacked structure composed of the above material layers is completed, although the deposition thickness of the first dielectric layer 22 is relatively thick, due to the intermediate planarization step P1 and etch-back step P2, the final total thickness is approximately 3400 angstroms. The applicant found that the thickness of the semiconductor structure formed under this fabrication process is actually thinner than the thickness of the semiconductor structure formed by the prior art (approximately 4000 angstroms), with a total thickness reduction of approximately 15%. Therefore, when other components such as contact structures are subsequently formed, the contact structures can more easily penetrate through the material layers to contact the underlying components, and are less prone to problems such as open circuits in the contact structures.

[0038] Based on the foregoing paragraphs and accompanying drawings, the present invention also has the following features:

[0039] In some embodiments of the present invention, a method for fabricating a semiconductor structure is provided, comprising providing a substrate 10, a first gate structure 12 and a second gate structure 14 located on the substrate 10, wherein the height of the first gate structure 12 is greater than the height of the second gate structure 14, depositing a second dielectric layer 22, wherein the thickness of the first dielectric layer 22 is greater than the height of the first gate structure, depositing a second dielectric layer 24 on the first dielectric layer, removing portions of the first dielectric layer and the second dielectric layer (planarization step P1 and etch-back step P2), and forming a third dielectric layer 26 and a fourth dielectric layer 28 on the second dielectric layer 24.

[0040] In some embodiments of the invention, the deposition thickness of the first dielectric layer 22 is greater than 1800 angstroms.

[0041] In some embodiments of the invention, the total height of the semiconductor structure is less than 3400 angstroms after the third dielectric layer 26 and the fourth dielectric layer 28 are formed.

[0042] In some embodiments of the present invention, the method for removing portions of the first dielectric layer 22 and the second dielectric layer 24 includes sequentially performing a planarization step P1 and an etch-through step P2.

[0043] In some embodiments of the present invention, the planarization step P1 removes only a portion of the second dielectric layer 24 without removing the first dielectric layer 22.

[0044] In some embodiments of the present invention, the etch-back step P2 simultaneously removes a portion of the second dielectric layer 24 and a portion of the first dielectric layer 22.

[0045] In some embodiments of the present invention, a first gate structure 12 is located in a first region R1, a second gate structure 14 is located in a second region R2, and a third region R3 is located next to the second region R2, wherein the third region R3 does not contain a gate structure.

[0046] In some embodiments of the present invention, after the etch-back step P2, the second dielectric layer 24 in the first region R1 and the second region R2 is completely removed, while a portion of the second dielectric layer 24 remains in the third region R3.

[0047] In some embodiments of the present invention, the first gate structure 12 includes a stacked structure of a dummy gate (FG) and a control gate (CG).

[0048] In some embodiments of the invention, the height of the first gate structure is less than 1700 angstroms.

[0049] In some embodiments of the present invention, the first dielectric layer 22 comprises a sub-atmospheric undoped-silicon glass (SAUSG) layer.

[0050] In some embodiments of the present invention, the second dielectric layer 24 comprises tetraethoxysilane (TEOS).

[0051] In some embodiments of the present invention, the third dielectric layer 26 comprises phosphosilicate glass (PSG).

[0052] In some embodiments of the invention, the thickness of the third dielectric layer 26 is less than 500 angstroms.

[0053] In some embodiments of the present invention, the fourth dielectric layer 28 comprises tetraethoxysilane (TEOS).

[0054] In some embodiments of the invention, the thickness of the fourth dielectric layer 28 is less than 700 angstroms.

[0055] In summary, the key feature of this invention is that gate structures of varying heights already exist on the semiconductor substrate. For example, the gate heights in the logic region and memory region of a memory element may differ, causing difficulties during deposition. This invention controls the deposition height of the first dielectric layer to be greater than that of the tallest gate structure, thus reducing the likelihood of voids in this step. Furthermore, the thickness of other material layers can be controlled in subsequent steps, resulting in a semiconductor structure with a lower overall thickness compared to existing technologies. This also facilitates the formation of subsequent contact structures and improves the yield of the semiconductor fabrication process.

[0056] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for fabricating a semiconductor structure, comprising: Provide a base; The first gate structure and the second gate structure are located on the substrate, wherein the height of the first gate structure is greater than the height of the second gate structure; A first dielectric layer is deposited, wherein the first dielectric layer directly contacts the first gate structure and the second gate structure, and the thickness of the first dielectric layer is greater than the height of the first gate structure; A second dielectric layer is deposited on the first dielectric layer; Remove portions of the first dielectric layer and the second dielectric layer; as well as A third and a fourth dielectric layer are formed on the second dielectric layer.

2. The fabrication method of claim 1, wherein the deposition thickness of the first dielectric layer is greater than 1800 angstroms.

3. The fabrication method as described in claim 1, wherein after the third dielectric layer and the fourth dielectric layer are formed, the total height of the semiconductor structure is less than 3400 angstroms.

4. The fabrication method as claimed in claim 1, wherein the method for removing portions of the first dielectric layer and the second dielectric layer comprises sequentially performing a planarization step and an etch-back step.

5. The fabrication method as described in claim 4, wherein the planarization step removes only a portion of the second dielectric layer without removing the first dielectric layer.

6. The fabrication method of claim 4, wherein the etch-back step simultaneously removes a portion of the second dielectric layer and a portion of the first dielectric layer.

7. The fabrication method of claim 4, wherein the first gate structure is located in the first region, the second gate structure is located in the second region, and a third region is located next to the second region, and the third region does not contain a gate structure.

8. The fabrication method of claim 7, wherein after the etch-back step, the second dielectric layer in the first region and the second region is completely removed, while a portion of the second dielectric layer remains in the third region.

9. The fabrication method of claim 1, wherein the first gate structure comprises a stacked structure of a dummy gate (FG) and a control gate (CG).

10. The fabrication method of claim 1, wherein the height of the first gate structure is less than 1700 angstroms.

11. The fabrication method of claim 1, wherein the first dielectric layer comprises a sub-atmospheric undoped-silicon glass (SAUSG) layer.

12. The fabrication method of claim 1, wherein the second dielectric layer comprises tetraethoxysilane (TEOS).

13. The fabrication method of claim 1, wherein the third dielectric layer comprises phosphosilicate glass (PSG).

14. The fabrication method of claim 13, wherein the thickness of the third dielectric layer is less than 500 angstroms.

15. The fabrication method of claim 1, wherein the fourth dielectric layer comprises tetraethoxysilane (TEOS).

16. The fabrication method of claim 15, wherein the thickness of the fourth dielectric layer is less than 700 angstroms.

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