Gate structure in transistor device and method of forming the same

Abstract

The present disclosure relates to gate structures in transistor devices and methods of forming the same. One method includes removing a first dummy gate structure to form a recess around a first nanostucture and a second nanostucture; depositing a sacrificial layer in the recess using flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostucture and the second nanostucture. The method further includes depositing a first work function metal in the recess; removing the first work function metal from the recess and the portion of the sacrificial layer; depositing a second work function metal in the recess, wherein the second work function metal has an opposite conductivity type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.

Description

Technical Field

[0001] This disclosure relates to gate structures in transistor devices and methods for forming them. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously increases the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to one embodiment of this disclosure, a method for forming a semiconductor device is provided, comprising: depositing a sacrificial layer around a first nanostructure and a second nanostructure using a non-conformal deposition process, wherein the first nanostructure is disposed on the second nanostructure and spaced apart from the second nanostructure by a first recess, and wherein the first nanostructure and the second nanostructure are disposed on a semiconductor substrate in a first device region; patterning the sacrificial layer, wherein after patterning the sacrificial layer, a remaining portion of the sacrificial layer is disposed in the first recess between the first nanostructure and the second nanostructure; depositing a first work function adjustment layer on the first nanostructure and the second nanostructure; patterning the first work function adjustment layer to remove a portion of the first work function adjustment layer in the first device region; removing the remaining portion of the sacrificial layer; after removing the remaining portion of the sacrificial layer, depositing a second work function adjustment layer around the first nanostructure and the second nanostructure; and depositing a gate fill material on the second work function adjustment layer.

[0005] According to another embodiment of this disclosure, a method for forming a semiconductor device is provided, comprising: removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess using flowable chemical vapor deposition (CVD); patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure; depositing a first work function metal in the recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal has a conductivity type opposite to that of the first work function metal; and depositing a fill metal in the recess on top of the second work function metal.

[0006] According to another embodiment of this disclosure, a method for forming a semiconductor device is provided, comprising: removing a first dummy gate structure to form a first recess, and removing a second dummy gate structure to form a second recess; depositing a sacrificial layer in the first recess and the second recess using flowable chemical vapor deposition (CVD); patterning the sacrificial layer to remove the sacrificial layer from the first recess while leaving a remainder of the sacrificial layer in the second recess, the remainder of the sacrificial layer being disposed between a first nanostructure and a second nanostructure; depositing a first work function metal in the first recess and the second recess, wherein the sacrificial layer prevents the first work function metal from depositing between the first nanostructure and the second nanostructure; patterning the first work function metal to remove the first work function metal from the second recess while leaving the first work function metal in the first recess; removing the remainder of the sacrificial layer; depositing a second work function metal in the second recess; and depositing a fill metal in the first recess above the first work function metal and in the second recess above the second work function metal. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 An example of a nanostructured field-effect transistor (nano-FET) according to some embodiments is shown in a three-dimensional view.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B , Figure 5C , Figure 6A , Figure 6B 、 Figure 6C 、 Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 11A 、 Figure 11B 、 Figure 11C 、 Figure 12A 、 Figure 12B 、 Figure 12C 、 Figure 13A 、 Figure 13B 、 Figure 13C 、 Figure 14A 、 Figure 14B 、 Figure 14C 、 Figure 15A 、 Figure 15B 、 Figure 15C 、 Figure 16A 、 Figure 16B 、 Figure 16C 、 Figure 17A 、 Figure 17B 、 Figure 17C 、 Figure 18A 、 Figure 18B 、 Figure 18C 、 Figure 18D 、 Figure 18E 、 Figure 19A 、 Figure 19B 、 Figure 19C 、 Figure 20A 、 Figure 20B 、 Figure 20C 、 Figure 21A 、 Figure 21B 、 Figure 21C 、 Figure 22A 、 Figure 22B 、 Figure 22C 、 Figure 23A 、 Figure 23B 、 Figure 23C 、 Figure 24A 、 Figure 24B 、 Figure 24C 、 Figure 25A 、 Figure 25B 、 Figure 25C 、 Figure 26A 、 Figure 26B 、 Figure 26C 、 Figure 27A 、 Figure 27B 、 Figure 27C 、 Figure 28A 、 Figure 28B 、 Figure 28C 、 Figure 29A 、 Figure 29B , Figure 29C , Figure 30A , Figure 30B and Figure 30C This is a cross-sectional view of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] In addition, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used herein to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0012] In various embodiments, alternative gate electrodes are formed for both p-type and n-type devices. In some embodiments, the work function adjustment layer of the n-type device is formed prior to the work function adjustment layer of the p-type device to allow for greater control over the threshold voltage of the resulting device. A method of forming the work function adjustment layer of the n-type device prior to the work function adjustment layer of the p-type device includes forming and patterning a sacrificial layer to prevent the work function adjustment layer of the n-type device from forming between the nanostructures of the p-type device. This helps prevent the work function adjustment layer from remaining on the p-type device, which could degrade the performance of the p-type device. The sacrificial layer can be deposited using a flowable chemical vapor deposition (CVD) method, which provides improved deposition profiles in bottom-up growth. Furthermore, the flowable CVD method can also provide improved gap filling between nanostructures without seams or gaps.

[0013] Figure 1 Examples of nanostructured FETs (e.g., nanowire FETs, nanosheet FETs, etc.) according to some embodiments are shown. Figure 1This is a 3D view, in which some features of the nanostructure FET have been omitted for clarity. Nanostructure FETs can be nanosheet field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), gate all-around field-effect transistors (GAAFETs), etc.

[0014] The nanostructure FET includes a nanostructure 66 (e.g., nanosheet, nanowire, etc.) on semiconductor fins 62 on a substrate 50 (e.g., a semiconductor substrate), and the nanostructure 66 serves as the channel region of the nanostructure FET. The nanostructure 66 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Isolation regions 72, such as shallow trench isolation (STI) regions, are disposed between adjacent semiconductor fins 62, which may protrude above and between adjacent isolation regions 72. Although the isolation regions 72 are shown / described as being separate from the substrate 50, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom portion of the semiconductor fin 62 is shown as being separate from the substrate 50, the bottom portion of the semiconductor fin 62 may be a single continuous material with respect to the substrate 50. In this context, a semiconductor fin 62 refers to a portion extending from between and above adjacent isolation regions 72.

[0015] Gate structure 131 is located above the top surface of semiconductor fin 62 and along the top, sidewalls, and bottom surface of nanostructure 66. Epitaxial source / drain regions 108 are disposed on semiconductor fin 62 on the opposite side of gate structure 131. Epitaxial source / drain regions 108 can be shared between different semiconductor fins 62. For example, adjacent epitaxial source / drain regions 108 can be electrically connected, for example, by coupling epitaxial source / drain regions 108 to the same source / drain contact.

[0016] Insulating fins 82 (also called hybrid fins or dielectric fins) are disposed above the isolation region 72 and between adjacent epitaxial source / drain regions 108. The insulating fins 82 prevent epitaxial growth to prevent some of the epitaxial source / drain regions 108 from merging during epitaxial growth. For example, insulating fins 82 may be formed at cell boundaries to separate the epitaxial source / drain regions 108 of adjacent cells.

[0017] Figure 1The reference cross sections used in the following figures are further illustrated. Cross section A-A' is along the longitudinal axis of the semiconductor fin 62 and in the direction of current flow between the epitaxial source / drain regions 108 of the nanostructure FET, for example. Cross section B-B' is along the longitudinal axis of the gate structure 131 and in a direction perpendicular to, for example, the current direction between the epitaxial source / drain regions 108 of the nanostructure FET. Cross section C-C' is parallel to cross section B-B' and extends through the epitaxial source / drain regions 108 of the nanostructure FET. For clarity, the following figures refer to these reference cross sections.

[0018] Figure 2-Figure 30C This is a view of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments. Figure 2 , Figure 3 and Figure 4 It is a 3D view. Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 28A , Figure 29B and Figure 30A Is along with Figure 1 The cross-sectional view is shown with a cross-section similar to the reference cross-section A-A'. Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 20C , Figure 21A , Figure 21B , Figure 21C , Figure 22A , Figure 22B , Figure 22C , Figure 23A , Figure 23B , Figure 23C , Figure 24A , Figure 24B , Figure 24C , Figure 25A , Figure 25B , Figure 25C , Figure 26A , Figure 26B , Figure 26C , Figure 27A , Figure 27B , Figure 27C , Figure 28B , Figure 29B and Figure 30B Is along with Figure 1 The cross-sectional view is shown with a cross-section similar to the reference cross-section B-B'. Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 28C , Figure 29C and Figure 30C Is along with Figure 1 The cross-sectional view is shown with a cross-section similar to the reference cross-section C-C'.

[0019] exist Figure 2 In this embodiment, a substrate 50 is provided for forming a nanostructure FET. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with p-type or n-type impurities) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates can also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 can include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or combinations thereof.

[0020] Substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, like an n-type nanostructure FET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, like a p-type nanostructure FET. The n-type region 50N can be adjacent to or physically separated from the p-type region 50P (not shown separately), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be provided between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0021] The substrate 50 may be lightly doped with p-type or n-type impurities. A punch-through (APT) implantation may be performed on the upper portion of the substrate 50 to form an APT region. During APT implantation, impurities may be implanted into the substrate 50. The impurities may have a conductivity type opposite to that of the source / drain regions subsequently formed in each of the n-type region 50N and the p-type region 50P. The APT region may extend below the source / drain regions in the nanostructured FET. The APT region can be used to reduce leakage from the source / drain regions to the substrate 50. In some embodiments, the doping concentration in the APT region is 10-1. 18 cm -3 Up to 10 19 cm -3 Within the range.

[0022] A multilayer stack 52 is formed on a substrate 50. The multilayer stack 52 includes alternating first semiconductor layers 54 and second semiconductor layers 56. The first semiconductor layers 54 are formed of a first semiconductor material, and the second semiconductor layers 56 are formed of a second semiconductor material. The semiconductor materials may each be selected from candidate semiconductor materials of the substrate 50. In the illustrated embodiment, the multilayer stack 52 includes three layers of each of the first semiconductor layers 54 and the second semiconductor layers 56. It should be understood that the multilayer stack 52 may include any number of first semiconductor layers 54 and second semiconductor layers 56. For example, the multilayer stack 52 may include one to ten layers of each of the first semiconductor layers 54 and the second semiconductor layers 56.

[0023] In the illustrated embodiment, and as will be described in more detail later, the first semiconductor layer 54 will be removed and the second semiconductor layer 56 will be patterned to form channel regions for a nanostructured FET in both the n-type region 50N and the p-type region 50P. The first semiconductor layer 54 is a sacrificial layer (or dummy layer) that will be removed in a subsequent process to expose the top and bottom surfaces of the second semiconductor layer 56. The first semiconductor material of the first semiconductor layer 54 is a material with high etch selectivity relative to the etching of the second semiconductor layer 56, such as silicon-germanium. The second semiconductor material of the second semiconductor layer 56 is a material suitable for both n-type and p-type devices, such as silicon.

[0024] In another embodiment (not shown separately), the first semiconductor layer 54 will be patterned to form a channel region for a nanostructured FET in one region (e.g., p-type region 50P), and the second semiconductor layer 56 will be patterned to form a channel region for a nanostructured FET in another region (e.g., n-type region 50N). The first semiconductor material of the first semiconductor layer 54 may be a material suitable for p-type devices, such as silicon germanium (e.g., Si). x Ge 1-x The second semiconductor material of the second semiconductor layer 56 can be a material suitable for n-type devices, such as silicon, silicon carbide, III-V compound semiconductor, II-VI compound semiconductor, etc. The etching of the first and second semiconductor materials relative to each other can have high etch selectivity, so that the first semiconductor layer 54 can be removed in the n-type region 50N without removing the second semiconductor layer 56, and the second semiconductor layer 56 can be removed in the p-type region 50P without removing the first semiconductor layer 54. Each layer can have a small thickness, for example, in the range of 5 nm to 30 nm.

[0025] exist Figure 3 In this process, trenches are patterned in substrate 50 and multilayer stack 52 to form semiconductor fins 62, nanostructures 64 and 66. Semiconductor fins 62 are semiconductor strips patterned in substrate 50. Nanostructures 64 and 66 respectively comprise the remainder of the first semiconductor layer 54 and the second semiconductor layer 56. The trenches can be patterned using any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching can be anisotropic.

[0026] The semiconductor fins 62 and nanostructures 64, 66 can be patterned using any suitable method. For example, one or more photolithography processes can be used to pattern the semiconductor fins 62 and nanostructures 64, 66, including dual-patterning processes or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography processes and self-aligned processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used as a mask 58 to pattern the semiconductor fins 62 and nanostructures 64, 66.

[0027] In some embodiments, the semiconductor fin 62 and nanostructures 64, 66 each have a width ranging from 8 nm to 40 nm. In the illustrated embodiment, the semiconductor fin 62 and nanostructures 64, 66 have substantially equal widths in the n-type region 50N and the p-type region 50P. In another embodiment, the semiconductor fin 62 and nanostructures 64, 66 in one region (e.g., the n-type region 50N) are wider or narrower than those in another region (e.g., the p-type region 50P). Furthermore, while each of the semiconductor fins 62 and nanostructures 64, 66 is shown to have a consistently consistent width, in other embodiments, the semiconductor fin 62 and / or nanostructures 64, 66 may have tapered sidewalls, such that the width of each of the semiconductor fins 62 and / or nanostructures 64, 66 continuously increases in the direction toward the substrate 50. In such embodiments, each of the nanostructures 64, 66 may have different widths and be trapezoidal in shape.

[0028] exist Figure 4 In this embodiment, an STI region 72 is formed on the substrate 50 and between adjacent semiconductor fins 62. The STI region 72 is disposed around at least a portion of the semiconductor fins 62 such that at least a portion of the nanostructures 64, 66 protrudes from between adjacent STI regions 72. In the illustrated embodiment, the top surface of the STI region 72 is lower than the top surface of the semiconductor fins 62. In some embodiments, the top surface of the STI region 72 is higher than or flush with (within process variations) the top surface of the semiconductor fins 62.

[0029] The STI region 72 can be formed by any suitable method. For example, an insulating material can be formed on the substrate 50 and the nanostructures 64, 66 and between adjacent semiconductor fins 62. The insulating material can be an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), or a combination thereof, and can be formed by a chemical vapor deposition (CVD) process, such as high-density plasma CVD (HDP-CVD), flowable chemical vapor deposition (FCVD), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In some embodiments, the insulating material is silicon oxide formed by FCVD. Once the insulating material is formed, an annealing process can be performed. In embodiments, the insulating material is formed such that an excess of insulating material covers the nanostructures 64, 66. Although each of the STI regions 72 is shown as a single layer, some embodiments may employ multiple layers. For example, in some embodiments, a pad (not shown separately) can be formed first along the surfaces of the substrate 50, the semiconductor fins 62, and the nanostructures 64, 66. Subsequently, an insulating material such as that described above can be formed on the pad.

[0030] A removal process is then applied to the insulating material to remove excess insulating material over the nanostructures 64, 66. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof may be employed. In some embodiments, the planarization process may expose or remove the mask 58. After the planarization process, the insulating material and the top surfaces of the mask 58 or nanostructures 64, 66 are coplanar (within process variations). Therefore, the top surfaces of the mask 58 (if present) or nanostructures 64, 66 are exposed through the insulating material. In the illustrated embodiment, the mask 58 remains on the nanostructures 64, 66. The insulating material is then recessed to form the STI region 72. The insulating material is recessed such that at least a portion of the nanostructures 64, 66 protrudes between adjacent portions of the insulating material. Furthermore, the top surface of the STI region 72 may have a flat surface (as shown), a convex surface, a concave surface (e.g., a dish shape), or a combination thereof by applying appropriate etching. The insulating material can be recessed using any acceptable etching process, such as a material-selective etching process for the insulating material (e.g., selectively etching the insulating material of the STI region 72 at a faster rate than the materials of the semiconductor fins 62 and nanostructures 64, 66). For example, diluted hydrofluoric acid (dHF) can be used as an etchant to perform oxide removal.

[0031] The previously described process is merely one example of how the semiconductor fins 62 and nanostructures 64, 66 can be formed. In some embodiments, the semiconductor fins 62 and / or nanostructures 64, 66 can be formed using masking and epitaxial growth processes. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes from the dielectric layer to form the semiconductor fins 62 and / or nanostructures 64, 66. The epitaxial structures may include alternating previously described semiconductor materials, such as a first semiconductor material and a second semiconductor material. In some embodiments in which the epitaxial structures are epitaxially grown, the epitaxially grown material can be in-situ doped during growth, which avoids prior and / or subsequent implantation, but in-situ doping and implantation doping can be used together.

[0032] Furthermore, suitable wells (not shown separately) may be formed in the nanostructures 64, 66, the semiconductor fins 62, and / or the substrate 50. These wells may have a conductivity type opposite to that of the source / drain regions subsequently formed in each of the n-type region 50N and the p-type region 50P. In some embodiments, a p-type well is formed in the n-type region 50N, and an n-type well is formed in the p-type region 50P. In some embodiments, either a p-type well or an n-type well is formed in both the n-type region 50N and the p-type region 50P.

[0033] In embodiments with different well types, masks such as photoresists (not shown separately) can be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, a photoresist can be formed over the semiconductor fins 62, nanostructures 64, 66, and STI region 72 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed using a spin-coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, etc., implanted into the region at a concentration of 10. 13 cm -3 Up to 10 14 cm -3 Within the specified range. After injection, the photoresist can be removed, for example, by any acceptable ashing process.

[0034] After or before implantation into the p-type region 50P, a mask, such as a photoresist (not shown separately), is formed over the semiconductor fins 62, nanostructures 64, 66, and STI region 72 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, etc., implanted into the region at a concentration of 10. 13 cm -3 Up to 10 14 cm -3 Within the specified range. After injection, the photoresist can be removed, for example, by any acceptable ashing process.

[0035] Following implantation into the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments where epitaxial structures are grown for semiconductor fins 62 and / or nanostructures 64, 66, the grown material can be in-situ doped during growth, which avoids implantation, but in-situ doping and implantation doping can be used together.

[0036] Figures 5A-17C Various additional steps in manufacturing the embodiment device are shown. Figures 5A-17C Features of either the n-type region 50N or the p-type region 50P are shown. For example, the structure shown can be applied to both the n-type region 50N and the p-type region 50P. Structural differences (if any) between the n-type region 50N and the p-type region 50P are described in the text of each figure. Insulating fins 82 are formed between the semiconductor fins 62, as will be described in more detail later. Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A and Figure 17A The semiconductor fin 62 and the structure formed thereon are shown. Figure 5B , Figure 5C , Figure 6B , Figure 6C , Figure 7B , Figure 7C , Figure 8B , Figure 8C , Figure 9B , Figure 9C , Figure 10B , Figure 10C , Figure 11B , Figure 11C , Figure 12B , Figure 12C , Figure 13B , Figure 13C , Figure 14B , Figure 14C , Figure 15B , Figure 15C , Figure 16B , Figure 16C , Figure 17B and Figure 17C Each of the two semiconductor fins 62, as well as the insulating fin 82 and the STI region 72, is shown in a respective cross-section disposed between the two semiconductor fins 62.

[0037] exist Figures 5A-5C In this process, a sacrificial layer 74 is conformally formed over mask 58, semiconductor fins 62, nanostructures 64 and 66, and STI region 72. The sacrificial layer 74 can be formed of a semiconductor material (e.g., a candidate semiconductor material selected from substrate 50), which can be grown by processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited by processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). For example, the sacrificial layer 74 can be formed of silicon or silicon-germanium.

[0038] exist Figures 6A-6C In this process, the sacrificial layer 74 is patterned to form the sacrificial spacer 76 using an etching process (e.g., dry etching, wet etching, or a combination thereof). The etching process can be anisotropic. As a result of the etching process, portions of the sacrificial layer 74 over the mask 58 and nanostructures 64, 66 are removed, and the STI region 72 between the nanostructures 64, 66 is partially exposed. The sacrificial spacer 76 is disposed over the STI region 72 and further disposed on the sidewalls of the mask 58, semiconductor fins 62, and nanostructures 64, 66.

[0039] In subsequent process steps, a dummy gate layer 84 can be deposited on a portion of the sacrificial spacer 76 (see below). Figures 11A-11C Furthermore, the dummy gate layer 84 can be patterned to provide a dummy gate 94, which includes the lower portion of the sacrificial spacer 76 (see below). Figures 12A-12CThese dummy gates 94 (e.g., patterned portions of the dummy gate layer 84 and portions of the sacrificial spacer 76) can then be replaced with a functional gate stack. Specifically, the sacrificial spacer 76 serves as a temporary spacer during processing to mark the boundaries of the insulating fins, and the sacrificial spacer 76 and nanostructure 64 are subsequently removed and replaced with a gate structure surrounding the nanostructure 66. The sacrificial spacer 76 is formed of a material with high etch selectivity relative to the material of the nanostructure 66. For example, the sacrificial spacer 76 can be formed of the same semiconductor material as the nanostructure 64, such that the sacrificial spacer 76 and the nanostructure 64 can be removed in a single process step. Alternatively, the sacrificial spacer 76 can be formed of a different material than the nanostructure 64.

[0040] Figures 7A to 9C An insulating fin 82 (also known as a hybrid fin or dielectric fin) is shown formed between the sacrificial spacer 76 adjacent to the semiconductor fin 62 and the nanostructures 64, 66. The insulating fin 82 can then be used to form the subsequently formed source / drain regions (see below). Figures 14A-14C They are insulated from each other and physically separated.

[0041] exist Figures 7A-7C In this process, a pad 78A and a filler material 78B are formed on top of the structure. The pad 78A is conformally deposited on the exposed surfaces of the STI region 72, mask 58, semiconductor fins 62, nanostructures 64 and 66, and sacrificial spacer 76 using acceptable deposition processes such as atomic layer deposition (ALD), chemical vapor deposition (CVD), and physical vapor deposition (PVD). The pad 78A can be formed from one or more dielectric materials that have high etch selectivity relative to the etching of the semiconductor fins 62, nanostructures 64 and 66, and sacrificial spacer 76, such as nitrides like silicon nitride, silicon carbonitride, silicon carbonitride oxycarbonate, etc. The pad 78A can reduce oxidation of the sacrificial spacer 76 during the subsequent formation of the filler material 78B, which can be useful during the subsequent removal of the sacrificial spacer 76.

[0042] Next, a filler material 78B is formed on top of the pad 78A to fill the remaining area between the semiconductor fin 62 and the nanostructures 64, 66 that was not filled by the sacrificial spacer 76 or the pad 78A. The filler material 78B can form most of the lower portion of the insulating fin 82 (see [link]). Figures 9A-9C ) so that the subsequently formed source / drain regions (see Figure 14CThey are insulated from each other. The filler material 78B can be formed by an acceptable deposition process such as ALD, CVD, PVD, etc. The filler material 78B can be formed from one or more dielectric materials that have high etch selectivity relative to the etching of semiconductor fins 62, nanostructures 64, 66, sacrificial spacers 76 and pads 78A, such as oxides, such as silicon oxide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, etc., or combinations thereof.

[0043] exist Figures 8A-8C In this process, one or more acceptable planarization processes and / or one or more etching processes can be used to remove the upper portion of the pad 78A and filler material 78B above the top surface of the mask 58. The etching process (one or more) can be selective for the pad 78A and filler material 78B (e.g., selectively etching the pad 78A and filler material 78B at a faster rate than sacrificing the spacer 76 and / or the mask 58). After etching, the top surface of the pad 78A and filler material 78B can be lower than the top surface of the mask 58. This is for illustrative purposes only. Figures 8A-8C The pad 78A and filler material 78B are shown as having flat top surfaces. In other embodiments, the top surfaces of the pad 78A and / or filler material 78B may be concave or convex. In other embodiments, the filler material 78B may be recessed below the top surface of the mask 58, while the pad 78A remains at the same level as the mask 58.

[0044] Figures 9A-9C A dielectric capping layer 80 is shown formed on pad 78A and filler material 78B, thereby forming insulating fins 82. The dielectric capping layer 80 may fill the remaining area above pad 78A, above filler material 78B, and between the sidewalls of mask 58. The dielectric capping layer 80 may be formed by an acceptable deposition process such as ALD, CVD, PVD, etc. The dielectric capping layer 80 may be formed from one or more dielectric materials having high etch selectivity relative to the etching of semiconductor fins 62, nanostructures 64, 66, sacrificial spacer 76, pad 78A, and filler material 78B. For example, the dielectric capping layer 80 may include high-k materials, such as hafnium oxide, zirconium oxide, aluminum zirconium oxide, aluminum hafnium oxide, hafnium silicon oxide, aluminum oxide, etc., or combinations thereof.

[0045] The dielectric capping layer 80 can be formed to initially cover the mask 58 and nanostructures 64, 66. Subsequently, a removal process is applied to remove one or more excess materials from the dielectric capping layer 80. In some embodiments, planarization processes such as CMP, etch-back processes, or combinations thereof can be used. The planarization process exposes the mask 58 such that the top surfaces of the mask 58, the sacrificial spacer 76, and the dielectric capping layer 80 are coplanar (within process variations). In the illustrated embodiment, the mask 58 is retained after the planarization process. In another embodiment, part or all of the mask 58 may also be removed by the planarization process.

[0046] As a result, insulating fins 82 are formed between and in contact with the sacrificial spacers 76. The insulating fins 82 include a liner 78A, a filler material 78B, and a dielectric capping layer 80. The sacrificial spacers 76 space the insulating fins 82 from the nanostructures 64, 66, and the size of the insulating fins 82 can be adjusted by adjusting the thickness of the sacrificial spacers 76.

[0047] exist Figures 10A-10C In this process, an etching process, for example, is used to remove the mask 58. This etching process can be a wet etching that selectively removes the mask 58 without significantly etching the insulating fin 82. This etching process can be anisotropic. Furthermore, this etching process (or a separate selective etching process) can be applied to reduce the height of the sacrificial spacer 76 to a level similar to that of the stacked nanostructures 64, 66 (e.g., the same within a process variation). After etching(one or more), the uppermost surface of the stacked nanostructures 64, 66 and the sacrificial spacer 76 can be exposed and can be below the uppermost surface of the insulating fin 82.

[0048] exist Figures 11A-11CIn this process, a dummy gate layer 84 is formed on the insulating fin 82, the sacrificial spacer 76, and the nanostructures 64, 66. Because the nanostructures 64, 66 and the sacrificial spacer 76 extend below the insulating fin 82, the dummy gate layer 84 can be disposed along the exposed sidewalls of the insulating fin 82. The dummy gate layer 84 can be deposited and then planarized, for example, by CMP. The dummy gate layer 84 can be formed of a conductive or non-conductive material, such as amorphous silicon, polysilicon, poly-SiGe, metal, metal nitride, metal silicide, metal oxide, etc., which can be deposited by physical vapor deposition (PVD), CVD, etc. The dummy gate layer 84 can also be formed of a semiconductor material (e.g., a candidate semiconductor material selected from the substrate 50), which can be grown by processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited by processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The dummy gate layer 84 can be formed of one or more materials that have high etch selectivity relative to the etching of an insulating material (e.g., insulating fin 82). A mask layer 86 can be deposited over the dummy gate layer 84. The mask layer 86 can be formed of a dielectric material such as silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 84 and a single mask layer 86 are formed across the n-type region 50N and the p-type region 50P.

[0049] exist Figures 12A-12C In this process, an acceptable photolithography and etching technique is used to pattern mask layer 86 to form mask 96. The pattern of mask 96 is then transferred to dummy gate layer 84 using any acceptable etching technique to form dummy gate 94. Dummy gate 94 covers the top surface of nanostructures 64, 66 that will be exposed in subsequent processing to form channel regions. The pattern of mask 96 can be used to separate adjacent dummy gate 94 entities. Dummy gate 94 may also have a longitudinal direction substantially perpendicular (within process variations) to the longitudinal direction of semiconductor fin 62. Mask 96 can optionally be removed after patterning, for example by any acceptable etching technique.

[0050] The sacrificial spacer 76 and the dummy gate 94 extend together along a portion of the nanostructure 66 that will be patterned to form the channel region 68. The subsequently formed gate structure will replace the sacrificial spacer 76 and the dummy gate 94. Forming the dummy gate 94 above the sacrificial spacer 76 allows the subsequently formed gate structure to have a greater height.

[0051] As described above, the dummy gate 94 can be formed of a semiconductor material. In such embodiments, the nanostructure 64, the sacrificial spacer 76, and the dummy gate 94 are all formed of a semiconductor material. In some embodiments, the nanostructure 64 and the sacrificial spacer 76 are formed of a first semiconductor material (e.g., silicon-germanium) and the dummy gate 94 is formed of a second semiconductor material (e.g., silicon), such that during a gate replacement process, the dummy gate 94 can be removed in a first etching step, and the nanostructure 64 and the sacrificial spacer 76 can be removed together in a second etching step. When the nanostructure 64 and the sacrificial spacer 76 are formed of silicon-germanium: the nanostructure 64 and the sacrificial spacer 76 can have similar germanium concentrations, the nanostructure 64 can have a greater germanium concentration than the sacrificial spacer 76, or the sacrificial spacer 76 can have a greater germanium concentration than the nanostructure 64. In some embodiments, the nanostructure 64 is formed of a first semiconductor material (e.g., silicon-germanium) and the sacrificial spacer 76 and the dummy gate 94 are formed of a second semiconductor material (e.g., silicon), such that the sacrificial spacer 76 and the dummy gate 94 can be removed together in a first etching step during a gate replacement process, and the nanostructure 64 can be removed in a second etching step.

[0052] Gate spacer 98 is formed on nanostructures 64, 66, and on the exposed sidewalls of mask 96 (if present) and dummy gate 94. Gate spacer 98 can be formed by conformally depositing one or more dielectric materials on dummy gate 94 and subsequently etching the dielectric material(s). Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., which can be formed by conformal deposition processes, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), etc. Other insulating materials formed by any acceptable process can be used. Any acceptable etching process (e.g., dry etching, wet etching, etc., or combinations thereof) can be performed to pattern the dielectric material(s). Etching can be anisotropic. During etching, some portions of the dielectric material(s) remain on the sidewalls of dummy gate 94 (thus forming gate spacer 98). After etching, the gate spacer 98 may have curved sidewalls or straight sidewalls.

[0053] Furthermore, implantation can be performed to form lightly doped source / drain (LDD) regions (not shown separately). In embodiments with different device types, similar to the implantation previously described for wells, a mask such as a photoresist (not shown separately) can be formed over the n-type region 50N while exposing the p-type region 50P, and an impurity of an appropriate type (e.g., p-type) can be implanted into the semiconductor fins 62 and / or nanostructures 64, 66 exposed in the p-type region 50P. The mask can then be removed. Subsequently, a mask such as a photoresist (not shown separately) can be formed over the p-type region 50P while exposing the n-type region 50N, and an impurity of an appropriate type (e.g., n-type) can be implanted into the semiconductor fins 62 and / or nanostructures 64, 66 exposed in the n-type region 50N. The mask can then be removed. The n-type impurity can be any of the previously described n-type impurities, and the p-type impurity can be any of the previously described p-type impurities. During implantation, the channel region 68 remains covered by the dummy gate 94, ensuring that the channel region 68 remains substantially free of impurities implanted to form the LDD region. The LDD region may have 10 15 cm -3 Up to 10 19 cm -3 Impurity concentration within the specified range. Annealing can be used to repair implantation damage and reactivate the implanted impurities.

[0054] Note that previous disclosures generally describe the process for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be employed, additional spacers can be formed and removed, etc. Furthermore, different structures and steps can be used to form n-type and p-type devices.

[0055] exist Figures 13A-13CIn the illustrated embodiment, source / drain recesses 104 are formed in nanostructures 64, 66 and sacrificial spacer 76. In this embodiment, the source / drain recesses 104 extend through nanostructures 64, 66 and sacrificial spacer 76 and into semiconductor fin 62. The source / drain recesses 104 may also extend into substrate 50. In various embodiments, the source / drain recesses 104 may extend to the top surface of substrate 50 without etching substrate 50; semiconductor fin 62 may be etched such that the bottom surface of the source / drain recesses 104 is disposed below the top surface of STI region 72, etc. The source / drain recesses 104 can be formed by etching nanostructures 64, 66 and sacrificial spacer 76 using an anisotropic etching process (e.g., RIE, NBE, etc.). During the etching process used to form the source / drain recesses 104, gate spacer 98 and dummy gate 94 jointly mask portions of semiconductor fin 62 and / or nanostructures 64, 66. Each of the nanostructures 64, 66 and the sacrificial spacer 76 can be etched using a single etching process, or multiple etching processes can be used to etch the nanostructures 64, 66 and the sacrificial spacer 76. A timed etching process can be used to stop etching the source / drain recess 104 after it has reached the desired depth.

[0056] Optionally, internal spacers 106 are formed on the sidewalls of the nanostructure 64, such as those exposed by the source / drain recesses 104. As will be described in more detail later, source / drain regions will subsequently be formed in the source / drain recesses 104, and the nanostructure 64 will subsequently be replaced by a corresponding gate structure. The internal spacers 106 act as an isolation feature between the subsequently formed source / drain regions and the subsequently formed gate structure. Furthermore, the internal spacers 106 can be used to substantially prevent damage to the subsequently formed source / drain regions by subsequent etching processes (e.g., etching processes for the subsequent removal of the nanostructure 64).

[0057] As an example of forming the internal spacer 106, the source / drain recess 104 may extend laterally. Specifically, portions of the sidewalls of the nanostructure 64 exposed by the source / drain recess 104 may be recessed. Although the sidewalls of the nanostructure 64 are shown as recessed, these sidewalls may be straight or convex. The sidewalls may be recessed by an acceptable etching process, such as an etching process selective for the nanostructure 64 (e.g., selectively etching the material of the nanostructure 64 at a faster rate than the material of the nanostructure 66). The etching may be isotropic. For example, when the nanostructure 66 is formed of silicon and the nanostructure 64 is formed of silicon germanium, the etching process may be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. In another embodiment, the etching process may be a dry etching using a fluorine-based gas such as hydrogen fluoride (HF). In some embodiments, the same etching process may be continuously performed to both form the source / drain recess 104 and recess the sidewalls of the nanostructure 64. The internal spacer 106 is then formed on the recessed sidewalls of the nanostructure 64. The internal spacer 106 can be formed by conformally forming an insulating material and subsequently etching that insulating material. The insulating material can be silicon nitride or silicon oxynitride, but any suitable material can be used, such as a low-k dielectric material. The insulating material can be deposited using a conformal deposition process (e.g., ALD, CVD, etc.). The etching of the insulating material can be anisotropic. For example, the etching process can be dry etching, such as RIE, NBE, etc. Although the outer sidewalls of the internal spacer 106 are shown as recessed relative to the sidewalls of the gate spacer 98, the outer sidewalls of the internal spacer 106 can extend beyond or be flush with the sidewalls of the gate spacer 98. In other words, the internal spacer 106 can partially fill, fully fill, or overfill the sidewall recesses. Furthermore, although the sidewalls of the internal spacer 106 are shown as recessed, the sidewalls of the internal spacer 106 can be straight or convex.

[0058] exist Figures 14A-14C In this process, an epitaxial source / drain region 108 is formed in the source / drain recess 104. The epitaxial source / drain region 108 is formed in the source / drain recess 104 such that each dummy gate 94 (and corresponding channel region 68) is disposed between corresponding adjacent pairs of epitaxial source / drain regions 108. In some embodiments, gate spacers 98 and internal spacers 106 are used to separate the epitaxial source / drain regions 108 from the dummy gate 94 and nanostructure 64 by appropriate lateral distances, respectively, such that the epitaxial source / drain regions 108 do not short-circuit with the subsequently formed gate of the resulting nanostructure FET. The material of the epitaxial source / drain regions 108 can be selected to apply stress in the corresponding channel region 68, thereby improving performance.

[0059] The epitaxial source / drain region 108 in the n-type region 50N can be formed by masking the p-type region 50P. Then, the epitaxial source / drain region 108 in the n-type region 50N is epitaxially grown in the source / drain recess 104 in the n-type region 50N. The epitaxial source / drain region 108 can include any acceptable material suitable for an n-type device. For example, if the nanostructure 66 is silicon, the epitaxial source / drain region 108 in the n-type region 50N can include a material on which tensile strain is applied to the channel region 68, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon arsenide, silicon phosphide, etc. The epitaxial source / drain region 108 in the n-type region 50N can be referred to as the "n-type source / drain region". The epitaxial source / drain region 108 in the n-type region 50N can have surfaces protruding from the corresponding surfaces of the semiconductor fins 62 and the nanostructures 64, 66, and can have facets.

[0060] The epitaxial source / drain region 108 in the p-type region 50P can be formed by masking the n-type region 50N. Then, the epitaxial source / drain region 108 in the p-type region 50P is epitaxially grown in the source / drain recess 104 in the p-type region 50P. The epitaxial source / drain region 108 can include any acceptable material suitable for a p-type device. For example, if the nanostructure 66 is silicon, the epitaxial source / drain region 108 in the p-type region 50P can include a material on which compressive strain is applied to the channel region 68, such as silicon germanium, boron-doped silicon germanium, silicon germanium phosphide, germanium, germanium tin, etc. The epitaxial source / drain region 108 in the p-type region 50P can be referred to as the "p-type source / drain region". The epitaxial source / drain region 108 in the p-type region 50P can also have surfaces protruding from the corresponding surfaces of the semiconductor fins 62 and the nanostructures 64, 66, and can have small facets.

[0061] The epitaxial source / drain regions 108, nanostructures 64, 66, and / or semiconductor fins 62 can be implanted with impurities to form source / drain regions, similar to the previously described process for forming LDD regions, followed by annealing. The impurity concentration of the epitaxial source / drain regions 108 can be up to 10⁻⁶. 19 cm -3 Up to 10 21 cm -3 Within the range. The n-type and / or p-type impurities used for the source / drain regions can be any of the previously described impurities. In some embodiments, the epitaxial source / drain regions 108 can be doped in situ during growth.

[0062] The epitaxial source / drain region 108 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 108 may each include a pad layer 108A, a main layer 108B, and a finishing layer 108C (or more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Any number of semiconductor material layers may be used for the epitaxial source / drain region 108. Each of the pad layer 108A, the main layer 108B, and the finishing layer 108C may be formed of different semiconductor materials and may be doped with different impurity concentrations. In some embodiments, the pad layer 108A may have a lower impurity concentration than the main layer 108B, and the finishing layer 108C may have a higher impurity concentration than the pad layer 108A and a lower impurity concentration than the main layer 108B. In an embodiment in which the epitaxial source / drain region includes three semiconductor material layers, a pad layer 108A can be grown in the source / drain recess 104, a main layer 108B can be grown on the pad layer 108A, and a finishing layer 108C can be grown on the main layer 108B.

[0063] As a result of the epitaxial process used to form the epitaxial source / drain regions 108, the upper surface of the epitaxial source / drain regions has small facets that extend laterally outward beyond the sidewalls of the semiconductor fins 62 and nanostructures 64, 66. However, the insulating fins 82 block lateral epitaxial growth. Therefore, adjacent epitaxial source / drain regions 108 remain separated after the epitaxial process is completed, as... Figure 14C As shown. The epitaxial source / drain region 108 contacts the sidewall of the insulating fin 82. In the illustrated embodiment, the epitaxial source / drain region 108 is grown such that the upper surface of the epitaxial source / drain region 108 is disposed below the top surface of the insulating fin 82. In various embodiments, the upper surface of the epitaxial source / drain region 108 is disposed above the top surface of the insulating fin 82; the upper surface of the epitaxial source / drain region 108 has portions disposed above and below the top surface of the insulating fin 82; and so on.

[0064] exist Figures 15A-15C In this process, a first interlayer dielectric (ILD) 114 is deposited over the epitaxial source / drain region 108, gate spacer 98, mask 96 (if present), or dummy gate 94. The first ILD 114 can be formed of a dielectric material, which can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), FCVD, etc. Acceptable dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used.

[0065] In some embodiments, a contact etch stop layer (CESL) 112 is formed between the first ILD 114 and the epitaxial source / drain region 108, gate spacer 98, and mask 96 (if present) or dummy gate 94. The CESL 112 can be formed of a dielectric material having high etch selectivity relative to the etching of the first ILD 114, such as silicon nitride, silicon oxide, silicon oxynitride, etc. The CESL 112 can be formed by any suitable method, such as CVD, ALD, etc.

[0066] exist Figures 16A-16C In this process, a removal process is performed to make the top surface of the first ILD 114 flush with the top surface of the mask 96 (if present) or the dummy gate 94. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), etch-back process, or a combination thereof may be employed. The planarization process may also remove the mask 96 on the dummy gate 94, as well as portions of the gate spacer 98 along the sidewalls of the mask 96. After the planarization process, the gate spacer 98, the first ILD 114, CESL 112, and the top surfaces of the mask 96 (if present) or the dummy gate 94 are coplanar (within process variations). Therefore, the top surface of the mask 96 (if present) or the dummy gate 94 is exposed through the first ILD 114. In the illustrated embodiment, the mask 96 is retained, and the planarization process makes the top surface of the first ILD 114 flush with the top surface of the mask 96.

[0067] exist Figures 17A-17C In the etching process, the mask 96 (if present) and the dummy gate 94 are removed to form the recess 116. In some embodiments, the dummy gate 94 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 94 at a rate faster than the first ILD 114 or the gate spacer 98. Each recess 116 exposes and / or covers a portion of the channel region 68. The portion of the nanostructure 66 that serves as the channel region 68 is disposed between adjacent pairs of epitaxial source / drain regions 108.

[0068] The remaining portion of nanostructure 64 is then removed to enlarge recess 116, thereby forming opening 118 in the region between nanostructures 66. The remaining portion of sacrificial spacer 76 is also removed to enlarge recess 116, thereby forming opening in the region between semiconductor fin 62 and insulating fin 82. The remaining portions of nanostructure 64 and sacrificial spacer 76 can be removed by any acceptable etching process that selectively etches one or more materials of nanostructure 64 and sacrificial spacer 76 at a rate faster than the material of nanostructure 66. The etching can be isotropic. For example, when nanostructure 64 and sacrificial spacer 76 are formed of silicon germanium and nanostructure 66 is formed of silicon, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. In some embodiments, a trimming process (not shown separately) is performed to reduce the thickness of exposed portions of nanostructure 66.

[0069] Figures 18A to 27C A cross-sectional view of a replacement gate formed in a recess 116 according to various embodiments is shown. Figure 18A and Figure 18C The relevant cross-section shows the formation of the gate dielectric in either the n-type region 50N or the p-type region 50P. Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A and Figure 27A A cross-sectional view showing adjacent replacement gates formed in both the n-type region 50N and the p-type region 50P is shown. Furthermore, to improve clarity, Figure 18D , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B , Figure 25B , Figure 26B and Figure 27B A detailed cross-sectional view of region 200N is shown, illustrating the filling of the recesses 116 between nanostructures 64 in the n-type region 50N; and Figure 18E , Figure 19C , Figure 20C , Figure 21C , Figure 22C , Figure 23C , Figure 24C , Figure 25C , Figure 26C and Figure 27CA detailed cross-sectional view of region 200P is shown, illustrating the filling of the recesses 116 between nanostructures 66 in p-type region 50P. In some embodiments, n-type region 50N may be adjacent to p-type region 50P, and insulating fins 82 separate the two regions.

[0070] exist Figures 18A-18E In this process, a gate dielectric layer 124 is formed in the recess 116. The gate dielectric layer 124 is deposited in the recess 116 surrounding the nanostructure 66 in both a first region (e.g., n-type region 50N) and a second region (e.g., p-type region 50P). The gate dielectric layer 124 may also be deposited in the first ILD 114, the gate spacer 98 (see... Figure 18A ) and the top surface of the insulating fin 82. In the illustrated embodiment, the gate dielectric layer 124 is multilayered, such as Figure 18D and Figure 18E The detailed diagram shows an interface layer 124A (or more generally, a first gate dielectric layer) and an overlying high-k dielectric layer 124B (or more generally, a second gate dielectric layer). The interface layer 124A may be formed of silicon oxide, and the high-k dielectric layer 124B may be formed of hafnium oxide, lanthanum oxide, or the like. Methods for forming the gate dielectric layer 124 may include molecular beam deposition (MBD), ALD, PECVD, etc. The gate dielectric layer 124 surrounds all (e.g., four) sides of the second nanostructure 66.

[0071] In some embodiments, the second nanostructure 66 has a width W1 ranging from 1 nm to 50 nm, for example, from 15 nm to 25 nm. In some embodiments, adjacent second nanostructures 66 are spaced apart by a pitch S1 ranging from 0.1 nm to 40 nm, for example, from 3 nm to 8 nm. If the pitch S1 is greater than 40 nm, a seam or gap may form between adjacent second nanostructures 66 after the gate structure is subsequently formed. If the pitch S1 is less than 0.1 nm, adjacent second nanostructures 66 may be prone to short-circuiting with each other.

[0072] exist Figures 19A-19C and Figures 20A-20CIn the process, a sacrificial layer 126 is deposited on the gate dielectric layer 124 in a first region (e.g., n-type region 50N) and a second region (e.g., p-type region 50P). The sacrificial layer 126 may be further deposited on the insulating fin 82. As will be described in more detail later, the sacrificial layer 126 is patterned to remove a portion of the sacrificial layer 126 in the first region (e.g., n-type region 50N), while leaving a portion of the sacrificial layer 126 in the second region (e.g., p-type region 50P). Specifically, the sacrificial layer 126 may be retained between the nanostructures 66 in the p-type region 50P, and the sacrificial layer 126 serves to facilitate the removal of the work function adjustment layer from the second region (e.g., p-type region 50P) by preventing the formation of a work function adjustment layer between the second nanostructures 66 in the second region (e.g., p-type region 50P). It has been observed that the material of the sacrificial layer 126 is more easily removed from between the nanostructures 66 than the work function adjustment layer.

[0073] The sacrificial layer 126 comprises any acceptable material that can be formed on and removed from the second nanostructures 66. For example, the sacrificial layer 126 is made of SiON. x The sacrificial layer 126 can be deposited using a non-conformal deposition process (e.g., a flowable CVD process), which provides an improved bottom-up growth profile and allows the formed sacrificial layer 126 to be without any seams or voids, thereby reducing manufacturing defects. As an example of a flowable CVD process, firstly in... Figures 18A-18C In this process, the precursor flows in the recess 116 within the corresponding flow window of each precursor. For example, the sacrificial layer 126 includes SiON. x In some embodiments, the flowing precursors may include a first precursor as a silane precursor (e.g., silane, trimethylsilaneamine, etc.), a second precursor as a nitrogen-based precursor (e.g., N2, NH3, combinations thereof), and an oxidant (e.g., H2O, O2, O3, combinations thereof). Initially, the precursors can be mixed within their respective respective flow windows. For example, when the precursors are a silane precursor, a nitrogen-based precursor, and an oxidant, the flow windows of each precursor in the initial stage can be 500 sccm to 750 sccm, 300 sccm to 600 sccm, and 50 sccm to 400 sccm, respectively. For example, the precursors can be mixed at a pressure of 0.5 Torr to 1 Torr and a temperature of 30°C to 200°C. By initially mixing the precursors with the above parameters, the sacrificial layer 126 can be deposited in a flowable state to achieve improved gap filling of the recess 116, which has a bottom-up profile and is free of seams and voids.

[0074] After the sacrificial layer 126 is deposited in a flowable state, a hardening process 202 can be performed, such as... Figures 20A-20CAs shown. The curing process 202 may include an oxidation treatment using a mixture of ozone and oxygen. In some embodiments, the ratio of ozone to oxygen may be in the range of 1:10 to 10:1. It has been observed that by adjusting the ratio of ozone to oxygen within the above range, desired flowability and insulation can be obtained in the sacrificial layer 126. Furthermore, the ozone / oxygen mixture treatment can be performed at a pressure of 100 Torr to 600 Torr and a temperature of 50°C to 250°C. Subsequently, curing using ultraviolet (UV) light can be performed to fully cure the sacrificial layer 126. UV curing can be performed at a wavelength in the range of 100 nm to 400 nm and a temperature in the range of 25°C to 150°C. It has been observed that by performing UV curing within the above wavelength and temperature range, desired material characteristics (hardness, stress, and insulation) can be achieved in the sacrificial layer 126.

[0075] exist Figures 21A-21C In this process, portions of the sacrificial layer 126 are removed from a first region (e.g., n-type region 50N) and a second region (e.g., p-type region 50P). Removal can be performed using acceptable etching techniques. Etching can include any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic, and the etching can be selective for the material of the gate dielectric layer 124 (e.g., etching the sacrificial layer 126 at a faster rate than the outermost gate dielectric layer 124, such as a high-k dielectric layer 124B). Figures 21A-21C As shown, in both the first region 50N and the second region 50P, the portion of the sacrificial layer 126 removed removes the exterior of the sacrificial layer 126 to expose the gate dielectric layer 124, but leaves the sacrificial layer 126 between vertically adjacent nanostructures 66 and extending between nanostructures 66 and fins 62. This removal of the exterior of the sacrificial layer 126 while leaving the interior can be called a trimming process.

[0076] After a portion of the sacrificial layer 126 is removed, the gate dielectric layer 124 remains on and covers the isolation region 72 (see example...). Figure 21A These portions of the gate dielectric layer 124 help protect the isolation region 72 from damage during subsequent deposition and removal processes.

[0077] exist Figures 22A-22CIn the second region (e.g., p-type region 50P), a first mask layer 128 is formed in a recess 116 over the sacrificial layer 126 and the insulating fin 82. The first mask layer 128 may be initially deposited in both the first region 50N and the second region 50P by spin coating or the like. The first mask layer 128 may comprise a polymeric material, such as poly(meth)acrylate, poly(maleimide), phenolic varnish, poly(ether), or combinations thereof. In some embodiments, the first mask layer 128 may be a bottom antireflective coating (BARC) material.

[0078] After deposition, the first mask layer 128 is patterned to remove the first mask layer 128 from the first region (e.g., n-type region 50N). The first mask layer 128 can be patterned by photolithography, etching processes such as isotropic or anisotropic etching processes, etc. Patterning the first mask layer 128 can expose the sacrificial layer 126 in the first region (e.g., n-type region 50N). After patterning the first mask layer 128, the first mask layer 128 is used as a mask to remove the sacrificial layer 126 from the first region (e.g., n-type region 50N). Removal can be performed by acceptable etching techniques. Etching can include any acceptable etching process, such as RIE, NBE, wet etching, etc., or combinations thereof. Etching can be anisotropic or isotropic.

[0079] exist Figures 23A-23C In this process, the first mask layer 128 is patterned to remove the remaining portion of the first mask layer 128, such as a portion of the first mask layer 128 in a second region (e.g., p-type region 50P). The first mask layer 128 can be removed by plasma ashing, etching processes such as isotropic or anisotropic etching processes, etc.

[0080] Further as Figures 23A-23CAs shown, in a first region (e.g., n-type region 50N), a gate electrode layer 130 is deposited on a gate dielectric layer 124 surrounding a nanostructure 66, and in a second region (e.g., p-type region 50P), the gate electrode layer 130 is deposited on the gate dielectric layer 124 and the sacrificial layer 126. The gate electrode layer 130 may be further deposited on and along the sidewalls of the insulating fin 82. As will be described in more detail later, the gate electrode layer 130 will be patterned to remove portions of the gate electrode layer 130 in the second region (e.g., p-type region 50P), while leaving portions of the gate electrode layer 130 in the first region (e.g., n-type region 50N). The presence of the sacrificial layer 126 in the second region (e.g., p-type region 50P) prevents the gate electrode layer 130 from being deposited between vertically adjacent nanostructures 66 in the second region. As a result, the gate electrode layer 130 can be more easily removed from the second region (e.g., p-type region 50P) in subsequent processing steps, and manufacturing defects can be reduced.

[0081] The gate electrode layer 130 may include a work function adjustment layer 130A and an adhesive layer 130B, such as Figures 23B-23C A detailed view is shown. When the work function adjustment layer 130A is removed from the second region (e.g., p-type region 50P), it is referred to as an "(one or more) n-type work function adjustment layer". The work function adjustment layer 130A comprises any acceptable material to adjust the work function of the device to the amount required for the application in which the device is to be formed, and can be deposited using any acceptable deposition process. For example, the work function adjustment layer 130A provides an n-type work function adjustment layer and is formed from any combination of n-type work function metals (NWFM), such as titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), TiAlC:N, titanium aluminum nitride (TiAlN), tantalum aluminum silicon (TaSiAl), WCl5, SnCl4, NbCl5, MoCl4, and combinations thereof, which can be deposited by ALD, CVD, PVD, etc. Although the work function adjustment layer 130A is shown as a single-layer structure, in other embodiments the work function adjustment layer 130A may have a multilayer structure.

[0082] The gate electrode layer 130 further includes an adhesive layer 130B formed on the work function adjustment layer 130A in a first region (e.g., n-type region 50N) and a second region (e.g., p-type region 50P). In the illustrated cross-section, in the first region 50N, the adhesive layer 130B may be fused between adjacent second nanostructures 66. The adhesive layer 130B comprises any acceptable material to promote adhesion and prevent diffusion. For example, the adhesive layer 130B may be formed of a metal or metal nitride, such as titanium nitride, aluminum titanium carbide, aluminum tantalum carbide, silicon-doped tantalum aluminum, etc., which can be deposited by ALD, CVD, PVD, etc. In a specific embodiment, the work function adjustment layer 130A comprises TiAl, and the adhesive layer 130B comprises TiN.

[0083] exist Figures 24A-24C In the first region 50N and the second region 50P, a second mask layer 132 is formed in the recess 116 above the adhesive layer 130B. The second mask layer 132 can be similar to the first mask layer 128 described above, and will not be repeated here. Figures 24A-24C As shown, the second mask layer 132 is patterned to remove the second mask layer 132 from the recess 116 in the second region (e.g., p-type region 50P). The second mask layer 132 can be removed by photolithography, etching processes such as isotropic or anisotropic etching processes, etc.

[0084] After patterning the second mask layer 132, Figures 25A-25C In this process, using a second mask layer 132 as a mask, the remaining portions of the work function adjustment layer 130A, adhesive layer 130B, and sacrificial layer 126 are removed from the second region (e.g., p-type region 50P). Removing the remaining portions of the work function adjustment layer 130A, adhesive layer 130B, and sacrificial layer 126 from the second region (e.g., p-type region 50P) extends the recess 116 in the second region to re-expose the gate dielectric layer 124 in the second region (e.g., p-type region 50P). Removal can be performed using acceptable photolithography and etching techniques. Etching can include any acceptable etching process, such as RIE, NBE, wet etching using, for example, ammonium hydroxide (NH4OH), diluted hydrofluoric acid (dHF), or combinations thereof. Etching can be isotropic.

[0085] In some embodiments, a single etch is performed to remove the remaining portions of the work function adjustment layer 130A, the adhesive layer 130B, and the sacrificial layer 126. This single etch can be selective in its application to the materials of the work function adjustment layer 130A, the adhesive layer 130B, and the remaining portions of the sacrificial layer 126 (e.g., selectively etching the materials of the work function adjustment layer 130A, the adhesive layer 130B, and the remaining portions of the sacrificial layer 126 at a faster rate than the materials of one or more of the gate dielectric layer 124). In some embodiments, multiple etch steps / processes are performed to remove the remaining portions of the work function adjustment layer 130A, the adhesive layer 130B, and the sacrificial layer 126. In various embodiments, the remaining portions of the sacrificial layer 126 are more easily removed from between the second nanostructures 66 than the work function adjustment layer / adhesive layer, thus providing better control over the threshold voltage of the adjusted device.

[0086] exist Figures 26A-26C In this process, the second mask layer 132 is patterned to remove the second mask layer 132 from the recess 116 in the first region (e.g., n-type region 50N). The second mask layer 132 can be removed by plasma ashing, etching processes such as isotropic or anisotropic etching processes, etc.

[0087] After removing the second mask layer 132 from the recess 116 in the first region (e.g., n-type region 50N), a work function adjustment layer 134 is deposited on the adhesive layer 130B in the first region (e.g., n-type region 50N) and on the gate dielectric layer 124 in the second region (e.g., p-type region 50P). When the work function adjustment layer 134 is the only work function adjustment layer in the second region (e.g., p-type region 50P), it may be referred to as a "p-type work function adjustment layer". The work function adjustment layer 134 comprises any acceptable material to adjust the work function of the device to the amount required for the application in which the device is to be formed, and can be deposited using any acceptable deposition process. For example, when the work function adjustment layer 134 is a p-type work function adjustment layer, it may be formed from a p-type work function metal (PWFM) such as titanium nitride (TiN), tantalum nitride (TaN), or combinations thereof, which may be deposited by ALD, CVD, PVD, etc. Although the work function adjustment layer 134 is shown as a single layer, in other embodiments, the work function adjustment layer 134 may have a multilayer structure. For example, in other embodiments, the work function adjustment layer 134 includes a titanium nitride (TiN) layer and a tantalum nitride (TaN) layer. The work function adjustment layer 134 is formed to a thickness sufficient to cause partial merging of the work function adjustment layer 134 between the second nanostructures 66 in the second region (e.g., p-type region 50P). The material of the work function adjustment layer 130A is different from the material of the work function adjustment layer 134. For example, the material of the work function adjustment layer 130A has an opposite conductivity type to that of the work function adjustment layer 134. As described above, the work function adjustment layer 130A may be formed of an n-type work function metal (NWFM), and the work function adjustment layer 134 may be formed of a p-type work function metal (PWFM). NWFM is different from PWFM. In some embodiments, after depositing the work function adjustment layer 134, the work function adjustment layer 134 can be patterned and removed from the first region (e.g., the n-type region 50N) using a combination of photolithography and etching, similar to the process described above for removing the gate electrode layer 130 from the second region (e.g., the p-type region 50P).

[0088] exist Figures 27A-27C In this process, a gate fill material 136 is deposited on the work function adjustment layer 134 and the adhesive layer 130B. The gate fill material can be deposited in the recess 116 (e.g., on top of the nanostructure 66) and on and along the sidewalls of the insulating fin 82. The gate fill material 136 comprises any acceptable low-resistance material. For example, the gate fill material 136 can be formed of metals such as tungsten, aluminum, cobalt, ruthenium, combinations thereof, etc., which can be deposited by ALD, CVD, PVD, etc. The gate fill material 136 fills the remaining portion of the recess 116. Figures 27A-27CAs shown in the cross-section, in either the first region 50N or the second region 50P, the gate fill material 136 does not extend between adjacent second nanostructures 66 because the region between adjacent second nanostructures 66 in these two regions has been filled by other layers.

[0089] Gate filler 136 can be initially deposited as overflow recess 116. Subsequently, a removal process is performed to remove excess material from the gate dielectric layer 124, work function adjustment layer 130A, adhesive layer 130B, work function adjustment layer 134, and filler 136, which protrude above the top surface of the first ILD 114 and gate spacer 98, thereby forming Figures 28A-28C The gate structure is shown. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof can be used. The gate dielectric layer 124 has a portion remaining in the recess 116 during planarization (thus forming the gate dielectric of the gate structure). The gate spacer 98, CESL 112, first ILD 114, and the top surface of the gate structure are coplanar (within process variations). The gate structure is a replacement gate for the resulting nanostructure FET and may be referred to as a "metal gate". The gate structure each extends along the top surface, sidewalls, and bottom surface of the channel region 68 of the nanostructure 66. The gate structure fills the region previously occupied by the nanostructure 64, sacrificial spacer 76, and dummy gate 94.

[0090] In some embodiments, isolation region 140 is formed to extend through some gate structures. Isolation region 140 is formed to divide (or “cut”) the gate structures into multiple gate structures, each gate structure including a gate electrode 138 (designated 138N and 138P) and a gate dielectric layer 124. For example, the gate structure in a first region (e.g., n-type region 50N) may include gate electrode 138N (e.g., including work function adjustment layer 130A, adhesive layer 130B, and gate fill material 136) and gate dielectric layer 124, and the gate structure in a second region (e.g., p-type region 50P) may include gate electrode 138P (e.g., including work function adjustment layer 134 and gate fill material 136) and gate dielectric layer 124. Gate structures in different regions of regions 50N and 50P can be separated from each other by isolation region 140 and insulating fins 82. The isolation region 140 can be formed of a dielectric material such as silicon nitride, silicon oxide, or silicon oxynitride, which can be deposited using deposition processes such as CVD or ALD. As an example of forming the isolation region 140, openings can be patterned in a desired gate structure. Any acceptable etching process (e.g., dry etching, wet etching, or combinations thereof) can be performed to pattern the openings. The etching can be anisotropic. One or more layers of dielectric material can be deposited in the openings. A removal process can be performed to remove excess portions of the dielectric material above the top surface of the gate structure, thereby forming the isolation region 140.

[0091] Figures 29A to 30C Further processing steps for forming the gate and source / drain contacts in either region 50N or 50P are shown. Figures 29A-29C In this configuration, the second ILD 144 is deposited over the gate spacer 98, CESL 112, the first ILD 114, and the gate electrode 138. In some embodiments, the second ILD 144 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 144 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., which can be deposited by any suitable method such as CVD, PECVD, etc.

[0092] In some embodiments, an etch stop layer (ESL) 142 is formed between the second ILD 144 and the gate spacer 98, CESL 112, the first ILD 114, and the gate structure. The ESL 142 may include a dielectric material having high etch selectivity relative to the etching of the second ILD 144, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0093] exist Figures 30A-30CIn this process, a gate contact 150 and a source / drain contact 148 are formed to contact the gate electrode 138 and the epitaxial source / drain region 108, respectively. The gate contact 150 is physically coupled and electrically coupled to the gate electrode 138. The source / drain contact 148 is physically coupled and electrically coupled to the epitaxial source / drain region 108.

[0094] As an example of forming the gate contact 150 and the source / drain contact 148, an opening for the gate contact 150 is formed through the second ILD 144 and ESL 142, and an opening for the source / drain contact 148 is formed through the second ILD 144, ESL 142, the first ILD 114, and CESL 112. These openings can be formed using acceptable photolithography and etching techniques. Pads (not shown separately), such as diffusion barrier layers, adhesion layers, etc., and conductive material are formed in the openings. The pads may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the surface of the second ILD 144. The remaining pads and conductive material form the gate contact 150 and the source / drain contact 148 in the openings. The gate contact 150 and the source / drain contact 148 can be formed using different processes or the same process. Although shown to be formed in the same cross-section, it should be understood that each of the gate contact 150 and the source / drain contact 148 can be formed in a different cross-section to avoid short circuits in the contacts.

[0095] Optionally, a metal-semiconductor alloy region 146 is formed at the interface between the epitaxial source / drain region 108 and the source / drain contact 148. The metal-semiconductor alloy region 146 may be a silicide region formed from metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanium region formed from metal germanides (e.g., titanium germanide, cobalt germanide, germanium nickelide, etc.), or a silicon-germanium region formed from both metal silicides and metal germanides. The metal-semiconductor alloy region 146 can be formed before one or more materials of the source / drain contact 148 by depositing metal in the opening of the source / drain contact 148 and then performing a thermal annealing process. The metal can be any metal capable of reacting with the semiconductor material (e.g., silicon, silicon-germanium, germanium, etc.) of the epitaxial source / drain region 108 to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal can be deposited using deposition processes such as ALD, CVD, PVD, etc. After the thermal annealing process, a cleaning process such as wet cleaning can be performed to remove any residual metal from the openings of the source / drain contact 148 (e.g., from the surface of the metal-semiconductor alloy region 146). Then, one or more materials of the source / drain contact 148 can be formed on the metal-semiconductor alloy region 146.

[0096] In various embodiments, alternative gate electrodes are formed for both p-type and n-type devices. In some embodiments, the work function adjustment layer of the n-type device is formed prior to the work function adjustment layer of the p-type device to allow for greater control over the threshold voltage of the resulting device. A method of forming the work function adjustment layer of the n-type device prior to the work function adjustment layer of the p-type device includes forming and patterning a sacrificial layer to prevent the work function adjustment layer of the n-type device from forming between the nanostructures of the p-type device. This helps prevent the work function adjustment layer from remaining on the p-type device, which could degrade the performance of the p-type device. The sacrificial layer can be deposited using a flowable chemical vapor deposition (CVD) method, which provides improved deposition profiles in bottom-up growth. Furthermore, the flowable CVD method can also provide improved gap filling between nanostructures without seams or gaps.

[0097] In some embodiments, a method includes: depositing a sacrificial layer around a first nanostructure and a second nanostructure using a non-conformal deposition process, wherein the first nanostructure is disposed on the second nanostructure and spaced apart from the second nanostructure by a first recess, and wherein the first nanostructure and the second nanostructure are disposed on a semiconductor substrate in a first device region; patterning the sacrificial layer, wherein after patterning the sacrificial layer, a remaining portion of the sacrificial layer is disposed in the first recess between the first nanostructure and the second nanostructure; depositing a first work function adjustment layer on the first nanostructure and the second nanostructure; patterning the first work function adjustment layer to remove a portion of the first work function adjustment layer in the first device region; removing the remaining portion of the sacrificial layer; after removing the remaining portion of the sacrificial layer, depositing a second work function adjustment layer around the first nanostructure and the second nanostructure; and depositing a gate fill material on the second work function adjustment layer. Optionally, in some embodiments, the non-conformal deposition process is a flowable chemical vapor deposition process. Optionally, in some embodiments, depositing the first work function adjustment layer includes: using a sacrificial layer to prevent the deposition of the first work function adjustment layer in the region between the first nanostructure and the second nanostructure. Optionally, in some embodiments, the method further includes: depositing a sacrificial layer around a third nanostructure and a fourth nanostructure using a non-conformal deposition process, wherein, in the second device region, the third nanostructure is disposed on top of the fourth nanostructure and separated from the fourth nanostructure by a second recess, wherein patterning the sacrificial layer includes removing the sacrificial layer from the second device region; and depositing a first work function adjustment layer around the third nanostructure and the fourth nanostructure, wherein, after patterning the first work function adjustment layer, the remaining portion of the first work function adjustment layer is disposed around the third nanostructure and the fourth nanostructure. Optionally, in some embodiments, the first device region is a p-type device region, and wherein the second device region is an n-type device region. Optionally, in some embodiments, the method further includes: depositing a second work function adjustment layer on top of the first work function adjustment layer in the second device region; and patterning the second work function adjustment layer to remove the second work function adjustment layer from the second device region, wherein depositing a gate fill material includes depositing a gate fill material on top of the first work function adjustment layer. Optionally, in some embodiments, depositing the sacrificial layer using a non-conformal deposition process includes depositing the sacrificial layer without seams or voids. Optionally, in some embodiments, the method further includes depositing a gate dielectric layer around the first nanostructure and the second nanostructure, wherein the gate dielectric layer separates the sacrificial layer from the first nanostructure and from the second nanostructure.

[0098] In some embodiments, a method includes: removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess using flowable chemical vapor deposition (CVD); patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure; depositing a first work function metal in the recess; removing the first work function metal and that portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal has a conductivity type opposite to that of the first work function metal; and depositing a fill metal on top of the second work function metal in the recess. Optionally, in some embodiments, the flowable CVD process includes: flowing one or more precursors in the recess to deposit an insulating material in a flowable state in the recess; performing an oxidation process to harden the insulating material; and curing the insulating material using ultraviolet light. Optionally, in some embodiments, the sacrificial layer includes SiON. x The flowable CVD process includes flowing a silane precursor, a nitrogen-based precursor, and an oxidant into a recess. Optionally, in some embodiments, the flowable CVD process includes: flowing the silane precursor at a rate in the range of 500 sccm to 750 sccm; flowing the nitrogen-based precursor at a rate in the range of 300 sccm to 600 sccm; and flowing the oxidant at a rate in the range of 50 sccm to 400 sccm. Optionally, in some embodiments, performing the oxidation treatment includes: exposing the insulating material to a mixture of ozone and oxygen. Optionally, in some embodiments, the ozone to oxygen ratio in the ozone and oxygen mixture is in the range of 1:10 to 10:1. Optionally, in some embodiments, curing the insulating material with ultraviolet light includes: curing the insulating material with ultraviolet light in the wavelength range of 100 nm to 400 nm. Optionally, in some embodiments, the first work function metal is n-type, and the second work function metal is p-type.

[0099] In some embodiments, a method includes: removing a first dummy gate structure to form a first recess, and removing a second dummy gate structure to form a second recess; depositing a sacrificial layer in the first and second recesses using flowable chemical vapor deposition (CVD); patterning the sacrificial layer to remove it from the first recess while leaving a remainder of the sacrificial layer in the second recess, the remainder of the sacrificial layer being disposed between a first nanostructure and a second nanostructure; depositing a first work function metal in the first and second recesses, wherein the sacrificial layer prevents the first work function metal from depositing between the first and second nanostructures; patterning the first work function metal to remove it from the second recess while leaving a remainder of the first work function metal in the first recess; removing the remainder of the sacrificial layer; depositing a second work function metal in the second recess; and depositing a fill metal on top of the first work function metal in the first recess and on top of the second work function metal in the second recess. Optionally, in some embodiments, the second work function metal has a conductivity type opposite to that of the first work function metal. Optionally, in some embodiments, insulating fins are disposed between the first and second recesses. Optionally, in some embodiments, the flowable CVD process includes: flowing one or more precursors in a first recess and a second recess to deposit an insulating material in a flowable state in the first recess and the second recess; performing an oxidation treatment to harden the insulating material; and curing the insulating material using ultraviolet light.

[0100] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0101] Example 1 is a method of forming a semiconductor device, comprising: depositing a sacrificial layer around a first nanostructure and a second nanostructure using a non-conformal deposition process, wherein the first nanostructure is disposed on the second nanostructure and spaced apart from the second nanostructure by a first recess, and wherein the first nanostructure and the second nanostructure are disposed on a semiconductor substrate in a first device region; patterning the sacrificial layer, wherein after patterning the sacrificial layer, a remaining portion of the sacrificial layer is disposed in the first recess between the first nanostructure and the second nanostructure; depositing a first work function adjustment layer on the first nanostructure and the second nanostructure; patterning the first work function adjustment layer to remove a portion of the first work function adjustment layer in the first device region; removing the remaining portion of the sacrificial layer; after removing the remaining portion of the sacrificial layer, depositing a second work function adjustment layer around the first nanostructure and the second nanostructure; and depositing a gate fill material on the second work function adjustment layer.

[0102] Example 2 is the method described in Example 1, wherein the non-conformal deposition process is a flowable chemical vapor deposition process.

[0103] Example 3 is the method of Example 1, wherein depositing the first work function adjustment layer includes: using the sacrificial layer to prevent the deposition of the first work function adjustment layer in the region between the first nanostructure and the second nanostructure.

[0104] Example 4 is the method of Example 1, further comprising: depositing the sacrificial layer around the third nanostructure and the fourth nanostructure using the non-conformal deposition process, wherein, in the second device region, the third nanostructure is disposed on the fourth nanostructure and separated from the fourth nanostructure by a second recess, wherein patterning the sacrificial layer includes removing the sacrificial layer from the second device region; and depositing the first work function adjustment layer around the third nanostructure and the fourth nanostructure, wherein, after patterning the first work function adjustment layer, the remaining portion of the first work function adjustment layer is disposed around the third nanostructure and the fourth nanostructure.

[0105] Example 5 is the method described in Example 4, wherein the first device region is a p-type device region, and wherein the second device region is an n-type device region.

[0106] Example 6 is the method of Example 4, further comprising: depositing the second work function adjustment layer over the first work function adjustment layer in the second device region; and patterning the second work function adjustment layer to remove the second work function adjustment layer from the second device region, wherein depositing the gate fill material includes depositing the gate fill material over the first work function adjustment layer.

[0107] Example 7 is the method described in Example 1, wherein depositing the sacrificial layer using the non-conformal deposition process includes depositing the sacrificial layer without seams or voids.

[0108] Example 8 is the method of Example 1, further comprising: depositing a gate dielectric layer around the first nanostructure and the second nanostructure, wherein the gate dielectric layer separates the sacrificial layer from the first nanostructure and from the second nanostructure.

[0109] Example 9 is a method of forming a semiconductor device, comprising: removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess using flowable chemical vapor deposition (CVD); patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure; depositing a first work function metal in the recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal has a conductivity type opposite to that of the first work function metal; and depositing a fill metal in the recess on top of the second work function metal.

[0110] Example 10 is the method of Example 9, wherein the flowable CVD process includes: flowing one or more precursors in the recess to deposit an insulating material in the recess in a flowable state; performing an oxidation treatment to harden the insulating material; and curing the insulating material using ultraviolet light.

[0111] Example 11 is the method described in Example 10, wherein the sacrificial layer comprises SiON. x Furthermore, the flowable CVD process includes: flowing a silane precursor, a nitrogen precursor, and an oxidant into the recess.

[0112] Example 12 is the method of Example 11, wherein the flowable CVD process includes: flowing the silane precursor at a rate in the range of 500 sccm to 750 sccm; flowing the nitrogen-based precursor at a rate in the range of 300 sccm to 600 sccm; and flowing the oxidant at a rate in the range of 50 sccm to 400 sccm.

[0113] Example 13 is the method of Example 10, wherein performing the oxidation treatment includes exposing the insulating material to a mixture of ozone and oxygen.

[0114] Example 14 is the method described in Example 13, wherein the ratio of ozone to oxygen in the mixture of ozone and oxygen is in the range of 1:10 to 10:1.

[0115] Example 15 is the method of Example 10, wherein curing the insulating material with ultraviolet light includes: curing the insulating material with ultraviolet light in the wavelength range of 100 nm to 400 nm.

[0116] Example 16 is the method described in Example 10, wherein the first work function metal is n-type, and wherein the second work function metal is p-type.

[0117] Example 17 is a method of forming a semiconductor device, comprising: removing a first dummy gate structure to form a first recess, and removing a second dummy gate structure to form a second recess; depositing a sacrificial layer in the first recess and the second recess using flowable chemical vapor deposition (CVD); patterning the sacrificial layer to remove the sacrificial layer from the first recess while leaving a remainder of the sacrificial layer in the second recess, the remainder of the sacrificial layer being disposed between a first nanostructure and a second nanostructure; depositing a first work function metal in the first recess and the second recess, wherein the sacrificial layer prevents the first work function metal from depositing between the first nanostructure and the second nanostructure; patterning the first work function metal to remove the first work function metal from the second recess while leaving the first work function metal in the first recess; removing the remainder of the sacrificial layer; depositing a second work function metal in the second recess; and depositing a fill metal in the first recess over the first work function metal and in the second recess over the second work function metal.

[0118] Example 18 is the method described in Example 17, wherein the second work function metal has an opposite conductivity type to the first work function metal.

[0119] Example 19 is the method described in Example 17, wherein an insulating fin is disposed between the first recess and the second recess.

[0120] Example 20 is the method described in Example 17, wherein the flowable CVD process includes: flowing one or more precursors in the first recess and the second recess to deposit an insulating material in a flowable state in the first recess and the second recess; performing an oxidation treatment to harden the insulating material; and curing the insulating material using ultraviolet light.

Claims

1. A method for forming a semiconductor device, comprising: A non-conformal deposition process is used to deposit a sacrificial layer around a first nanostructure and a second nanostructure, wherein the first nanostructure is disposed on the second nanostructure and separated from the second nanostructure by a first recess, and wherein the first nanostructure and the second nanostructure are disposed on a semiconductor substrate in the first device region. The sacrificial layer is patterned, wherein, after the sacrificial layer is patterned, the remaining portion of the sacrificial layer is disposed in the first recess between the first nanostructure and the second nanostructure; A first work function adjustment layer is deposited on the first nanostructure and the second nanostructure; Pattern the first work function adjustment layer to remove a portion of the first work function adjustment layer in the first device region; Remove the remaining portion of the sacrificial layer; After removing the remaining portion of the sacrificial layer, a second work function adjustment layer is deposited around the first nanostructure and the second nanostructure; and A gate fill material is deposited on top of the second work function adjustment layer. The non-conformal deposition process is a flowable chemical vapor deposition process.

2. The method according to claim 1, wherein, Depositing the first work function adjustment layer includes using the sacrificial layer to prevent the deposition of the first work function adjustment layer in the region between the first nanostructure and the second nanostructure.

3. The method according to claim 1, further comprising: The sacrificial layer is deposited around the third nanostructure and the fourth nanostructure using the non-conformal deposition process, wherein, in the second device region, the third nanostructure is disposed on the fourth nanostructure and separated from the fourth nanostructure by a second recess, wherein patterning the sacrificial layer includes removing the sacrificial layer from the second device region; and A first work function adjustment layer is deposited around the third nanostructure and the fourth nanostructure, wherein, after the first work function adjustment layer is patterned, the remaining portion of the first work function adjustment layer is disposed around the third nanostructure and the fourth nanostructure.

4. The method according to claim 3, wherein, The first device region is a p-type device region, and the second device region is an n-type device region.

5. The method according to claim 3, further comprising: In the second device region, a second work function adjustment layer is deposited on top of the first work function adjustment layer; as well as Patterning the second work function adjustment layer to remove the second work function adjustment layer from the second device region, wherein depositing the gate fill material includes depositing the gate fill material on the first work function adjustment layer.

6. The method according to claim 1, wherein, Depositing the sacrificial layer using the non-conformal deposition process includes depositing the sacrificial layer without seams or voids.

7. The method according to claim 1, further comprising: A gate dielectric layer is deposited around the first nanostructure and the second nanostructure, wherein the gate dielectric layer separates the sacrificial layer from the first nanostructure and the sacrificial layer from the second nanostructure.

8. A method of forming a semiconductor device, comprising: The first dummy gate structure is removed to form a recess around the first nanostructure and the second nanostructure; A sacrificial layer was deposited in the recess using a flowable chemical vapor deposition (CVD) process. The sacrificial layer is patterned to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure; A first work function metal is deposited in the recess; Remove the portion of the first work function metal and the sacrificial layer from the recess; A second work function metal is deposited in the recess, wherein the second work function metal has a conductivity type opposite to that of the first work function metal; as well as A filler metal is deposited on top of the second work function metal in the recess.

9. The method according to claim 8, wherein, The flowable chemical vapor deposition (CVD) process includes: One or more precursors flow in the recess to deposit an insulating material in a flowable state in the recess; Perform an oxidation treatment to harden the insulating material; and The insulating material is cured using ultraviolet light.

10. The method according to claim 9, wherein, The sacrificial layer includes SiON. x Furthermore, the flowable chemical vapor deposition (CVD) process includes: flowing a silane precursor, a nitrogen-based precursor, and an oxidant into the recess.

11. The method according to claim 10, wherein, The flowable chemical vapor deposition (CVD) process includes: The silane precursor was flowed at a rate in the range of 500 sccm to 750 sccm; The nitrogen-based precursor was flowed at a rate in the range of 300 sccm to 600 sccm; and The oxidant is flowed at a rate in the range of 50 sccm to 400 sccm.

12. The method according to claim 9, wherein, Performing the oxidation process includes exposing the insulating material to a mixture of ozone and oxygen.

13. The method according to claim 12, wherein, The ozone-to-oxygen ratio of the ozone and oxygen mixture is in the range of 1:10 to 10:

1.

14. The method according to claim 9, wherein, Curing the insulating material with ultraviolet light includes curing the insulating material with ultraviolet light in the wavelength range of 100 nm to 400 nm.

15. The method according to claim 9, wherein, The first work function metal is of type n, and the second work function metal is of type p.

16. A method of forming a semiconductor device, comprising: The first dummy gate structure is removed to form the first recess, and the second dummy gate structure is removed to form the second recess; A sacrificial layer is deposited in the first recess and the second recess using a flowable chemical vapor deposition (CVD) process; The sacrificial layer is patterned to remove it from the first recess while leaving a portion of the sacrificial layer in the second recess, the remaining portion of the sacrificial layer being disposed between the first nanostructure and the second nanostructure. A first work function metal is deposited in the first recess and the second recess, wherein the sacrificial layer prevents the first work function metal from being deposited between the first nanostructure and the second nanostructure; Patterning the first work function metal to remove the first work function metal from the second recess while leaving the first work function metal in the first recess; Remove the remaining portion of the sacrificial layer; Deposit a second work function metal in the second recess; and Filler metal is deposited on the first work function metal in the first recess and on the second work function metal in the second recess.

17. The method according to claim 16, wherein, The second work function metal has the opposite conductivity type to the first work function metal.

18. The method according to claim 16, wherein, Insulating fins are disposed between the first recess and the second recess.

19. The method of claim 16, wherein, The flowable chemical vapor deposition (CVD) process includes: One or more precursors flow in the first recess and the second recess to deposit insulating material in a flowable state in the first recess and the second recess; Perform an oxidation treatment to harden the insulating material; and The insulating material is cured using ultraviolet light.

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