Method for manufacturing a semiconductor device
By performing precise mask trimming and etching in the boundary regions of semiconductor devices, the problem of polysilicon residue was solved, improving device reliability and process accuracy, and reducing contact failures in metal wiring.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SK HYNIX INC
- Filing Date
- 2022-04-22
- Publication Date
- 2026-07-31
AI Technical Summary
During the manufacturing process of semiconductor devices, polysilicon residue exists at the boundary between the cell region and the peripheral region, affecting the reliability of the device.
Polysilicon residue is reduced by performing precise mask trimming and etching at the boundary region between the cell region and the peripheral region, including selective etching using peripheral open masks and cell open masks to ensure clear definition of the boundary region.
It improves the reliability of semiconductor devices, reduces polysilicon residue, prevents subsequent metal wiring contact failures, and improves the accuracy and efficiency of the process.
Smart Images
Figure CN115249663B_ABST
Abstract
Description
[0001] Cross-reference to related applications
[0002] This application claims priority to Korean Patent Application No. 10-2021-0055217, filed on April 28, 2021, the entirety of which is incorporated herein by reference. Technical Field
[0003] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device including bit lines. Background Technology
[0004] As semiconductor devices become more densely integrated, the design rules for components used in semiconductor devices have been reduced. Furthermore, in the manufacturing methods of highly integrated semiconductor devices, processes for forming bit lines in the cell array region and for forming gate patterns in the peripheral circuit region can be performed simultaneously. Summary of the Invention
[0005] Various embodiments of the present invention provide methods for manufacturing semiconductor devices that can solve the problem of polysilicon residue at the boundary region between the cell region and the peripheral region.
[0006] According to an embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming an insulating layer on a substrate, the substrate including a cell region and a peripheral region; forming an opening in the insulating layer by selectively etching the insulating layer in the cell region; forming a plug conductive layer to fill the opening and cover the insulating layer; etching the plug conductive layer and the insulating layer in the peripheral region using a peripheral open mask covering the cell region; trimming the peripheral open mask to expose the plug conductive layer in a boundary region where the cell region and the peripheral region are in contact with each other; etching the plug conductive layer in the boundary region using the trimmed peripheral open mask; forming a peripheral gate conductive layer on the entire surface of the substrate; and etching the peripheral gate conductive layer using a cell open mask.
[0007] In one embodiment, the present invention can improve the reliability of semiconductor devices by solving the problem of polysilicon residue occurring at the boundary region between the cell region and the peripheral region. Attached Figure Description
[0008] Figure 1 This is a plan view illustrating a semiconductor device according to an embodiment of the present invention.
[0009] Figures 2A to 2P This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
[0010] Figure 3A and Figure 3BThis is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. Detailed Implementation
[0011] Various embodiments will be described with reference to sectional views, plan views, and block diagrams, which serve as schematic representations of the invention. Therefore, the structure of the figures can be modified by manufacturing techniques and / or tolerances. Embodiments of the invention are not limited to the specific structures shown in the figures, but include structural variations that may result from manufacturing processes. Furthermore, the shapes of any regions shown in the schematic figures are intended to illustrate specific examples of the structure of various element regions and are not intended to limit the scope of the invention.
[0012] Figure 1 This is a plan view illustrating a semiconductor device according to an embodiment of the present invention. Figures 2A to 2P This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 3A and Figure 3B This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention.
[0013] like Figure 1 As shown, the semiconductor device includes an active region 13 defined by an isolation layer 12 in a semiconductor substrate. Word lines WL intersecting the active region 13 are formed in the semiconductor substrate.
[0014] The bit line structure BL is formed in a direction perpendicular to the word line WL.
[0015] like Figure 2A As shown, a substrate 11 may be provided, comprising cell regions (CELL) and peripheral regions (PERI). The cell region (CELL) may include word lines, bit lines, capacitors, etc. The cell region (CELL) can be a memory cell region for storing data and can be driven by selecting word lines and bit lines. The peripheral region (PERI) may include a core region and a peripheral circuit region. The peripheral region (PERI) is formed around the cell region (CELL) and is configured as a circuit region for driving and controlling the memory cells.
[0016] The substrate 11 may include an active region 13 defined by an isolation layer 12. The active region 13 may be separated by the isolation layer 12 at a constant interval. Cell regions and peripheral regions may be separated by the isolation layer 12.
[0017] Substrate 11 may be a material suitable for semiconductor processing. Substrate 11 may include a semiconductor substrate. Substrate 11 may be made of a silicon-containing material. Substrate 11 may include, for example, silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, combinations thereof, or multilayers thereof. Substrate 11 may also include other semiconductor materials such as germanium. Substrate 11 may include a III / V cluster semiconductor substrate, for example, a composite semiconductor substrate such as GaAs. Substrate 11 may be a silicon-on-insulator (SOI) substrate.
[0018] The isolation layer 12 can be formed using a shallow trench isolation (STI) process. The STI process is as follows: The substrate 11 is etched to form a separation trench. The separation trench is filled with an insulating material, thereby forming the isolation layer 12. The isolation layer 12 may include, for example, silicon oxide, silicon nitride, or a combination thereof. Chemical vapor deposition (CVD) or other deposition processes can be used to fill the separation trench with the insulating material. Planarization processes such as chemical mechanical polishing (CMP) may be additionally used.
[0019] Next, a buried gate structure BG can be formed in the substrate 11 of the cell region CELL. The buried gate structure BG may include a gate trench 15, a gate insulating layer 16 covering the bottom and sidewalls of the gate trench 15, a buried gate electrode 17 partially filling the gate trench 15 on the gate insulating layer 16, and a gate capping layer 18' formed on the buried gate electrode 17.
[0020] The method for forming the buried grid structure BG is as follows.
[0021] First, a gate trench 15 can be formed in the substrate 11 of the cell region (CELL). The gate trench 15 may have a line shape intersecting the active region 13 and the isolation layer 12. The gate trench 15 can be formed by forming a mask pattern on the substrate 11 and using the mask pattern as an etch mask to perform an etching process. A hard mask layer 14 can be used as an etch barrier for forming the gate trench 15. The hard mask layer 14 may have a shape patterned by the mask pattern. The hard mask layer 14 may cover the entire surface of the substrate in the peripheral region (PERI). The hard mask layer 14 may include silicon oxide. The hard mask layer 14 may be TEOS (tetraethyl orthosilicate). The bottom surface of the gate trench 15 may be located at a horizontal position higher than the bottom surface of the isolation layer 12.
[0022] Although not shown, a portion of the isolation layer 12 of the cell region CELL can be recessed to make the active region 13 below the gate trench 15 protrude. Therefore, a fin-like region (reference numerals omitted) can be formed below the gate trench 15. The fin-like region can be part of the channel region.
[0023] Next, a gate insulating layer 16 can be formed on the bottom surface and sidewalls of the gate trench 15. Before forming the gate insulating layer 16, etching damage on the surface of the gate trench 15 can be repaired. For example, the sacrificial oxide can be removed after forming a sacrificial oxide through thermal oxidation.
[0024] The gate insulating layer 16 can be formed by a thermal oxidation process. For example, the gate insulating layer 16 can be formed by oxidizing the bottom and sidewalls of the gate trench 15.
[0025] In another embodiment, the gate insulating layer 16 can be formed by a deposition method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The gate insulating layer 16 may include, for example, a high-k material, an oxide, a nitride, an oxide nitride, or a combination thereof. High-k materials may include hafnium oxide. Hafnium-containing materials may include, for example, hafnium oxide, hafnium silicon oxide, hafnium silicon oxide nitride, or a combination thereof. In another embodiment, the high-k material may include, for example, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxide nitride, aluminum oxide, or a combination thereof.
[0026] In another embodiment, the gate insulating layer 16 can be formed by depositing a pad polysilicon layer and then subjecting the pad polysilicon layer to free radical oxidation.
[0027] In another embodiment, the gate insulating layer 16 can be formed by forming a pad silicon nitride layer and then subjecting the pad silicon nitride layer to free radical oxidation.
[0028] Next, a buried gate electrode 17 can be formed on the gate insulating layer 16. To form the buried gate electrode 17, a recessing process can be performed after the formation of the conductive layer to fill the gate trench 15. The recessing process can be performed by an etch-back process, or by a chemical mechanical polishing (CMP) process followed by an etch-back process in that sequence. The buried gate electrode 17 may have a groove shape that partially fills the gate trench 15. That is, the upper surface of the buried gate electrode 17 may be located at a lower level than the upper surface of the active region 13. The buried gate electrode 17 may comprise a metal, a metal nitride, or a combination thereof. For example, the buried gate electrode 17 may be formed of titanium nitride (TiN), tungsten (W), or a titanium nitride / tungsten (TiN / W) stack. The titanium nitride / tungsten (TiN / W) stack may have a structure in which titanium nitride is conformally formed and then the gate trench 15 is partially filled with tungsten. The buried gate electrode 17 may be made solely of titanium nitride and may be referred to as a "TiN-only" structure buried gate electrode 17. The buried gate electrode 17 may have a dual-gate structure in which a titanium nitride / tungsten (TiN / W) stack and a polysilicon layer are used.
[0029] Next, capping layers 18 and 18' can be formed on the entire surface of the substrate 11, including the buried gate electrode 17. Capping layers 18 and 18' may include an insulating material. Therefore, capping layers 18 and 18' may be referred to as insulating layers. Capping layers 18 and 18' may include silicon nitride. In another embodiment, capping layers 18 and 18' may include silicon oxide. In yet another embodiment, capping layers 18 and 18' may have a NON (nitride-oxide-nitride) structure.
[0030] The capping layers 18 and 18' can be divided into a gate capping layer 18' that fills the gaps in the gate trench 15 on the buried gate electrode 17 and a protective capping layer 18 that covers the upper surface of the hard mask layer 14. The buried gate structure BG can be formed by the gate insulating layer 16, the buried gate electrode 17, and the gate capping layer 18'. The buried gate structure BG can be referred to as a "word line WL".
[0031] In one embodiment, the upper surface of the protective cover layer 18 may be located at a higher horizontal position than the upper surface of the hard mask layer 14. In this embodiment, the protective cover layer 18 may cover both the hard mask layer 14 and the buried gate structure BG.
[0032] Next, impurity regions (not shown) can be formed on both sides of the buried gate structure BG in the substrate 11. The impurity regions can be formed by a doping process such as embedding. The impurity regions can be referred to as source / drain regions. The impurity regions between adjacent buried gate structures BG can be the regions to which bit line contact plugs will be connected. The impurity regions outside the buried gate structure BG can be the regions to which memory node contact plugs will be connected.
[0033] like Figure 2B As shown, a bit line contact hole 21 can be formed. The bit line contact hole 21 can be disposed between adjacent buried gate structures BG. The bit line contact hole 21 can be formed by etching the protective capping layer 18 and the hard mask layer 14 using a contact mask (not shown). A portion of the substrate 11 can be exposed through the bit line contact hole 21. The bit line contact hole 21 can have a diameter controlled by a predetermined linewidth. The bit line contact hole 21 can have a shape that exposes a portion of the active region 13. The bit line contact hole 21 has a diameter larger than the width of the minor axis of the active region 13. Therefore, in the etching process used to form the bit line contact hole 21, the isolation layer 12 and a portion of the active region 13 can be etched. That is, the isolation layer 12 and the active region 13 below the bit line contact hole 21 can be recessed to a predetermined depth. Therefore, the bottom of the bit line contact hole 21 can extend into the substrate 11.
[0034] like Figure 2CAs shown, a plug conductive layer 22A can be formed on the bit line contact hole 21 and the protective capping layer 18. The plug conductive layer 22A can be applied to the bit line contact and a portion of the bit line structure. The plug conductive layer 22A may include a material that has etch selectivity relative to the protective capping layer 18. The plug conductive layer 22A may include polysilicon. The plug conductive layer 22A may include polysilicon doped with impurities.
[0035] like Figure 2D and Figure 2E As shown, a peripheral open mask 23 can be formed on the plug conductive layer 22A of the cell region CELL. The peripheral open mask 23 is a mask used to open the peripheral region and can cover the boundary region where the cell region CELL and the peripheral region PERI are in contact with each other. The peripheral open mask 23 may include a photoresist.
[0036] Subsequently, the plug conductive layer 22A, protective capping layer 18, and hard mask layer 14 exposed through the peripheral open mask 23 can be etched sequentially. Therefore, the etched plug conductive layer 22B, protective capping layer 18, and hard mask layer 14 may remain on the upper surface of the substrate in which cell regions (CELLs) and boundary regions where cell regions (CELLs) and peripheral regions (PERIs) contact each other can be formed. The substrate 11 can be exposed in the peripheral regions (PERIs).
[0037] like Figures 2F to 2H As shown, the peripheral open mask 23T can be modified. The modified peripheral open mask 23T can expose the plug conductive layer 22B in the boundary region where the cell region CELL and the peripheral region PERI are in contact with each other. That is, the modified peripheral open mask 23T can completely cover the plug conductive layer 22B in the cell region CELL, and selectively expose the plug conductive layer 22B at the boundary region where the cell region CELL and the peripheral region PERI are in contact with each other.
[0038] Subsequently, the cell region CELL, in which the plug conductive layer 22B is exposed by the trimmed peripheral open mask 23T, and the boundary region where the peripheral region PERI contacts it, can be etched. Therefore, the plug conductive layer 22C can remain only in the cell region CELL. An etching process using the trimmed peripheral open mask 23T can be performed to expose the exposed portion of the protective capping layer 18. Therefore, the protective capping layer 18 remains in the boundary region where the cell region CELL and the peripheral region PERI contact each other. The substrate 11 can be exposed in the peripheral region PERI.
[0039] Subsequently, the trimmed peripheral open mask 23T can be removed. The trimmed peripheral open mask 23T can be removed by a stripping process.
[0040] like Figure 2I and Figure 2J As shown, barrier layers 24A and 24B and peripheral gate conductive layer 25A can be sequentially formed on the entire surface of substrate 11, including plug conductive layer 22C.
[0041] Barrier layers 24A and 24B may cover the entire surface of the substrate 11 in the plug conductive layer 22C and the peripheral region PERI. Although not shown, barrier layers 24A and 24B may also be formed on a protective capping layer 18 in the boundary region where the cell region CELL and the peripheral region PERI contact each other. Barrier layers 24A and 24B may comprise a material with etch selectivity relative to the plug conductive layer 22C and the peripheral gate conductive layer 25A. Barrier layers 24A and 24B may comprise an insulating material. Barrier layers 24A and 24B may comprise silicon oxide. Barrier layer 24B in the cell region may act as a separation layer separating the plug conductive layer 22C from the peripheral gate conductive layer 25A in the cell region. In subsequent processes, barrier layer 24B in the cell region may act as an etch stop to prevent damage to the plug conductive layer 22C when etching the peripheral gate conductive layer 25A. Barrier layer 24A in the peripheral region PERI may act as a gate insulating layer.
[0042] like Figures 2K to 2N As shown, a cell opening mask 26 can be formed on the peripheral gate conductive layer 25A of the peripheral region PERI. The cell opening mask 26 is a mask used to open the cell region and can also cover the peripheral region PERI and the boundary region where the cell region CELL and the peripheral region PERI contact each other. That is, the boundary region where the cell region CELL and the peripheral region PERI contact each other can be... Figure 2E Both the peripheral open mask 23 and the unit open mask 26 cover the area. The unit open mask 26 may include photoresist.
[0043] Subsequently, the peripheral gate conductive layer 25A of the cell region CELL can be etched using the cell open mask 26. Thus, a peripheral gate conductive layer 25B can be formed, and the peripheral gate conductive layer 25B can be retained in the peripheral region PERI and the boundary region where the peripheral region PERI and the cell region CELL contact each other. In the etching process using the cell open mask 26, the plug conductive layer 22C is not damaged due to the presence of the barrier layer 24B on the plug conductive layer 22C. For example, the etching process can have etching selectivity relative to the barrier layer 24B, and can be performed under conditions where only the peripheral gate conductive layer 25A can be selectively etched.
[0044] In another embodiment, such as Figure 3A and Figure 3BAs shown, the etching process can be performed after the peripheral gate conductive layer 25B in the boundary region where the cell region CELL and the peripheral region PERI are in contact with each other is exposed by trimming the cell open mask 26.
[0045] Subsequently, the barrier layer 24B of the cell region can be removed. The barrier layer 24B can be removed by a wet etching process, but is not limited to this. The process of removing the barrier layer 24B can be performed while minimizing damage to the plug conductive layer 22C. The process of removing the barrier layer 24B can be performed with etch selectivity relative to the plug conductive layer 22C.
[0046] Therefore, the plug conductive layer 22C can be retained on the substrate 11 of the cell region CELL, and the peripheral gate conductive layer 25B can be retained on the substrate 11 of the peripheral region PERI (e.g., Figure 2M (As shown). Since the boundary region where the cell region CELL and the peripheral region PERI contact is covered by the cell open mask 26, the peripheral gate conductive layer 25B can be retained on the protective cover layer 18.
[0047] Subsequently, the unit open mask 26 can be removed (e.g.) Figure 2N (As shown). The cell open mask 26 can be removed by a stripping process.
[0048] like Figure 2O and Figure 2P As shown, a bit line conductive layer 27A and a patterned hard mask layer 28A can be sequentially formed on the entire surface of a substrate 11, which includes a plug conductive layer 22C and a peripheral gate conductive layer 25B.
[0049] Bit line conductive layer 27A can serve as the bit line of the cell region CELL and the gate electrode of the peripheral region PERI. Bit line conductive layer 27A may include a metal-containing material. Bit line conductive layer 27A may include, for example, a metal, a metal nitride, a metal silicide, or a combination thereof. In one embodiment, bit line conductive layer 27A may include tungsten (W). In another embodiment, bit line conductive layer 27A may include a stack of titanium nitride and tungsten (TiN / W). When bit line conductive layer 27A includes a stack of titanium nitride and tungsten (TiN / W), the titanium nitride may act as a barrier.
[0050] The patterned hard mask layer 28A serves as a bitline hard mask for the cell region (CELL) and a gate hard mask for the peripheral region (PERI). The patterned hard mask layer 28A may include a material with etch selectivity relative to the bitline conductive layer 27A, the plug conductive layer 22C, and the peripheral gate conductive layer 25B. The patterned hard mask layer 28A may include an insulating material. The patterned hard mask layer 28A may include silicon oxide or silicon nitride. In one embodiment, the patterned hard mask layer 28A may be formed of silicon nitride.
[0051] Subsequently, a first pattern mask 29 and a second pattern mask 29' can be formed on the patterned hard mask layer 28A. The first pattern mask 29 defines the bit lines of the cell region CELL. The second pattern mask 29' defines the gate pattern of the peripheral region PERI. The first pattern mask 29 and the second pattern mask 29' can be formed simultaneously, or they can be formed separately through individual processes.
[0052] Subsequently, as Figure 2P As shown, a bit line structure BL can be formed in the cell region CELL, in which bit line contact plugs 22, bit lines 27, and bit line hard masks 28 are stacked. In the peripheral region PERI, a peripheral gate structure PG can be formed, in which a peripheral gate insulating layer 24, a first peripheral gate electrode 25, a second peripheral gate electrode 27', and a peripheral gate hard mask 28' are stacked.
[0053] The bit line structure BL and the peripheral gate structure PG can be formed by etching using a first pattern mask 29 and a second pattern mask 29'. The bit line structure BL can be formed by sequentially etching the patterned hard mask layer 28A, the bit line conductive layer 27A, and the plug conductive layer 22C of the cell region CELL using the first pattern mask 29. The peripheral gate structure PG can be formed by sequentially etching the patterned hard mask layer 28A, the bit line conductive layer 27A, the peripheral gate conductive layer 25B, and the barrier layer 24B of the peripheral region PERI using the second pattern mask 29'.
[0054] The bitline structure BL and the gate structure PG can be formed simultaneously. The pattern hard mask layer 28A, bitline conductive layer 27A, and peripheral gate conductive layer 25B, which are not covered by the first pattern mask 29 and the second pattern mask 29', can be completely removed. Although not shown, after forming the bitline structure BL and the gate structure PG, a thick layer formed at the boundary region between the cell region CELL and the peripheral region PERI is... Figure 2M The thickness of the outer gate conductive layer 25B covered by the cell open mask may be retained.
[0055] Although not shown, as a subsequent process, memory elements can be formed in the cell region and metal wiring can be formed in the cell region and the peripheral region. The word line WL, bit line structure BL, and memory elements in the cell region, and the gate structure PG in the peripheral region, can be electrically connected to the metal wiring via metal wiring contacts.
[0056] As described above, by using a modified peripheral open mask 23T to remove the plug conductive layer 22C disposed at the boundary region where the cell region CELL and the peripheral region PERI contact, the thickness of the polysilicon layer retained in the region where the cell open mask 26 and the peripheral open mask 23 overlap (i.e., the boundary region where the cell region CELL and the peripheral region PERI contact each other) can be reduced. Therefore, by minimizing the thickness of the polysilicon layer retained in the boundary region where the cell region CELL and the peripheral region PERI contact, or by preventing the residue of the polysilicon layer after the patterning process used to form the bit line structure BL and the peripheral gate structure PG, contact failures in subsequent metal wiring can be prevented.
[0057] The invention described above is not limited to the embodiments and accompanying drawings. Those skilled in the art will readily understand that various substitutions, changes, or modifications can be made without departing from the scope of this disclosure.
Claims
1. A method for manufacturing a semiconductor device, the method comprising: An insulating layer is formed on a substrate, the substrate including a unit region and a peripheral region; An opening is formed by selectively etching the insulating layer above the substrate in the cell region; A plug conductive layer is formed to fill the opening and cover the insulating layer; The plug conductive layer and the insulating layer above the substrate in the peripheral region are etched by using an open mask covering the periphery of the cell region; The peripheral open mask is modified to expose the plug conductive layer above the substrate in the boundary region where the cell region and the peripheral region are in contact with each other; The plug conductive layer above the substrate in the boundary region is etched using a modified peripheral open mask; An outer gate conductive layer is formed on the entire surface of the substrate; as well as The peripheral gate conductive layer is etched using a cell open mask.
2. The method of claim 1, further comprising, prior to forming the peripheral gate conductive layer: A barrier layer is formed on the entire surface of the substrate.
3. The method of claim 2, wherein, The barrier layer has etch selectivity relative to the peripheral gate conductive layer and the plug conductive layer.
4. The method of claim 2, wherein, The barrier layer comprises silicon oxide.
5. The method of claim 1, wherein, The peripheral open mask includes a photoresist.
6. The method of claim 1, wherein, Etching the peripheral gate conductive layer using the cell open mask includes: The cell opening mask is formed on the peripheral gate conductive layer above the substrate in the peripheral region; and The peripheral gate conductive layer is etched above the substrate in the boundary region where the cell region and the peripheral region are in contact with each other by using a modified cell open mask.
7. The method of claim 1, wherein, The unit open mask includes a photoresist.
8. The method of claim 1, wherein, The plug conductive layer comprises a material that is etch-selective relative to the insulating layer.
9. The method of claim 1, wherein, The insulating layer comprises silicon nitride.
10. The method of claim 1, wherein, The plug conductive layer comprises polycrystalline silicon.
11. The method of claim 1, wherein, The peripheral gate conductive layer comprises a material that is etch-selective relative to the insulating layer.
12. The method of claim 1, wherein, The peripheral gate conductive layer comprises polycrystalline silicon.
13. The method of claim 1, wherein, The substrate in the cell region includes a buried gate structure.
14. The method of claim 13, wherein, The opening is located between adjacent buried grid structures.
15. The method of claim 13, wherein, The bottom surface of the opening is located at a horizontal position higher than the upper surface of the gate electrode of the buried gate structure.
16. The method of claim 1, further comprising: After etching the peripheral gate conductive layer using the cell open mask. A bit line conductive layer and a bit line hard mask layer are sequentially formed on the entire surface of the substrate. as well as A bit line structure is formed over a substrate in the cell region and a peripheral gate structure is formed over a substrate in the peripheral region by using a pattern mask.
17. The method of claim 16, wherein, The pattern mask includes a first pattern mask and a second pattern mask with different line widths.