Semiconductor package including multiple semiconductor chips

Abstract

A semiconductor package includes a lower redistribution layer, a lower semiconductor die, and a plurality of conductive connection structures attached to the lower redistribution layer. An upper redistribution layer is disposed on the lower semiconductor die and the plurality of conductive connection structures. An upper semiconductor die has an active face corresponding to an active face of the lower semiconductor die and is disposed on the upper redistribution layer. The lower semiconductor die includes a semiconductor substrate having a first surface and a second surface opposite the first surface. An upper wiring structure is disposed on the first surface of the semiconductor substrate. A buried power rail fills a portion of a buried rail hole extending from the first surface toward the second surface. A through via electrode fills a through hole extending from the second surface toward the first surface.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2021-0055052, filed with the Korean Intellectual Property Office on April 28, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to semiconductor packaging, and more specifically, to semiconductor packaging comprising multiple semiconductor chips. Background Technology

[0004] With advancements in the electronics industry, electronic devices have become smaller and lighter. This is at least partly achieved through more integrated semiconductor devices. Furthermore, with the proliferation and development of mobile products, electronic devices are becoming increasingly miniaturized and multifunctional. Summary of the Invention

[0005] A semiconductor package includes a lower redistribution layer having a lower redistribution conductive structure. A lower semiconductor chip and a plurality of conductive connection structures are attached to the lower redistribution layer. An upper redistribution layer has an upper redistribution conductive structure disposed on the lower semiconductor chip and the plurality of conductive connection structures. An upper semiconductor chip having an active surface corresponding to an active surface of the lower semiconductor chip is disposed on the upper redistribution layer. The upper semiconductor chip is electrically connected to the upper redistribution conductive structure. The lower semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite to each other. An upper wiring structure is disposed on the first surface of the semiconductor substrate and is electrically connected to the upper redistribution conductive structure. A buried power track filling a portion of a buried via extends from the first surface of the semiconductor substrate toward its second surface. A through electrode filling a via extends from the second surface of the semiconductor substrate toward the first surface. The through electrode electrically connects the buried power track to the lower redistribution conductive structure.

[0006] A semiconductor package includes a lower redistribution layer having a lower redistribution conductive structure. A lower semiconductor chip and a plurality of conductive connection structures are attached to the lower redistribution layer. An upper redistribution layer has an upper redistribution conductive structure disposed on the lower semiconductor chip and the plurality of conductive connection structures. The upper semiconductor chip is disposed on the upper redistribution layer and electrically connected to the upper redistribution conductive structure. The lower semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite to each other. Buried power tracks extend from the first surface of the semiconductor substrate toward the second surface. Through electrodes extend from the second surface of the semiconductor substrate toward its first surface and electrically connect the buried power tracks to the lower redistribution conductive structure. The lower semiconductor chip is powered via a lower power path generated by the lower redistribution conductive structure, the through electrodes, and the buried power tracks.

[0007] The lower and upper semiconductor chips send and receive signals to each other via internal signal paths generated along the upper redistributed conductive structure, rather than through electricity.

[0008] A semiconductor package includes a lower redistribution layer having a lower redistribution conductive structure. A plurality of external connection terminals are attached to a plurality of external connection pads disposed at the bottom of the lower redistribution layer. A lower semiconductor chip and a plurality of conductive connection structures are attached to the lower redistribution layer. A molding compound surrounds the lower semiconductor chip and the plurality of conductive connection structures on the lower redistribution layer. An upper redistribution layer includes an upper redistribution conductive structure disposed on the lower semiconductor chip, the plurality of conductive connection structures, and the molding compound, the thickness of the upper redistribution layer being less than the thickness of the lower redistribution layer. The upper semiconductor chip has an active surface corresponding to the active surface of the lower semiconductor chip and is disposed on the upper redistribution layer, the upper semiconductor chip being electrically connected to the upper redistribution conductive structure. The lower semiconductor chip includes: a semiconductor substrate having a first surface and a second surface opposite to each other; a plurality of fin-type active regions protruding upward from the first surface of the semiconductor substrate; a gate line extending in a direction intersecting the plurality of fin-type active regions; an upper wiring structure disposed on the gate line and electrically connected to an upper redistribution conductive structure; a passivation layer covering the upper wiring structure; a lower wiring structure covering the second surface of the semiconductor substrate and electrically connected to the lower redistribution conductive structure; a buried power track filling a portion of a buried track hole extending from the first surface of the semiconductor substrate toward the second surface; and a through electrode extending from the second surface of the semiconductor substrate to the first surface and filling a via communicating with the buried track hole, the through electrode electrically connecting the buried power track to the lower redistribution conductive structure. Attached Figure Description

[0009] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a cross-sectional view of the lower semiconductor chip of a semiconductor package according to an exemplary embodiment of the present invention;

[0011] Figures 2A to 2M This is a cross-sectional view illustrating a method for manufacturing a lower semiconductor chip of a semiconductor package according to an exemplary embodiment of the present invention;

[0012] Figures 3A to 3F This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention;

[0013] Figure 4 This is a cross-sectional view of a semiconductor package according to an example embodiment of the present invention;

[0014] Figure 5 This is a cross-sectional view of a semiconductor package according to an example embodiment of the present invention;

[0015] Figure 6 This is a cross-sectional view of the lower semiconductor chip of a semiconductor package according to an exemplary embodiment of the present invention;

[0016] Figure 7 This is a cross-sectional view of a semiconductor package according to an example embodiment of the present invention;

[0017] Figure 8 This is a cross-sectional view illustrating an example embodiment of a semiconductor package according to the present invention; and

[0018] Figure 9 This is a cross-sectional view illustrating the operation of a semiconductor package according to an exemplary embodiment of the present invention. Detailed Implementation

[0019] In describing embodiments of the present disclosure illustrated in the accompanying drawings, specific terminology has been used for clarity. However, this disclosure is not intended to be limited to the specific terminology chosen so far, and it should be understood that each particular element includes all technical equivalents that operate in a similar manner.

[0020] Figure 1 This is a cross-sectional view of the lower semiconductor chip of a semiconductor package according to an exemplary embodiment of the present invention.

[0021] refer to Figure 1 The lower semiconductor chip 100 may include a first semiconductor substrate 110 having a first surface 110a and a second surface 110b opposite to the first surface 110a, and a plurality of fin-type active regions FA protruding upward from the first surface 110a of the first semiconductor substrate 110. The first surface 110a of the first semiconductor substrate 110 may be referred to as the main surface of the first semiconductor substrate 110. The first surface 110a and the second surface 110b of the first semiconductor substrate 110 may extend along a first horizontal direction (X direction) and a second horizontal direction (Y direction).

[0022] Multiple finned active regions FA may protrude upward from the main surface (e.g., the first surface 110a of the first semiconductor substrate 110) in a vertical direction (Z direction). The first semiconductor substrate 110 may include a semiconductor material such as Si or Ge, or a compound semiconductor material such as SiGe, SiC, GaAs, InAs, or InP. The first semiconductor substrate 110 may include conductive regions, such as impurity-doped wells or impurity-doped structures. In some embodiments, the multiple finned active regions FA may be arranged at a certain spacing in a first horizontal direction (X direction) and may extend parallel to each other in a second horizontal direction (Y direction).

[0023] A device isolation film 120 covering the lower portion of the sidewalls of multiple fin-type active regions FA can be formed between the multiple fin-type active regions FA. The multiple fin-type active regions FA can protrude upward from the device isolation film 120 in a fin shape. The device isolation film 120 may include, for example, oxides, nitrides, or oxynitrides.

[0024] On the first semiconductor substrate 110, a plurality of gate lines 140 may extend in a direction intersecting with a plurality of finned active regions FA. In some embodiments, the plurality of gate lines 140 may extend in a first horizontal direction (X direction). A gate insulating film 142 may be disposed between the gate lines 140 and the finned active regions FA. An interlayer insulating layer 145 may cover the device isolation film 120 and the plurality of gate lines 140.

[0025] The gate insulating film 142 may include a silicon oxide film, a high-k dielectric film, or a combination thereof. The high-k dielectric film may include a material with a dielectric constant greater than that of the silicon oxide film. The high-k dielectric film may include a metal oxide or a metal oxynitride. An interface film may be disposed between the gate insulating film 142 and the fin-type active region FA. The interface film may include an oxide film, a nitride film, or an oxynitride film.

[0026] Gate line 140 may have a structure comprising a metal nitride layer, a metal layer, a conductive capping layer, and a gap-filling metal film stacked sequentially. The metal nitride layer and the metal layer may include Ti, Ta, W, Ru, Nb, Mo, and / or Hf. The gap-filling metal film may include a W film or an Al film. Gate line 140 may each include a layer containing a work function metal. The layer containing the work function metal may include Ti, W, Ru, Nb, Mo, Hf, Ni, CO, Pt, Yb, Tb, Dy, Er, and / or Pd. In some embodiments, gate line 140 may each include a TiAlC / TiN / W stacked structure, a TiN / TaN / TiAlC / TiN stacked structure, or a TiN / TaN / TiN / TiAlC / TiN / W stacked structure, but the invention is not limited thereto.

[0027] In some embodiments, the lower semiconductor chip 100 may be a logic semiconductor chip. For example, the lower semiconductor chip 100 may include a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip. A plurality of finned active regions FA and a plurality of gate lines 140 may form a first semiconductor device serving as a CPU, GPU, or AP in the active surface of the first semiconductor substrate 110 or in its first surface 110a.

[0028] In this document, logic semiconductor chips are not memory semiconductor chips, but rather semiconductor chips used to perform logical operations. For example, a logic semiconductor chip may include logic units. Logic units can be configured in various ways to include multiple circuit elements, including transistors, registers, etc. Logic units can be configured to form, for example, AND, NAND, OR, NOR, XOR, XNOR, inverters (INV), adders (ADD), buffers (BUF), delay units (DLY), filters (FIL), multiplexers (MXT / MXIT), OAI (OR / AND / inverter), AO (AND / OR), AOI (AND / OR / inverter), D flip-flops, reset flip-flops, master-slave flip-flops, latches, etc., and logic units can also be configured to form standard units that perform desired logical functions, such as counters, buffers, etc.

[0029] The upper wiring structure SBEOL can be disposed on the interlayer insulating layer 145. The upper wiring structure SBEOL may include a plurality of upper wiring lines 152, a plurality of upper wiring vias 154, a plurality of connection vias 156, and an upper wiring interlayer insulating layer 158 that at least partially surrounds the plurality of upper wiring lines 152 and the plurality of upper wiring vias 154. The plurality of upper wiring vias 154 can electrically connect the upper wiring lines 152 at different vertical heights (e.g., arranged in different wiring layers) to each other. The plurality of connection vias 156 can electrically connect the plurality of upper wiring lines 152 to a plurality of gate lines 140.

[0030] In some embodiments, a portion of the plurality of upper wiring lines 152 may be used as a plurality of lower chip connection pads.

[0031] The multiple top wiring lines 152, multiple top wiring vias 154, and multiple connection vias 156 may include metallic materials such as copper (Cu), aluminum (Al), and tungsten (W). The top wiring interlayer insulation layer 158 may include insulating materials and low-k dielectric layers such as high-density plasma (HDP) oxide films, tetraethyl silicate (TEOS) oxide films, Tonen silazane (TOSZ) films, spin-coated glass (SOG) films, and undoped quartz glass (USG) films.

[0032] Passivation layer 160 may cover the upper wiring structure SBEOL. During the fabrication of a semiconductor package including the lower semiconductor chip 100, passivation layer 160 may serve as an etch stop film. Passivation layer 160 may include, for example, silicon nitride.

[0033] Figure 1The illustration shows that the top surfaces of a plurality of upper wiring lines 152 are completely covered by the upper wiring inter-insulation layer 158 and the passivation layer 160, but the invention is not limited thereto. For example, portions of the upper wiring inter-insulation layer 158 and the passivation layer 160 may be removed, and a portion of the top surface of a portion of the upper wiring lines 152 may be exposed.

[0034] Multiple buried vias (BPRH) can penetrate the device isolation film 120 and extend into the first semiconductor substrate 110. The multiple buried vias (BPRH) can be spaced apart from multiple fin active regions (FA). The multiple buried vias (BPRH) can extend between multiple gate lines 140 and multiple through electrodes 174. Multiple buried power tracks (BPR) can be disposed within the multiple buried vias (BPRH). A buried track insulating layer 132 can be disposed between the buried power tracks (BPR) and the first semiconductor substrate 110.

[0035] The buried track insulating layer 132 may conformally cover the inner surface of the buried track via BPRH. The buried track insulating layer 132 may conformally cover the inner surface of the buried track via BPRH and a portion of the bottom surface of the buried track via BPRH. For example, the buried track insulating layer 132 may extend from between the buried power track BPR and the first semiconductor substrate 110 to between the buried power track BPR and the device isolation film 120. The top end of the buried track insulating layer 132 may contact the lower surface of the gate line 140, or contact the lower surface of the gate line 140 and the lower surface of the interlayer insulating layer 145. The buried track insulating layer 132 may include a nitride. For example, the buried track insulating layer 132 may include silicon nitride.

[0036] The buried electric track barrier (BPR) may include a conductive material such as metal. The buried electric track barrier (BPR) may include a track barrier membrane covering at least a portion of the inner and bottom surfaces of the buried track hole (BPRH), and a track filler layer covering the track barrier membrane and filling at least a portion of the buried track hole (BPRH). For example, the track barrier membrane may include TiN, and the track filler layer may include W or Ru.

[0037] In some embodiments, the buried power track BPR may fill only the lower portion of the buried track hole BPRH, and the buried insulating layer 134 may fill the upper portion of the buried track hole BPRH. The buried track insulating layer 132 may extend from between the buried power track BPR and the first semiconductor substrate 110, through between the buried power track BPR and the device isolation film 120, and reach between the buried insulating layer 134 and the device isolation film 120. The buried insulating layer 134 may comprise silicon oxide, silicon nitride, or a combination thereof.

[0038] A power via 136 penetrating the buried insulating layer 134 may be disposed between the buried power rail BPR and the gate line 140, thereby electrically connecting the buried power rail BPR to the gate line 140. In some embodiments, after forming a power via penetrating the buried insulating layer 134 and exposing the buried power rail BPR on its bottom surface, and then filling the power via with a conductive material for forming a plurality of gate lines 140, the power via 136 may then be integrally formed with any one of the plurality of gate lines 140.

[0039] A through-hole TSH can extend from the second surface 110b of the first semiconductor substrate 110 into the first semiconductor substrate 110. The through-hole TSH can communicate with a buried track via BPRH. In some embodiments, the through-hole TSH can have a tapered shape, wherein its horizontal width decreases as the through-hole TSH extends from the second surface 110b of the first semiconductor substrate 110 into the first semiconductor substrate 110, for example, the horizontal width increases as the through-hole TSH extends toward the second surface 110b of the first semiconductor substrate 110.

[0040] The through-hole TSH can be filled by the through electrode 174 and the through-hole insulating film 172 between the first semiconductor substrate 110 and the through electrode 174.

[0041] The through-hole insulating film 172 may include an oxide film, a nitride film, a carbide film, a polymer film, or a combination thereof. In some embodiments, the through-hole insulating film 172 may be formed using a CVD process. The through-hole insulating film 172 may include a high aspect ratio process (HARP) oxide based on ozone / tetraethyl orthosilicate (O3 / TEOS) formed by a subatmospheric pressure CVD process.

[0042] The through-hole TSH may have a tapered shape, wherein its horizontal width decreases from the second surface 110b of the first semiconductor substrate 110 towards the buried power track BPR. The through electrode 174 may include a conductive plug that contacts the buried power track BPR and extends to the second surface 110b of the first semiconductor substrate 110, and a conductive barrier film that at least partially surrounds the conductive plug. The conductive plug may include copper or tungsten. For example, the conductive plug may include Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W, or W alloys, but the invention is not limited thereto. For example, the conductive plug may include Al, Au, Be, Bi, Co, Cu, Hf, In, Mn, Mo, Ni, Pb, Pd, Pt, Rh, Re, Ru, Ta, Te, Ti, W, Zn, Zr, or may include a stacked structure of two or more of the above materials. The conductive barrier film may include W, WN, WC, Ti, TiN, Ta, TaN, Ru, Ru, Co, Mn, WN, Ni, and / or NiB in a single layer or multiple layers, but the present invention is not limited thereto. The conductive plug and the conductive barrier film may be formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD) processes, but the present invention is not limited thereto.

[0043] A bottom wiring structure (PBEOL) can be disposed on a second surface 110b of a first semiconductor substrate 110. The PBEOL may include a plurality of bottom wiring lines 182, a plurality of bottom wiring vias 184, and a bottom wiring inter-insulating layer 186 at least partially surrounding the plurality of bottom wiring lines 182 and the bottom wiring vias 184. The plurality of bottom wiring vias 184 can electrically connect the plurality of bottom wiring lines 182 to a plurality of through electrodes 174. In some embodiments, when the plurality of bottom wiring lines 182 have two or more wiring layers, a portion of the plurality of bottom wiring vias 184 can electrically connect the plurality of bottom wiring lines 182 located at different vertical heights, for example, the bottom wiring lines 182 may be arranged in different wiring layers.

[0044] A wiring layer refers to an electrical path extending in a plane at the same vertical height. The upper wiring structure (SBEOL) can have more wiring layers than the lower wiring structure (PBEOL). For example, the upper wiring structure (SBEOL) can have at least two wiring layers, and the lower wiring structure (PBEOL) can have at least one wiring layer. The thickness of the upper wiring structure (SBEOL) in the vertical direction (Z-direction) can be greater than the thickness of the lower wiring structure (PBEOL).

[0045] The lower semiconductor chip 100 can send and receive signals, such as data signals and control signals, other than power signals, to an external source through the upper wiring structure SBEOL, and can be supplied with external power through the lower wiring structure PBEOL. Therefore, the upper wiring structure SBEOL can be referred to as a signal wiring structure, and the lower wiring structure PBEOL can be referred to as a power wiring structure. In some embodiments, the lower semiconductor chip 100 can be supplied with power and ground from an external source through the lower wiring structure PBEOL.

[0046] According to an example of the present invention, the lower semiconductor chip 100 can transmit and receive signals such as data signals and control signals other than power signals through an upper wiring structure SBEOL disposed on a first surface 110a of the first semiconductor substrate 110, and can be supplied with external power through a lower wiring structure PBEOL disposed on a second surface 110b of the first semiconductor substrate 110. Therefore, in the lower semiconductor chip 100, signals and power can be provided separately through the upper and lower portions, thus minimizing interference between signals and power. Furthermore, even when the integration density of the lower semiconductor chip 100 increases (e.g., when the width of the multiple fin active regions FA decreases), signals and power can be stably supplied to the lower semiconductor chip 100.

[0047] Figures 2A to 2M This is a cross-sectional view illustrating a method for manufacturing a lower semiconductor chip of a semiconductor package according to an exemplary embodiment of the present invention.

[0048] refer to Figure 2A After forming a buffer layer 112 and a plurality of hard mask patterns 114 on the first semiconductor substrate 110, a portion of the first semiconductor substrate 110 can be removed using the plurality of hard mask patterns 114 to form a plurality of fin active regions FA. In the process of forming a plurality of fin active regions FA, the buffer layer 112 can also be patterned and divided into a plurality of sections.

[0049] The first semiconductor substrate 110 may be a wafer substrate WF, through which multiple lower semiconductor chips can be produced. Multiple finned active regions FA may protrude upward from the first surface 110a of the first semiconductor substrate 110.

[0050] For example, buffer layer 112 may include oxides, nitrides, or oxynitrides. In some embodiments, multiple hard mask patterns 114 may be formed using a pattern density-increasing technique utilizing spacers, such as dual patterning technique (DPT) or quadruple patterning technique (QPT). The multiple hard mask patterns 114 may include a stacked structure having at least two layers comprising different insulating materials, including oxides, nitrides, oxynitrides, polysilicon, and / or carbon-containing films. The carbon-containing film may include spin-coated hard mask (SOH) material. The SOH material may include hydrocarbons or derivatives thereof, wherein the SOH material has a relatively high carbon content of about 85% to about 99% by weight based on the total weight of the SOH material.

[0051] refer to Figure 2B The preliminary device isolation layer 120P can fill the space between multiple finned active regions FA. The preliminary device isolation layer 120P can cover, for example, the sidewalls of multiple finned active regions FA, multiple patterned buffer layers 112, and multiple hard mask patterns 114. In some embodiments, the preliminary device isolation layer 120P can cover the upper surface of the multiple hard mask patterns 114, and then a portion of the preliminary device isolation layer 120P on the top surface of the multiple hard mask patterns 114 can be removed to expose the top surface of the multiple hard mask patterns 114.

[0052] refer to Figure 2C Multiple buried vias BPRH can extend through the preliminary device isolation layer 120P into the first semiconductor substrate 110. The multiple buried vias BPRH can penetrate the preliminary device isolation layer 120P and extend from the first surface 110a of the first semiconductor substrate 110 toward its second surface 110b, but not to its second surface 110b. The multiple buried vias BPRH can be spaced apart from multiple fin active regions FA.

[0053] refer to Figure 2D A covering insulating layer 132P can be formed covering the inner surfaces (e.g., its side and bottom surfaces) of the multiple buried track holes BPRH and the top surface of the preliminary device isolation layer 120P. The covering insulating layer 132P can conformally cover the side and bottom surfaces of the multiple buried track holes BPRH and the top surface of the preliminary device isolation layer 120P. For example, the covering insulating layer 132P can have a thickness of about 5 nm to about 9 nm. The covering insulating layer 132P may include a nitride.

[0054] After forming a track material layer covering the insulating layer 132P and filling multiple buried track holes BPRH, multiple buried electric tracks BPRs that fill a portion of the lower part of the multiple buried track holes BPRH can be formed by removing a portion of the upper part of the track material layer in the multiple buried track holes BPRH.

[0055] The buried electric track (BPR) can include a conductive material such as a metal. The buried electric track (BPR) can include a track barrier film covering a portion of the lower part of the inner side and bottom surface of the buried track hole (BPRH), and a track fill layer covering the track barrier film and filling a portion of the lower part of the buried track hole (BPRH). For example, the track barrier film can include TiN, and the track fill layer can include W or Ru. In some embodiments, the thickness of the track barrier film can be less than the thickness of the covering insulating layer. For example, the track barrier film can have a thickness of about 2 nm to about 6 nm.

[0056] After the buried electric track (BPR) is formed, a buried insulation layer 134 can be formed to fill the upper part of the buried track hole (BPRH). The buried insulation layer 134 may include silicon oxide, silicon nitride, or a combination thereof.

[0057] Let's refer to each other. Figure 2D and Figure 2E The portion covering the insulating layer 132P and the preliminary device isolation layer 120P can form the buried track insulating layer 132 and the device isolation film 120. Multiple fin-shaped active regions FA can protrude upward from the device isolation film 120 in a fin shape.

[0058] For example, a portion of the top surface of the insulating layer 132P covering the preliminary device isolation layer 120P, a portion of the upper part of the preliminary device isolation layer 120P, and a portion of the side surface of the insulating layer 132P covering the upper part of the preliminary device isolation layer 120P (e.g., the upper part of the side surface covering the buried track hole BPRH) can be removed to form the buried track insulation layer 132 and the device isolation film 120. In the process of forming the buried track insulation layer 132 and the device isolation film 120, a portion of the upper part of the buried insulation layer 134 filling the upper part of the plurality of buried track holes BPRH can be removed together.

[0059] refer to Figure 2F Multiple gate lines 140 extending in the X direction can be formed while intersecting with multiple finned active regions FA, and multiple gate insulating films 142 are formed between the multiple finned active regions FA and the multiple gate lines 140.

[0060] In some embodiments, an alternative gate process can be used to form a plurality of gate insulating films 142 and a plurality of gate lines 140, wherein a plurality of dummy gate insulating films and a plurality of dummy gate lines are first formed, the plurality of dummy gate insulating films and a plurality of dummy gate lines can be removed after some subsequent processes have been performed, and then the plurality of gate insulating films 142 and a plurality of gate lines 140 can be formed.

[0061] A power via 136 penetrating the buried insulation layer 134 can be formed between the buried power track BPR and the gate line 140.

[0062] In some embodiments, after forming a power via through the buried insulating layer 134 and exposing the buried power rail BPR on its bottom surface, and then filling the power via with a conductive material for forming a plurality of gate lines 140, the power via 136 can then be integrally formed with any one of the plurality of gate lines 140.

[0063] In some embodiments, a power via 136 can be formed by filling the power via with a conductive material, and then a gate line 140 in contact with the power via 136 can be formed separately.

[0064] refer to Figure 2G An interlayer insulating layer 145 can be formed covering the device isolation film 120 and the plurality of gate lines 140, and then an upper wiring structure SBEOL can be formed on the interlayer insulating layer 145. The upper wiring structure SBEOL may include a plurality of upper wiring lines 152, a plurality of upper wiring vias 154, a plurality of connection vias 156, and an upper wiring interlayer insulating layer 158 that at least partially surrounds the plurality of upper wiring lines 152 and the plurality of upper wiring vias 154. The plurality of upper wiring vias 154 may penetrate at least a portion of the upper wiring interlayer insulating layer 158 and may connect the upper wiring lines 152 disposed on different wiring layers to each other. The plurality of connection vias 156 may connect the plurality of upper wiring lines 152 to the plurality of gate lines 140. In some embodiments, the plurality of connection vias 156 may penetrate the interlayer insulating layer 145 and connect the plurality of upper wiring lines 152 to the plurality of gate lines 140. In some embodiments, a plurality of connection vias 156 may penetrate a portion of the lower part of the upper wiring interlayer insulating layer 158 and the interlayer insulating layer 145, and connect a plurality of upper wiring lines 152 to a plurality of gate lines 140.

[0065] The passivation layer 160 may cover the upper wiring structure SBEOL. The passivation layer 160 may include a material having etch characteristics different from those of the upper wiring inter-insulation layer 158. For example, the upper wiring inter-insulation layer 158 may include silicon oxide, and the passivation layer 160 may include silicon nitride.

[0066] refer to Figure 2H It can be reversed. Figure 2G The resulting structure allows the passivation layer 160 to face the first support substrate 10, and the passivation layer 160 can then be attached to the first support substrate 10. A release film 20 can be disposed between the first support substrate 10 and the passivation layer 160.

[0067] refer to Figure 2IA plurality of through-holes (TSHs) can be formed extending from the second surface 110b of the first semiconductor substrate 110 into the first semiconductor substrate 110. The plurality of through-holes (TSHs) can extend from the second surface 110b of the first semiconductor substrate 110 into a plurality of buried power tracks (BPRs). In some embodiments, the through-holes (TSHs) can have a tapered shape, wherein the horizontal width of the through-holes (TSHs) decreases as the through-holes (TSHs) extend from the second surface 110b of the first semiconductor substrate 110 into the first semiconductor substrate 110.

[0068] Multiple through-hole insulating films 172 can be formed covering the side surfaces of multiple through-hole TSHs, and multiple through electrodes 174 can be formed covering the multiple through-hole insulating films 172 and filling the multiple through-hole TSHs. The multiple through-hole insulating films 172 can conformally cover the side surfaces of the multiple through-hole TSHs. The multiple through electrodes 174 can contact multiple buried power rails (BPRs).

[0069] refer to Figure 2J The lower wiring structure PBEOL can be formed on the second surface 110b of the first semiconductor substrate 110. The lower wiring structure PBEOL may include a plurality of lower wiring lines 182, a plurality of lower wiring vias 184, and a lower wiring inter-insulating layer 186 that at least partially surrounds the plurality of lower wiring lines 182 and the lower wiring vias 184. The plurality of lower wiring vias 184 may penetrate the lower wiring inter-insulating layer 186 and may connect the plurality of lower wiring lines 182 to a plurality of through electrodes 174.

[0070] refer to Figure 2K It can be reversed. Figure 2J The resulting structure allows the lower wiring structure PBEOL to face the dicing film 30, and the lower wiring structure PBEOL can then be attached to the dicing film 30.

[0071] Let's refer to each other. Figure 2K and Figure 2L The first support substrate 10 attached to the release film 20 can be removed from the passivation layer 160.

[0072] refer to Figure 2M It can be done by cutting Figure 2L The resulting structure is used to form multiple lower semiconductor chips 100. Cleaving regions CR can be formed between the multiple lower semiconductor chips 100. Cleaving regions CR can be formed using blade cutting, plasma cutting, or laser cutting. Individual lower semiconductor chips 100 can be separated from the cleaving film 30.

[0073] Figures 3A to 3F This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention.

[0074] refer to Figure 3A The lower redistribution layer 200 can be formed on the second support substrate 40. The lower redistribution layer 200 may include a plurality of lower redistribution insulating layers 210 and lower redistribution conductive structures 220. The lower redistribution conductive structures 220 may include a plurality of lower redistribution line patterns 222 and a plurality of lower redistribution vias 224, wherein the plurality of lower redistribution line patterns 222 may be disposed on at least one surface of the top and bottom surfaces of each of the plurality of lower redistribution insulating layers 210, and the plurality of lower redistribution vias 224 may penetrate at least one of the plurality of lower redistribution insulating layers 210 to contact and connect with a portion of the plurality of lower redistribution line patterns 222 respectively.

[0075] Each of the plurality of under-redistribution insulating layers 210 may include a material film comprising, for example, an organic compound. In some embodiments, the plurality of under-redistribution insulating layers 210 may include a material film comprising an organic polymer material. For example, each of the plurality of under-redistribution insulating layers 210 may include a photoimageable dielectric (PID), an Ajinomoto laminate (ABF), or a photosensitive polyimide (PSPI).

[0076] The plurality of lower redistribution line patterns 222 and the plurality of lower redistribution vias 224 may comprise metal or an alloy thereof. In some embodiments, the plurality of lower redistribution vias 224 may have a tapered shape, wherein their horizontal width decreases from their top side to their bottom side. At least a portion of the plurality of lower redistribution line patterns 222 may be integrally formed with a portion of the plurality of lower redistribution vias 224. In some embodiments, a portion of the plurality of lower redistribution line patterns 222 may be integrally formed with a portion of the plurality of lower redistribution vias 224, wherein the portion of the lower redistribution vias covers the lower side of the portion of the plurality of lower redistribution line patterns 222. In some embodiments, a portion of the plurality of lower redistribution line patterns 222 may be integrally formed with a portion of the plurality of lower redistribution vias 224, wherein the portion of the lower redistribution vias covers the upper side of the portion of the plurality of lower redistribution line patterns 222.

[0077] The lower redistribution seed layer 226 may be disposed between a plurality of lower redistribution line patterns 222 and a plurality of lower redistribution insulating layers 210, and between a plurality of lower redistribution vias 224 and a plurality of lower redistribution insulating layers 210. In some embodiments, the lower redistribution seed layer 226 may be disposed between each bottom surface of a plurality of lower redistribution line patterns 222 and a plurality of lower redistribution vias 224 and any lower redistribution insulating layer of a plurality of lower redistribution insulating layers 210, and between the side surfaces of a plurality of lower redistribution vias 224 and any lower redistribution insulating layer of a plurality of lower redistribution insulating layers 210.

[0078] For example, the lower redistribution seed layer 226 can be formed by performing PVD, and multiple lower redistribution line patterns 222 and multiple lower redistribution vias 224 can be formed by performing electroplating or electroless plating using the lower redistribution seed layer 226 as a seed. The lower redistribution seed layer 226 can be, for example, copper (Cu), titanium (Ti), titanium-tungsten (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), chromium (Cr), and / or aluminum (Al).

[0079] In some embodiments, the lower redistribution layer 200 may further include a plurality of external connection pads 242 disposed at the lower portion of the lower redistribution layer 200. For example, the plurality of external connection pads 242 may first be formed on the second support substrate 40, and then a plurality of lower redistribution insulating layers 210 and lower redistribution conductive structures 220 may be formed. The plurality of external connection pads 242 may be electrically connected to the lower redistribution conductive structures 220.

[0080] In some embodiments, the lower redistribution layer 200 may not include a plurality of external connection pads 242, and a portion of the plurality of lower redistribution line patterns 222 and the plurality of lower redistribution vias 224 may be used as a plurality of external connection pads.

[0081] In some embodiments, the lower redistribution layer 200 may further include a plurality of lower connection pads 244 disposed at the upper portion of the lower redistribution layer 200. In some embodiments, the plurality of external connection pads 242 and the plurality of lower connection pads 244 may comprise a material that is the same as or similar to the lower redistribution line pattern 222. For example, the plurality of lower connection pads 244 electrically connected to the lower redistribution conductive structure 220 may be formed on the plurality of lower redistribution insulating layers 210 and the lower redistribution conductive structure 220.

[0082] In some embodiments, the lower redistribution layer 200 may not include a plurality of lower connection pads 244, and a portion of the plurality of lower redistribution line patterns 222 may be used as a plurality of lower connection pads.

[0083] refer to Figure 3B Multiple conductive connection structures 310 and the lower semiconductor chip 100 can be attached to the lower redistribution layer 200. The multiple conductive connection structures 310 can be attached to a portion of the multiple lower connection pads 244. The lower semiconductor chip 100 can be attached to some of the other lower connection pads 244. The top surfaces of the multiple conductive connection structures 310 can be located at a higher vertical height than the top surface of the lower semiconductor chip 100 (e.g., the top surface of the passivation layer 160).

[0084] In some embodiments, the plurality of conductive connection structures 310 may be directly attached to a portion of the plurality of lower connection pads 244. For example, each of the plurality of conductive connection structures 310 may include a through-hole (TMV), conductive solder, conductive pillar, or at least one conductive bump. In some embodiments, each of the plurality of conductive connection structures 310 may include a copper pillar.

[0085] Multiple first chip connection terminals 190 may be disposed between the lower semiconductor chip 100 and multiple lower connection pads 244. The multiple first chip connection terminals 190 may connect a portion of the multiple lower wiring lines 182 of the lower semiconductor chip 100 to the multiple lower connection pads 244. For example, the multiple first chip connection terminals 190 may include bumps or solder balls.

[0086] refer to Figure 3C A first molding element 320 covering multiple conductive connection structures 310 and the lower semiconductor chip 100 may be formed on the lower redistribution layer 200. The first molding element 320 may include, for example, an epoxy molding compound (EMC). In some embodiments, the first molding element 320 may fill the space between the lower redistribution layer 200 and the lower semiconductor chip 100, and may enclose multiple first chip connection terminals 190.

[0087] In some embodiments, an underfill layer may first be formed encapsulating a plurality of first chip connection terminals 190 between the lower redistribution layer 200 and the lower semiconductor chip 100, and then a first molding 320 may be formed. The underfill layer may include, for example, an epoxy resin formed by a capillary underfill method. Alternatively, the underfill layer may include a non-conductive film (NCF).

[0088] refer to Figure 3D A planarization process can be performed until the passivation layer 160 of the underlying semiconductor chip 100 is exposed, and as a result, the upper portions of the first molding 320 and the plurality of conductive connection structures 310 can be removed. The top surfaces of the first molding 320, the plurality of conductive connection structures 310, and the underlying semiconductor chip 100 can be located at the same vertical height to be coplanar. For example, the top surfaces of the first molding 320, the plurality of conductive connection structures 310, and the passivation layer 160 can be located at the same vertical height to be coplanar.

[0089] refer to Figure 3EThe upper redistribution layer 400 can be formed on the first molding part 320. The upper redistribution layer 400 may include at least one upper redistribution insulating layer 410 and an upper redistribution conductive structure 420. The upper redistribution conductive structure 420 may include a plurality of upper redistribution line patterns 422 and a plurality of upper redistribution vias 424, wherein the plurality of upper redistribution line patterns 422 may be disposed on at least one surface of the top and bottom surfaces of each of the plurality of upper redistribution insulating layers 410, and the plurality of upper redistribution vias 424 may penetrate at least one upper redistribution insulating layer 410 to contact and connect with a portion of the plurality of upper redistribution line patterns 422 respectively. At least a portion of the plurality of upper redistribution line patterns 422 may be integrally formed with a portion of the plurality of upper redistribution vias 424.

[0090] In some embodiments, the plurality of upper redistribution vias 424 may have a tapered shape, wherein their horizontal width decreases from their top side to their bottom side. For example, the horizontal width of the plurality of upper redistribution vias 424 may increase as the vias 424 move away from the lower semiconductor chip 100.

[0091] The upper redistribution seed layer 426 can be disposed between a plurality of upper redistribution line patterns 422 and at least one upper redistribution insulating layer 410, and between a plurality of upper redistribution vias 424 and at least one upper redistribution insulating layer 410.

[0092] A portion of the plurality of upper redistribution vias 424 can be connected to the upper wiring structure SBEOL via passivation layer 160. For example, a portion of the plurality of upper redistribution vias 424 can be connected to a portion of the plurality of upper wiring lines 152.

[0093] Each of the upper redistribution insulating layer 410, upper redistribution line pattern 422, upper redistribution via 424, and upper redistribution seed layer 426 may be made of the same or similar material as each of the lower redistribution insulating layer 210, lower redistribution line pattern 222, lower redistribution via 224, and lower redistribution seed layer 226, and may have a generally similar shape, such that a detailed description thereof may be omitted. It is understood that elements not described herein are at least similar to corresponding elements described elsewhere in this specification.

[0094] In some embodiments, the number of stacked upper redistribution insulating layers 410 in the upper redistribution layer 400 may be less than the number of stacked lower redistribution insulating layers 210 in the lower redistribution layer 200. In some embodiments, the upper redistribution layer 400 may have fewer wiring layers compared to the lower redistribution layer 200. In some embodiments, the thickness of the upper redistribution layer 400 may be less than the thickness of the lower redistribution layer 200.

[0095] The lower redistribution layer 200, the upper redistribution layer 400, the lower semiconductor chip 100 between the lower redistribution layer 200 and the upper redistribution layer 400, the multiple conductive connection structures 310 and the first molding 320 can be collectively referred to as the lower package LP.

[0096] refer to Figure 3F The upper package UP can be attached to the lower package LP. The upper package UP may include at least one upper semiconductor chip 500. In some embodiments, the upper package UP may also include a second molding 580 that at least partially surrounds the at least one upper semiconductor chip 500.

[0097] The upper semiconductor chip 500 may include a second semiconductor substrate 510 and a plurality of upper chip connection pads 520, wherein the upper semiconductor device 512 is disposed on the active surface of the second semiconductor substrate 510, and the plurality of upper chip connection pads 520 are disposed on the active surface of the second semiconductor substrate 510. The upper package UP may be attached to the lower package LP, wherein the active surface of the upper semiconductor chip 500 on which the upper semiconductor device 512 is disposed faces the lower package LP. The active surfaces of the upper semiconductor chip 500 and the lower semiconductor chip 100 may face each other.

[0098] The second semiconductor substrate 510 may include a semiconductor material such as Si or Ge, or a compound semiconductor material such as SiGe, SiC, GaAs, InAs, or InP. The second semiconductor substrate 510 may include conductive regions, such as impurity-doped wells or impurity-doped structures.

[0099] In some embodiments, the upper semiconductor chip 500 may be a logic semiconductor chip. For example, the upper semiconductor chip 500 may include a CPU chip, a GPU chip, or an AP chip, and the second semiconductor element 512 may be used as a CPU, GPU, or AP.

[0100] In some embodiments, the upper semiconductor chip 500 may be a memory semiconductor chip. For example, the upper semiconductor chip 500 may include a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a flash memory chip, an electrically erasable programmable read-only memory (EEPROM) chip, a phase-change random access memory (PRAM) chip, a magnetic random access memory (MRAM) chip, or a resistive random access memory (RRAM) chip.

[0101] In some embodiments, when the upper package UP has a plurality of upper semiconductor chips 500, some of the plurality of upper semiconductor chips 500 may be CPU chips, GPU chips or AP chips, and some of the other chips 500 may be memory semiconductor chips.

[0102] In some embodiments, a plurality of second chip connection terminals 550 may be disposed between the upper semiconductor chip 500 and the upper redistribution layer 400. The plurality of second chip connection terminals 550 may connect a portion of a plurality of upper redistribution line patterns 422 to a plurality of upper chip connection pads 520.

[0103] Figure 3F The second molding 580 is shown directly covering the top surface of the upper redistribution layer 400, but the invention is not limited thereto. In some embodiments, the upper package UP may include a package substrate, an upper semiconductor chip 500 attached to the package substrate, a second molding 580 covering the package substrate and encapsulating the upper semiconductor chip 500, and a plurality of second chip connection terminals 550 disposed between the package substrate and the upper redistribution layer 400.

[0104] In some embodiments, a portion of the plurality of upper redistribution line patterns 422 may directly contact and be electrically connected to a plurality of upper chip connection pads 520. For example, a portion of the plurality of upper redistribution line patterns 422 and the plurality of upper chip connection pads 520 may come into contact with each other through thermal expansion, and then a plurality of coupling pads may be formed by diffusion bonding, in which metal atoms diffuse into a single unit.

[0105] Figure 4 This is a cross-sectional view illustrating an example embodiment of a semiconductor package according to a concept of the present invention.

[0106] Let's refer to each other. Figure 3F and Figure 4 Multiple external connection pads 242 can be exposed by removing the second support substrate 40 from the lower redistribution layer 200. Multiple external connection terminals 600 can be attached to the multiple external connection pads 242 to form a semiconductor package 1.

[0107] Semiconductor package 1 may be a stacked package (PoP) in which an upper package UP is attached to a lower package LP. The lower package LP may include a lower semiconductor chip 100 attached to a lower redistribution layer 200, a plurality of conductive connection structures 310, a first molding 320 at least partially surrounding the plurality of conductive connection structures 310 and the lower semiconductor chip 100, and an upper redistribution layer 400. The lower package LP may be a fan-out wafer-level package (FOWLP). The upper semiconductor package UP may include an upper semiconductor chip 500 and a second molding 580 at least partially surrounding the upper semiconductor chip 500. The upper package UP may be attached to the lower package LP such that the active surface of the upper semiconductor chip 500 faces the active surface of the lower semiconductor chip 100.

[0108] The lower semiconductor chip 100 and the upper semiconductor chip 500 can be configured such that their active surfaces face each other, and can transmit and receive signals other than electrical signals, such as data signals and control signals, through the upper redistribution conductive structure 420 of the upper redistribution layer 400. Therefore, the lower semiconductor chip 100 and the upper semiconductor chip 500 can transmit and receive signals to each other at a faster speed and with a wider bandwidth.

[0109] The lower semiconductor chip 100 can be powered from an external source via a plurality of buried power rails (BPRs), a plurality of through electrodes 174, and the lower redistribution conductive structure 220 of the lower redistribution layer 200. In some embodiments, the lower semiconductor chip 100 can be powered from an external source via a plurality of buried power rails (BPRs), a plurality of through electrodes 174, a lower wiring structure (PBEOL), and the lower redistribution conductive structure 220 of the lower redistribution layer 200. The upper semiconductor chip 500 can be powered from an external source via the upper redistribution conductive structure 420 of the upper redistribution layer 400, a portion of a plurality of conductive connection structures 310, and the lower redistribution conductive structure 220 of the lower redistribution layer 200.

[0110] At least one of the lower semiconductor chip 100 and the upper semiconductor chip 500 can send signals to and receive signals from an external source via the upper redistribution conductive structure 420 of the upper redistribution layer 400, some other conductive connection structures among the plurality of conductive connection structures 310, and the lower redistribution conductive structure 220 of the lower redistribution layer 200.

[0111] In the semiconductor package 1, according to the present invention, the lower semiconductor chip 100 can send and receive signals from the upper semiconductor chip 500 via its top surface, and can be supplied with external power via its bottom surface, thereby shortening the signal transmission path between the lower semiconductor chip 100 and the upper semiconductor chip 500 and reducing power loss. Therefore, the lower semiconductor chip 100 and the upper semiconductor chip 500 can send and receive signals to each other at a faster speed and with a wider bandwidth, thereby improving the operating speed of the semiconductor package 1. Furthermore, in the semiconductor package 1, the signal transmission path and the power transmission path can be separated to avoid signal interference caused by power and reduce power loss, thus increasing the operational reliability of the semiconductor package 1.

[0112] Figure 5 This is a cross-sectional view illustrating an example embodiment of a semiconductor package according to a concept based on the present invention. For example, in Figure 5 In, with Figures 1 to 4 The same reference numerals may denote the same or similar components, and repeated descriptions may be omitted.

[0113] refer to Figure 5Semiconductor package 2 can be a stacked package, wherein the upper package UP is located on the lower package LPa. The lower package LPa may include an extension layer 300 attached to the lower redistribution layer 200 and having a mounting space 360G, a lower semiconductor chip 100 housed in the mounting space 360G and attached to the lower redistribution layer 200, a first molding 380 at least partially surrounding the lower semiconductor chip 100 and filling the mounting space 360G, and an upper redistribution layer 400. The lower package LPa may be a fan-out panel-level package (FOPLP). The upper semiconductor package UP may include an upper semiconductor chip 500 and a second molding 580 at least partially surrounding the upper semiconductor chip 500. The upper package UP may be attached to the lower package LPa such that the active surface of the upper semiconductor chip 500 faces the active surface of the lower semiconductor chip 100.

[0114] The extension layer 300 may at least partially surround the periphery of at least one semiconductor chip 100. In some embodiments, the extension layer 300 may be a panel. The horizontal width and horizontal area of ​​the mounting space 360G may be greater than the horizontal width and horizontal area of ​​the lower semiconductor chip 100, respectively. The side surfaces of the lower semiconductor chip 100 may be spaced apart from the inner side surfaces of the mounting space 360G.

[0115] The extension layer (300) may include, for example, a printed circuit board (PCB), a ceramic substrate, a wafer for manufacturing a package, or an interposer. In some embodiments, the extension layer 300 may include a multilayer printed circuit board. A mounting space 360G may be formed in the extension layer 300 as an opening or cavity. The mounting space 360G may be formed in a portion of the extension layer 300, for example, in a central region. The mounting space 360G may be recessed or open from the top surface of the extension layer 300 to a predetermined depth. To make the extension layer 300 recessed or open, dry etching, wet etching, screen printing, drilling, or laser drilling processes may be used.

[0116] In some embodiments, the extension layer 300 may include a substrate 360 ​​and a plurality of conductive connection structures 370 extending through the substrate 360.

[0117] The substrate 360 ​​may include phenolic resin, epoxy resin, and / or polyimide. The substrate 360 ​​may include, for example, flame retardant 4 (FR-4), tetrafunctional epoxy resin, polyphenylene ether, epoxy resin / polyphenylene oxide, bismaleimide triazine (BT), thermosetting resin, cyanate ester, polyimide, and / or liquid crystal polymer.

[0118] Each of the plurality of conductive connection structures 370 may include a plurality of wiring patterns 372 extending in a horizontal direction (X and / or Y direction) and a plurality of conductive vias 374 extending in a vertical direction (Z direction). The plurality of conductive connection structures 370 may include copper, nickel, stainless steel or beryllium copper.

[0119] In some embodiments, the extended layer 300 may be a multilayer substrate, wherein the substrate base 360 ​​is formed in a multilayer configuration. A plurality of wiring patterns 372 in the extended layer 300 may be disposed on at least a portion of the top and bottom surfaces of the plurality of layers forming the substrate base 360.

[0120] Multiple conductive vias 374 in the extended layer 300 can penetrate at least a portion of the substrate 360 ​​to electrically connect wiring patterns 372 arranged in different wiring layers to each other.

[0121] The first molding element 380 may fill the space between the lower semiconductor chip 100 and the extended layer 300. For example, the first molding element 380 may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin containing reinforcing materials such as inorganic fillers, and may include, for example, Ajinomoto laminate (ABF), FR-4, and BT. Furthermore, the first molding element 380 may include molding materials such as epoxy molding compounds (EMC) or photosensitive materials such as photosensitive image sealants (PIE). In some embodiments, the first molding element 380 may cover the top surface of the extended layer 300.

[0122] In some embodiments, the first molding 380 can be formed by depositing a silicon oxide of a predetermined thickness on the exposed portion within the mounting space 360G and then filling the unfilled portion of the mounting space 360G with a polymer such as polyimide.

[0123] In some embodiments, since a polymer such as polyimide covers the top surface of the lower semiconductor chip 100 and the extension layer 300, the first molding 380 may at least partially surround the side and top surfaces of the lower semiconductor chip 100.

[0124] In some embodiments, after a polymer, such as polyimide, fills the mounting space 360G, an insulating material may then cover the polymer and the extended layer 300 to form a first molding 380. The insulating material may include, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

[0125] An upper redistribution layer 400 may be disposed on the first molding part 380. The upper redistribution layer 400 may include at least one upper redistribution insulating layer 410 and an upper redistribution conductive structure 420. The upper redistribution conductive structure 420 may include a plurality of upper redistribution line patterns 422 and a plurality of upper redistribution through-holes 424, wherein the plurality of upper redistribution line patterns 422 may be disposed on at least one surface of the top and bottom surfaces of each of the plurality of upper redistribution insulating layers 410, and the plurality of upper redistribution through-holes 424 may penetrate at least one upper redistribution insulating layer 410 to contact and connect with a portion of the plurality of upper redistribution line patterns 422, respectively. In some embodiments, the plurality of upper redistribution through-holes 424 may have a tapered shape, wherein their horizontal width decreases from the top side to the bottom side.

[0126] The upper redistribution seed layer 426 can be disposed between a plurality of upper redistribution line patterns 422 and at least one upper redistribution insulating layer 410, and between a plurality of upper redistribution vias 424 and at least one upper redistribution insulating layer 410.

[0127] A portion of the multiple upper redistribution vias 424 can be connected to the upper wiring structure SBEOL by passing through the first molding 380 and the passivation layer 160.

[0128] The lower semiconductor chip 100 and the upper semiconductor chip 500 can be configured such that their active surfaces face each other, and can transmit and receive signals other than electrical signals, such as data signals and control signals, through the upper redistribution conductive structure 420 of the upper redistribution layer 400. Therefore, the lower semiconductor chip 100 and the upper semiconductor chip 500 can transmit and receive signals to each other at a faster speed and with a wider bandwidth.

[0129] The lower semiconductor chip 100 can be powered from an external source via a plurality of buried power rails (BPRs), a plurality of through electrodes 174, and the lower redistribution conductive structure 220 of the lower redistribution layer 200. In some embodiments, the lower semiconductor chip 100 can be powered from an external source via a plurality of buried power rails (BPRs), a plurality of through electrodes 174, a lower wiring structure (PBEOL), and the lower redistribution conductive structure 220 of the lower redistribution layer 200. The upper semiconductor chip 500 can receive power from an external source via the upper redistribution conductive structure 420 of the upper redistribution layer 400, a portion of a plurality of conductive connection structures 370, and the lower redistribution conductive structure 220 of the lower redistribution layer 200.

[0130] At least one of the lower semiconductor chip 100 and the upper semiconductor chip 500 can send signals to and receive signals from an external source via the upper redistribution conductive structure 420 of the upper redistribution layer 400, some other conductive connection structures among the plurality of conductive connection structures 370, and the lower redistribution conductive structure 220 of the lower redistribution layer 200.

[0131] In the semiconductor package 2, according to the present invention, the lower semiconductor chip 100 can send and receive signals from the upper semiconductor chip 500 via its top surface, and can be supplied with external power via its bottom surface, thereby shortening the signal transmission path between the lower semiconductor chip 100 and the upper semiconductor chip 500. Therefore, the lower semiconductor chip 100 and the upper semiconductor chip 500 can send and receive signals to each other at a faster speed and with a wider bandwidth, thereby improving the operating speed of the semiconductor package 2. Furthermore, in the semiconductor package 2, the signal transmission path and the power transmission path can be separated to avoid signal interference caused by power, thus increasing the operational reliability of the semiconductor package 2.

[0132] Figure 6 This is a cross-sectional view of a semiconductor chip in a semiconductor package according to an exemplary embodiment of the present invention. Figure 6 In, with Figure 1 The same reference numerals shown may denote the same or similar components, and repeated descriptions may be omitted.

[0133] refer to Figure 6 The lower semiconductor chip 100a may include a first semiconductor substrate 110 having a first surface 110a and a second surface 110b opposite to each other, and a plurality of fin-type active regions FA protruding upward from the first surface 110a of the first semiconductor substrate 110.

[0134] Multiple finned active regions FA can protrude upward from the main surface (e.g., the first surface 110a of the first semiconductor substrate 110) in a vertical direction (Z direction). Device isolation films 120 covering the lower portions of the sidewalls of the multiple finned active regions FA can be formed between the multiple finned active regions FA. The multiple finned active regions FA can protrude upward from the device isolation films 120 in a fin shape.

[0135] On the first semiconductor substrate 110, a plurality of gate lines 140 may extend in a direction intersecting with a plurality of finned active regions FA. A gate insulating film 142 may be disposed between the gate lines 140 and the finned active regions FA. An interlayer insulating layer 145 may cover the device isolation film 120 and the plurality of gate lines 140.

[0136] In some embodiments, the lower semiconductor chip 100a may be a logic semiconductor chip. For example, the lower semiconductor chip 100a may be a central processing unit chip, a graphics processing unit chip, or an application processor chip.

[0137] The upper wiring structure SBEOL can be disposed on the interlayer insulating layer 145. The upper wiring structure SBEOL may include a plurality of upper wiring lines 152, a plurality of upper wiring vias 154, a plurality of connection vias 156, and an upper wiring interlayer insulating layer 158 that at least partially surrounds the plurality of upper wiring lines 152 and the plurality of upper wiring vias 154. The plurality of connection vias 156 can electrically connect the plurality of upper wiring lines 152 to a plurality of gate lines 140.

[0138] The passivation layer 160 can cover the wiring structure SBEOL.

[0139] Multiple buried vias BPRH can extend between multiple gate lines 140 and multiple through electrodes 174 by penetrating through the device isolation film 120 and then extending into the first semiconductor substrate 110. The multiple buried vias BPRH can be spaced apart from multiple finned active regions FA. Multiple buried power tracks BPR can be disposed within the multiple buried vias BPRH, and a buried track insulating layer 132 can be disposed between the buried power tracks BPR and the first semiconductor substrate 110.

[0140] In some embodiments, the buried power rail BPR may fill only the lower part of the buried rail hole BPRH, and the buried insulating layer 134 may fill the upper part of the buried rail hole BPRH. A power via 136 penetrating the buried insulating layer 134 may be provided between the buried power rail BPR and the gate line 140, thereby electrically connecting the buried power rail BPR to the gate line 140.

[0141] A through-hole TSH can extend from the second surface 110b of the first semiconductor substrate 110 into the first semiconductor substrate 110 and can communicate with the buried track via BPR. In some embodiments, the through-hole TSH can have a tapered shape, wherein the horizontal width of the through-hole TSH decreases as it extends from the second surface 110b of the first semiconductor substrate 110 into the first semiconductor substrate 110 and into the buried power track BPR. The through-hole TSH can be filled by a through electrode 174 and a through-hole insulating film 172 between the first semiconductor substrate 110 and the through electrode 174.

[0142] Multiple bottom wiring pads 188 may be disposed on a second surface 110b of the first semiconductor substrate 110. The multiple bottom wiring pads 188 may be connected to multiple through electrodes 174. In some embodiments, the multiple bottom wiring pads 188 may cover the bottom surface of the multiple through electrodes 174.

[0143] The lower semiconductor chip 100a can have multiple lower wiring pads 188, but without Figure 1 The diagram shows the lower wiring structure PBEOL included in the lower semiconductor chip 100.

[0144] The lower semiconductor chip 100a can send and receive signals such as data signals and control signals other than power signals to an external source through the upper wiring structure SBEOL, and can be supplied with external power through multiple lower wiring pads 188.

[0145] According to the present invention, the lower semiconductor chip 100a can transmit and receive signals such as data signals and control signals other than power signals through the upper wiring structure SBEOL disposed on the first surface 110a of the first semiconductor substrate 110, and can be supplied with external power through a plurality of lower wiring pads 188 disposed on the second surface 110b of the first semiconductor substrate 110. Therefore, in the lower semiconductor chip 100a, signals and power can be provided separately through the upper and lower parts, and thus interference between signals and power can be minimized. Furthermore, even when the integration density of the lower semiconductor chip 100a increases (e.g., when the width of the plurality of fin active regions FA decreases), signals and power can be stably supplied to the lower semiconductor chip 100a.

[0146] Figure 7 This is a cross-sectional view illustrating an example embodiment of a semiconductor package according to a concept based on the present invention. Figure 7 In, with Figure 4 and Figure 6 The same reference numerals shown may denote the same or similar components, and repeated descriptions may be omitted.

[0147] refer to Figure 7 Semiconductor package 3 can be a stacked package, wherein the upper package UP is located on the lower package LPb. The lower package LPb may include a lower semiconductor chip 100a attached to the lower redistribution layer 200, a plurality of conductive connection structures 310, a first molding 320 at least partially surrounding the plurality of conductive connection structures 310 and the lower semiconductor chip 100a, and an upper redistribution layer 400. The upper semiconductor package UP may include an upper semiconductor chip 500 and a second molding 580 at least partially surrounding the upper semiconductor chip 500. The upper package UP may be attached to the lower package LPb such that the active surface of the upper semiconductor chip 500 faces the active surface of the lower semiconductor chip 100.

[0148] The lower semiconductor chip 100a can be attached to some of the other lower connection pads among a plurality of lower connection pads 244. A plurality of first chip connection terminals 190 can be disposed between the lower semiconductor chip 100a and the plurality of lower connection pads 244. The plurality of first chip connection terminals 190 can connect a plurality of lower wiring pads 188 of the lower semiconductor chip 100a to the plurality of lower connection pads 244.

[0149] The lower semiconductor chip 100a and the upper semiconductor chip 500 can be configured such that their active surfaces face each other, and can transmit and receive signals other than electrical signals, such as data signals and control signals, through the upper redistribution conductive structure 420 of the upper redistribution layer 400. Therefore, the lower semiconductor chip 100a and the upper semiconductor chip 500 can transmit and receive signals to each other at a faster speed and with a wider bandwidth.

[0150] The lower semiconductor chip 100a can be powered from an external source via a plurality of buried power rails (BPRs), a plurality of through electrodes 174, and the lower redistribution conductive structure 220 of the lower redistribution layer 200. In some embodiments, the lower semiconductor chip 100a can be powered from an external source via a plurality of buried power rails (BPRs), a plurality of through electrodes 174, a lower wiring structure (PBEOL), and the lower redistribution conductive structure 220 of the lower redistribution layer 200. The upper semiconductor chip 500 can be powered from an external source via the upper redistribution conductive structure 420 of the upper redistribution layer 400, a portion of a plurality of conductive connection structures 310, and the lower redistribution conductive structure 220 of the lower redistribution layer 200.

[0151] At least one of the lower semiconductor chip 100a and the upper semiconductor chip 500 can send signals to and receive signals from an external source via the upper redistribution conductive structure 420 of the upper redistribution layer 400, some other conductive connection structures among the plurality of conductive connection structures 310, and the lower redistribution conductive structure 220 of the lower redistribution layer 200.

[0152] In the semiconductor package 3, according to the present invention, the lower semiconductor chip 100a can send and receive signals from the upper semiconductor chip 500 via its top surface, and can receive external power via its bottom surface, thereby shortening the signal transmission path between the lower semiconductor chip 100a and the upper semiconductor chip 500. Therefore, the lower semiconductor chip 100a and the upper semiconductor chip 500 can send and receive signals to each other at a faster speed and with a wider bandwidth, thereby improving the operating speed of the semiconductor package 3. Furthermore, in the semiconductor package 3, the signal transmission path and the power transmission path can be separated to avoid signal interference caused by power, thus increasing the operational reliability of the semiconductor package 3.

[0153] Figure 8 This is a cross-sectional view illustrating an example embodiment of a semiconductor package according to a concept based on the present invention. For example, in Figure 8 In, with Figures 5 to 7 The same reference numerals may denote the same or similar components, and repeated descriptions may be omitted.

[0154] refer to Figure 8 Semiconductor package 4 can be a stacked package, wherein the upper package UP is located on the lower package LPc. The lower package LPc may include an extension layer 300 attached to the lower redistribution layer 200 and having a mounting space 360G, a lower semiconductor chip 100a housed in the mounting space 360G and attached to the lower redistribution layer 200, a first molding 380 at least partially surrounding the lower semiconductor chip 100a and filling the mounting space 360G, and an upper redistribution layer 400. The lower package LPc can be a fan-out panel-level package. The upper semiconductor package UP may include an upper semiconductor chip 500 and a second molding 580 at least partially surrounding the upper semiconductor chip 500. The upper package UP may be attached to the lower package LPc such that the active surface of the upper semiconductor chip 500 faces the active surface of the lower semiconductor chip 100a.

[0155] The extension layer 300 may at least partially surround the periphery of at least one semiconductor chip 100a. The horizontal width and horizontal area of ​​the mounting space 360G may be greater than the horizontal width and horizontal area of ​​the lower semiconductor chip 100a. The side surfaces of the lower semiconductor chip 100a may be spaced apart from the inner side surfaces of the mounting space 360G.

[0156] The upper redistribution layer 400 may be disposed on the first molding part 380. The upper redistribution layer 400 may include at least one upper redistribution insulating layer 410 and an upper redistribution conductive structure 420.

[0157] The lower semiconductor chip 100a and the upper semiconductor chip 500 can be configured such that their active surfaces face each other, and can transmit and receive signals other than electrical signals, such as data signals and control signals, through the upper redistribution conductive structure 420 of the upper redistribution layer 400. Therefore, the lower semiconductor chip 100a and the upper semiconductor chip 500 can transmit and receive signals to each other at a faster speed and with a wider bandwidth.

[0158] The lower semiconductor chip 100a can be powered from an external source via a plurality of buried power rails (BPRs), a plurality of through electrodes 174, and the lower redistribution conductive structure 220 of the lower redistribution layer 200. In some embodiments, the lower semiconductor chip 100a can be powered from an external source via a plurality of buried power rails (BPRs), a plurality of through electrodes 174, a plurality of lower wiring pads 188, and the lower redistribution conductive structure 220 of the lower redistribution layer 200. The upper semiconductor chip 500 can be powered from an external source via the upper redistribution conductive structure 420 of the upper redistribution layer 400, a portion of a plurality of conductive connection structures 370, and the lower redistribution conductive structure 220 of the lower redistribution layer 200.

[0159] At least one of the lower semiconductor chip 100a and the upper semiconductor chip 500 can send signals to and receive signals from an external source via the upper redistribution conductive structure 420 of the upper redistribution layer 400, some other conductive connection structures among the plurality of conductive connection structures 310, and the lower redistribution conductive structure 220 of the lower redistribution layer 200.

[0160] In the semiconductor package 4, according to the present invention, the lower semiconductor chip 100a can send and receive signals from the upper semiconductor chip 500 via its top surface, and can receive external power via its bottom surface, thereby shortening the signal transmission path between the lower semiconductor chip 100a and the upper semiconductor chip 500. Therefore, the lower semiconductor chip 100 and the upper semiconductor chip 500 can send and receive signals to each other at a faster speed and with a wider bandwidth, thereby improving the operating speed of the semiconductor package 4. Furthermore, in the semiconductor package 4, the signal transmission path and the power transmission path can be separated to avoid signal interference caused by power, thus increasing the operational reliability of the semiconductor package 4.

[0161] Figure 9 This is a cross-sectional view illustrating the operation of a semiconductor package according to an exemplary embodiment of the present invention. For example, Figure 9 It shows Figure 4 The diagram shows a cross-sectional view of the operation of semiconductor package 1, and is related to... Figure 4 The same reference numerals may denote the same or similar components, and repeated descriptions may be omitted.

[0162] refer to Figure 9Semiconductor package 1 can be a stacked package, wherein the upper package UP is located on the lower package LP. The lower package LP may include a lower semiconductor chip 100 attached to the lower redistribution layer 200, a plurality of conductive connection structures 310, a first molding 320 at least partially surrounding the plurality of conductive connection structures 310 and the lower semiconductor chip 100, and an upper redistribution layer 400. The upper semiconductor package UP may include an upper semiconductor chip 500 and a second molding 580 at least partially surrounding the upper semiconductor chip 500. The upper package UP may be attached to the lower package LPb such that the active surface of the upper semiconductor chip 500 faces the active surface of the lower semiconductor chip 100.

[0163] When semiconductor package 1 is operational, a lower power path (LPP), an upper power path (UPP), an internal signal path (ISP), and an external signal path (OSP) can be generated. The lower semiconductor chip 100 can be supplied with external power via the lower power path (LPP). The upper semiconductor chip 500 can be supplied with external power via the upper power path (UPP). Therefore, the lower semiconductor chip 100 and the upper semiconductor chip 500 can send and receive signals to and from each other via the internal signal path (ISP). At least one of the semiconductor chips, lower semiconductor chip 100 and upper semiconductor chip 500, can send signals to and receive signals from an external source via the external signal path (OSP).

[0164] The lower power path (LPP) can be generated along the external connection terminal 600, multiple external connection pads 242, the lower redistribution conductive structure 220 of the lower redistribution layer 200, multiple lower connection pads 244, multiple first chip connection terminals 190, the lower wiring structure PBEOL, multiple through electrodes 174, and multiple buried power tracks (BPR).

[0165] In some embodiments, the upper power path UPP may be generated along the external connection terminal 600, a plurality of external connection pads 242, the lower redistribution conductive structure 220 of the lower redistribution layer 200, a plurality of lower connection pads 244, some of the conductive connection structures in the plurality of conductive connection structures 310, the upper redistribution conductive structure 420 of the upper redistribution layer 400, and a plurality of second chip connection terminals 550.

[0166] In some embodiments, the internal signal path ISP can be generated along the upper wiring structure SBEOL, the upper redistribution conductive structure 420 of the upper redistribution layer 400, a plurality of second chip connection terminals 550 and a plurality of upper chip connection pads 520.

[0167] In some embodiments, when the semiconductor package 1 does not have a plurality of second chip connection terminals 550, the upper power path UPP can be generated along the external connection terminal 600, a plurality of external connection pads 242, the lower redistribution conductive structure 220 of the lower redistribution layer 200, a plurality of lower connection pads 244, some of the conductive connection structures among the plurality of conductive connection structures 310, and the upper redistribution conductive structure 420 of the upper redistribution layer 400, and the internal signal path ISP can be generated along the upper wiring structure SBEOL, the upper redistribution conductive structure 420 of the upper redistribution layer 400, and the plurality of upper chip connection pads 520.

[0168] The external signal path (OSP) can be generated along the external connection terminal 600, multiple external connection pads 242, the lower redistribution conductive structure 220 of the lower redistribution layer 200, multiple lower connection pads 244, some of the conductive connection structures in multiple conductive connection structures 310, and the upper redistribution conductive structure 420 of the upper redistribution layer 400.

[0169] When the external signal path OSP transmits and receives signals between the lower semiconductor chip 100 and the outside, the external signal path OSP can be generated along the external connection terminal 600, multiple external connection pads 242, the lower redistribution conductive structure 220 of the lower redistribution layer 200, multiple lower connection pads 244, some conductive connection structures among the multiple conductive connection structures 310, the upper redistribution conductive structure 420 of the upper redistribution layer 400, and the upper wiring structure SBEOL. When the external signal path OSP transmits and receives signals between the upper semiconductor chip 500 and the outside, the external signal path OSP can be generated along the external connection terminal 600, multiple external connection pads 242, the lower redistribution conductive structure 220 of the lower redistribution layer 200, multiple lower connection pads 244, some conductive connection structures among the multiple conductive connection structures 310, the upper redistribution conductive structure 420 of the upper redistribution layer 400, and multiple second chip connection terminals 550.

[0170] In semiconductor package 1, the number of signals transmitted and received through the internal signal path (ISP) can be greater than the number of signals transmitted and received through the external signal path (OSP). The extension length of the external signal path (OSP) can be greater than the extension length of the internal signal path (ISP). The bandwidth of the internal signal path (ISP) can be greater than the bandwidth of the external signal path (OSP).

[0171] In semiconductor package 1, the internal signal path (ISP) with a greater number of signals can have a shorter extension length and a wider bandwidth, thus improving its operating speed. Furthermore, in semiconductor package 1, the signal transmission path and the power transmission path can be separated to avoid signal interference caused by power, thereby increasing the operational reliability of semiconductor package 1.

[0172] Figure 5 , Figure 7 and Figure 8 The operation of semiconductor packages 2, 3, and 4 shown is also similar to that in the reference. Figure 9 The operation of the semiconductor package 1 described herein is generally similar, and it is understood that elements not described herein are at least similar to their counterparts described elsewhere in this specification, to the extent that their detailed descriptions are omitted.

[0173] exist Figure 5 In the semiconductor package 2 shown, the external signal path OSP and the upper power path UPP can be connected through multiple conductive connection structures 370 instead of Figure 9 The semiconductor package 1 shown is generated by multiple conductive connection structures 310.

[0174] exist Figure 7 In the semiconductor package 3 shown, the lower power path LPP can be connected via multiple lower wiring pads 188 instead of Figure 9 The semiconductor package 1 shown is generated using the lower wiring structure PBEOL.

[0175] exist Figure 8 In the semiconductor package 4 shown, the external signal path OSP and the upper power path UPP can be connected through multiple conductive connection structures 370 instead of Figure 9 The semiconductor package 1 shown is generated by multiple conductive connection structures 310, while the lower power path LPP can be generated through multiple lower wiring pads 188 instead of Figure 9 The semiconductor package 1 shown is generated using the lower wiring structure PBEOL.

[0176] Although various embodiments of the inventive concept have been specifically shown and described, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor package, comprising: The lower redistribution layer includes the lower redistribution conductive structure; A lower semiconductor chip is disposed on the lower redistribution layer; Multiple conductive connection structures are attached to the lower redistribution layer; The upper redistribution layer has an upper redistribution conductive structure disposed on the lower semiconductor chip and the plurality of conductive connection structures; as well as An upper semiconductor chip has an active surface corresponding to the active surface of the lower semiconductor chip and is disposed on the upper redistribution layer. The upper semiconductor chip is electrically connected to the upper redistribution conductive structure. The lower semiconductor chip includes: A semiconductor substrate having a first surface and a second surface opposite to the first surface; An upper wiring structure is disposed on the first surface of the semiconductor substrate and electrically connected to the upper redistribution conductive structure; Buried electrical tracks, filling a portion of a buried track aperture extending from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate; and A through electrode fills a through-hole extending from the second surface of the semiconductor substrate to the first surface of the semiconductor substrate, the through electrode electrically connecting the buried power rail to the lower redistribution conductive structure.

2. The semiconductor package according to claim 1, wherein, The top surface of the lower semiconductor chip and the top surface of the plurality of conductive connection structures are at the same vertical height.

3. The semiconductor package according to claim 1, further comprising: A molded component, at least partially surrounding the lower semiconductor chip and the plurality of conductive connection structures, is disposed on the lower redistribution layer. The top surface of the lower semiconductor chip, the top surface of the plurality of conductive connection structures, and the top surface of the molding are disposed on the same plane.

4. The semiconductor package according to claim 3, wherein, The lower semiconductor chip further includes a passivation layer that at least partially covers the upper wiring structure, and the top surface of the passivation layer, the top surface of the plurality of conductive connection structures, and the top surface of the molding are at the same vertical height.

5. The semiconductor package according to claim 1, wherein, The thickness of the lower redistribution layer is greater than the thickness of the upper redistribution layer.

6. The semiconductor package according to claim 1, wherein, Each of the lower semiconductor chip and the upper semiconductor chip includes a logic semiconductor chip.

7. The semiconductor package according to claim 1, wherein, The lower semiconductor chip further includes: a plurality of finned active regions protruding upward from the first surface of the semiconductor substrate; and gate lines extending in a direction intersecting the plurality of finned active regions. The buried track hole is separated from the plurality of fin-shaped active regions and extends between the gate line and the through electrode.

8. The semiconductor package according to claim 1, further comprising: A substrate having a mounting space for accommodating the lower semiconductor chip, the substrate being disposed on the lower redistribution layer; as well as A molded part that at least partially fills the mounting space. The plurality of conductive connection structures extend through the substrate.

9. The semiconductor package according to claim 1, wherein, The lower semiconductor chip further includes a lower wiring structure covering the second surface of the semiconductor substrate. The lower wiring structure includes lower wiring lines, lower wiring vias, and a lower wiring inter-insulating layer at least partially surrounding the lower wiring lines and the lower wiring vias. The through electrode and the lower redistribution conductive structure are electrically connected to each other via the lower wiring line, the lower wiring via, and the chip connection terminal between the lower wiring structure and the lower redistribution conductive structure.

10. The semiconductor package according to claim 1, wherein, The lower semiconductor chip also includes a lower wiring pad covering the bottom surface of the through electrode, and The through electrode and the lower redistribution conductive structure are electrically connected to each other via the lower wiring pad and the chip connection terminal between the lower wiring pad and the lower redistribution conductive structure.

11. The semiconductor package according to claim 1, wherein, The through-hole has a tapered shape, wherein the horizontal width of the tapered shape decreases as the through-hole extends from the second surface of the semiconductor substrate toward the buried power track.

12. A semiconductor package, comprising: The lower redistribution layer has a lower redistribution conductive structure; A lower semiconductor chip is disposed on the lower redistribution layer; Multiple conductive connection structures are attached to the lower redistribution layer; The upper redistribution layer has an upper redistribution conductive structure disposed on the lower semiconductor chip and the plurality of conductive connection structures; as well as An upper semiconductor chip is disposed on the upper redistribution layer and electrically connected to the upper redistribution conductive structure. The lower semiconductor chip includes: a semiconductor substrate having a first surface and a second surface opposite to the first surface; buried power rails extending from the first surface of the semiconductor substrate toward the second surface; and through electrodes extending from the second surface of the semiconductor substrate toward the first surface of the semiconductor substrate, electrically connecting the buried power rails to the lower redistribution conductive structure. The lower semiconductor chip is powered via a lower power path, which is generated via the lower redistributed conductive structure, the through electrode, and the buried power rail. The lower semiconductor chip and the upper semiconductor chip send and receive signals other than electrical signals to each other via an internal signal path defined by the upper redistributed conductive structure.

13. The semiconductor package according to claim 12, wherein, The upper semiconductor chip is powered via an upper power path defined by the lower redistributed conductive structure, some of the plurality of conductive connection structures, and the upper redistributed conductive structure.

14. The semiconductor package of claim 13, wherein, At least one of the upper semiconductor chip and the lower semiconductor chip sends a signal to and receives a signal from an external source via an external signal path, the external signal path being defined by the lower redistributed conductive structure, some other conductive connection structures among the plurality of conductive connection structures, and the upper redistributed conductive structure.

15. The semiconductor package of claim 14, wherein, The extension length of the external signal path is greater than the extension length of the internal signal path.

16. The semiconductor package of claim 12, wherein, The lower semiconductor chip is disposed on the first surface of the semiconductor substrate, and further includes: an upper wiring structure electrically connected to the upper redistribution conductive structure; and a passivation layer at least partially covering the upper wiring structure. The top surface of the passivation layer and the top surface of the plurality of conductive connection structures are at the same vertical height.

17. The semiconductor package of claim 16, further comprising: A molded part, at least partially surrounding the lower semiconductor chip and the plurality of conductive connection structures on the lower redistribution layer, wherein the top surface of the passivation layer and the top surface of the plurality of conductive connection structures are at the same vertical height as the top surface of the molded part.

18. A semiconductor package, comprising: The lower redistribution layer has a lower redistribution conductive structure; Multiple external connection terminals are attached to multiple external connection pads disposed at the bottom of the lower redistribution layer; A lower semiconductor chip is disposed on the lower redistribution layer; Multiple conductive connection structures are attached to the lower redistribution layer; A molded component that at least partially surrounds the lower semiconductor chip and the plurality of conductive connection structures on the lower redistribution layer; The upper redistribution layer includes an upper redistribution conductive structure on the lower semiconductor chip, the plurality of conductive connection structures, and the molding, wherein the thickness of the upper redistribution layer is less than the thickness of the lower redistribution layer; as well as An upper semiconductor chip has an active surface corresponding to the active surface of the lower semiconductor chip and is disposed on the upper redistribution layer. The upper semiconductor chip is electrically connected to the upper redistribution conductive structure. The lower semiconductor chip includes: A semiconductor substrate having a first surface and a second surface opposite to the first surface; Multiple fin-shaped active regions protrude upward from the first surface of the semiconductor substrate; Gate lines extend in a direction that intersects with the plurality of finned active regions; An upper wiring structure is disposed on the gate line and electrically connected to the upper redistribution conductive structure; A passivation layer that at least partially covers the upper wiring structure; The lower wiring structure at least partially covers the second surface of the semiconductor substrate and is electrically connected to the lower redistribution conductive structure; Burying electrical tracks by filling a portion of the buried track holes extending from the first surface to the second surface of the semiconductor substrate; and A through electrode extends from the second surface of the semiconductor substrate to the first surface and fills a through hole communicating with the buried track hole, the through electrode electrically connecting the buried power track to the lower redistribution conductive structure.

19. The semiconductor package of claim 18, wherein, The buried track hole extends between the gate line and the through electrode, and The through-hole has a tapered shape, wherein the horizontal width of the tapered shape increases as the through-hole extends from the buried power track to the second surface of the semiconductor substrate.

20. The semiconductor package of claim 18, wherein, The top surfaces of the plurality of conductive connection structures, the top surface of the passivation layer, and the top surface of the molded part are at the same vertical height.

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