Semiconductor devices and their fabrication methods

Abstract

Semiconductor devices and methods are provided that facilitate physical failure analysis (PFA) testing from the back side of the device. In at least one embodiment, a device is provided comprising a semiconductor device layer including a plurality of diffusion regions. A first interconnect structure is disposed on a first side of the semiconductor device layer, and the first interconnect structure includes at least one electrical contact. A second interconnect structure is disposed on a second side of the semiconductor device layer, and the second interconnect structure includes a plurality of back-side power rails. Each of the back-side power rails at least partially overlaps with a corresponding diffusion region among the plurality of diffusion regions and defines an opening exposing a portion of the corresponding diffusion region located on the second side of the semiconductor device layer. Embodiments of this application also relate to semiconductor devices and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this application provide semiconductor devices and methods for forming the same. Background Technology

[0002] In semiconductor device manufacturing, physical failure analysis (PFA) can be used, for example, to test semiconductor devices or dies on semiconductor wafers to determine the cause of certain defects that may exist in the die. Defects can be related to many causes, including, for example, flaws in the die design and flaws in the manufacturing process used to manufacture the die.

[0003] Physical Fault Analysis (PFA) typically requires probing the die using wafer testing equipment. Fault areas can be identified by applying known electrical test vectors and tracing these vectors through the circuitry within the die. PFA testing tools may include a radiation source that illuminates the die from the front side to observe potential defects or fault areas within the die. Once the fault area is identified, additional steps such as manual network tracing are performed to determine the layer where the fault occurred. Summary of the Invention

[0004] Some embodiments of this application provide a semiconductor device including: a semiconductor device layer including a plurality of diffusion regions, the semiconductor device layer having a first side and a second side opposite to the first side; a first interconnect structure located on the first side of the semiconductor device layer, the first interconnect structure including at least one electrical contact; and a second interconnect structure located on the second side of the semiconductor device layer, the second interconnect structure including a plurality of back-side power rails, each of the back-side power rails at least partially overlapping a corresponding diffusion region among the plurality of diffusion regions and defining an opening exposing a portion of the corresponding diffusion region located on the second side of the semiconductor device layer.

[0005] Other embodiments of this application provide a method for forming a semiconductor device, comprising: forming a plurality of back-side power rails on the back side of a semiconductor device layer, the semiconductor device layer including a plurality of diffusion regions, each of the back-side power rails at least partially overlapping a corresponding diffusion region among the plurality of diffusion regions and defining an opening exposing a portion of the corresponding diffusion region located on the back side of the semiconductor device layer, wherein a front-side interconnect structure is disposed on the front side of the semiconductor device layer and includes at least one electrical contact.

[0006] Some embodiments of this application provide a method of forming a semiconductor device, comprising: forming a front-side interconnect structure on a first side of a semiconductor device layer, the front-side interconnect structure including forming at least one electrical contact; forming a back-side interconnect structure on a second side of the semiconductor device layer opposite to the first side, the back-side interconnect structure including: forming a plurality of back-side power rails, each of the back-side power rails at least partially overlapping a corresponding diffusion region among a plurality of diffusion regions of the semiconductor device layer and defining an opening exposing a portion of the corresponding diffusion region located on the second side of the semiconductor device layer; and forming a back-side power delivery network on the plurality of back-side power rails, the plurality of back-side power rails being disposed between the back-side power delivery network and the second side of the semiconductor device layer. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figure 1A This is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.

[0009] Figure 1B This illustrates some embodiments. Figure 1A The diagram shows a plan view of the back-side power delivery network, back-side power rails, and back-side vias of the device's back-side interconnect structure.

[0010] Figure 1C This is an illustrative representation according to some embodiments. Figure 1A A 3D view of the components of the front interconnect structure of the device shown.

[0011] Figure 2 This illustrates some embodiments. Figure 1A A plan view of the back-side power delivery network, back-side power rails, and back-side vias of the device's back-side interconnect structure.

[0012] Figures 3A to 3C This is a plan view illustrating a method for manufacturing a back-side power delivery network, back-side power rails, and back-side vias of a back-side interconnect structure according to some embodiments.

[0013] Figures 4A to 4G A method for manufacturing a semiconductor device according to some embodiments is shown. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0016] The embodiments provided herein include devices and methods that facilitate physical fault analysis (PFA) testing from the back side of a device. The device includes a semiconductor device layer that is at least partially exposed from the back side of the device through openings formed in power rails. This allows PFA to be performed from the back side without radiation from the PFA tester being blocked by the power rails, as in conventional methods. Instead, radiation can reach the exposed portion of the semiconductor device layer through the openings. This results in improved global fault isolation, or PFA testing, which improves device yield because they can be tested more effectively and efficiently from the back side of the device, and because front-side power rail placement can reduce wiring resources on the front side of the device. Therefore, by placing the power rails on the back side of the device, additional area is available for signal routing on the front side.

[0017] Furthermore, it is advantageous to move the power rail layout to the back side of the device (opposite to the front side), especially since the device has increasingly smaller part sizes, as the power rail layout facilitates denser placement of semiconductor devices (e.g., transistors) while further allowing for efficient PFA testing of the device without being obstructed by the power rails above.

[0018] Furthermore, due to the presence of openings in the power rails in some embodiments of the present invention, the maximum width of the power rails can be increased compared to conventional power rails. This results in the power rails of the present invention having lower resistance than conventional power rails.

[0019] Figure 1A This is a cross-sectional view illustrating a semiconductor device 100 according to some embodiments of the present invention. The semiconductor device 100 can be any semiconductor device, such as, but not limited to, a logic device, a memory device, or any other semiconductor device. In some embodiments, the semiconductor device 100 is a logic device, or a static random access memory (SRAM) device formed of logic transistors. Figure 1A As shown, device 100 includes substrate 102, bonding layer 104, back-side interconnect structure 106 and front-side interconnect structure 108.

[0020] Substrate 102 can be any suitable substrate. In some embodiments, substrate 102 can be a semiconductor wafer. In some embodiments, substrate 102 can be a single-crystal silicon (Si) wafer, an amorphous Si wafer, a gallium arsenide (GaAs) wafer, or any other semiconductor wafer. In some embodiments, substrate 102 can be a carrier wafer that may be substantially free of electrical components and can be used to bond to device 100 (e.g., to back-side interconnect structure 106) during processing of device 100, such as during physical failure analysis (PFA) testing.

[0021] Device 100 also includes a semiconductor device layer 110. Semiconductor device layer 110 includes a plurality of semiconductor devices. The semiconductor devices included in semiconductor device layer 110 can be any semiconductor device in the various embodiments. In some embodiments, semiconductor device layer 110 includes one or more transistors, which can include any suitable transistor structure, including, for example, FinFET, gate-all-around (GAA) transistors, etc. In some embodiments, semiconductor device layer 110 includes one or more GAA transistors. In some embodiments, semiconductor device layer 110 can be a logic layer including one or more semiconductor devices, and may also include their interconnection structures configured and arranged to provide logic functions such as AND, OR, XOR, XNOR, or NOT, or storage functions such as flip-flops or latches.

[0022] In some embodiments, semiconductor device layer 110 may include a memory device, which may be any suitable memory device, such as, for example, a static random access memory (SRAM) device. The memory device may include a plurality of memory cells constructed in rows and columns, but other embodiments are not limited to this arrangement. Each memory cell may include a plurality of transistors (e.g., six) connected between a first voltage source (e.g., VDD) and a second voltage source (e.g., VSS or ground), such that one of the two memory nodes may be occupied by information to be stored, with complementary information stored at the other memory node.

[0023] Device 100 includes power management circuitry 112 (which may be referred to herein as “plug circuitry 112”) electrically coupled to semiconductor device layer 110. Plug circuitry 112 may include any suitable circuitry for controlling or otherwise managing communication signals (such as input power signals) to or from semiconductor device layer 110. In some embodiments, plug circuitry 112 may include power gating circuitry that can reduce power consumption, for example, by cutting off current to unused circuit blocks (e.g., blocks or electrical components in semiconductor device layer 110), thereby reducing standby or leakage power. In some embodiments, plug circuitry 112 includes switching devices, such as a plurality of transistors, for sending or receiving electrical signals to or from semiconductor device layer 110, such as circuitry (e.g., transistors, etc.) for turning semiconductor device layer 110 on and off.

[0024] The plug circuit 112 can be configured to be laterally adjacent to the first side of the semiconductor device layer 110, such as... Figure 1A As shown in the diagram. The input / output layer 114 can be configured to be laterally adjacent to the second side of the semiconductor device layer 110, with the second side opposite to the first side. For example, as Figure 1A As shown, the plug circuit 112 may be configured to be adjacent to the left side of the semiconductor device layer 110, while the input / output layer 114 may be configured to be adjacent to the right side of the semiconductor device layer 110. In some embodiments, the input / output layer 114 may be electrically coupled to the semiconductor device layer 110. The input / output layer 114 may include any circuitry suitable for receiving or sending input or output signals to the semiconductor device layer 110.

[0025] The back-side interconnect structure 106 is disposed on the back side of the semiconductor device layer 110, for example, as... Figure 1A As shown on the lower side. The back-side interconnect structure 106 may include any suitable electrical interconnect structure, circuitry, wiring, etc., suitable for receiving electrical signals from or sending electrical signals to the semiconductor device layer 110.

[0026] In some embodiments, the back-side interconnect structure 106 includes a back-side power rail 116 disposed between the back-side power delivery network 118 and a plurality of back-side vias 120.

[0027] The back-side power rail 116 may include a plurality of wires or power rails operably supplying or receiving electrical signals (e.g., power or voltage signals) to or from semiconductor devices in the semiconductor device layer 110. The back-side power rail 116 may be formed of any suitable conductive material. In some embodiments, the back-side power rail 116 is formed of or comprises metal.

[0028] A back-side via 120 is disposed between and extends between the back-side power rail 116 and the semiconductor device layer 110, and electrically couples the back-side power rail 116 to the semiconductor device layer 110. The back-side via 120 can be any suitable conductive via, and in some embodiments, the back-side via 120 is a metallic via.

[0029] A back-side power delivery network 118 is disposed between the back-side power rail 116 and the substrate 102, for example, on the back side of the back-side power rail 116. In various embodiments, the back-side power delivery network 118 may include a plurality of wires that can be used to selectively deliver electrical signals (e.g., power or voltage signals) to or from the back-side power rail 116 and / or the semiconductor device layer 110. The back-side power delivery network 118 may be formed of any suitable conductive material. In some embodiments, the back-side power delivery network 118 is formed of or comprises a metallic material.

[0030] The back-side interconnect structure 106 may further include an insulating layer 122 covering the back-side power rails 116, the back-side power delivery network 118, and the back-side vias 120. The insulating layer 122 may be formed of any suitable insulating material, and in some embodiments, the insulating layer 122 electrically insulates or isolates the various electrical components within the back-side interconnect structure 106 from each other. In some embodiments, the insulating layer 122 may be formed of a dielectric material, which may include one or more of silicon dioxide (SiO2), SiON, SiOC, and SiOCN, or any other suitable insulating material. The insulating layer 122 may be disposed on and in contact with the bonding layer 104.

[0031] Bonding layer 104 bonds substrate 102 to back-side interconnect structure 106. Bonding layer 104 can be formed of any material to suitably bond back-side interconnect structure 106 and substrate 102. In some embodiments, bonding layer 104 includes an oxide layer, such as silicon dioxide. However, the embodiments provided herein are not limited thereto, and any other suitable material for bonding layer 104 can be used in various embodiments. In some embodiments, bonding layer 104 is formed by a thermal oxidation process. For example, the carrier wafer may be or include silicon, which may be thermally oxidized to form silicon dioxide bonding layer 104.

[0032] The front interconnect structure 108 includes a plurality of metallization layers electrically coupled to each other via one or more conductive vias. The metallization layers extend between electrical contacts 124 and one or more of plug circuit 112, input / output layer 114, and semiconductor device layer 110. In some embodiments, the metallization layers electrically couple power contacts 124a to plug circuit 112. In some embodiments, the metallization layers electrically couple input / output contacts 124b to input / output layer 114.

[0033] The front interconnect structure 108 may further include an insulating layer 126 covering the various metallization layers and vias of the front interconnect structure 108. The insulating layer 126 may be formed of any suitable insulating material, and in some embodiments, the insulating layer 126 electrically insulates or isolates the various electrical components within the front interconnect structure 108 from each other. In some embodiments, the insulating layer 126 may be formed of a dielectric material, which may include one or more of silicon dioxide (SiO2), SiON, SiOC, and SiOCN, or any other suitable insulating material. The insulating layer 126 may be disposed on the front side of the semiconductor device layer 110, the plug circuit 112, and the input / output layer 114, and may contact the front side of the semiconductor device layer 110, the plug circuit 112, and the input / output layer 114.

[0034] like Figure 1A As shown, physical fault analysis (PFA) can be performed on device 100. PFA can be performed to test the functionality of device 100, such as the functionality of semiconductor devices in semiconductor device layer 100. In some embodiments, PFA can be performed to automatically identify or detect defects or hot spots in device 100, such as defects or hot spots in semiconductor device layer 100. Such defects may include hot spots (e.g., “IR” voltage drops), which may be caused by various problems, such as high-resistance regions in the back-side power rail 116, insufficient spacing, and / or linewidth margins. Furthermore, in some embodiments, PFA can be performed to automatically identify or detect defects in semiconductor devices in semiconductor device layer 100, which may include, for example, defective hot spots, as well as defects related to the formation of semiconductor devices.

[0035] In some embodiments, PFA testing can be performed from the back side of device 100. For example, during PFA testing, a PFA tester 130 can be used to illuminate device 100 from the back side using any suitable radiation. In some embodiments, the PFA tester 130 can be an emission microscopy (EMMI) tester. Emission microscopy (EMMI) is an effective optical analysis technique for detecting and locating certain integrated circuit (IC) faults, such as faults within semiconductor device layers 100. Emission microscopy is non-invasive and can be performed from either the front or back side of the device; however, as Figure 1AAs shown, emission microscopy can be performed from the back side of device 100. Many device defects cause weak light emission in the visible and near-infrared (IR) spectra, which can be detected during PFA testing of device 100.

[0036] In some embodiments, one or more cameras (not shown) are included as part of the PFA tester 130. For example, an emission microscope can use a sensitive camera to observe and capture light emission from the semiconductor device layer 110, which may be associated with defects, thus aiding in the detection and localization of certain IC defects. Because emission can be detected from the back side, EMMI can use an IR laser to create a superimposed image of the circuitry through the die. This allows faults to be directly correlated with circuit components, thereby accelerating fault resolution. A typical EMMI photograph consists of a superimposed image of two images: the circuitry and the emission point. For clarity, each can be arbitrarily colored in a different manner.

[0037] In some embodiments, the PFA tester 130 may be a laser tester that uses laser radiation to illuminate the back side of the device 100. For example, the PFA tester 130 may be or utilize a laser signal injection microscope (LSIM) or any other laser testing technique.

[0038] In some embodiments, PFA testing may include testing device 100 using a physical wafer testing apparatus or a wafer tester. The wafer tester may be any conventional wafer testing apparatus that can be used in physical fault analysis. For example, the wafer tester may include a wafer detector (not shown) that can apply one or more electrical test patterns to each of a plurality of dies on a semiconductor device, such as in semiconductor device layer 110. The wafer tester may be positioned, for example, on the front side of device 100 (e.g., on or connected to electrical contact 124), and during PFA testing, one or more electrical test signals (e.g., electrical test vectors) may be applied to device 100 and to semiconductor device layer 110. PFA testing can therefore be used to diagnose or detect defects or faults in semiconductor device layer 110.

[0039] Figure 1B This is a plan view showing the back-side power delivery network 118, back-side power rails 116, and back-side vias 120 of the back-side interconnect structure 106 of device 100. Figure 1B The plan view is located in the XY plane as seen from the back side of the device, for example, along... Figure 1A The direction shown is 125.

[0040] like Figure 1BAs shown, the semiconductor device layer 110 includes multiple diffusion regions 110N and 110P. The diffusion regions may include n-type diffusion regions 110N and p-type diffusion regions 110P. The n-type diffusion region 110N may have n-type conductivity and may be doped with one or more n-type dopants, while the p-type diffusion region 110P may have p-type conductivity and may be doped with one or more p-type dopants.

[0041] The diffusion regions 110N and 110P can be along the first direction (e.g., as shown in the image). Figure 1B The diffusion regions 110N and 110P extend along the x-axis direction shown in the diagram and can be parallel to and spaced apart from each other. In some embodiments, the diffusion regions 110N and 110P form the source / drain regions of transistors within the semiconductor device layer 110. The arrangement of the n-type diffusion regions 110N and p-type diffusion regions 110P facilitates the formation and selective operation of transistors of different conductivity types in the semiconductor device layer 110. For example, the semiconductor device layer 110 may include p-type transistors (such as p-type metal-oxide-semiconductor (PMOS) transistors) and n-type transistors (such as n-type metal-oxide-semiconductor (NMOS) transistors). The gate electrode of the transistor can be connected to a control signal for turning the transistor on and off. In some embodiments, the control signal may be provided, for example, from the plug circuit 112.

[0042] In some embodiments, one or more transistors have conductive regions (e.g., source / drain regions) in diffusion regions 110N, 110P that are operatively connected to a first voltage source (e.g., VDD) on a first back-side power rail. For example, in some embodiments, the conductive regions of a PMOS transistor may be operatively connected to the first voltage source. In some embodiments, one or more transistors have conductive regions (e.g., source / drain regions) in diffusion regions 110N, 110P that are operatively connected to a second voltage source (e.g., VDD) on a second back-side power rail. For example, in some embodiments, the conductive regions of an NMOS transistor may be operatively connected to the second voltage source.

[0043] like Figure 1B As shown, the power delivery network 118 may include one or more first power delivery lines 118a and one or more second power delivery lines 118b. The first power delivery lines 118a are arranged along a second direction transverse to the first direction (e.g., as shown in the diagram). Figure 1BThe second direction extends along the y-axis direction shown in the diagram. In some embodiments, the second direction is orthogonal or substantially orthogonal to the first direction. The first power supply line 118a is configured to selectively receive voltage from a first voltage source (e.g., VDD) or supply voltage to one or more of the back-side power rails 116. For example, each first power supply line 118a may be electrically coupled to one or more of the back-side power rails 116, and thus can selectively receive voltage from the first voltage source or supply voltage to one or more back-side power rails 116.

[0044] One or more second power supply lines 118b extend along a second direction and may be parallel to or substantially parallel to the first power supply line 118a, and may be spaced apart from each other and spaced apart from the first power supply line 118a along a first direction (e.g., the x-axis direction). The second power supply lines 118b are configured to selectively receive voltage from a second voltage source (e.g., VSS) or supply voltage to one or more of the back-side power rails 116. For example, each second power supply line 118a may be electrically coupled to one or more of the back-side power rails 116, and thus can selectively receive voltage from a second voltage source or supply voltage to one or more back-side power rails 116. In some embodiments, the voltage of the second voltage source may be different from the voltage of the first voltage source.

[0045] like Figure 1B As shown, the back-side power rail 116 may include a plurality of power rails 116a, 116b, 116c that typically extend along a first direction (e.g., the x-axis direction). The power rails 116a, 116b, 116c are spaced apart from each other along a second direction, as shown. The power rails 116a, 116b, 116c may be electrically coupled to diffusion regions 110N, 110P of the semiconductor device layer 110, for example, through a back-side via 120. The back-side via 120 may extend through a portion of the insulating layer 122 to connect the respective regions of the diffusion regions 110N, 110P to the power rails 116a, 116b, 116c. Therefore, power rails 116a, 116b, and 116c are configured to deliver electrical signals (e.g., VDD or VSS) to or receive electrical signals from semiconductor devices in semiconductor device layer 110, such as to conductive regions (e.g., source / drain regions) of semiconductor devices in diffusion regions 110N and 110P or from conductive regions (e.g., source / drain regions) of semiconductor devices in diffusion regions 110N and 110P.

[0046] like Figure 1BAs shown, portions of the diffusion regions 110N and 110P of the semiconductor device layer 110 are exposed through openings 142 in power rails 116a and 116b. For example, the first power rail 116a may include an opening 142 that exposes a portion of the underlying diffusion region 110N, as shown. The second power rail 116b may substantially or completely overlap with a first underlying diffusion region of the first type (e.g., a p-type diffusion region 110P, as shown) and may include an opening 142 that exposes a portion of an adjacent underlying diffusion region of the first type (e.g., an adjacent p-type diffusion region 110P). In various embodiments, one or more of the power rails 116a, 116b, and 116c may substantially or completely overlap with the first type of diffusion region, while the opening 142 may expose a portion of a second type of diffusion region.

[0047] Each of the power rails 116a, 116b, and 116c may have a first width 144 measured along a second direction (e.g., the y-axis direction), which may be the maximum width of the power rails 116a, 116b, and 116c, as shown. However, at the opening 142, the power rails 116a, 116b, and 116c have a second width 145, which is smaller than the first width 144 measured along the second direction. That is, the smaller second width 145 of the power rails 116a, 116b, and 116c defines the opening 142, which extends inwardly from the first width 144 into the power rails 116a, 116b, and 116c.

[0048] In some embodiments, a larger opening 142' may be formed in one or more of the power rails 116a, 116b, 116c. The larger opening 142' may be substantially twice the length of the opening 142 (e.g., in the x-axis direction). For example, the larger opening 142' may be two openings 142 that are formed successively and continuously along their length.

[0049] Openings 142 and 142' facilitate or improve back-side PFA testing of device 100 because opening 142 exposes portions of the diffusion regions 110N and 110P of semiconductor device layer 110, allowing the exposed portions of diffusion regions 110N and 110P to be imaged or otherwise inspected by PFA tester 130 from the back side of device 100. In other words, the back-side power rail 116 does not obstruct the PFA tester 130 from observing, imaging, or otherwise inspecting portions of diffusion regions 110N and 110P.

[0050] Figure 1C This is a schematic 3D view illustrating the components of device 100. Specifically, Figure 1C The front interconnect structure 108 is shown in more detail. (See diagram below.) Figure 1CAs shown, the front interconnect structure 108 includes a plurality of metallization layers 262 electrically coupled to each other through one or more conductive vias 264. The front interconnect structure 108 may include any number of metallization layers. Although Figure 1C The illustration shows only a portion of the metallization layer, but it will be readily understood that each metallization layer may include a conductor extending in a respective path along a plane including a first direction (e.g., the x-axis direction) and a second direction (e.g., the y-axis direction).

[0051] The metallization layer is connected via conductive via 264 to provide a conductive path between electrical contact 124 and one or more of plug circuit 112, input / output layer 114 and semiconductor device layer 110.

[0052] Figure 2 This is a plan view showing the back-side power delivery network 118, back-side power rails 116, and back-side vias 120 of the back-side interconnect structure 106 of device 100. Figure 2 The view and Figure 1B The views shown are the same; however, Figure 2 Additional dimensions are shown for the back-side power delivery network 118, back-side power rails 116, and back-side vias 120 of the back-side interconnect structure 106.

[0053] like Figure 2 As shown, the power lines 118 (e.g., 118a, 118b) of the power delivery network may have a spacing 151, which may be measured along a first direction (e.g., the x-axis direction) between the first power line 118a (e.g., the center of the first power line 118a) and the second power line 118b (e.g., the center of the second power line 118b). In some embodiments, the spacing 151 is greater than the gate spacing of the transistors of the semiconductor device layer 110, which may be referred to as the contact polysilicon pitch (CPP). In some embodiments, the spacing 151 is greater than twice the contact polysilicon pitch of the transistors of the semiconductor device layer 110. In some embodiments, the spacing 151 is less than 50 times the contact polysilicon pitch, and in some embodiments, the spacing 151 is less than 25 times the contact polysilicon pitch. In some embodiments, the spacing 151 is in the range from about 2 times the contact polysilicon pitch to about 24 times the contact polysilicon pitch. In some embodiments, the spacing 151 is in the range from about 90 nm to about 1000 nm.

[0054] In some embodiments, the opening 142 may have a length 152 along a first direction (e.g., the x-axis direction), the length 152 being equal to or substantially equal to the contact polysilicon spacing of the transistors of the semiconductor device layer 110. In some embodiments, the length 152 of the opening 142 is greater than the contact polysilicon spacing. In some embodiments, the length 152 is less than 25 times the contact polysilicon spacing, and in some embodiments, the length 152 is less than 15 times the contact polysilicon spacing. In some embodiments, the length 152 is in the range from about 1 times the contact polysilicon spacing to about 10 times the contact polysilicon spacing. In some embodiments, the length 152 is in the range from about 45 nm to about 450 nm. These dimensions for the length 152 of the opening 142 facilitate or improve back-side PFA testing of the device 100 because the opening 142 is sized to expose a portion of the diffusion regions 110N, 110P of the semiconductor device layer 110 in a sufficiently large size so that the exposed portions of the diffusion regions 110N, 110P can be properly imaged or otherwise inspected by the PFA tester 130 from the back side of the device 100.

[0055] The opening 142 may have a width 153 along a second direction (e.g., the y-axis direction), the width 153 being equal to or substantially equal to the width of the diffusion layers 110N and 110P along the second direction. In some embodiments, the width 153 of the opening 142 may be greater than the width of the diffusion layers 110N and 110P. In some embodiments, the width 153 of the opening 142 may be less than the width of the diffusion layers 110N and 110P. In some embodiments, the width 153 is in the range from about 10 nm less than the width of the diffusion layers 110N and 110P to about 10 nm greater than the width of the diffusion layers 110N and 110P. In some embodiments, the width 153 of the opening 142 is less than the length 152 of the opening 142. These dimensions for the width 153 of the opening 142 facilitate or improve back-side PFA testing of the device 100 because the opening 142 is sized to expose portions of the diffusion regions 110N, 110P of the semiconductor device layer 110 of a sufficiently large size so that the exposed portions of the diffusion regions 110N, 110P can be properly imaged or otherwise inspected by the PFA tester 130 from the back side of the device 100.

[0056] like Figure 2As shown, the openings 142 of the power lines 118 of the power delivery network may have a spacing 154, which can be measured along a first direction (e.g., the x-axis direction) between adjacent openings 142 of the power lines (e.g., between the centers of adjacent openings 142). In some embodiments, the spacing 154 is greater than the contact polysilicon spacing of the transistors of the semiconductor device layer 110. In some embodiments, the spacing 154 is greater than twice the contact polysilicon spacing of the transistors of the semiconductor device layer 110. In some embodiments, the spacing 154 is less than 20 times the contact polysilicon spacing, and in some embodiments, the spacing 154 is less than 10 times the contact polysilicon spacing. In some embodiments, the spacing 154 is in the range from about 2 times the contact polysilicon spacing to about 10 times the contact polysilicon spacing. In some embodiments, the spacing 154 is in the range from about 90 nm to about 450 nm. In some embodiments, the spacing 154 of the openings 142 is less than the spacing 151 of the power lines 118.

[0057] like Figure 2 As shown, the back-side power rails 116 may have a spacing 155, which may be measured along a second direction (e.g., the y-axis direction) between the first power rail 116a (e.g., the center of the first power rail 116a) and the second power rail 116b (e.g., the center of the second power rail 116b). In some embodiments, the spacing 155 is smaller than the cell height of the transistors or other components of the semiconductor device layer 110. In some embodiments, the spacing 155 is in the range from about half the cell height to about one time the cell height. In some embodiments, the spacing 155 is in the range from about 50 nm to about 100 nm.

[0058] Figure 2 The dimensions of the back-side power delivery network 118, back-side power rails 116, and back-side vias 120 of the back-side interconnect structure 106 shown offer several advantages, including reduced device scaling or increased density of semiconductor devices that can be provided in the semiconductor device layer 110, while also contributing to improved back-side PFA testing, as portions of the diffusion layers 110N and 110P exposed through the opening 142 can be properly imaged.

[0059] Figures 3A to 3C This is a plan view showing the method of manufacturing the back-side power delivery network 118, back-side power rails 116, and back-side vias 120 of the back-side interconnect structure 106.

[0060] like Figure 3AAs shown, a back-side via 120 can be formed in regions of the diffusion layers 110N and 110P. The back-side via 120 can be formed using any suitable technique. For example, in some embodiments, the back-side via 120 can be formed by an etching process that defines a via opening extending through a portion of the insulating layer 122 and exposing portions of the diffusion regions 110N and 110P (e.g., source / drain regions). The opening can then be at least partially filled with a conductive material to form the back-side via 120.

[0061] like Figure 3B As shown, the back-side power rail 116 is formed above the back-side via 120 and the diffusion layers 110N and 110P. For ease of explanation, Figure 3B Only the back power rail 116 is shown; however, it will be readily understood that the back power rail 116 is formed above the back via 120 and the diffusion layers 110N, 110P.

[0062] The back-side power rails 116 may include a plurality of power rails 116a, 116b, 116c that typically extend along a first direction (e.g., the x-axis direction). The power rails 116a, 116b, 116c are spaced apart from each other along a second direction, as shown. The power rails 116a, 116b, 116c may be formed on portions of the insulating layer 122 and are configured to contact the back-side via 120. Therefore, the back-side via 120 can connect the respective regions of the diffusion regions 110N, 110P to the power rails 116a, 116b, 116c. Power rails 116a, 116b, and 116c are configured to deliver electrical signals (e.g., VDD or VSS) to or receive electrical signals from semiconductor devices in semiconductor device layer 110, such as to conductive regions (e.g., source / drain regions) of semiconductor devices in diffusion regions 110N and 110P or from conductive regions of semiconductor devices in diffusion regions 110N and 110P.

[0063] The back-side power rails 116 can be formed using any suitable technique. For example, in some embodiments, the back-side power rails 116 are formed by patterned deposition to form power rails 116a, 116b, 116c having the shapes and dimensions discussed earlier herein. For example, portions of the insulating layer 122 can be selectively removed by photolithography or other patterning processes, and the back-side power rails 116a, 116b, 116c can be deposited.

[0064] like Figure 3CAs shown, a power delivery network 118 is formed above the back-side power rails 116. The power delivery network 118 may include one or more first power delivery lines 118a and one or more second power delivery lines 118b. The first power delivery lines 118a extend along a second direction (e.g., the y-axis direction) transverse to the first direction. The first power delivery lines 118a are configured to selectively receive voltage from a first voltage source (e.g., VDD) or deliver voltage to one or more of the back-side power rails 116. For example, each first power delivery line 118a may be electrically coupled to one or more of the back-side power rails 116, and thus can selectively receive voltage from the first voltage source or deliver voltage to one or more of the back-side power rails 116. The second power delivery lines 118b are configured to selectively receive voltage from a second voltage source (e.g., VSS) or deliver voltage to one or more of the back-side power rails 116. For example, each second power delivery line 118b may be electrically coupled to one or more of the back-side power rails 116, and thus can selectively receive voltage from the second voltage source or deliver voltage to one or more of the back-side power rails 116.

[0065] The power delivery network 118 can be formed using any suitable technique. For example, in some embodiments, the power delivery network is formed by patterned deposition to form power delivery lines 118a, 118b having the shapes and dimensions discussed earlier herein.

[0066] In some embodiments, the insulating layer 122 is formed in a multilayer process. For example, a first layer of the insulating layer 122 may be formed substantially around the back-side via 120, a second layer of the insulating layer 122 may be formed around the back-side power rail 116, and a third layer of the insulating layer 122 may be formed around the power delivery network 118.

[0067] Figures 4A to 4G A method for manufacturing device 100 according to some embodiments is shown.

[0068] like Figure 4A As shown, the method can begin with receiving a semiconductor device 200. Device 200 includes a semiconductor device layer 110, a plug circuit 112, an input / output layer 114, and a front-side interconnect structure 108, which may be the same as or substantially the same as those previously described herein.

[0069] Device 200 also includes a substrate 202 attached to the back side of semiconductor device layer 110. In some embodiments, a stop layer 204 may be included between substrate 202 and the back side of semiconductor device layer 110. Substrate 202 may be any suitable substrate. In some embodiments, substrate 202 is a semiconductor substrate, such as a silicon substrate. In some embodiments, stop layer 204 is a semiconductor layer, such as a silicon germanium (SiGe) layer.

[0070] In some embodiments, substrate 206 is attached to the front side of front interconnect structure 108, as shown. Substrate 206 can be any suitable substrate, and in some embodiments, substrate 206 is a dielectric layer or dielectric substrate. In some embodiments, substrate 206 can be an electrical insulator, such as a dielectric layer, used as an electrical insulating material between active regions or wires of device 200. For example, substrate 206 can electrically insulate portions of wires or components of front interconnect structure 108 from each other or from electrical contacts 124 (e.g., 124a, 124b). In some embodiments, substrate 206 is a glass substrate. In some embodiments, substrate 206 is an undoped silicate glass substrate.

[0071] In some embodiments, substrate 206 is bonded to the front side of front interconnect structure 108, for example, using any suitable bonding technique. In some embodiments, substrate 206 is formed by any suitable technique, including, for example, by deposition. In some embodiments, substrate 206 is an undoped silicate glass substrate or layer deposited by plasma-enhanced CVD (PECVD), HDP-CVD, SACVD, or any suitable deposition technique.

[0072] In some embodiments, a dielectric layer 208 is formed on a substrate 206. The dielectric layer 208 may be formed of any suitable dielectric material. In some embodiments, the dielectric layer 208 is a silicon nitride (SiN) layer. In some embodiments, an oxide layer 210 is formed on the dielectric layer 208. In some embodiments, the oxide layer 210 is a high-density plasma oxide.

[0073] like Figure 4B As shown, the method includes bonding a carrier substrate 212 to the device 200. The carrier substrate 212 can be bonded to the front side of the front interconnect structure 108 of the device 200 using any suitable technique. In some embodiments, the carrier substrate 212 is bonded to the device 200 via a thermal oxidation process (e.g., bonded to substrate 206). For example, the carrier substrate 212 may be a semiconductor substrate capable of forming a thermal oxide layer via a thermal oxidation process; in some embodiments, the thermal oxidation process may be a conventional thermal oxidation process. In some embodiments, the carrier substrate 212 may be a silicon substrate, and thermal oxidation may cause the formation of an oxide layer 214 that bonds the carrier substrate 212 to the device 200, for example, to an oxide layer 210.

[0074] like Figure 4CAs shown, substrate 202 and stop layer 204 are removed at the back side of device 200. Substrate 202 and stop layer 204 can be removed using any suitable technique. In some embodiments, substrate 202 and stop layer 204 can be removed by selectively removing stop layer 204, which causes release and removal of substrate 202. For example, in some embodiments, stop layer 204 can be removed by an etching process that selectively removes stop layer 204, thereby releasing substrate 202 from device 200 and allowing removal of substrate 202 and stop layer 204.

[0075] In some embodiments, the substrate 202 and the stop layer 204 can be removed by a thinning process. The thinning process can include any suitable thinning process, including, for example, mechanical polishing, chemical mechanical polishing (CMP), wet etching, and atmospheric downstream plasma (ADP) dry chemical etching (DCE).

[0076] like Figure 4D As shown, a back-side interconnect structure 106 is formed on the back side of the device 200. In some embodiments, forming the back-side interconnect structure 106 includes forming an insulating layer 122 on the back side of the device 200 and forming the back-side interconnect structure 106 in the insulating layer 122.

[0077] The back-side interconnect structure 106 can, for example, be connected via about Figures 3A to 3C The back-side interconnect structure 106 is formed using the processes shown and described. For example, the back-side interconnect structure 106 can be formed by forming back-side vias 120 that extend through the insulating layer 122 and contact regions (e.g., source / drain regions) of the diffusion regions 110N, 110P of the semiconductor device layer 110. In some embodiments, one or more of the back-side vias 120 are formed to contact electrical components within the plug layer 112. Back-side power rails 116 are formed over the back-side vias 120 and the semiconductor device layer 110, and may include a plurality of power rails as previously discussed herein. The back-side power rails may be formed on portions of the insulating layer 122 and are formed to contact the back-side vias 120. A power delivery network 118 may be formed over the back-side power rails 116, for example by deposition, and power delivery lines 118a, 118b of the back-side interconnect structure 106 may be formed to contact one or more of the back-side power rails 116.

[0078] The insulating layer 122 is formed to cover the back-side power rail 116, the back-side power delivery network 118, and the back-side via 12. The insulating layer 122 can be formed of any suitable insulating material, and in some embodiments, the insulating layer 122 electrically insulates or isolates the various electrical components within the back-side interconnect structure 106 from each other. In some embodiments, the insulating layer 122 can be formed of a dielectric material, which may include one or more of silicon dioxide (SiO2), SiON, SiOC, and SiOCN, or any other suitable insulating material.

[0079] like Figure 4E As shown, the method includes a second bonding process to bond a substrate 102 to the back side of a back-side interconnect structure 106. In some embodiments, the substrate 102 may be bonded to the back side of the back-side interconnect structure 106 via a bonding layer 104. The bonding layer 104 may be formed of any material to suitably bond the back-side interconnect structure 106 and the substrate 102, which may be a carrier wafer. In some embodiments, the bonding layer 104 includes an oxide layer, such as silicon dioxide. However, the embodiments provided herein are not limited thereto, and any other suitable material for the bonding layer 104 may be used in the various embodiments. In some embodiments, the bonding layer 104 is formed by a thermal oxidation process. For example, the carrier wafer may be or include silicon, which may be thermally oxidized to form the silicon dioxide bonding layer 104. In some embodiments, the thermal oxidation process may form an oxide layer 222 and a thermally oxidized layer 224.

[0080] like Figure 4F As shown, substrate 212 is removed from the front side of device 200. Substrate 212 can be removed using any suitable technique. In some embodiments, substrate 212 can be removed using a thinning process. The thinning process can include any suitable thinning process, including, for example, mechanical polishing, chemical mechanical polishing (CMP), wet etching, and atmospheric downstream plasma (ADP) dry chemical etching (DCE). In some embodiments, oxide layers 214 and 210 are removed simultaneously or during the same process as removing substrate 212. In some embodiments, dielectric layer 208 is exposed by removing substrate 212.

[0081] like Figure 4G As shown, device 100 is accomplished by forming electrical contacts 124. Electrical contacts 124 can be formed using any suitable technique, including by deposition, soldering, placement of solder balls, etc. Electrical contacts 124 can be formed on the uppermost metallization layer of the front-side interconnect structure 108. In some embodiments, electrical contacts 124 may include power contacts and input / output contacts. Although Figure 4G Only two electrical contacts 124 are shown, but it will be readily understood that any number of electrical contacts can be included in device 100 and can be coupled to various different metallization paths, such as plug circuit 112, semiconductor device layer 110, or input / output layer 114.

[0082] Figure 4G The device 100 shown is Figure 1A The device 100 shown is substantially the same; however, Figure 4GIt is also shown that substrate 206 and dielectric layer 208 can remain on the top surface of front interconnect structure 108, and electrical contacts 124 can be formed above substrate 206 and dielectric layer 208. Furthermore, as... Figure 4G As shown, a dielectric layer 230 that can extend between electrical contacts 124 can be formed on the dielectric layer 208.

[0083] Embodiments of the present invention offer several advantages. For example, the openings in the power rails allow Physical Failure Analysis (PFA) testing to be performed from the back side of the semiconductor device layer, without the radiation from the PFA tester being blocked by the power rails. Instead, the radiation can reach the exposed portions of the semiconductor device layer through the openings. This results in improved PFA testing of the device, which in turn improves device yield. Furthermore, by placing the power rails on the back side of the device, additional area can be used for signal routing on the front side.

[0084] Furthermore, the power rails of the present invention facilitate denser placement of semiconductor devices (e.g., transistors), while further allowing for efficient PFA testing of the devices without being obstructed by the power rails above. Additionally, due to the presence of openings in the power rails in some embodiments of the present invention, the maximum width of the power rails can be increased compared to conventional power rails. This results in power rails of the present invention having lower resistance than conventional power rails.

[0085] According to one embodiment, the device includes a semiconductor device layer comprising a plurality of diffusion regions. A first interconnect structure is disposed on a first side of the semiconductor device layer, and the first interconnect structure includes at least one electrical contact. A second interconnect structure is disposed on a second side of the semiconductor device layer, and the second interconnect structure includes a plurality of back-side power rails. Each of the back-side power rails at least partially overlaps with a corresponding diffusion region among the plurality of diffusion regions and defines an opening exposing a portion of the corresponding diffusion region located on the second side of the semiconductor device layer.

[0086] In another embodiment, a method is provided that includes forming a plurality of back-side power rails on the back side of a semiconductor device layer. The semiconductor device layer includes a plurality of diffusion regions, and each of the back-side power rails at least partially overlaps with a corresponding diffusion region among the plurality of diffusion regions and defines an opening exposing a portion of the corresponding diffusion region located on the back side of the semiconductor device layer. A front-side interconnect structure is disposed on the front side of the semiconductor device layer and includes at least one electrical contact.

[0087] In another embodiment, the method includes forming a front-side interconnect structure on a first side of a semiconductor device layer, the front-side interconnect structure including at least one electrical contact. A back-side interconnect structure is formed on a second side of the semiconductor device layer opposite to the first side. Forming the back-side interconnect structure includes forming a plurality of back-side power rails, each of which at least partially overlaps with a corresponding diffusion region among a plurality of diffusion regions of the semiconductor device layer and defines an opening exposing a portion of the corresponding diffusion region located on the second side of the semiconductor device layer. Forming the back-side interconnect structure also includes forming a back-side power delivery network on the plurality of back-side power rails, the plurality of back-side power rails being disposed between the back-side power delivery network and the second side of the semiconductor device layer.

[0088] Some embodiments of this application provide a semiconductor device comprising: a semiconductor device layer including a plurality of diffusion regions, the semiconductor device layer having a first side and a second side opposite to the first side; a first interconnect structure located on the first side of the semiconductor device layer, the first interconnect structure including at least one electrical contact; and a second interconnect structure located on the second side of the semiconductor device layer, the second interconnect structure including a plurality of back-side power rails, each of the back-side power rails at least partially overlapping a corresponding diffusion region among the plurality of diffusion regions and defining an opening exposing a portion of the corresponding diffusion region located on the second side of the semiconductor device layer. In some embodiments, the semiconductor device further includes: a substrate, the second interconnect structure being disposed between the substrate and the semiconductor device layer. In some embodiments, each of the back-side power rails has a length extending along a first direction, and the opening has a length in the first direction ranging from 45 nm to 450 nm. In some embodiments, each of the back-side power rails has a length extending along a first direction, and the opening has a length in the second direction ranging from 20 nm to 40 nm, the second direction being transverse to the first direction. In some embodiments, each of the back-side power rails has a length extending along a first direction, and the spacing between adjacent back-side power rails in a second direction transverse to the first direction is in the range of 50 nm to 100 nm. In some embodiments, each of the back-side power rails has a length extending along the first direction, and the spacing between adjacent openings of at least one of the back-side power rails is in the range of 90 nm to 450 nm. In some embodiments, the semiconductor device further includes a back-side power delivery network located on the plurality of back-side power rails, the plurality of back-side power rails being disposed between the back-side power delivery network and the second side of the semiconductor device layer. In some embodiments, the back-side power rails extend along the first direction, and the back-side power delivery network includes a plurality of power delivery lines extending along a second direction transverse to the first direction. In some embodiments, the spacing between adjacent power delivery lines in the plurality of power delivery lines in the first direction is in the range of 90 nm to 1000 nm. In some embodiments, the semiconductor device further includes a power management circuit transversely spaced from the semiconductor device layer, wherein the at least one electrical contact is electrically coupled to the power management circuit through the first interconnect structure.

[0089] Other embodiments of this application provide a method of forming a semiconductor device, comprising: forming a plurality of back-side power rails on the back side of a semiconductor device layer, the semiconductor device layer including a plurality of diffusion regions, each of the back-side power rails at least partially overlapping a corresponding diffusion region among the plurality of diffusion regions and defining an opening exposing a portion of the corresponding diffusion region located on the back side of the semiconductor device layer, wherein a front-side interconnect structure is disposed on the front side of the semiconductor device layer and includes at least one electrical contact. In some embodiments, the method further comprises: performing a physical failure analysis (PFA) test on the semiconductor device layer from the back side of the semiconductor device layer, the physical failure analysis test comprising irradiating the exposed portion of the diffusion region with radiation using a physical failure analysis tester. In some embodiments, forming the plurality of back-side power rails comprises forming each of the back-side power rails having a length extending along a first direction, and the opening having a first length along the first direction, the first length being in the range from the contact polysilicon spacing of a transistor in the semiconductor device layer to ten times the contact polysilicon spacing. In some embodiments, forming the plurality of back-side power rails includes forming each of the back-side power rails having a length extending along a second direction, and the opening having a second length along the second direction, the second length being less than a first length along the first direction. In some embodiments, forming the plurality of back-side power rails includes forming each of the back-side power rails having a length extending along a first direction, and the spacing between adjacent back-side power rails in the plurality of back-side power rails along a second direction transverse to the first direction is in the range of 50 nm to 100 nm. In some embodiments, forming the plurality of back-side power rails includes forming each of the back-side power rails having a length extending along a first direction and having a spacing between adjacent openings of at least one of the back-side power rails, the spacing being in the range of two to ten times the contact polysilicon spacing of the transistors in the semiconductor device layer. In some embodiments, the method further includes forming a back-side power delivery network on the plurality of back-side power rails, the plurality of back-side power rails being disposed between the back-side power delivery network and the back side of the semiconductor device layer. In some embodiments, forming the back-side power delivery network includes forming the plurality of back-side power rails having a spacing along the first direction between adjacent power delivery lines among the plurality of power delivery lines, the spacing being in the range of two times the contact polysilicon spacing of transistors in the semiconductor device layer to twenty-four times the contact polysilicon spacing.

[0090] Further embodiments of this application provide a method of forming a semiconductor device, comprising: forming a front-side interconnect structure on a first side of a semiconductor device layer, the front-side interconnect structure including forming at least one electrical contact; forming a back-side interconnect structure on a second side of the semiconductor device layer opposite to the first side, the back-side interconnect structure including: forming a plurality of back-side power rails, each of the back-side power rails at least partially overlapping a corresponding diffusion region among a plurality of diffusion regions of the semiconductor device layer and defining an opening exposing a portion of the corresponding diffusion region located on the second side of the semiconductor device layer; and forming a back-side power delivery network on the plurality of back-side power rails, the plurality of back-side power rails being disposed between the back-side power delivery network and the second side of the semiconductor device layer. In some embodiments, forming the back-side interconnect structure further includes: forming a plurality of back-side vias extending between the semiconductor device layer and the plurality of back-side power rails.

[0091] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

[0092] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalent embodiments enjoyed by such claims. Therefore, the claims are not limited to the invention.

Claims

1. A semiconductor device, comprising: A semiconductor device layer includes multiple diffusion regions, the semiconductor device layer having a first side and a second side opposite to the first side; A first interconnect structure is located on the first side of the semiconductor device layer, and the first interconnect structure includes at least one electrical contact. as well as A second interconnect structure is located on the second side of the semiconductor device layer. The second interconnect structure includes a plurality of back-side power rails, each of which at least partially overlaps with a corresponding diffusion region among the plurality of diffusion regions and defines an opening that exposes a portion of the corresponding diffusion region located on the second side of the semiconductor device layer.

2. The semiconductor device according to claim 1, further comprising: A substrate, wherein the second interconnect structure is disposed between the substrate and the semiconductor device layer.

3. The semiconductor device according to claim 1, wherein, Each of the plurality of back-side power rails has a length extending along a first direction, and the opening along the first direction has a length in the range of 45 nm to 450 nm.

4. The semiconductor device according to claim 1, wherein, Each of the plurality of back-side power rails has a length extending along a first direction, and the opening has a length in the range of 20 nm to 40 nm along a second direction, the second direction being orthogonal to the first direction.

5. The semiconductor device according to claim 1, wherein, Each of the plurality of back-side power rails has a length extending along a first direction, and the spacing between adjacent back-side power rails in the plurality of back-side power rails along a second direction orthogonal to the first direction is in the range of 50 nm to 100 nm.

6. The semiconductor device according to claim 1, wherein, Each of the plurality of back-side power rails has a length extending along a first direction, and the spacing between adjacent openings of at least one of the plurality of back-side power rails is in the range of 90 nm to 450 nm.

7. The semiconductor device according to claim 1, further comprising: A back-side power supply network is located on the plurality of back-side power rails, which are disposed between the back-side power supply network and the second side of the semiconductor device layer.

8. The semiconductor device according to claim 7, wherein, The plurality of back-side power rails extend along a first direction, and the back-side power delivery network includes a plurality of power delivery lines extending along a second direction orthogonal to the first direction.

9. The semiconductor device according to claim 8, wherein, The spacing between adjacent power transmission lines in the plurality of power transmission lines along the first direction is in the range of 90 nm to 1000 nm.

10. The semiconductor device according to claim 1, further comprising: The power management circuit is laterally spaced from the semiconductor device layer. The at least one electrical contact is electrically coupled to the power management circuit through the first interconnection structure.

11. A method of forming a semiconductor device, comprising: A plurality of back-side power rails are formed on the back side of a semiconductor device layer, the semiconductor device layer including a plurality of diffusion regions, each of the plurality of back-side power rails at least partially overlapping a corresponding diffusion region among the plurality of diffusion regions and defining an opening exposing the portion of the corresponding diffusion region located on the back side of the semiconductor device layer. The front interconnect structure is disposed on the front side of the semiconductor device layer and includes at least one electrical contact.

12. The method of claim 11, further comprising: Physical Fault Analysis (PFA) testing is performed on the semiconductor device layer from the back side, the physical fault analysis testing including irradiating the exposed portion of the diffusion region with radiation using a physical fault analysis tester.

13. The method according to claim 11, wherein, Forming the plurality of back-side power rails includes forming each of the plurality of back-side power rails having a length extending along a first direction, and the opening having a first length along the first direction, the first length being in the range from the contact polysilicon spacing of the transistor in the semiconductor device layer to ten times the contact polysilicon spacing.

14. The method according to claim 13, wherein, Forming the plurality of back-side power rails includes forming each of the plurality of back-side power rails having a width extending along a second direction, and the opening having a first width along the second direction, the first width being less than the first length along the first direction.

15. The method according to claim 11, wherein, Forming the plurality of back-side power rails includes forming each of the plurality of back-side power rails having a length extending along a first direction, and the spacing between adjacent back-side power rails in the plurality of back-side power rails along a second direction orthogonal to the first direction is in the range of 50 nm to 100 nm.

16. The method according to claim 11, wherein, Forming the plurality of back-side power rails includes forming each of the plurality of back-side power rails, each of the plurality of back-side power rails having a length extending along a first direction and having a spacing between adjacent openings of at least one of the plurality of back-side power rails, the spacing being in the range of two to ten times the contact polysilicon spacing of the transistors in the semiconductor device layer.

17. The method of claim 11, further comprising: A back-side power supply network is formed on the plurality of back-side power rails, and the plurality of back-side power rails are disposed between the back-side power supply network and the back side of the semiconductor device layer.

18. The method according to claim 17, wherein, Forming the back-side power delivery network includes forming a plurality of power delivery lines having a spacing in a first direction between adjacent power delivery lines, the spacing being in the range of two times to twenty-four times the contact polysilicon spacing of transistors in the semiconductor device layer.

19. A method of forming a semiconductor device, comprising: A front-side interconnect structure is formed on a first side of the semiconductor device layer, wherein forming the front-side interconnect structure includes forming at least one electrical contact. A back-side interconnect structure is formed on the second side of the semiconductor device layer opposite to the first side, wherein forming the back-side interconnect structure includes: A plurality of back-side power rails are formed, each of the plurality of back-side power rails at least partially overlapping a corresponding diffusion region among a plurality of diffusion regions of the semiconductor device layer and defining an opening that exposes a portion of the corresponding diffusion region located on the second side of the semiconductor device layer; as well as A back-side power supply network is formed on the plurality of back-side power rails, and the plurality of back-side power rails are disposed between the back-side power supply network and the second side of the semiconductor device layer.

20. The method according to claim 19, wherein, The back-side interconnect structure further includes: Multiple back-side vias are formed extending between the semiconductor device layer and the multiple back-side power rails.

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