A display panel and a method for manufacturing the same

Abstract

The present invention provides a display panel and a manufacturing method thereof, the manufacturing method comprising: providing a first substrate, one side of the first substrate has a plurality of spaced Micro-LED chips; providing a second substrate, one side surface of the second substrate has a plurality of conductive layers; forming an isolation layer on the second substrate, the isolation layer has a plurality of opening groups, each opening group includes a first opening and a second opening exposing the surface of the conductive layer, the width of the first opening is smaller than the width of the P-type electrode, and the width of the second opening is smaller than the width of the N-type electrode; forming a first bonding layer in the first opening, and forming a second bonding layer in the second opening; using the isolation layer to support the chip body, bonding the P-type electrode to the first bonding layer, and bonding the N-type electrode to the second bonding layer, the P-type electrode is embedded in the first bonding layer, and the N-type electrode is embedded in the second bonding layer. The method avoids the bonding failure between the Micro-LED chip and the first bonding layer and the second bonding layer.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a method for preparing the same. Background Art

[0002] Light Emitting Diode (LED) is an important optoelectronic semiconductor component. Light Emitting Diode has the advantages of low power consumption, small size, high brightness, easy matching with integrated circuits, and high reliability, so it is widely used as a light source. With the development of technology, Micro-LED has been applied in display, optical communication, indoor positioning, biology and medical fields, and is expected to be further expanded to wearable / implantable devices, augmented reality / virtual reality, vehicle display, ultra-large display, optical communication / optical interconnection, medical detection, smart car lights, space imaging and other fields, with clear and considerable market prospects. The application of Micro-LED chips in display technology requires millions or even tens of millions of Micro-LED chips to be accurately and efficiently moved to the display panel. Taking a 4K TV as an example, the number of Micro-LED chips that need to be transferred is as high as 24 million (calculated based on 4000×2000×R / G / B three colors). Even if 10,000 Micro-LED chips are transferred at a time, it needs to be repeated 2,400 times.

[0003] However, the prior art suffers from poor accuracy in the bonding position of the Micro-LED chip and the substrate, resulting in failure of the bonding between the Micro-LED chip and the bonding layer. Summary of the invention

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the problem of bonding failure between the Micro-LED chip and the bonding layer in the prior art, thereby providing a display panel and a method for preparing the same.

[0005] The present invention provides a method for preparing a display panel, comprising: providing a first substrate, wherein one side of the first substrate has a plurality of spaced Micro-LED chips, wherein the Micro-LED chip comprises: a chip body; a P-type electrode and an N-type electrode, which are located on a partial surface of one side of the chip body; providing a second substrate, wherein one side surface of the second substrate has a plurality of conductive layers; forming an isolation layer on the second substrate, wherein the isolation layer has a plurality of opening groups, wherein each opening group comprises a first opening and a second opening spaced apart, wherein the first opening and the second opening respectively expose the surface of the conductive layer, wherein the width of the first opening is smaller than the width of the P-type electrode, and the width of the second opening is smaller than the width of the N-type electrode; forming a first bonding layer in the first opening, and forming a second bonding layer in the second opening; supporting the chip body with the isolation layer, bonding the P-type electrode to the first bonding layer, and bonding the N-type electrode to the second bonding layer at the same time, wherein the P-type electrode is embedded in the first bonding layer, and the N-type electrode is embedded in the second bonding layer.

[0006] Optionally, the chip body includes: an N-type semiconductor layer; an active layer located on a portion of the surface on one side of the N-type semiconductor layer; a P-type semiconductor layer located on a surface of the active layer facing away from the N-type semiconductor layer; the P-type electrode is located on a portion of the surface of the P-type semiconductor layer facing away from the active layer; the N-type electrode is located on a portion of the surface on one side of the N-type semiconductor layer on the sides of the active layer, the P-type semiconductor layer and the P-type electrode; in the process of bonding the P-type electrode to the first bonding layer and bonding the N-type electrode to the second bonding layer, the isolation layer is used to support the P-type semiconductor layer around the P-type electrode.

[0007] Optionally, it also includes: before forming the first bonding layer in the first opening, forming a first slope surface at the junction between the side wall of the first opening and the top surface of the isolation layer around the first opening; before forming the second bonding layer in the second opening, forming a second slope surface at the junction between the side wall of the second opening and the top surface of the isolation layer around the second opening.

[0008] Optionally, a first angle is formed between the top surface of the isolation layer connected to the first slope surface and the first slope surface; tan(180°-θ1)>μ1, θ1 is the first angle, and μ1 is the friction coefficient of the first slope surface.

[0009] Optionally, a second angle is formed between the top surface of the isolation layer connected to the second slope surface and the second slope surface; tan(180°-θ2)>μ2; θ2 is the second angle, and μ2 is the friction coefficient of the second slope surface.

[0010] Optionally, it also includes: before bonding the P-type electrode to the first bonding layer and the N-type electrode to the second bonding layer, forming a blocking layer on the isolation layer around the opening group, the blocking layer having a third opening, and the width of the third opening is greater than the width of the Micro-LED chip.

[0011] Optionally, the width of the third opening is less than or equal to 1.5 times the width of the Micro-LED chip.

[0012] Optionally, the blocking layer is a light-shielding blocking layer.

[0013] Optionally, the material of the light-shielding blocking layer is light-shielding resin.

[0014] Optionally, after the P-type electrode is bonded to the first bonding layer and the N-type electrode is bonded to the second bonding layer, the height of the top surface of the barrier layer facing away from the second substrate is greater than the height of the top surface of the Micro-LED chip facing away from the second substrate.

[0015] Optionally, in the process of bonding the P-type electrode to the first bonding layer and the N-type electrode to the second bonding layer, the binding device used has a characteristic alignment accuracy; the width of the first opening is greater than or equal to the sum of the width of the P-type electrode and 2 times the characteristic alignment accuracy, and the width of the second opening is greater than or equal to the sum of the width of the N-type electrode and 2 times the characteristic alignment accuracy.

[0016] Optionally, in the step of forming a first bonding layer in the first opening and forming a second bonding layer in the second opening, the thickness of the first bonding layer is greater than or equal to 80% of the depth of the first opening and less than or equal to the depth of the first opening, and the thickness of the second bonding layer is greater than or equal to 80% of the depth of the second opening and less than or equal to the depth of the second opening.

[0017] Optionally, the thickness of the isolation layer is less than or equal to 50% of the difference in thickness between the N-type electrode and the P-type electrode.

[0018] Optionally, the isolation layer has a thickness of 500nm to 1000nm.

[0019] Optionally, the material of the first bonding layer and the second bonding layer is solder; the material of the first bonding layer and the second bonding layer is conductive glue.

[0020] The present invention also provides a display panel, comprising: a first substrate, one side of the first substrate having a plurality of spaced Micro-LED chips, the Micro-LED chip comprising: a chip body; a P-type electrode and an N-type electrode, located on a partial surface of one side of the chip body; a second substrate, one side surface of the second substrate having a plurality of conductive layers; an isolation layer located on one side of the second substrate, the isolation layer having a plurality of opening groups, each opening group comprising a first opening and a second opening spaced apart, the first opening and the second opening being respectively located on the conductive layer, the width of the first opening being smaller than the width of the P-type electrode, and the width of the second opening being smaller than the width of the N-type electrode; a first bonding layer located in the first opening; a second bonding layer located in the second opening; the P-type electrode being embedded in the first bonding layer, and the N-type electrode being embedded in the second bonding layer; the chip body being in contact with the top surface of a portion of the isolation layer.

[0021] Optionally, the chip body includes: an N-type semiconductor layer; an active layer located on a portion of the surface on one side of the N-type semiconductor layer; a P-type semiconductor layer located on a surface of the active layer facing away from the N-type semiconductor layer; the P-type electrode located on a portion of the surface of the P-type semiconductor layer facing away from the active layer; the N-type electrode located on a portion of the surface of the N-type semiconductor layer on the sides of the active layer, the P-type semiconductor layer and the P-type electrode; the P-type semiconductor layer around the P-type electrode is in contact with the top surface of the isolation layer around the first opening.

[0022] Optionally, a first slope surface is provided between the sidewall of the first opening and the top surface of the isolation layer around the first opening; and a second slope surface is provided between the sidewall of the second opening and the top surface of the isolation layer around the second opening.

[0023] Optionally, a first angle is formed between the top surface of the isolation layer connected to the first slope surface and the first slope surface; tan(180°-θ1)>μ1, θ1 is the first angle, and μ1 is the friction coefficient of the first slope surface.

[0024] Optionally, a second angle is formed between the top surface of the isolation layer connected to the second slope surface and the second slope surface; tan(180°-θ2)>μ2; θ2 is the second angle, and μ2 is the friction coefficient of the second slope surface.

[0025] Optionally, it also includes: a blocking layer, located on the isolation layer around the opening group, the blocking layer having a third opening, and the width of the third opening is greater than the width of the Micro-LED chip.

[0026] Optionally, the width of the third opening is less than or equal to 1.5 times the width of the Micro-LED chip.

[0027] Optionally, the blocking layer is a light-shielding blocking layer.

[0028] Optionally, the material of the light-shielding blocking layer is light-shielding resin.

[0029] Optionally, after the P-type electrode is bonded to the first bonding layer and the N-type electrode is bonded to the second bonding layer, the height of the top surface of the barrier layer facing away from the second substrate is greater than the height of the top surface of the Micro-LED chip facing away from the second substrate.

[0030] Optionally, the width of the first opening is greater than or equal to the sum of the width of the P-type electrode and twice the feature alignment accuracy, and the width of the second opening is greater than or equal to the sum of the width of the N-type electrode and twice the feature alignment accuracy, and the feature alignment accuracy is 0.5μm to 2μm.

[0031] Optionally, the thickness of the first bonding layer is greater than or equal to 80% and less than or equal to the depth of the first opening, and the thickness of the second bonding layer is greater than or equal to 80% and less than or equal to the depth of the second opening.

[0032] Optionally, the thickness of the isolation layer is less than or equal to 50% of the difference in thickness between the N-type electrode and the P-type electrode.

[0033] Optionally, the isolation layer has a thickness of 500nm to 1000nm.

[0034] Optionally, the material of the first bonding layer and the second bonding layer is solder; the material of the first bonding layer and the second bonding layer is conductive glue.

[0035] The technical solution of the present invention has the following beneficial effects:

[0036] The method for preparing a display panel provided by the technical solution of the present invention supports the chip body with the isolation layer, bonds the P-type electrode to the first bonding layer and bonds the N-type electrode to the second bonding layer at the same time, the P-type electrode is embedded in the first bonding layer, and the N-type electrode is embedded in the second bonding layer. The first opening allows the P-type electrode to enter, and the second opening allows the N-type electrode to enter. The isolation layer supports the chip body around the P-type electrode, increasing the self-alignment function. The lateral offset of the Micro-LED chip is limited by the side walls of the first opening and the side walls of the second opening, ensuring the stability of the bonding. Secondly, the material of the first bonding layer can be limited in the first opening, and the material of the second bonding layer can be limited in the second opening, reducing the lateral offset of the material of the first bonding layer and the material of the second bonding layer during the bonding process, and avoiding short circuits between the first bonding layer and the second bonding layer. In summary, the bonding failure between the Micro-LED chip and the first bonding layer and the second bonding layer is avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 to Figure 2 is a schematic diagram of a process for preparing a display panel;

[0039] Figure 3 to Figure 4 is a schematic diagram of another process for preparing a display panel;

[0040] Figures 5 to 10 A schematic diagram of a process for preparing a display panel provided by an embodiment of the present invention;

[0041] Figures 11 to 13 A schematic diagram of a process for preparing a display panel provided by another embodiment of the present invention;

[0042] Figures 14 to 16 A schematic diagram of a process for preparing a display panel provided in accordance with another embodiment of the present invention. DETAILED DESCRIPTION

[0043] As described in the background art, the prior art has the problem that the accuracy of the bonding position between the Micro-LED chip and the substrate is poor, resulting in bonding failure.

[0044] A method for preparing a display panel, comprising: referring to Figure 1, providing a first substrate 101, the first substrate having a conductive column 102, the surface of the conductive column 102 facing away from the first substrate 101 is provided with solder 103; providing a second substrate 105, a side surface of the second substrate 105 having a plurality of spaced Micro-LED chips 104; the second substrate 105 and the first substrate 101 are arranged opposite to each other, and the electrodes of the Micro-LED chips 104 face the solder 103; referring to Figure 2 , soldering the electrodes of the Micro-LED chip 104 to the solder 103 .

[0045] However, during the process of welding the electrodes of the Micro-LED chip 104 and the solder 103 together, there will be a certain deviation between the electrodes of the Micro-LED chip 104 and the solder 103, resulting in cold solder joints or even short circuits. Research has found that the reasons are: 1. During the alignment process of the electrodes of the Micro-LED chip 104 and the solder 103, they are limited by the alignment accuracy of the alignment equipment; 2. Reflow soldering is used to weld the electrodes of the Micro-LED chip 104 and the solder 103. During the reflow soldering process, the solder 103 will melt, and the position of the electrodes of the Micro-LED chip 104 relative to the solder 103 will shift; 3. The eutectic vacuum furnace used to weld the electrodes of the Micro-LED chip 104 and the solder 103 together does not have a pressure system, and cannot ensure that the relative position of the Micro-LED chip 104 and the solder 103 remains unchanged.

[0046] Another method for preparing a display panel, referring to Figure 3 , providing a first substrate 101a, wherein the surface of the first substrate 101a has a plurality of electrodes (not shown), the surface of the electrodes has a conductive colloid 102a, and the conductive colloid 102a has conductive particles 106 inside; referring to Figure 6 , providing a second substrate 105, a side surface of the second substrate 105 has a plurality of spaced Micro-LED chips 104, the Micro-LED chips 104 including a P-type electrode and an N-type electrode; referring to Figure 4 , the second substrate 105 and the first substrate 101a are arranged opposite to each other, the P-type electrode of the Micro-LED chip 104 is bonded to a part of the conductive colloid 102a, and the N-type electrode of the Micro-LED chip 104 is bonded to a part of the conductive colloid 102a.

[0047] However, during the process of bonding the N-type electrode of the Micro-LED chip 104 to a portion of the conductive colloid 102 a , when the distance between the N-type electrode and the P-type electrode is small, a short circuit between the N-type electrode and the P-type electrode may occur.

[0048] In the above method, the risk of bonding failure between the electrodes of the Micro-LED chip 104 and the bonding layer (solder 103 or conductive colloid 102a) is relatively high.

[0049] The present invention provides a display panel and a method for preparing the same, which can avoid bonding failure between a Micro-LED chip and a bonding layer.

[0050] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0051] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0052] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0053] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0054] Example 1

[0055] An embodiment of the present invention provides a method for manufacturing a display panel, comprising:

[0056] S1: providing a first substrate, wherein one side of the first substrate has a plurality of spaced Micro-LED chips, wherein the Micro-LED chip comprises: a chip body; a P-type electrode and an N-type electrode, which are located on a portion of a surface of one side of the chip body;

[0057] S2: providing a second substrate, wherein a surface of one side of the second substrate has a plurality of conductive layers;

[0058] S3: forming an isolation layer on the second substrate, wherein the isolation layer has a plurality of opening groups, each of the opening groups includes a first opening and a second opening spaced apart from each other, the first opening and the second opening respectively expose a surface of the conductive layer, the width of the first opening is smaller than the width of the P-type electrode, and the width of the second opening is smaller than the width of the N-type electrode;

[0059] S4: forming a first bonding layer in the first opening, and forming a second bonding layer in the second opening;

[0060] S5: The chip body is supported by the isolation layer, and the P-type electrode is bonded to the first bonding layer and the N-type electrode is bonded to the second bonding layer at the same time, the P-type electrode is embedded in the first bonding layer, and the N-type electrode is embedded in the second bonding layer.

[0061] In this embodiment, the first opening allows the P-type electrode to enter, and the second opening allows the N-type electrode to enter. The isolation layer supports the chip body around the P-type electrode, increasing the self-alignment function. The lateral offset of the Micro-LED chip is limited by the side walls of the first opening and the second opening, ensuring the stability of the bonding. Secondly, the material of the first bonding layer can be limited in the first opening, and the material of the second bonding layer can be limited in the second opening, reducing the lateral offset of the material of the first bonding layer and the material of the second bonding layer during the bonding process, and avoiding a short circuit between the first bonding layer and the second bonding layer. In summary, the bonding failure between the Micro-LED chip and the first bonding layer and the second bonding layer is avoided.

[0062] Combine the following Figures 5 to 10 Provide a detailed description.

[0063] refer to Figure 5 A first substrate 300 is provided, and one side of the first substrate 300 has a plurality of spaced Micro-LED chips, and the Micro-LED chip includes: a chip body; a P-type electrode 304 and an N-type electrode 305, which are located on a partial surface of one side of the chip body.

[0064] The chip body includes: an N-type semiconductor layer 301; an active layer 302 located on a portion of the surface on one side of the N-type semiconductor layer 301; a P-type semiconductor layer 303 located on a side of the active layer 302 away from the N-type semiconductor layer 301; the P-type electrode 304 located on a portion of the surface of the P-type semiconductor layer 303 away from the active layer 302; and the N-type electrode 305 located on a portion of the surface on one side of the N-type semiconductor layer 301 at the sides of the active layer 302, the P-type semiconductor layer 303 and the P-type electrode 304.

[0065] In this embodiment, the P-type electrode 304 is located on a surface of a portion of the P-type semiconductor layer 303 that is away from the active layer 302 , that is, a portion of the surface of the P-type semiconductor layer 303 is not covered by the P-type electrode 304 .

[0066] In one embodiment, the difference between the total area of ​​the surface of the P-type semiconductor layer 303 facing away from the active layer 302 and the projected area of ​​the P-type electrode 304 on the surface of the P-type semiconductor layer 303 is 50 μm. 2 ~200μm 2 , for example 50 μm 2 、80μm 2 , 100μm 2 , 120μm 2 、150μm 2 、180μm 2 or 200 μm 2 .

[0067] In one embodiment, the distance between the N-type electrode 305 and the P-type electrode 304 in the Micro-LED chip is 5 micrometers to 6 micrometers.

[0068] refer to Figure 6 A second substrate 201 is provided, and a surface of one side of the second substrate 201 has a plurality of conductive layers 206.

[0069] The second substrate 201 is a driving substrate, and includes a substrate body and a driving circuit located on one side of the substrate body. The conductive layer is located on the side of the driving circuit away from the substrate body, and the conductive layer 206 is electrically connected to the driving circuit.

[0070] The conductive layer 206 is a contact electrode, and is formed by film formation, photolithography, and etching. The material of the conductive layer 206 includes metal or alloy, and the metal is, for example, Al, Ti, or Mo.

[0071] refer to Figure 7An isolation layer 207 is formed on the second substrate 201, and the isolation layer 207 has a plurality of opening groups, each of which includes a first opening 2071 and a second opening 2072 spaced apart from each other. The first opening 2071 and the second opening 2072 respectively expose the surface of the conductive layer 206, and the width of the first opening 2071 is smaller than the width of the P-type electrode 304, and the width of the second opening 2072 is smaller than the width of the N-type electrode 305.

[0072] The step of forming the isolation layer 207 includes: forming an initial isolation layer (not shown) covering the conductive layer 206 on the second substrate 201 ; and patterning the initial isolation layer so that the initial isolation layer forms the isolation layer 207 .

[0073] In one embodiment, the thickness of the isolation layer 207 is less than or equal to 50% of the difference in thickness between the N-type electrode 305 and the P-type electrode 304. The thickness of the isolation layer 207 refers to the dimension in the direction perpendicular to the surface of the second substrate 201; the thickness of the N-type electrode 305 and the thickness of the P-type electrode 304 both refer to the dimension in the direction perpendicular to the surface of the first substrate. The advantages of this arrangement are: the thickness of the isolation layer 207 is relatively thin, saving costs; at the same time, it can ensure that the P-type electrode 304 has better contact with the material of the subsequent first bonding layer, and the N-type electrode 305 has better contact with the material of the subsequent second bonding layer.

[0074] In a specific embodiment, the thickness of the isolation layer 207 is 500 nm to 1000 nm.

[0075] The material of the isolation layer 207 includes SiO2 or Si3N4.

[0076] The width of the conductive layer 206 at the bottom of the first opening 2071 is greater than or equal to the width of the first opening 2071, and the width of the conductive layer 206 at the bottom of the second opening 2072 is greater than or equal to the width of the second opening 2072. The width of the conductive layer 206 at the bottom of the first opening 2071 is greater than or equal to the sum of the width of the P-type electrode 304 and 2 times the feature alignment accuracy, and the width of the conductive layer 206 at the bottom of the second opening 2072 is greater than or equal to the sum of the N-type electrode 305 and 2 times the feature alignment accuracy. The feature alignment accuracy is the alignment accuracy of the binding device used in the subsequent process of bonding the P-type electrode 304 to the first bonding layer 2081 and the N-type electrode 305 to the second bonding layer 2082.

[0077] refer to Figure 8 , a first bonding layer 2081 is formed in the first opening 2071 , and a second bonding layer 2082 is formed in the second opening 2072 .

[0078] In one embodiment, the material of the first bonding layer 2081 and the second bonding layer 2082 is solder, and the solder includes In solder or lead-free solder containing tin.

[0079] In another embodiment, the material of the first bonding layer 2081 and the second bonding layer 2082 is conductive glue, and the conductive glue is anisotropic conductive glue.

[0080] The melting point of the first bonding layer 2081 is lower than the melting point of the conductive layer 206 and lower than the melting point of the isolation layer 207. The melting point of the second bonding layer 2082 is lower than the melting point of the conductive layer 206 and lower than the melting point of the isolation layer 207.

[0081] In the steps of forming the first bonding layer 2081 in the first opening 2071 and forming the second bonding layer 2082 in the second opening 2072, the thickness of the first bonding layer 2081 is greater than or equal to 80% of the depth of the first opening 2071 and less than or equal to the depth of the first opening 2071, and the thickness of the second bonding layer 2082 is greater than or equal to 80% of the depth of the second opening 2072 and less than or equal to the depth of the second opening 2072. In this way, in the subsequent bonding process, the material of the first bonding layer 2081 can surround the P-type electrode, the material of the second bonding layer 2082 can surround the N-type electrode, and the overflow of the material of the first bonding layer 2081 and the material of the second bonding layer 2082 can be prevented from causing a short circuit.

[0082] In a specific embodiment, the thickness of the first bonding layer 2081 is 400 nm to 800 nm, and the thickness of the second bonding layer 2082 is 400 nm to 800 nm.

[0083] refer to Fig. 9 The chip body is supported by the isolation layer 207, the P-type electrode 304 is bonded to the first bonding layer 2081, and the N-type electrode 305 is bonded to the second bonding layer 2082. The P-type electrode 304 is embedded in the first bonding layer 2081, and the N-type electrode 305 is embedded in the second bonding layer 2082.

[0084] During the process of bonding the P-type electrode 304 to the first bonding layer 2081 and bonding the N-type electrode 305 to the second bonding layer 2082 , the isolation layer 207 supports the P-type semiconductor layer 303 around the P-type electrode 304 .

[0085] In the process of bonding the P-type electrode 304 to the first bonding layer 2081 and the N-type electrode 305 to the second bonding layer 2082, the binding device used has a characteristic alignment accuracy; the width of the first opening 2071 is greater than or equal to the sum of the width of the P-type electrode 304 and 2 times the characteristic alignment accuracy, and the width of the second opening 2072 is greater than or equal to the sum of the width of the N-type electrode 305 and 2 times the characteristic alignment accuracy. In one embodiment, the characteristic alignment accuracy is 0.5μm to 2μm.

[0086] When the material of the first bonding layer 2081 and the second bonding layer 2082 is solder, reflow soldering is used to bond the P-type electrode 304 to the first bonding layer 2081 and to bond the N-type electrode 305 to the second bonding layer 2082 .

[0087] When the material of the first bonding layer 2081 and the second bonding layer 2082 is conductive glue, the P-type electrode 304 is squeezed with the first bonding layer 2081, and the P-type electrode 304 is interconnected with the conductive particles in the first bonding layer 2081; the N-type electrode 305 is squeezed with the second bonding layer 2082, and the N-type electrode 305 is interconnected with the conductive particles in the second bonding layer 2082.

[0088] The first opening 2071 allows the P-type electrode 304 to enter, and the second opening 2072 allows the N-type electrode 305 to enter, and the isolation layer 207 supports the P-type semiconductor layer 303 around the P-type electrode 304. This not only increases the self-alignment function, but also ensures the flatness of the top surface of all Micro-LED chips away from the second substrate to a certain extent, so that the consistency of the light output angle of the Micro-LED chip is enhanced; and the effective light emitting area of ​​the Micro-LED chip is increased.

[0089] refer to Fig.10 , debonding the Micro-LED chip from the first substrate 300.

[0090] In a specific embodiment, ultraviolet light is used to debond the first substrate 300 and the Micro-LED chip.

[0091] Example 2

[0092] refer to Fig.11 , Fig.11 For Figure 7 Based on the schematic diagram, a first slope surface A1 is formed at the junction between the side wall of the first opening 2071 and the top surface of the isolation layer 207 around the first opening 2071; a second slope surface A2 is formed at the junction between the side wall of the second opening 2072 and the top surface of the isolation layer 207 around the second opening 2072.

[0093] In one embodiment, a first angle is formed between the top surface of the isolation layer 207 connected to the first slope surface A1 and the first slope surface A1; tan(180°-θ1)>μ1, θ1 is the first angle, and μ1 is the friction coefficient of the first slope surface.

[0094] In one embodiment, a second angle is formed between the top surface of the isolation layer 207 connected to the second slope surface A2 and the second slope surface A2; tan(180°-θ2)>μ2; θ2 is the second angle, and μ2 is the friction coefficient of the second slope surface.

[0095] The advantage of setting the first angle and the second angle is that it ensures that the P-type electrode 304 of the Micro-LED chip can automatically enter the first opening, and the N-type electrode 305 of the Micro-LED chip can automatically enter the second opening, thereby reducing the yield loss to a certain extent.

[0096] refer to Fig.12 After forming the first slope surface A1, a first bonding layer 2081a is formed in the first opening 2071; after forming the second slope surface A2, a second bonding layer 2082a is formed in the second opening 2072.

[0097] refer to Fig.13 , the chip body is supported by the isolation layer 207, the P-type electrode 304 is bonded to the first bonding layer 2081a, and the N-type electrode 305 is bonded to the second bonding layer 2082a, the P-type electrode 304 is embedded in the first bonding layer 2081a, and the N-type electrode 305 is embedded in the second bonding layer 2082a; then, the Micro-LED chip is debonded from the first substrate 300.

[0098] Example 3

[0099] refer to Fig.14 , Fig.14 For Figure 7 Based on the schematic diagram, a blocking layer 211 is formed on the isolation layer 207 around the opening group, and the blocking layer 211 has a third opening, and the width of the third opening is greater than the width of the Micro-LED chip.

[0100] In one embodiment, the material of the barrier layer 211 is a light-shielding resin, which is a resin with a light-shielding effect, but the material of the barrier layer 211 is not limited to this material. The width of the third opening should be slightly larger than the width of the Micro-LED chip to ensure that the Micro-LED chip can smoothly fall into the third opening. One third opening corresponds to one Micro-LED chip.

[0101] The function of the barrier layer 211 includes: limiting the position of the Micro-LED chip, and one Micro-LED chip falls into one third opening.

[0102] In one embodiment, the blocking layer 211 is a light-shielding blocking layer. The blocking layer 211 is used to block the crosstalk between the lights emitted by adjacent Micro-LED chips. The material of the light-shielding blocking layer may be, for example, a light-shielding resin.

[0103] The blocking layer 211 may also be made of a non-light-shielding material.

[0104] In one embodiment, a width of the third opening is greater than a width of the Micro-LED chip and less than or equal to 1.5 times the width of the Micro-LED chip.

[0105] In one embodiment, the barrier layer 211 is a light shielding barrier layer. After the P-type electrode is bonded to the first bonding layer and the N-type electrode is bonded to the second bonding layer, the height of the top surface of the barrier layer 211 facing away from the second substrate is greater than the height of the top surface of the Micro-LED chip facing away from the second substrate. The advantage of this arrangement is that it can better avoid crosstalk between the lights emitted by adjacent Micro-LED chips.

[0106] It should be noted that, in other embodiments, after the P-type electrode is bonded to the first bonding layer and the N-type electrode is bonded to the second bonding layer, the height of the top surface of the barrier layer 211 facing away from the second substrate is less than or equal to the height of the top surface of the Micro-LED chip facing away from the second substrate.

[0107] In this embodiment, the first slope surface is formed at the junction between the sidewall of the first opening 2071 and the top surface of the isolation layer 207 around the first opening 2071; and the second slope surface is formed at the junction between the sidewall of the second opening 2072 and the top surface of the isolation layer 207 around the second opening 2072. After the first slope surface and the second slope surface are formed, the barrier layer 211 is formed. The description of the first slope surface and the second slope surface refers to the above-mentioned embodiment and will not be described in detail.

[0108] It should be noted that, in other embodiments, when the barrier layer 211 is formed, the first slope surface and the second slope surface may not be provided.

[0109] refer to Fig.15 , a first bonding layer 2081 b is formed in the first opening 2071 ; and a second bonding layer 2082 b is formed in the second opening 2072 .

[0110] In this embodiment, the first bonding layer 2081b and the second bonding layer 2082b are formed after the barrier layer 211 is formed. In other embodiments, the barrier layer 211 is formed after the first bonding layer 2081b and the second bonding layer 2082b are formed.

[0111] refer to Fig.16 The isolation layer 207 is used to support the chip body, and the P-type electrode 304 is bonded to the first bonding layer 2081b while the N-type electrode 305 is bonded to the second bonding layer 2082b. The P-type electrode 304 is embedded in the first bonding layer 2081b, and the N-type electrode 305 is embedded in the second bonding layer 2082b.

[0112] Example 4

[0113] This embodiment provides a display panel, referring to Fig.10 ,include:

[0114] A plurality of spaced Micro-LED chips, each of which comprises: a chip body; a P-type electrode 304 and an N-type electrode 305, which are located on a portion of a surface of one side of the chip body;

[0115] A second substrate 201, wherein a surface of one side of the second substrate 201 has a plurality of conductive layers 206;

[0116] An isolation layer 207 located on one side of the second substrate 201, wherein the isolation layer 207 has a plurality of opening groups, each of which includes a first opening and a second opening spaced apart from each other, wherein the first opening and the second opening are located on the conductive layer 206, respectively, wherein the width of the first opening is smaller than the width of the P-type electrode 304, and the width of the second opening is smaller than the width of the N-type electrode 305;

[0117] a first bonding layer located in the first opening;

[0118] a second bonding layer located in the second opening;

[0119] The P-type electrode 304 is embedded in the first bonding layer, and the N-type electrode 305 is embedded in the second bonding layer; the chip body is in contact with the top surface of a portion of the isolation layer 207 .

[0120] The chip body includes: an N-type semiconductor layer 301; an active layer 302 located on a portion of the surface of one side of the N-type semiconductor layer 301; a P-type semiconductor layer 303 located on a side of the active layer 302 away from the N-type semiconductor layer 301; the P-type electrode 304 located on a portion of the surface of the P-type semiconductor layer 303 away from the active layer 302; and the N-type electrode 305 located on a portion of the surface of one side of the N-type semiconductor layer 301 at the side of the active layer 302, the P-type semiconductor layer 303 and the P-type electrode 304. The P-type semiconductor layer 303 around the P-type electrode 304 contacts the top surface of the isolation layer 207 around the first opening.

[0121] In one embodiment, the width of the first opening is greater than or equal to the sum of the width of the P-type electrode 304 and 2 times the feature alignment accuracy, and the width of the second opening is greater than or equal to the sum of the N-type electrode 305 and 2 times the feature alignment accuracy, and the feature alignment accuracy is 0.5μm to 2μm.

[0122] In one embodiment, the thickness of the first bonding layer is greater than or equal to 80% and less than or equal to the depth of the first opening, and the thickness of the second bonding layer is greater than or equal to 80% and less than or equal to the depth of the second opening.

[0123] In one embodiment, the thickness of the isolation layer 207 is less than or equal to 50% of the difference between the thickness of the N-type electrode and the thickness of the P-type electrode.

[0124] In one embodiment, the isolation layer 207 has a thickness of 500 nm to 1000 nm.

[0125] The material of the first bonding layer and the second bonding layer is solder; the material of the first bonding layer and the second bonding layer is conductive glue.

[0126] Example 5

[0127] The difference between this embodiment and embodiment 4 is that: Fig.13 There is a first slope surface A1 (reference Fig.12 ); a second slope surface A2 is provided between the side wall of the second opening and the top surface of the isolation layer 207 around the second opening (reference Fig.12 ).

[0128] In one embodiment, a first angle is formed between the top surface of the isolation layer connected to the first slope surface and the first slope surface; tan(180°-θ1)>μ1, θ1 is the first angle, and μ1 is the friction coefficient of the first slope surface.

[0129] In one embodiment, a second angle is formed between the top surface of the isolation layer connected to the second slope surface and the second slope surface; tan(180°-θ2)>μ2; θ2 is the second angle, and μ2 is the friction coefficient of the second slope surface.

[0130] Example 6

[0131] The difference between this embodiment and embodiment 5 is that: Fig.16 The display panel further includes: a blocking layer 211, located on the isolation layer 207 around the opening group, and having a third opening in the blocking layer 211, and a width of the third opening is greater than a width of the Micro-LED chip.

[0132] In one embodiment, a width of the third opening is less than or equal to 1.5 times a width of the Micro-LED chip.

[0133] In one embodiment, the blocking layer 211 is a light-shielding blocking layer. The material of the light-shielding blocking layer is a light-shielding resin. In other embodiments, the material of the blocking layer 211 can also be a non-light-shielding material.

[0134] In one embodiment, the blocking layer 211 is a light shielding blocking layer, and the height of the top surface of the blocking layer facing away from the second substrate is greater than the height of the top surface of the Micro-LED chip facing away from the second substrate.

[0135] In another embodiment, a height of a top surface of the barrier layer facing away from the second substrate is less than or equal to a height of a top surface of the Micro-LED chip facing away from the second substrate.

[0136] The contents of this embodiment that are the same as those of Embodiment 5 will not be described in detail.

[0137] Example 7

[0138] The difference between this embodiment and embodiment 4 is that the display panel further comprises: a barrier layer located on the isolation layer around the opening group, the barrier layer having a third opening, the width of the third opening being greater than the width of the Micro-LED chip. In one embodiment, the width of the third opening is less than or equal to 1.5 times the width of the Micro-LED chip.

[0139] In one embodiment, the blocking layer 211 is a light-shielding blocking layer. The material of the light-shielding blocking layer is a light-shielding resin. In other embodiments, the material of the blocking layer 211 can also be a non-light-shielding material.

[0140] In one embodiment, the barrier layer 211 is a light shielding barrier layer, and the height of the top surface of the barrier layer facing away from the second substrate is greater than the height of the top surface of the Micro-LED chip facing away from the second substrate. In another embodiment, the height of the top surface of the barrier layer facing away from the second substrate is less than or equal to the height of the top surface of the Micro-LED chip facing away from the second substrate.

[0141] The same contents between this embodiment and embodiment 4 will not be described in detail.

[0142] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A method for preparing a display panel, characterized in that: include: A first substrate is provided, wherein one side of the first substrate has a plurality of spaced Micro-LED chips, wherein the Micro-LED chip comprises: a chip body; a P-type electrode and an N-type electrode, which are located on a portion of a surface of one side of the chip body; The chip body comprises: an N-type semiconductor layer; an active layer located on a portion of the surface of one side of the N-type semiconductor layer; a P-type semiconductor layer located on a side of the active layer away from the N-type semiconductor layer; the P-type electrode located on a portion of the surface of the P-type semiconductor layer away from the active layer; the N-type electrode located on a portion of the surface of one side of the N-type semiconductor layer at the side of the active layer, the P-type semiconductor layer and the P-type electrode; A portion of the surface of the P-type semiconductor layer is not covered by the P-type electrode; providing a second substrate, wherein a side surface of the second substrate has a plurality of conductive layers; An isolation layer is formed on the second substrate, wherein the thickness of the isolation layer is less than or equal to 50% of the difference between the thickness of the N-type electrode and the thickness of the P-type electrode, and the isolation layer has a plurality of opening groups, each of which includes a first opening and a second opening spaced apart from each other, the first opening and the second opening respectively expose the surface of the conductive layer, the width of the first opening is greater than the width of the P-type electrode, and the width of the second opening is greater than the width of the N-type electrode; A first slope surface is formed at the junction between the side wall of the first opening and the top surface of the isolation layer around the first opening; a second slope surface is formed at the junction between the side wall of the second opening and the top surface of the isolation layer around the second opening; a first angle is formed between the top surface of the isolation layer connected to the first slope surface and the first slope surface; tan(180°-θ1)>μ1, θ1 is the first angle, μ1 is the friction coefficient of the first slope surface, and a second angle is formed between the top surface of the isolation layer connected to the second slope surface and the second slope surface; tan(180°-θ2)>μ2; θ2 is the second angle, μ2 is the friction coefficient of the second slope surface; forming a first bonding layer in the first opening, and forming a second bonding layer in the second opening, wherein the material of the first bonding layer and the second bonding layer is conductive glue; The isolation layer supports the chip body, and the isolation layer supports the P-type semiconductor layer around the P-type electrode, the P-type electrode is bonded to the first bonding layer and the N-type electrode is bonded to the second bonding layer, the P-type electrode is embedded in the first bonding layer, and the N-type electrode is embedded in the second bonding layer; In the process of bonding the P-type electrode to the first bonding layer and the N-type electrode to the second bonding layer, the binding device used has a characteristic alignment accuracy; the width of the first opening is greater than or equal to the sum of the width of the P-type electrode and 2 times the characteristic alignment accuracy, and the width of the second opening is greater than or equal to the sum of the width of the N-type electrode and 2 times the characteristic alignment accuracy.

2. The method for preparing a display panel according to claim 1, characterized in that: Also includes: Before bonding the P-type electrode to the first bonding layer and the N-type electrode to the second bonding layer, a barrier layer is formed on the isolation layer around the opening group, wherein the barrier layer has a third opening, and the width of the third opening is greater than the width of the Micro-LED chip.

3. The method for preparing a display panel according to claim 2, characterized in that: The width of the third opening is less than or equal to 1.5 times the width of the Micro-LED chip.

4. The method for preparing a display panel according to claim 2, characterized in that: The barrier layer is a light-shielding barrier layer.

5. The method for preparing a display panel according to claim 4, characterized in that: The material of the light-shielding blocking layer is light-shielding resin.

6. The method for preparing a display panel according to claim 2, characterized in that: After the P-type electrode is bonded to the first bonding layer and the N-type electrode is bonded to the second bonding layer, the height of the top surface of the barrier layer facing away from the second substrate is greater than the height of the top surface of the Micro-LED chip facing away from the second substrate.

7. The method for preparing a display panel according to claim 1, characterized in that: A first bonding layer is formed in the first opening, and in the step of forming a second bonding layer in the second opening, the thickness of the first bonding layer is greater than or equal to 80% of the depth of the first opening and less than or equal to the depth of the first opening, and the thickness of the second bonding layer is greater than or equal to 80% of the depth of the second opening and less than or equal to the depth of the second opening.

8. The method for preparing a display panel according to claim 1, characterized in that: The thickness of the isolation layer is 500nm-1000nm.

9. A display panel, characterized in that: include: A first substrate, one side of which has a plurality of spaced Micro-LED chips, the Micro-LED chip comprising: a chip body; a P-type electrode and an N-type electrode, located on a portion of a surface of one side of the chip body; The chip body comprises: an N-type semiconductor layer; an active layer located on a portion of the surface of one side of the N-type semiconductor layer; a P-type semiconductor layer located on a side of the active layer away from the N-type semiconductor layer; the P-type electrode located on a portion of the surface of the P-type semiconductor layer away from the active layer; the N-type electrode located on a portion of the surface of one side of the N-type semiconductor layer at the side of the active layer, the P-type semiconductor layer and the P-type electrode; Part of the surface of the P-type semiconductor layer is not covered by the P-type electrode; A second substrate, wherein a surface of one side of the second substrate has a plurality of conductive layers; an isolation layer located on one side of the second substrate, wherein the thickness of the isolation layer is less than or equal to 50% of the difference between the thickness of the N-type electrode and the thickness of the P-type electrode, wherein the isolation layer has a plurality of opening groups, each of which includes a first opening and a second opening spaced apart, wherein the first opening and the second opening are respectively located on the conductive layer, wherein the width of the first opening is greater than the width of the P-type electrode, and the width of the second opening is greater than the width of the N-type electrode; A first slope surface is formed at the junction between the side wall of the first opening and the top surface of the isolation layer around the first opening; a second slope surface is formed at the junction between the side wall of the second opening and the top surface of the isolation layer around the second opening; a first angle is formed between the top surface of the isolation layer connected to the first slope surface and the first slope surface; tan(180°-θ1)>μ1, θ1 is the first angle, μ1 is the friction coefficient of the first slope surface, and a second angle is formed between the top surface of the isolation layer connected to the second slope surface and the second slope surface; tan(180°-θ2)>μ2; θ2 is the second angle, μ2 is the friction coefficient of the second slope surface; a first bonding layer located in the first opening; a second bonding layer located in the second opening; The material of the first bonding layer and the second bonding layer is conductive glue; The P-type electrode is embedded in the first bonding layer, and the N-type electrode is embedded in the second bonding layer; the isolation layer supports the P-type semiconductor layer around the P-type electrode, and the chip body contacts the top surface of a portion of the isolation layer; In the process of bonding the P-type electrode to the first bonding layer and the N-type electrode to the second bonding layer, the binding device used has a characteristic alignment accuracy; the width of the first opening is greater than or equal to the sum of the width of the P-type electrode and 2 times the characteristic alignment accuracy, and the width of the second opening is greater than or equal to the sum of the width of the N-type electrode and 2 times the characteristic alignment accuracy.

10. The display panel according to claim 9, characterized in that: Also includes: The barrier layer is located on the isolation layer around the opening group, and the barrier layer has a third opening, and the width of the third opening is greater than the width of the Micro-LED chip.

11. The display panel according to claim 10, characterized in that: The width of the third opening is less than or equal to 1.5 times the width of the Micro-LED chip.

12. The display panel according to claim 10, characterized in that: The barrier layer is a light-shielding barrier layer.

13. The display panel according to claim 12, characterized in that: The material of the light-shielding blocking layer is light-shielding resin.

14. The display panel according to claim 10, characterized in that: After the P-type electrode is bonded to the first bonding layer and the N-type electrode is bonded to the second bonding layer, the height of the top surface of the barrier layer facing away from the second substrate is greater than the height of the top surface of the Micro-LED chip facing away from the second substrate.

15. The display panel according to claim 9, characterized in that: The thickness of the first bonding layer is greater than or equal to 80% and less than or equal to the depth of the first opening, and the thickness of the second bonding layer is greater than or equal to 80% and less than or equal to the depth of the second opening.

16. The display panel according to claim 9, characterized in that: The thickness of the isolation layer is 500nm-1000nm.

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