Semiconductor structure and method of forming the same
By using a multi-step process to form tapered dielectric fins in a semiconductor structure, the problem that dielectric isolation structures cannot isolate adjacent source/drain structures has been solved, achieving effective isolation and performance improvement.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
- Filing Date
- 2022-05-31
- Publication Date
- 2026-07-03
Smart Images
Figure CN115249738B_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention generally relate to dielectric isolation structures, and more particularly to dielectric isolation structures between adjacent source / drain structures. Background Technology
[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advancements in integrated circuit materials and design have enabled each generation of integrated circuits to have smaller and more complex circuits than the previous generation. In the evolution of integrated circuits, functional density (such as the number of interconnects per unit chip area) typically increases as geometric dimensions (such as the smallest component (or line) that the manufacturing process can produce) shrink. Shrinking dimensions generally facilitates increased production capacity and reduced costs. However, shrinking dimensions also increases the complexity of handling and manufacturing integrated circuits.
[0003] For example, as integrated circuit technology advances to smaller technology nodes, multi-gate devices have been introduced to increase gate-channel coupling, reduce off-state current, and reduce short-channel effects to improve gate control. Multi-gate devices can generally be viewed as devices where the gate structure or a portion thereof is located on multiple sides of the channel region. Examples of multi-gate devices include fin field-effect transistors (FETs) and multi-bridge channel transistors (MCTs), which are becoming increasingly popular and are strong candidates for high-efficiency and low-leakage-current applications. The gate of a FET can cover multiple sides of a raised channel, such as the top and sidewalls of a fin covering a semiconductor material extending from the substrate. The gate structure of a MCT can extend to partially or completely surround the channel region to contact both sides or more of the channel region. Because the gate structure of a MCT surrounds the channel region, it can also be viewed as a gate-around transistor or a fully wound gate transistor. The channel region of a MCT can be a nanowire, nanosheet, or other nanostructure; therefore, a MCT can also be viewed as a nanowire transistor or a nanosheet transistor.
[0004] Dielectric isolation structures are used to isolate integrated circuit device structures that may come into contact with each other. For example, dielectric fins are used to isolate source / drain structures epitaxially grown from channel components of multi-gate devices (such as multi-bridge channel transistors). Without dielectric fins, adjacent source / drain structures may merge, creating unwanted electrical connections. While existing dielectric isolation structures are suitable for their intended purpose, they do not meet all requirements. Summary of the Invention
[0005] An exemplary embodiment of the present invention relates to a method for forming a semiconductor structure. The method includes forming a plurality of epitaxial layers stacked on a substrate; forming a first fin structure and a second fin structure from a portion of the stack and the substrate; forming an isolation structure between the first fin structure and the second fin structure; forming a cladding layer on the first fin structure and the second fin structure; conformally depositing a first dielectric layer on the cladding layer; depositing a second dielectric layer on the first dielectric layer; planarizing the first dielectric layer and the second dielectric layer until the cladding layer is exposed; performing an etching process to etch the second dielectric layer to form a cap recess; performing a trimming process to trim the first dielectric layer to widen the cap recess; and depositing a cap structure in the widened cap recess.
[0006] Another exemplary embodiment of the present invention relates to a method for forming a semiconductor structure. The method includes receiving a workpiece comprising a first fin structure and a second fin structure located on a substrate, an isolation structure located between the first fin structure and the second fin structure, a cladding layer located on the isolation structure and extending along the sidewalls of the first fin structure and the second fin structure, a compliant dielectric layer contacting the cladding layer and the isolation structure, and a filling dielectric layer located on the compliant dielectric layer and spaced from the first fin structure, the second fin structure, and the isolation structure by the compliant dielectric layer. The method further includes performing an etching process to etch the filling dielectric layer to form a cap recess; performing a trimming process to trim the compliant dielectric layer to widen the cap recess; and depositing a cap structure in the widened cap recess.
[0007] Another exemplary embodiment of the present invention relates to a semiconductor structure. The semiconductor structure includes a first dielectric fin and a second dielectric fin; a plurality of channel components located between the first dielectric fin and the second dielectric fin; and a gate structure located between the first dielectric fin and the second dielectric fin, and enclosing each channel component. Each of the first and second dielectric fins includes a substrate structure and a cap structure located on the substrate structure. The cap structure includes a bottom width and a top width, the top width being greater than the bottom width, such that the cap structure includes a tapered profile. Attached Figure Description
[0008] Figure 1 This is a flowchart of a method for forming a semiconductor structure in one or more embodiments of the present invention.
[0009] Figures 2 to 17 In one or more embodiments of the present invention, the workpiece is in Figure 1 Partial sectional views during various production stages of the method.
[0010] Figure 18 This is an enlarged cross-sectional view of the cover structure in one or more embodiments of the present invention.
[0011] The reference numerals in the attached figures are explained as follows:
[0012] H1: First Height
[0013] H2: Second Altitude
[0014] H3: Third Height
[0015] H4: Fourth Height
[0016] W: Final top width
[0017] WB: Bottom width
[0018] WT: Top width
[0019] 100: Method
[0020] 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130: Step 200: Workpiece
[0021] 202: Substrate
[0022] 204: Stacking
[0023] 206: Sacrificial Layer
[0024] 206T: Top Sacrificial Layer
[0025] 208: Channel Layer
[0026] 208T: Top Channel Layer
[0027] 211: Trench
[0028] 212: Fin-like structure
[0029] 212B: Base portion
[0030] 212T: Top
[0031] 214: Semiconductor Pad
[0032] 216: Isolation Structure
[0033] 218: Coating
[0034] 220: First dielectric layer
[0035] 221: The lid is concave.
[0036] 222: Second dielectric layer
[0037] 223: Widened lid with indentation
[0038] 224: Cover structure
[0039] 230: Dielectric fins
[0040] 232: Dummy Gate Stack
[0041] 234: Gate spacer
[0042] 240: Source / Drain Structure
[0043] 250: Gate structure
[0044] 260: Void
[0045] 2080: Channel Component Detailed Implementation
[0046] The following detailed description, accompanied by accompanying drawings, will aid in understanding various aspects of the invention. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of the various structures may be increased or decreased arbitrarily for clarity.
[0047] It is understood that the different embodiments or examples provided below may implement different structures of the embodiments of the present invention. The embodiments of specific components and arrangements are intended to simplify this disclosure and not to limit the invention. For example, a description of forming a first component on a second component includes direct contact between the two, or the two being spaced apart by other additional components rather than in direct contact. Furthermore, various embodiments of the invention may repeatedly use the same reference numerals for brevity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same correspondence.
[0048] Furthermore, spatial relative terms such as "below," "under," "lower," "above," "upper," or similar terms can be used to simplify the description of the relative relationship between one element and another in the illustration. Spatial relative terms can be extended to elements used in other directions, not just those shown in the illustration. For example, if the device in the illustration is flipped, the element below or beneath will become the element above or above. Elements can also be rotated 90° or other angles; therefore, directional terms are only used to describe the direction shown in the illustration.
[0049] Furthermore, when numerical values or ranges are described using terms such as "about," "approximately," or similar expressions, they are intended to cover values within a reasonable range, such as those inherent to the manufacturing process that are considered by those skilled in the art. For example, based on known manufacturing tolerances related to the numerical value, the numerical value or range covers a reasonable range including the number, for example, within + / - 10% of the number. For example, when the thickness of the material layer is about 5 nm and the manufacturing tolerance for deposited material layers is known to those skilled in the art to be 15%, the included size range is 4.25 nm to 5.75 nm. Moreover, the same reference numerals may be repeatedly used in various embodiments of the invention for brevity, but elements with the same reference numerals in various embodiments and / or settings do not necessarily have the same correspondence.
[0050] In fabricating multi-bridge channel transistors, dielectric fins or hybrid fins can be implemented to provide a variety of functions. During the formation of the source / drain structure, dielectric fins or hybrid fins can prevent the epitaxially grown material from merging and causing unwanted short circuits. After the gate is formed, the dielectric fins or hybrid fins can be used as part of a gate dicing structure to divide the gate structure into multiple components. In some examples, the dielectric fins include a substrate structure and a cap structure located on the substrate structure. Compared to the cap structure, the substrate structure has a lower dielectric constant to reduce parasitic capacitance between adjacent gate structures. The cap structure has greater etch resistance than the substrate structure and can serve as a capping layer for the substrate structure. Embodiments of the present invention provide dielectric fins with cap structures to facilitate the patterning of source / drain structures and the formation of gates. In some embodiments, the cap structure of the present invention includes a bottom width and a top width, with the top width being greater than the bottom width. The larger top width of this tapered profile facilitates the patterning of the source / drain structure, while the smaller bottom width allows for contact with more gate trenches. Furthermore, this invention provides a multi-step process to form the cap structure. The cap structure does not extend excessively downwards into the low-dielectric-constant substrate structure, thereby increasing parasitic capacitance.
[0051] Various embodiments of the present invention will be further described with reference to the drawings. Figure 1 A flowchart of a method 100 for forming a semiconductor device is shown. Method 100 is merely illustrative and is not intended to limit the scope of the embodiments of the present invention to the actual content described in Method 100. Additional steps may be provided before, during, and after Method 100, and additional embodiments of the method may substitute, omit, or rearrange some of the described steps. All steps are not detailed here for the sake of simplicity. Method 100 will be used in conjunction with... Figures 2 to 17 The explanation is as follows, and Figures 2 to 17Partial cross-sectional views of workpiece 200 at different manufacturing stages of an embodiment of method 100 are shown. Since a semiconductor device or semiconductor structure is subsequently formed from workpiece 200, workpiece 200 can also be regarded as a semiconductor device or semiconductor structure depending on the content requirements. Figures 2 to 17 The X, Y, and Z directions in the diagram are aligned and perpendicular to each other. For example, the X direction in one diagram may be parallel to the X direction in another diagram. Furthermore, similar structures are indicated using similar reference numerals in the embodiments of the present invention.
[0052] like Figure 1 and Figure 2 As shown, step 102 of method 100 involves receiving the workpiece 200. (As...) Figure 2 As shown, workpiece 200 includes a substrate 202 and a stack 204 located on the substrate 202. In one embodiment, the substrate 202 may be a silicon substrate. In some other embodiments, the substrate 202 may contain other semiconductor materials such as germanium, silicon germanium, or group III-V semiconductor materials. Examples of group III-V semiconductor materials may include gallium arsenide, indium phosphide, gallium phosphide, gallium nitride, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, or gallium indium arsenide. The substrate 202 may also contain an insulating layer such as a silicon oxide layer to have a silicon-on-insulator structure or a germanium-on-insulator structure. In some embodiments, the substrate 202 may contain one or more well regions (such as n-type well regions doped with n-type dopants such as phosphorus or arsenic, or p-type well regions doped with p-type dopants such as boron or indium) for forming different types of devices. The methods for doping n-type and p-type wells may employ ion implantation or thermal diffusion.
[0053] like Figure 2 As shown, the stack 204 includes multiple sacrificial layers 206 sandwiched between multiple channel layers 208. The channel layers 208 and the sacrificial layers 206 may have different semiconductor compositions. In some embodiments, the channel layers 208 are composed of silicon and the sacrificial layers 206 are composed of silicon-germanium. In these embodiments, the additional germanium content in the sacrificial layers 206 can be used to selectively remove the sacrificial layers 206 or to recess the sacrificial layers 206 without substantially damaging the channel layers 208. In some embodiments, the deposition method of the sacrificial layers 206 and the channel layers 208 may employ an epitaxial process. The epitaxial deposition method of the stack 204 may employ techniques primarily based on chemical vapor deposition, such as vapor phase epitaxy and / or ultra-high vacuum chemical vapor deposition, molecular beam epitaxy, and / or other suitable processes. The sacrificial layers 206 and channel layers 208 may be deposited one after another to form the stack 204. In the described embodiment, stack 204 may further include a top channel layer 208T and a top sacrificial layer 206T, which together act as a hard mask to protect the rest of stack 204 below, and subsequent processes can completely remove the top channel layer 208T and the top sacrificial layer 206T. (Disregarding the top channel layer 208T and the top sacrificial layer 206T...) Figure 2The stack 204 shown includes three sacrificial layers 206 and three channel layers 208, and is for illustrative purposes only and not for limiting the embodiments of the invention to the extent not actually described in the claims. The number of layers in the stack 204 depends on the number of channel components required by the semiconductor device, such as workpiece 200. In some embodiments, the number of channel layers 208 (excluding the top channel layer 208T) may be between 2 and 10.
[0054] like Figure 1 , Figure 3 ,and Figure 4 As shown, step 104 of method 100 forms a fin structure 212. In some embodiments, step 104 patternes a portion of the stack 204 and the substrate 202 to form the fin structure 212 defined by the trench 211. Figure 3 As shown, each fin structure 212 includes a base portion 212B formed from a portion of the substrate 202 and a top portion 212T formed from the stack 204. The top portion 212T is located on the base portion 212B. The fin structure 212 extends longitudinally along the Y direction and perpendicularly from the substrate 202 along the Z direction. The patterning method for the fin structure 212 can employ suitable processes, including dual patterning or multiple patterning processes. Generally, dual patterning or multiple patterning processes combine photolithography and self-alignment processes, which can produce a pattern pitch smaller than that obtained using a single direct photolithography process. For example, in one embodiment, a hard mask layer can be deposited on the stack 204 first, followed by the formation of a material layer on the hard mask layer. The material layer can be patterned using a photolithography process. Spacers can be formed along the sides of the patterned material layer using a self-alignment process. The material layer is then removed, and the remaining spacers or cores can then be used to pattern the hard mask layer. After the patterned hard mask layer is applied, it can be used to etch the stack 204 and the substrate 202 to pattern the fin structure 212. The etching process may include dry etching, wet etching, reactive ion etching, and / or other suitable processes. In some embodiments, a semiconductor pad 214 may be deposited on the fin structure 212, such as... Figure 4 As shown. The semiconductor pad 214 may comprise silicon or silicon-rich silicon-germanium. In some embodiments, the semiconductor pad 214 may be deposited using atomic layer deposition, plasma-assisted atomic layer deposition, vapor phase epitaxy, molecular beam epitaxy, or a suitable method.
[0055] like Figure 1 and Figure 5 As shown, step 106 of method 100 forms the isolation structure 216. After forming the fin structure 212, the following steps are taken: Figure 5The isolation structure 216 shown is located between adjacent fin structures 212. The isolation structure 216 can also be considered as a shallow trench isolation structure 216. In one example of the process, the dielectric material used for the isolation structure 216 is first deposited on the semiconductor pads 214 on the workpiece 200 to fill the trenches 211 between the fin structures 212. In some embodiments, the dielectric material may comprise silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass, a low dielectric constant dielectric layer, a combination of the above, and / or other suitable materials. In various examples, the dielectric material deposition method may be a chemical vapor deposition process, a flowable chemical vapor deposition process, spin coating, and / or other suitable processes. The deposited dielectric material can then be thinned and planarized by methods such as chemical mechanical polishing until at least a portion of the semiconductor pads 214 is exposed. The planarized dielectric material can be further recessed by dry etching, wet etching, and / or a combination of the above to form the isolation structure 216. Figure 5 As shown, the top 212T of the fin structure 212 protrudes above the isolation structure 216, while the isolation structure 216 may surround the base portion 212B of the fin structure 212.
[0056] like Figure 1 and Figure 6 As shown, step 108 of method 100 forms a cladding layer 218 on the fin structure 212. In some embodiments, the composition of the cladding layer 218 may be similar to that of the sacrificial layer 206. In one example, the composition of the cladding layer 218 may be silicon-germanium. The similarity in composition between the sacrificial layer 206 and the cladding layer 218 allows subsequent processes to selectively remove both the sacrificial layer 206 and the cladding layer 218 simultaneously. In some embodiments, the method for compliantly epitaxially growing the cladding layer 218 may employ vapor phase epitaxy or molecular beam epitaxy. Figure 6 As shown, the cladding layer 218 may be selectively located on the exposed surface of the semiconductor pad 214, rather than on the isolation structure 216 composed of dielectric material. In some examples, the thickness of the cladding layer 218 may be between about 5 nm and about 10 nm. After the cladding layer 218 is deposited, a portion of the isolation structure 216 exposed in the trench 211 is narrowed by the semiconductor pad 214 and the cladding layer 218.
[0057] like Figure 1 and Figure 7 As shown, step 110 of method 100 deposits a first dielectric layer 220 and a second dielectric layer 222 on the overlay (including deposition in the trench 211). In this example of the process, the first dielectric layer 220 may be conformally deposited on the workpiece 200 (including deposition in the trench 211), such as... Figure 7As shown. The deposition method of the first dielectric layer 220 may employ plasma-assisted chemical vapor deposition, atomic layer deposition, or a suitable method. The first dielectric layer 220 may line the sidewalls and lower surface of the trench 211, which may be defined by the overlay 218 prior to step 110. The first dielectric layer 220 may also be considered as a dielectric pad or outer layer. In some embodiments, the thickness of the first dielectric layer 220 is between about 3 nm and about 6 nm, for example, between about 4 nm and about 5 nm. A second dielectric layer 222 is then deposited on the first dielectric layer 220 on the workpiece 200, which may employ chemical vapor deposition, sub-pressure chemical vapor deposition, flowable chemical vapor deposition, atomic layer deposition, spin coating, and / or other suitable processes. The second dielectric layer 222 may also be considered as a dielectric filler layer or inner layer. The first dielectric layer 220 may comprise silicon, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, or a suitable oxidizable dielectric material. In some examples, the first dielectric layer 220 is oxygen-free. In other examples, the first dielectric layer 220 is at least not completely oxidized. In the embodiments described, the first dielectric layer 220 may comprise silicon carbonitride. The second dielectric layer 222 may comprise silicon oxide, or other dielectric layers that are completely oxidized or difficult to oxidize with an oxidizing agent. In the embodiments described, the second dielectric layer 222 is composed of silicon oxide.
[0058] like Figure 1 and Figure 8 As shown, step 112 of method 100 planarizes the workpiece 200 after depositing the first dielectric layer 220 and the second dielectric layer 222. The planarization process in step 112 can be performed using a chemical mechanical polishing process until the overlay 218 is exposed, as shown. Figure 8 As shown. Figure 8 As shown, the top channel layer 208T, semiconductor pad 214, first dielectric layer 220, and the upper surface of the second dielectric layer 222 are coplanar.
[0059] like Figure 1 and Figure 9As shown, step 114 of method 100 selectively etches the second dielectric layer 222 to form a cap recess 221. The etching process of step 114 is highly selective for the second dielectric layer 222 (which is composed of silicon oxide in the described embodiment). In some embodiments, the selective etching process of step 114 can be a chemical oxide removal process or atomic layer etching. For example, the workpiece 200 containing the second dielectric layer 222 can be treated with alternating ammonia and hydrofluoric acid. The chemical treatment can produce hexafluorosilicate ((NH4)2SiF6), which can be removed by an annealing process or a deionized water rinsing process. In one example of the process, the workpiece 200 is processed in cycles of multiple chemical treatments. Each cycle includes a first period of ammonia treatment and a second period of hydrofluoric acid treatment. The first period is shorter than the second period. In some examples, the first period is about half the length of the second period to ensure proper chemical treatment of the second dielectric layer 222. The processing cycles can be repeated 2 to 6 times. A selective etching process can be configured to selectively etch the second dielectric layer 222 while maintaining a substantially flat bottom profile. For example... Figure 9 As shown, because the etching process in step 114 has high selectivity for the second dielectric layer 222, the top channel layer 208T, the overlay layer 218, and the first dielectric layer 220 are not actually etched. Step 114 can form the cap recess 221.
[0060] like Figure 1 and Figure 10 As shown, step 116 of method 100 modifies the first dielectric layer 220 to widen the cap recess 221, thereby forming a widened cap recess 223. The modification process of step 116 is selective for the first dielectric layer 220, which is composed of an oxidizable dielectric material such as silicon carbonitride as described in the embodiments. In some embodiments, the selective modification process of step 116 can be divided into a chemical treatment step and a rinsing step. The chemical treatment step may use an oxidizing agent to oxidize the first dielectric layer 220, but not the second dielectric layer 222. The rinsing step may use an acid to remove the products of the chemical treatment step. For example, step 116 may involve treating the workpiece 200 containing the first dielectric layer 220 with a mixture of high-temperature sulfuric acid and hydrogen peroxide in the chemical treatment step, and then rinsing the workpiece 200 with dilute hydrofluoric acid. The mixture of high-temperature sulfuric acid and hydrogen peroxide oxidizes the first dielectric layer 220, while the dilute hydrofluoric acid removes the oxide. It is worth noting that the trimming process in step 116 can also etch the second dielectric layer 222, the overlay 218, and the top channel layer 208T, but at a lower etching rate. In some embodiments, a third-stage chemical treatment step and a fourth-stage rinsing step can be performed, with the fourth stage being shorter than the third stage. In some examples, the third stage is approximately 10 to 15 times longer than the fourth stage to ensure selective trimming of the first dielectric layer 220 and minimized etching of the second dielectric layer 222. Figure 10As shown, because the trimming process in step 116 is selective for the first dielectric layer 220, the cap recess 221 can be widened to form a widened cap recess 223. Figure 10 In some embodiments shown, each widened cap recess 223 includes a bottom width WB and a top width WT, with the top width WT being greater than the bottom width WB. Thus, each widened cap recess 223 includes a tapered profile that gradually narrows downwards along the Z-direction. In some examples, the bottom width WB is between about 10 nm and 15 nm, while the top width WT is between about 16 nm and about 20 nm. In other words, due to the trimming in step 116, the ratio of the top width WT to the bottom width WB can be between about 1.1 and 1.6. When this width ratio is less than 1.1, the cost of the additional trimming step may outweigh the benefits. When this width ratio is greater than 1.6, the cap structure filling the widened cap recess 223 may have too much unused portion, potentially hindering the channel release process or the gate formation process. In some embodiments, a cleaning process can be performed after the trimming process. The cleaning process may employ a mixture of high-temperature sulfuric acid and hydrogen peroxide.
[0061] like Figure 10 As shown, the widened cover recess 223 can extend partially downward into the first dielectric layer 220 and the second dielectric layer 222. Since the trimming process in step 116 is selective for the first dielectric layer 220, the extent to which the widened cover recess 223 extends into the first dielectric layer 220 is greater than the extent to which it extends into the second dielectric layer 222.
[0062] like Figure 1 and Figure 11 As shown, step 118 of method 100 forms a cap structure 224 in the widened cap recess 223. The cap structure 224 may comprise aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, aluminum zirconium oxide, hafnium oxide, or a suitable dielectric material. The material selection of the cap structure 224 makes it more resistant to anisotropic dry etching processes than other exposed structures and layers. Notably, the dielectric constant of the cap structure 224 is greater than that of the second dielectric layer 222. In one example of the process, the dielectric material used for the cap structure 224 can be deposited on the workpiece 200 using atomic layer deposition or chemical vapor deposition. The dielectric material used for the cap structure 224 can then be planarized using a chemical mechanical polishing process to remove excess dielectric material on the overlay 218 to form the cap structure 224. Figure 11The cap structure 224 is shown. The cap structure 224 may continue the shape of the widened cap recess 223. Step 118 may form dielectric fins 230. Each dielectric fin 230 includes a first dielectric layer 220, a second dielectric layer 222, and a cap structure 224. The first dielectric layer 220 and the second dielectric layer 222 may form the substrate structure of the dielectric fin 230, while the cap structure 224 covers the substrate structure from the top. Although the widened cap recess 223 facilitates the formation of the cap structure 224, small non-elongated voids 260 may still exist on the upper surface near the cap structure 224. As described below, subsequent etching or planarization processes can easily remove the voids 260, leaving a substantially void-free and seamless cap structure 224. Once the planarization process is completed, the first height H1 of the cap structure 224 may be between approximately 20 nm and approximately 40 nm.
[0063] like Figure 1 and Figure 12 As shown, step 120 of method 100 recesses the top channel layer 208T, the top sacrificial layer 206T, and the top of the cover layer 218. In one example of the process, anisotropic etching of the workpiece 200 can selectively remove the top of the cover layer 218, the top of the semiconductor pad 214, the top channel layer 208T, and the top sacrificial layer 206T to expose the channel layer 208. The anisotropic etching in step 120 can be a dry etching process, which includes hydrogen, fluorine-containing gases (such as carbon tetrafluoride, nitrogen trifluoride, sulfur hexafluoride, difluoromethane, fluoroform, and / or hexafluoroethane), chlorine-containing gases (such as chlorine, chloroform, carbon tetrachloride, and / or boron trichloride), bromine-containing gases (such as hydrogen bromide and / or bromoform), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. It is worth noting that the anisotropic etching in step 120 is a maskless and self-aligned process because the anisotropic etching step etches the cap structure 224 at a significantly slower rate. This means that anisotropic etching can substantially reduce the height of the cap structure 224 and round the upper surface of the cap structure 224, such as... Figure 12 As shown. During this stage, the void 260 (not shown) may be removed or partially exposed. It is noteworthy that the first dielectric layer 220 may cover the lower portion of the sidewall of the cap structure 224. The cap structure 224 has a large top width WT, which helps it resist etching in step 120. Due to its tapered profile, step 120 may consume excessive amounts of the cap structure 224, causing the source / drain structures 240 of step 124 to merge (as described below).
[0064] like Figure 1 , Figure 13 ,and Figure 14As shown, step 122 of method 100 forms a dummy gate stack 232 on the fin structure 212. In some embodiments, a gate replacement process (or post-gate process) may be used, wherein the dummy gate stack 232 may serve as a placeholder for the functional gate structure. Other processes and arrangements are also possible. Although Figure 13 Not shown, the dummy gate stack 232 includes a dummy dielectric layer, and dummy gates are located on the dummy dielectric layer. The region of the fin structure 212 beneath the dummy gate stack 232 can be considered a channel region. Each channel region in the fin structure 212 may be sandwiched between two source / drain regions used to form the source / drain along the Y direction. In one example of the process, the dummy dielectric layer may be blanket-deposited on the workpiece 200 by a process such as chemical vapor deposition. Then, a material layer for the dummy gates is blanket-deposited on the dummy dielectric layer. Next, a photolithography process is used to pattern the dummy dielectric layer and the material layer for the dummy gates to form the dummy gate stack 232. In some embodiments, the dummy dielectric layer may comprise silicon oxide, and the dummy gates may comprise polysilicon. Figure 13 As shown, the dummy gate stack 232 is located on the cover structure 224 and contacts the sidewall and upper surface of the cover structure 224.
[0065] like Figure 14 As shown, at least one gate spacer 234 is formed along the sidewall of the dummy gate stack 232. The at least one gate spacer 234 may include two or more gate spacer layers. The dielectric material used for the at least one gate spacer 234 may be selected to selectively remove the dummy gate stack 232. Suitable dielectric materials used for the at least one gate spacer 234 may include silicon nitride, silicon carbonitride, silicon carbonitride, silicon oxide, silicon carbonitride, silicon carbide, silicon oxynitride, and / or combinations thereof. In one example of the process, at least one gate spacer 234 may be compliantly deposited on the workpiece 200, and the deposition method may be chemical vapor deposition, sub-pressure chemical vapor deposition, or atomic layer deposition.
[0066] like Figure 1 and Figure 15 As shown, step 124 of method 100 forms the source / drain structure 240. Step 124 includes recessing the source / drain region of the fin structure 212 to form a source / drain recess, forming an inner spacer structure, and depositing the source / drain structure 240 in the source / drain recess. Using a dummy gate stack 232 and at least one gate spacer 234 as an etching mask, the workpiece 200 can be anisotropically etched to form the source / drain recess (not shown, which is located in...). Figure 15A source / drain structure 240 is filled in the source / drain region of the fin structure 212. The anisotropic etching in step 120 may include a dry etching process or a suitable etching process. For example, a dry etching process may be performed using oxygen-containing gas, hydrogen-containing gas, fluorine-containing gas (such as carbon tetrafluoride, sulfur hexafluoride, nitrogen trifluoride, difluoromethane, and / or hexafluoroethane), chlorine-containing gas (such as chlorine, chloroform, carbon tetrachloride, and / or boron trichloride), bromine-containing gas (such as hydrogen bromide and / or bromoform), iodine-containing gas, other suitable gases and / or plasma, and / or combinations thereof. The dry etching process in step 124 may etch at least one gate spacer 234, cap structure 224, and first dielectric layer 220 at a slower rate, and substantially without etching the dielectric fins. Multiple channel layers 208, multiple sacrificial layers 206, and sidewalls of capping layer 218 are exposed in the source / drain recess.
[0067] Although not illustrated, step 124 may also form an inner spacer structure to sandwich the channel layer 208. After forming the source / drain recess, the exposed sacrificial layer 206 in the source / drain region may be selectively partially recessed to form the inner spacer recess, without substantially etching the exposed channel layer 208. Since the cladding layer 218 has a similar composition to the sacrificial layer 206 (e.g., silicon-germanium), step 124 may also etch the cladding layer 218. In embodiments where the channel layer 208 is substantially composed of silicon, the sacrificial layer 206 is substantially composed of silicon-germanium, and the cladding layer 218 is substantially composed of silicon-germanium, the method of selectively partially recessing the sacrificial layer 206 and the cladding layer 218 may include etching with a mixture of ammonium hydroxide, hydrogen peroxide, and water. After forming the inner spacer recess, chemical vapor deposition or atomic layer deposition can be used to conformally deposit an inner spacer material layer on the workpiece 200, including deposition on and within the space left by the removal of the inner spacer recess and the overlay 218. The inner spacer material may comprise silicon nitride, silicon carbonitride, silicon carbonitride, silicon oxide, silicon carbonitride, silicon carbide, or silicon oxynitride. After depositing the inner spacer material layer, the inner spacer material layer can be etched back to form the inner spacer structure.
[0068] Step 124 may also include depositing a source / drain structure 240 in a source / drain recess. In some embodiments, the source / drain structure 240 may be selectively epitaxially deposited on the exposed semiconductor surfaces of the channel layer 208 and the substrate 202. The deposition method of the source / drain structure 240 may employ epitaxial processes, such as vapor phase epitaxy, ultra-high vacuum chemical vapor deposition, molecular beam epitaxy, and / or other suitable processes. The source / drain structure 240 may be n-type or p-type. When the source / drain structure 240 is n-type, it may contain silicon and be doped with an n-type dopant such as phosphorus or arsenic. When the source / drain structure 240 is p-type, it may contain silicon germanium or germanium and be doped with a p-type dopant such as boron or boron difluoride. In-situ doping may be performed during the deposition of the source / drain structure 240, or out-of-situ doping of the source / drain structure 240 may be performed using a planting process such as a junction planting process. Although not illustrated, the source / drain structure 240 may contain multiple epitaxial layers with different doping concentrations. For example... Figure 15 As shown, the dielectric fin 230 can serve as a separator for the source / drain structures in adjacent source / drain recesses. If the dielectric fin 230 is not formed or is not high or wide enough, adjacent source / drain structures 240 may merge, causing an unwanted short circuit.
[0069] like Figure 1 As shown, step 126 of method 100 removes the dummy gate stack 232. Step 126 includes depositing a contact etch stop layer and an interlayer dielectric layer, and removing the dummy gate stack 232. Although not illustrated, the contact etch stop layer and the interlayer dielectric layer may be deposited on the source / drain structure 240 to protect it from subsequent processes. The contact etch stop layer may comprise silicon nitride, which may be deposited on the source / drain structure 240, and the deposition method may be atomic layer deposition or chemical vapor deposition. The material of the interlayer dielectric layer may include an oxide of tetraethoxysilane, undoped silicate glass, doped silicon oxide (such as borosilicate glass, fluorosilicate glass, phosphosilicate glass, or borosilicate glass), and / or other suitable dielectric materials. The method of depositing the interlayer dielectric layer on the contact etch stop layer may be spin coating, a flowable chemical vapor deposition process, or other suitable deposition techniques. After the deposition of the contact etching stop layer and the interlayer dielectric layer, the workpiece 200 can be planarized using a process such as chemical mechanical polishing to provide a flat upper surface that exposes the dummy gate stack 232.
[0070] Next, the exposed dummy gate stack 232 is removed from the workpiece 200 using a selective etching process. The selective etching process can be a selective wet etching process, a selective dry etching process, or a combination thereof. In the embodiment described, the selective etching process can selectively remove the dummy dielectric layer and the dummy gate without substantially damaging the cap structure 224, at least one gate spacer 234, and the first dielectric layer 220. After removing the dummy gate stack 232, a gate trench is formed in the channel region. The at least one gate spacer 234 defines the gate trench.
[0071] like Figure 1 and Figure 16 As shown, step 128 of method 100 removes the sacrificial layer 206 in the channel region to release the channel assembly 2080. After removing the dummy gate stack 232, the channel layer 208, sacrificial layer 206, and capping layer 218 in the channel region are exposed in the gate trench. Since the sacrificial layer 206 and capping layer 218 are similar in composition and are exposed between the channel layers 208, both can be selectively removed to release the channel layer 208 and form the channel assembly 2080, as shown. Figure 16 As shown. The channel assembly 2080 can be stacked vertically along the Z direction. The method for selectively removing the sacrificial layer 206 and the capping layer 218 can be selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, selective wet etching includes etching with a mixture of ammonium hydroxide, hydrogen peroxide, and water. In some other embodiments, the selective removal step includes removing the silicon germanium oxide after oxidizing it. For example, oxidation can be provided by ozone cleaning, followed by removal of the silicon germanium oxide with an etchant such as ammonium hydroxide. After removing the sacrificial layer 206 and the capping layer 218 in the channel region, the first dielectric layer 220, the channel assembly 2080, the upper surface of the substrate portion 212B, and the isolation structure 216 can be exposed in the gate trench. The tapered profile of the capping structure 224 ensures that the capping structure 224 does not pinch against or restrict contact with the underlying sacrificial layer 206.
[0072] like Figure 1 , Figure 16 ,and Figure 17As shown, step 130 of method 100 forms a gate structure 250 to cover each channel component 2080. The layered structure 250 may include an interface layer on the channel component 2080 and the substrate 202, a gate dielectric layer on the interface layer, and a gate layer on the gate dielectric layer. In some embodiments, the interface layer comprises silicon oxide and may be formed by a pre-cleaning process. Examples of pre-cleaning processes may be RCE SC-1 (containing ammonia, hydrogen peroxide, and water) and / or RCA SC-2 (containing hydrogen chloride, hydrogen peroxide, and water). The pre-cleaning process may oxidize the exposed surfaces of the channel component 2080 and the substrate 202 to form the interface layer. A gate dielectric layer is then deposited on the interface layer, which may be performed using atomic layer deposition, chemical vapor deposition, and / or other suitable methods. The gate dielectric layer may comprise a high-dielectric-constant dielectric material. The high-dielectric-constant dielectric material described herein has a high dielectric constant, for example, greater than the dielectric constant of thermally oxidized silicon (approximately 3.9). In one embodiment, the gate dielectric layer may comprise hafnium oxide. In other embodiments, the gate dielectric layer may comprise other high dielectric constant dielectric layers, such as titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium dioxide, zirconium silicon oxide, lanthanum oxide, aluminum oxide, zirconium oxide, yttrium oxide, strontium titanate, barium titanate, barium zirconium oxide, hafnium lanthanum oxide, lanthanum silicon oxide, aluminum silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, barium strontium titanate, silicon nitride, silicon oxynitride, combinations thereof, or other suitable materials. After forming or depositing the interface layer and the gate dielectric layer, a gate layer may be deposited on the gate dielectric layer. The gate layer may be a multilayer structure, comprising at least one work function layer and a metal filling layer. For example, the at least one work function layer may comprise titanium nitride, titanium aluminum, titanium aluminum nitride, tantalum nitride, tantalum aluminum, tantalum aluminum nitride, tantalum aluminum carbide, tantalum carbonitride, or tantalum carbide. The metal filler layer may comprise aluminum, tungsten, nickel, titanium, ruthenium, cobalt, platinum, silicon tantalum nitride, copper, other refractory metals, other suitable metallic materials, or combinations thereof. In various embodiments, the gate layer may be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, electron beam evaporation, or other suitable processes. The tapered profile of the cap structure 224 ensures that the cap structure 224 does not pinch against or restrict contact with the adjacent channel layer 208, or the channel assembly 2080.
[0073] In various embodiments, planarization processes such as chemical mechanical polishing can be performed to remove excess material, providing a substantially flat surface for the gate structure. Figure 17 As shown, the deposited gate structure 250 can cover each channel assembly 2080 and contact the dielectric fin 230. More specifically, the gate structure 250 directly contacts the first dielectric layer 220 and the cap structure 224. The second dielectric layer 222 is separated from the gate structure 250 by the first dielectric layer 220. Figure 17As shown, after forming the gate structure 250, the workpiece 200 can be planarized until the dielectric fins divide the gate structure 250 into multiple components. Each dielectric fin 230 includes a first dielectric layer 220 and a second dielectric layer 222 as a bottom, and a cap structure 224 as a top. Figure 17 As shown, the cap structure 224 includes a second height H2, the bottom includes a third height H3, and the entire dielectric fin 230 includes a fourth height H4. In some examples, the second height H2 may be between about 10 nm and 30 nm, the third height H3 may be between about 30 nm and about 70 nm, and the fourth height H4 may be between about 40 nm and about 100 nm. The ratio of the second height H2 to the third height H3 may be between about 0.3 and about 1. This ratio is important because it ensures that the cap structure 224 has sufficient thickness to withstand the etching process but is not directly located between two adjacent source / drain structures 240.
[0074] Figure 18 yes Figure 17 A magnified cross-sectional view of the cover structure 224. Due to the etching process in step 120 and the planarization process in step 130, Figure 18 The cover structure 224 includes a bottom width WB and a final top width W, wherein the final top width W is greater than the bottom width WB and the final top width W is less than the top width WT. In this way, the cover structure 224 still has a tapered profile. The bottom width WB is between approximately 10 nm and approximately 15 nm, while the final top width W is between approximately 15.5 nm and approximately 18 nm. Figure 18 The cap structure 224 may also have a second height H2, which is smaller than the first height H1. As described above, the second height H2 may be between about 10 nm and about 30 nm. The cap structure 224 extends partially into the first dielectric layer 220 and the second dielectric layer 222 along the Z direction. Due to the trimming process in step 116, the cap structure 224 extends further into the first dielectric layer 220 than into the second dielectric layer 222. The dielectric constant of the second dielectric layer 222 is lower than that of the first dielectric layer 220 and can be used to reduce parasitic capacitance. The cap structure 224 is composed of a metal oxide, whose dielectric constant is even greater than that of the first dielectric layer 220. Due to the process of implementing the embodiments of the present invention, the cap structure 224 does not extend excessively into the second dielectric layer 222, thereby avoiding unwanted increases in parasitic capacitance. After the chemical mechanical polishing in step 130, the voids 260 can be removed. The tapered profile of the widened cap recess 223 prevents the formation of elongated slit-like voids. Elongated slit-like voids can degrade the integrity of the cap structure 224 during various etching or planarization processes.
[0075] Based on the foregoing, it is clear that the embodiments of the present invention offer numerous advantages compared to existing processes. However, it should be understood that other embodiments may offer additional advantages; not all advantages need to be described here, and not all embodiments need to possess specific advantages. For example, the process disclosed in the embodiments of the present invention can form a widened cap recess and a cap structure that gradually narrows downwards (tapered). The wider top width of the cap structure facilitates the patterning of the source / drain structure, while the narrower bottom width increases the process allowance for channel release and gate formation. Furthermore, the tapered profile avoids the formation of slit-like voids in the cap structure.
[0076] An exemplary embodiment of the present invention relates to a method for forming a semiconductor structure. The method includes forming a plurality of epitaxial layers stacked on a substrate; forming a first fin structure and a second fin structure from a portion of the stack and the substrate; forming an isolation structure between the first fin structure and the second fin structure; forming a cladding layer on the first fin structure and the second fin structure; conformally depositing a first dielectric layer on the cladding layer; depositing a second dielectric layer on the first dielectric layer; planarizing the first dielectric layer and the second dielectric layer until the cladding layer is exposed; performing an etching process to etch the second dielectric layer to form a cap recess; performing a trimming process to trim the first dielectric layer to widen the cap recess; and depositing a cap structure in the widened cap recess.
[0077] In some embodiments, the overlay comprises silicon germanium, the first dielectric layer comprises silicon carbonitride, silicon carbide, or silicon nitride, and the second dielectric layer comprises silicon oxide. In some examples, the etching process includes multiple cycles of chemical oxide removal. In some embodiments, the etching process includes the use of ammonia and hydrofluoric acid. In some embodiments, the trimming process includes a chemical treatment step, which includes the use of an oxidizing agent; and a rinsing step, which includes the use of an acid. In some embodiments, the oxidizing agent includes a mixture of high-temperature sulfuric acid and hydrogen peroxide, and the acid includes dilute hydrofluoric acid. In some examples, the chemical treatment step lasts for a first time period, and the rinsing step lasts for a second time period, the second time period being shorter than the first time period, and the ratio of the first time period to the second time period being between about 10 and 15. In some embodiments, the method further includes performing a cleaning process after the trimming process. The cleaning process includes the use of a mixture of high-temperature sulfuric acid and hydrogen peroxide.
[0078] Another exemplary embodiment of the present invention relates to a method for forming a semiconductor structure. The method includes receiving a workpiece comprising a first fin structure and a second fin structure located on a substrate, an isolation structure located between the first fin structure and the second fin structure, a cladding layer located on the isolation structure and extending along the sidewalls of the first fin structure and the second fin structure, a compliant dielectric layer contacting the cladding layer and the isolation structure, and a filling dielectric layer located on the compliant dielectric layer and spaced from the first fin structure, the second fin structure, and the isolation structure by the compliant dielectric layer. The method further includes performing an etching process to etch the filling dielectric layer to form a cap recess; performing a trimming process to trim the compliant dielectric layer to widen the cap recess; and depositing a cap structure in the widened cap recess.
[0079] In some embodiments, prior to the etching process, the first fin structure, the second fin structure, the overlay, the compliant dielectric layer, and the upper surface of the fill dielectric layer are coplanar. In some embodiments, the fill dielectric layer comprises silicon oxide, while the compliant dielectric layer is substantially oxygen-free. In some embodiments, the compliant dielectric layer comprises silicon carbonitride. In some embodiments, the cap structure comprises aluminum oxide, hafnium oxide, zirconium oxide, or zinc oxide. In some embodiments, the top width of the widened cap recess is greater than the bottom width, such that the widened cap recess comprises a tapered profile.
[0080] Another exemplary embodiment of the present invention relates to a semiconductor structure. The semiconductor structure includes a first dielectric fin and a second dielectric fin; a plurality of channel components located between the first dielectric fin and the second dielectric fin; and a gate structure located between the first dielectric fin and the second dielectric fin, and enclosing each channel component. Each of the first and second dielectric fins includes a substrate structure and a cap structure located on the substrate structure. The cap structure includes a bottom width and a top width, the top width being greater than the bottom width, such that the cap structure includes a tapered profile.
[0081] In some embodiments, the bottom width is between about 10 nm and about 15 nm, and the top width is between about 15.5 nm and about 18 nm. In some embodiments, the substrate structure includes an outer layer to contact the gate structure, an inner layer spaced from the gate structure by the outer layer, and a cap structure having a first depth extending partially into the outer layer and a second depth extending partially into the inner layer, the second depth being less than the first depth. In some embodiments, the inner layer comprises silicon oxide, and the outer layer is substantially oxygen-free. In some examples, the outer layer comprises silicon carbonitride.
[0082] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and modify other processes and structures to achieve the same objectives and / or advantages as the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention.
Claims
1. A method for forming a semiconductor structure, comprising: Multiple epitaxial layers are stacked on a substrate; A first fin structure and a second fin structure are formed from the stack and a portion of the substrate; An isolation structure is formed between the first fin structure and the second fin structure; A coating is formed on the first fin structure and the second fin structure; A first dielectric layer is compliantly deposited on the coating; A second dielectric layer is deposited on the first dielectric layer; Planarize the first dielectric layer and the second dielectric layer until the cladding layer is exposed; An etching process is performed to etch the second dielectric layer to form a cap recess; A trimming process is performed to widen the cover recess by trimming the first dielectric layer, wherein the cover recess includes a bottom width and a top width, the top width being greater than the bottom width; and A cap structure is deposited in the widened cap depression.
2. The method for forming a semiconductor structure as described in claim 1, The coating includes silicon and germanium. The first dielectric layer includes silicon carbonitride, silicon carbide, or silicon nitride, and The second dielectric layer includes silicon oxide.
3. The method for forming a semiconductor structure as claimed in claim 1, wherein the etching process includes multiple cycles of chemical oxide removal.
4. The method for forming a semiconductor structure as described in claim 3, wherein the etching process includes using ammonia and hydrofluoric acid.
5. The method for forming a semiconductor structure as claimed in claim 1, wherein the trimming process includes: A chemical treatment step, including the use of an oxidizing agent; as well as One rinsing step includes the use of an acid.
6. The method for forming a semiconductor structure as claimed in claim 5, wherein the oxidant comprises a mixture of high-temperature sulfuric acid and hydrogen peroxide, and the acid comprises dilute hydrofluoric acid.
7. The method for forming a semiconductor structure as described in claim 5, The chemical treatment step lasts for a first time period, and The rinsing step lasts for a second period, which is shorter than the first period.
8. The method for forming a semiconductor structure as claimed in claim 7, wherein the ratio of the first time period to the second time period is between 10 and 15.
9. The method for forming a semiconductor structure as described in claim 1, further comprising: Following this finishing process, a cleaning process is performed, which includes using a mixture of high-temperature sulfuric acid and hydrogen peroxide.
10. A method for forming a semiconductor structure, comprising: Receive a workpiece, which includes: A first fin-like structure and a second fin-like structure are located on a substrate. An isolation structure is located between the first fin-like structure and the second fin-like structure. A cladding layer is located on the isolation structure and extends along the sidewalls of the first fin structure and the second fin structure. A compliant dielectric layer, contacting the cladding and the isolation structure, and A filling dielectric layer is located on the compliant dielectric layer and is separated from the first fin structure, the second fin structure, and the isolation structure by the compliant dielectric layer; An etching process is performed to etch the fill dielectric layer to form a capping recess; A trimming process is performed to adjust the widened cover recess to conform to the dielectric layer, wherein the cover recess includes a bottom width and a top width, the top width being greater than the bottom width; and A cap structure is deposited in the widened cap depression.
11. The method of forming a semiconductor structure as claimed in claim 10, wherein prior to the etching process, the first fin structure, the second fin structure, the cladding layer, the compliant dielectric layer, and the upper surface of the filling dielectric layer are coplanar.
12. The method of forming a semiconductor structure as claimed in claim 10, wherein the filling dielectric layer comprises silicon oxide, and the compliant dielectric layer is substantially oxygen-free.
13. The method of forming a semiconductor structure as claimed in claim 12, wherein the compliant dielectric layer comprises silicon carbonitride.
14. The method of forming a semiconductor structure as claimed in claim 10, wherein the cap structure comprises aluminum oxide, hafnium oxide, zirconium oxide, or zinc oxide.
15. The method of forming a semiconductor structure as claimed in claim 10, wherein the top width of the widened cover recess is greater than the bottom width, such that the widened cover recess includes a tapered profile.
16. A semiconductor structure comprising: A first dielectric fin and a second dielectric fin; Multiple channel components are located between the first dielectric fin and the second dielectric fin; and A gate structure is located between the first dielectric fin and the second dielectric fin, and covers each of the channel components; The first dielectric fin and the second dielectric fin each include a substrate structure and a cap structure located on the substrate structure, and the top surface of the first dielectric fin is higher than one of the channel components; and The cover structure includes a bottom width and a top width, the top width being greater than the bottom width, such that the cover structure includes a tapered profile.
17. The semiconductor structure as described in claim 16, The bottom width is between 10 nm and 15 nm, and The width of the top is between 15.5 nm and 18 nm.
18. The semiconductor structure as described in claim 16, The substrate structure includes an outer layer for contacting the gate structure, and an inner layer, wherein the inner layer is separated from the gate structure by the outer layer. The cover structure has a first depth extending partially into the outer layer and a second depth extending partially into the inner layer, wherein the second depth is less than the first depth.
19. The semiconductor structure of claim 18, wherein the inner layer comprises silicon oxide and the outer layer is substantially oxygen-free.
20. The semiconductor structure of claim 18, wherein the outer layer comprises silicon carbonitride.