High voltage device and method of controlling the same

Abstract

A high voltage device formed by a plurality of modular low voltage cells and a control method thereof are provided. Each low voltage cell is composed of a low voltage semiconductor device and a low voltage passive element, and each low voltage cell is a two-quadrant or four-quadrant switch with bi-directional current flow. All low voltage cells can be identical and have a delay time between their control timing. By this, the total on and off time of the high voltage device can be controlled to reduce the output equivalent dv / dt. Voltage balancing among the low voltage cells can be achieved by the disclosed control algorithm.

Description

Technical Field

[0001] This case relates to a high-voltage device and its control method, particularly a high-voltage device and its control method formed by multiple modular low-voltage devices and suitable for medium-voltage applications. Background Technology

[0002] Semiconductor devices are a key component of power conversion systems. In medium-voltage (e.g., 1kV to 100kV) applications, high-voltage devices can be used to simplify the conversion system architecture. For example, when using a 10kV SiC device, two-level phase bridge arms can operate even when the bus voltage is about 6 to 8kV. Many documents on high-voltage wide-bandgap devices have been published in industry and academia, as shown in references [1]-[5]. However, existing high-voltage planar wide-bandgap devices still have many drawbacks, which are summarized below.

[0003] First, high-voltage devices (e.g., above 3.3kV) are still immature, with extremely low device yield ratios, resulting in very high costs. Second, single high-voltage devices, due to structural limitations, exhibit higher conduction losses compared to multiple low-voltage devices connected in a cascaded configuration. Furthermore, single high-voltage devices also face the challenge of heat dissipation. Finally, the high dv / dt in high-voltage applications generates significant harmonics, making system integration or improving output filtering and insulation requirements more challenging. It should be noted that the disadvantages of high-voltage wide-bandgap devices are not limited to the above points. Some published literature focuses on using cascaded configurations of multiple low-voltage devices to overcome the aforementioned and other shortcomings of high-voltage wide-bandgap devices.

[0004] Figure 1 A conventional cascaded high-voltage device structure is shown, employing MOSFETs (metal-oxide-semiconductor field-effect transistors) and JFETs (junction gate field-effect transistors) connected in a cascaded configuration, as illustrated in references [6]-[8]. To balance voltage distribution (especially during fast transients), passive RC circuits are connected in parallel to mitigate the formation of a uniform dynamic voltage (dv / dt) across devices at different locations, thereby distributing the dynamic voltage evenly. However, the parallel capacitors will store more energy, and the energy stored in the circuit paths between devices will lead to higher switching losses. Furthermore, voltage distribution is extremely sensitive to the values ​​of passive components, making it difficult to scale up in a modular manner.

[0005] Figure 2 Showing something similar to Figure 1Another traditional cascaded high-voltage device structure uses capacitors and Zener diodes for clamping to balance dynamic voltage distribution, as shown in reference [9]. However, this scheme is still limited by high switching losses and the high sensitivity of Zener diode characteristics. Figure 1 and Figure 2 Both schemes shown employ passive circuitry for voltage balancing, and these designs will be difficult to scale up in a modular fashion while maintaining good voltage distribution.

[0006] Figure 3 This paper presents a conventional dynamic voltage (dv / dt) control method applicable to multiple semiconductor devices connected in a cascaded configuration, as shown in reference

[10] . Figure 3 As shown, voltage distribution is achieved through active dv / dt control embedded in the gate driver. In this scheme, since there is no external snubber or balancing circuit, lower switching losses can be achieved technically. The gate driver implements dv / dt control. The device's dynamic voltage is distributed and can be used to control the current injection circuit, which is connected to the device's gate pin to decrease or increase dv / dt by injecting or absorbing gate current.

[0007] Figure 4 Another conventional dynamic voltage (dv / dt) control method is shown, applicable to multiple semiconductor devices connected in a cascaded configuration. See references

[11] -

[12] . Figure 4 As shown, it achieves voltage distribution through an active delay time control function embedded in the gate driver, by sensing the drain-source voltage of the sensor and comparing it with a reference value to generate negative feedback and provide a controllable delay time in the gate channel. Figure 3 and Figure 4 The proposed solution is quite complex and requires a high-precision controller in the gate driver, making it difficult to expand its application to more devices in cascaded architectures.

[0008] Figure 5 A conventional high-voltage phase bridge arm architecture based on a flying capacitor converter is shown, as illustrated in reference

[13] . Figure 5As shown, in the architecture based on flying capacitors, the semiconductor devices in the phase bridge arms are controlled at quasi-two-level, resulting in a smaller capacitor size. To achieve higher power density and reduce the number of passive components, the switching devices on the positive or negative terminals can be controlled to operate at quasi-two-level, while also achieving a smaller equivalent dv / dt at the switching node. However, since C1 is a low-voltage capacitor while C2 and C3 are higher-voltage capacitors (in medium-voltage applications, more low-voltage capacitors need to be connected in series), this scheme is not a modular solution and it is difficult to minimize the parasitic effects of the switching loop. Therefore, its switching losses are high, and it is difficult to expand its application to cascaded architectures with more units.

[0009] Figure 6 A conventional circuit comprising two integrated capacitor blocked transistor (ICBT) units is shown, each ICBT unit having two active semiconductor devices (e.g., MOSFETs) and a capacitor, as shown in reference

[14] . ICBT units can be connected in series or in parallel for applications requiring higher voltage or higher power. This approach is modular and can therefore be scaled up. However, in this approach, when ICBT units are connected in series, all connected ICBT units switch synchronously and their output dv / dt cannot be controlled.

[0010] Figure 7 A typical modular multi-level converter (MMC) structure suitable for high voltage DC (HVDC) applications is shown. As shown in reference

[15] . In order to reduce the space occupied and the size of the energy storage element, the MMC bridge arm is controlled in quasi-two-level (Q2L) mode, but its switching frequency is still in the range of 100 to 1000 Hz, and the corresponding control and balancing methods are still similar to those of traditional MMC.

[0011] References:

[0012] [1] S.Sabri et al., "New generation 6.5kV SiC power MOSFET," 2017IEEE5th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Albuquerque, NM, 2017, pp.246-250.

[0013] [2]V.Pala et al.,“10kV and 15kV silicon carbide power MOSFETs fornext-generation energy conversion and transmission systems,”2014IEEE EnergyConversion Congress and Exposition(ECCE),Pittsburgh,PA,2014,pp.449-454.

[0014] [3]A.Bolotnikov et al.,“Overview of 1.2kV–2.2kV SiC MOSFETs targetedfor industrial power conversion applications,”2015IEEE Applied PowerElectronics Conference and Exposition(APEC),Charlotte,NC,2015,pp.2445-2452,doi:10.1109 / APEC.2015.7104691.

[0015] [4]J.L.Hostetler,P.Alexandrov,X.Li,L.Fursin and A.Bhalla,“6.5kV SiCnormally-off JFETs—Technology status,”2014IEEE Workshop on Wide BandgapPower Devices and Applications,Knoxville,TN,2014,pp.143-146.

[0016] [5]A.Bolotnikov,et al.“SiC Charge-Balanced Devices OfferingBreakthrough Performance Surpassing the 1-D Ron Versus BV Limit”,ECSCRM 2018.

[0017] [6]K.Vechalapu,S.Bhattacharya and E.Aleoiza,“Performance evaluationof series connected 1700V SiC MOSFET devices,”2015IEEE 3rd Workshop on WideBandgap Power Devices and Applications(WiPDA),Blacksburg,VA,2015,pp.184-191.

[0018] [7]L.Zhang,S.Sen,Z.Guo,X.Zhao,A.Q.Huang and X.Song,“7.2-kV / 60-AAustin SuperMOS:An Enabling SiC Switch Technology for Medium VoltageApplications,”2019IEEE Electric Ship Technologies Symposium(ESTS),Washington,DC,USA,2019,pp.523-529,doi:10.1109 / ESTS.2019.8847863.

[0019] [8]X.Song,A.Q.Huang,S.Sen,L.Zhang,P.Liu and X.Ni,“15-kV / 40-A FREEDMSuper-cascode:A Cost-Effective SiC High-Voltage and High-Frequency PowerSwitch,”in IEEE Transactions on Industry Applications,vol.53,no.6,pp.5715-5727,Nov.-Dec.2017.

[0020] [9]B.Gao,A.J.Morgan,Y.Xu,X.Zhao and D.C.Hopkins,“6.0kV,100A,175kHzsuper cascode power module for medium voltage,high power applications,”2018IEEE Applied Power Electronics Conference and Exposition (APEC),San Antonio,TX,2018,pp.1288-1293.

[0021]

[10] Raszmann,Emma Barbara,“Series-Connection of Silicon CarbideMOSFET Modules using Active Gate-Drivers with dv / dt Control,”2019 MasterThesis.

[0022]

[11] Xiang Lin,“Active Voltage Balancing for Series-Connected 10kV SiCMOSFETs,”WBG-HPCS Review Q3-2019.

[0023] 12.P.Wang,F.Gao,Y.Jing,Q.Hao,K.Li and H.Zhao,“An Integrated GateDriver with Active Delay Control Method for Series Connected SiC MOSFETs,”2018 IEEE 19th Workshop on Control and Modeling for Power Electronics(COMPEL),Padua,2018,pp.1-6.

[0024]

[13] P. Czyz, P. Papamanolis, T. Guillod, F. Krismer and J. W. Kolar, "New 40kV / 300kVA Quasi-2-Level Operated 5-Level Flying Capacitor SiC 'Super-Switch' IPM," 2019 10th International Conference on Power Electronics and ECCE Asia (ICPE 2019-ECCE Asia), Busan, Korea (South), 2019, pp. 813-820.

[0025]

[14] "Power Converter Having Integrated Capacitor-Blocked Transistor Cells" US Patent, US 9,525,348 B1, 2016.

[0026]

[15] I. A. Gowaid, G. P. Adam, A. M. Massoud, S. Ahmed, D. Holliday and B. W. Williams, "Quasi Two-Level Operation of Modular Multilevel Converter for Use in a High-Power DC Transformer With DC Fault Isolation Capability," in IEEE Transactions on Power Electronics, vol. 30, no. 1, pp. 108-123, Jan. 2015, doi: 10.1109 / TPEL.2014.2306453. Summary of the Invention

[0027] This invention provides a high-voltage device formed by multiple modular low-voltage units. Each low-voltage unit consists of low-voltage semiconductor devices and low-voltage passive components, and each low-voltage unit is a two-quadrant or four-quadrant switch that allows bidirectional current flow. In some embodiments, all low-voltage units may be identical and have a delay time between their control sequences. This allows control of the total on and off times of the high-voltage device to reduce the output equivalent dv / dt. Voltage balance among the low-voltage units can be achieved through the disclosed control algorithm. Due to the modular technology, the switching loop impedance of each low-voltage unit can be maintained excellently, resulting in extremely low switching losses even in hard-switching applications. This invention provides a modular construction scheme that can be extended to other applications, such as two-level hard-switching converters, two-level soft-switching converters, and multi-level converters.

[0028] According to one aspect of the concept, this invention provides a high-voltage device comprising multiple modular units, each modular unit including a first terminal, a second terminal, and a control terminal. The multiple modular units are connected in series, with the first terminal of any modular unit connected to the second terminal of an adjacent modular unit. Each modular unit includes multiple low-voltage semiconductor devices and one or more low-voltage passive components.

[0029] In one embodiment, the one or more low-voltage passive components include a capacitor.

[0030] In one embodiment, the plurality of low-voltage semiconductor devices includes at least two power MOSFETs.

[0031] In one embodiment, each modular unit is a two-quadrant switch that allows bidirectional current flow.

[0032] In one embodiment, the two-quadrant switch includes an active main switch, an active auxiliary switch, and a capacitor. The active main switch, the active auxiliary switch, and the capacitor are connected to form a circuit loop. A first node between the active main switch and the active auxiliary switch is connected to a first end, and a second node between the active main switch and the capacitor is connected to a second end.

[0033] In one embodiment, the two-quadrant switch includes a first circuit loop connected to a first end and a second circuit loop connected to a second end. The first circuit loop includes a first active main switch, a first auxiliary switch, and a first capacitor connected in series, and the second circuit loop includes a second active main switch, a second auxiliary switch, and a second capacitor connected in series. A first node in the first circuit loop located between the first active main switch and the first capacitor is connected to a second node in the second circuit loop located between the second active main switch and the second capacitor.

[0034] In one embodiment, each modular unit is a four-quadrant switch.

[0035] In one embodiment, the four-quadrant switch includes first, second, and third circuit arms connected in parallel between the first terminal and the second terminal. The first circuit arm includes a first auxiliary switch and a first capacitor connected in series, the second circuit arm includes a first main switch and a second main switch connected in series, and the third circuit arm includes a second auxiliary switch and a second capacitor connected in series.

[0036] In one embodiment, the sources of the first and second main switches are interconnected.

[0037] In one embodiment, the four-quadrant switch includes a first circuit loop connected to a first end and a second circuit loop connected to a second end. The first circuit loop includes a first active main switch, a first auxiliary switch, and a first capacitor connected in series. The second circuit loop includes a second active main switch, a second auxiliary switch, and a second capacitor connected in series. A first node in the first circuit loop located between the first active main switch and the first capacitor is connected to a second node in the second circuit loop located between the second active main switch and the second capacitor.

[0038] In one embodiment, the control terminal receives control signals from corresponding modular units, wherein the control signals of each modular unit are offset by a delay time.

[0039] According to another aspect of this invention, a high-voltage half-bridge device is provided, comprising: a first end, a second end, a third end, an upper bridge arm, and a lower bridge arm. The upper bridge arm is connected between the first end and the second end and includes a plurality of first low-voltage modular units connected in a cascaded configuration. The lower bridge arm is connected between the first end and the third end and includes a plurality of second low-voltage modular units connected in a cascaded configuration. The number of first low-voltage modular units and second low-voltage modular units is equal.

[0040] In one embodiment, both the first low-voltage modular unit and the second low-voltage modular unit are two-quadrant switches that allow bidirectional current flow.

[0041] In one embodiment, the high-voltage half-bridge device further includes a control terminal, wherein the control terminal receives a control signal from each low-voltage modular unit, and each control signal is offset by a corresponding delay time.

[0042] According to another aspect of the concept, this invention provides a control method based on controlling the aforementioned high-voltage device. The control method includes: transmitting control signals to the control terminal of each modular unit, wherein each control signal is offset by a corresponding delay time; sensing the unit voltage of each modular unit; and balancing the voltages of multiple units.

[0043] In one embodiment, for any modular unit, the step of balancing the voltages of multiple units includes: determining a voltage difference by comparing the corresponding unit voltage with a reference voltage; determining a duty cycle difference based on the voltage difference; and adjusting the duty cycle of the control signal of the corresponding modular unit using the duty cycle difference.

[0044] In one embodiment, the control method further includes sensing the polarity of the output current of the high-voltage device, wherein the step of adjusting the duty cycle includes: subtracting the duty cycle difference when the corresponding unit voltage is greater than the reference voltage and the output current polarity is greater than zero, or when the corresponding unit voltage is not greater than the reference voltage and the output current polarity is not greater than zero; and adding the duty cycle difference to the duty cycle when the corresponding unit voltage is greater than the reference voltage and the output current polarity is not greater than zero, or when the corresponding unit voltage is not greater than the reference voltage and the output current polarity is greater than zero.

[0045] In one embodiment, the step of balancing multiple unit voltages includes: sensing the polarity of the output current of the high-voltage device; sorting the multiple unit voltages of the multiple modular units; when the output current polarity is greater than zero, sorting the modular unit with the larger unit voltage in a leading position among any two modular units; and when the output current polarity is not greater than zero, sorting the modular unit with the larger unit voltage in a lagging position among any two modular units. Attached Figure Description

[0046] Figure 1 This illustrates a traditional cascaded high-voltage device structure.

[0047] Figure 2 This illustrates another traditional cascaded high-voltage device structure.

[0048] Figure 3 This paper presents a conventional dynamic voltage (dv / dt) control method applicable to multiple semiconductor devices connected in a cascaded configuration.

[0049] Figure 4 This demonstrates another conventional dynamic voltage (dv / dt) control method applicable to multiple semiconductor devices connected in a cascaded configuration.

[0050] Figure 5 This paper illustrates a conventional high-voltage phase bridge arm architecture based on a flying capacitor converter.

[0051] Figure 6 A conventional circuit comprising two ICBT units is shown, wherein each ICBT unit has two active semiconductor devices (e.g., MOSFETs) and a capacitor.

[0052] Figure 7This paper illustrates a typical modular multilevel converter (MMC) structure suitable for high-voltage direct current (HVDC) applications.

[0053] Figure 8 This invention illustrates a high-voltage device having a super-switching architecture formed by multiple modular units connected in series, as shown in one embodiment of the present invention.

[0054] Figure 9 Show Figure 8 An example of a modular unit in the design, which has a half-bridge two-level two-quadrant unit structure.

[0055] Figure 10 Show Figure 8 Another example of a modular unit in the design is a cascaded half-bridge three-level two-quadrant unit structure.

[0056] Figure 11 Show Figure 8 Another example of modular units in this paper, which has a T-shaped four-quadrant unit structure.

[0057] Figure 12 Show Figure 8 Another example of modular units in this example is a four-quadrant unit structure.

[0058] Figure 13 Showing will Figure 11 The T-shaped four-quadrant unit structure is used in one application of the Vienna rectifier.

[0059] Figure 14 Showing will Figure 9 The unit with a half-bridge two-quadrant unit structure is used in one application of a typical phase bridge arm architecture.

[0060] Figure 15A and Figure 15B exemplify Figure 14 The modulation strategy of the phase bridge arm architecture in the middle.

[0061] Figure 16 exemplify Figure 14 The waveforms of voltage, current, and gate signal in the phase bridge arm architecture.

[0062] Figure 17 The control algorithm of one embodiment of this case is shown.

[0063] Figure 18 Showing the use of Figure 17 The balancing method of the control algorithm in the text.

[0064] Figure 19 The control algorithm of another embodiment of this case is shown.

[0065] Figure 20 Showing the use of Figure 19 The balancing method of the control algorithm in the text.

[0066] Figure 21 This invention illustrates a three-level flying capacitor converter employing a two-quadrant superswitcher in one embodiment.

[0067] Figure 22 This invention illustrates a three-level diode neutral point clamping converter employing a two-quadrant superswitcher in one embodiment.

[0068] Figure 23 This invention illustrates a three-level active neutral point clamping converter employing a two-quadrant superswitcher in one embodiment.

[0069] Figure 24 This illustration shows a Taipei rectifier employing a two-quadrant super switch in one embodiment of this invention.

[0070] The reference numerals in the attached figures are explained as follows:

[0071] S1, S2, S3, S n S n-1 :switch

[0072] C1, C2, C3, C n C n-1 :capacitance

[0073] R1, R2, R3, R n R n-1 R g1 R g2 R gn R gn-1 :resistance

[0074] D1, D2, D3, D n-1 :diode

[0075] V DS1 V DS2 V CTRL :Voltage

[0076] C M :capacitance

[0077] Q1, Q2, Q3, Q4: Switches

[0078] PWM_S1, PWM_S2: PWM signals

[0079] V ref Reference voltage

[0080] C DC_P C DC_N :capacitance

[0081] S 1_P S 2_P S 3_P S 4_P S 1_N S 2_N S 3_N S 4_N :switch

[0082] C A1 C A2 C: Capacitor

[0083] S 1’ S 2’ :switch

[0084] L: Inductance

[0085] R: Resistance

[0086] 800: Device

[0087] 810_1, 810_2, 810_N: Modular Units

[0088] PWM1, PWM2, PWM N PWM signal

[0089] 910, 1010, 1110, 1210: Units

[0090] 910p: Upper endpoint

[0091] 910n: Lower endpoint

[0092] p, n: Terminals

[0093] S 1M S 2M S 1T S 2T Main switch

[0094] S 1A S 2A Auxiliary switch

[0095] C 1A C 2A :capacitance

[0096] 1011, 1211: First circuit loop

[0097] 1012, 1212: Second circuit loop

[0098] D 11 D 1n D 21 D 2n :diode

[0099] C11 C 1n C 21 C 2n :capacitance

[0100] 1400: Half-bridge arm

[0101] 1410_1, 1410_n, 1420_1, 1420_n: Cascaded Units

[0102] P, N, SW: Terminals

[0103] S P1M S PnM S N1M S NnM S P1A S PnA S N1A S NnA :switch

[0104] C P1A C PnA C N1A C NnA :capacitance

[0105] P1M, P2M, P3M, P4M, P1A, P2A, N1A, N1M, N2A, N2M: Switching waveforms

[0106] Vsw: Node voltage

[0107] V DC V out :Voltage

[0108] t d t d1 t d2 t d3 t d4 t d5 t d6 t delay Delay time

[0109] I top I bom Current

[0110] t dead Dead Zone Time

[0111] 1710: Quasi-two-level generation module

[0112] 1720: Circular Sequence Module

[0113] 1730: Controller

[0114] V C Unit voltage

[0115] V C_ref Reference voltage

[0116] ΔD: Duty cycle difference

[0117] U c1 U cn :sequence

[0118] I O Output current

[0119] 1810: Quasi-two-level generation module

[0120] 1820: Sequence Controller Detailed Implementation

[0121] Some typical embodiments that embody the features and advantages of this invention will be described in detail in the following description. It should be understood that this invention can have various variations in different forms, all of which do not depart from the scope of this invention, and the descriptions and illustrations therein are essentially for illustrative purposes and not intended to limit this invention.

[0122] This invention provides a high-voltage device based on multiple modular low-voltage units. Figure 8 This illustration shows a high-voltage device 800 with a super-switch architecture formed by multiple modular units connected in series, according to one embodiment of this invention. The term "super-switch" as used herein refers to a high-voltage switch composed of multiple low-voltage switches arranged in series. Figure 8As shown, the device 800 includes multiple modular units 810_1, 810_2, ..., 810_N connected in series. Each modular unit 810_1, 810_2, ..., 810_N includes a first terminal, a second terminal, and a control terminal. In any of the modular units 810_1, 810_2, ..., 810_N, the first terminal of any modular unit is connected to the second terminal of the adjacent modular unit, and each modular unit can form a two-quadrant or four-quadrant switch that allows bidirectional current flow. The modular unit structure can have two-level output or multi-level output. Terminal 1 and terminal 2 are considered as two output terminals of the super switch architecture. This invention adopts a modular architecture, and each modular unit 810_1, 810_2, ..., 810_N is identical. In some embodiments, each of the modular units 810_1, 810_2, ..., 810_N includes multiple low-voltage semiconductor devices and one or more low-voltage passive components, and can be controlled by sending control signals (e.g., PWM (pulse width modulation) signals) to the control terminals (e.g., the gates of the low-voltage semiconductor devices) of the modular units 810_1, 810_2, ..., 810_N. Furthermore, as... Figures 9 to 12 As shown, the modular units 810_1, 810_2, ..., 810_N can be two-level or multi-level structures. In some embodiments, the low-voltage semiconductor device is a power MOSFET, and the low-voltage passive component is a capacitor, both of which can operate in the range of approximately 50–600V or approximately 500–1200V.

[0123] Figure 9 Show Figure 8 An example of modular units 810_1, 810_2, ..., 810_N (i.e., unit 910) is shown, where unit 910 has a half-bridge two-level two-quadrant unit structure. For example... Figure 9 As shown, unit 910 includes terminals p and n, wherein terminal p is located at the active main switch S. 1M and active auxiliary switch S 1A Between, terminal n is located at the active main switch S 1M With capacitor C 1A Between. The active main switch S of unit 910. 1M Active auxiliary switch S 1A and capacitor C 1A They are connected to form a circuit loop. In this embodiment, switch S 1M The drain and switch S 1A The source terminal is connected to the upper terminal 910p, where the upper terminal 910p is connected to terminal p; while switch S 1MThe source and capacitor C 1A It is connected to the lower terminal 910n, where the lower terminal 910n is connected to terminal n. A control signal (e.g., a PWM signal) is transmitted to switch S. 1M and switch S 1A The gate of the control unit 910 can be used. In medium-voltage applications, multiple units 910, each consisting of multiple low-voltage semiconductor devices, are connected in series, wherein the terminal p of any unit 910 is connected to the terminal n of an adjacent unit 910.

[0124] Figure 10 Show Figure 8 Another example of the modular units 810_1, 810_2, ..., 810_N (i.e., unit 1010) is shown, which has a cascaded half-bridge three-level two-quadrant unit structure. For example... Figure 10 As shown, unit 1010 includes a terminal p connected to the first circuit loop 1011 and a terminal n connected to the second circuit loop 1012. The first circuit loop 1011 includes a first main switch S connected in series. 1M First auxiliary switch S 1A and the first capacitor C 1A The second circuit loop 1012 includes a second main switch S connected in series. 2M Second auxiliary switch S 2A Second capacitor C 2A In the first circuit loop 1011, located at the first main switch S 1M With the first capacitor C 1A One node between them is connected in the second circuit loop 1012 located at the second main switch S. 2M With the second capacitor C 2A A node between them. Control signals (e.g., PWM signals) are transmitted to switch S. 1M S 1A S 2M and S 2A The gate of the control unit 1010 can be used. In medium-voltage applications, multiple units 1010, each consisting of multiple low-voltage semiconductor devices, are connected in series, wherein the terminal p of any unit 1010 is connected to the terminal n of an adjacent unit 1010.

[0125] Figure 11 Show Figure 8 Another example of the modular units 810_1, 810_2, ..., 810_N (i.e., unit 1110), unit 1110 has a T-type four-quadrant unit structure. For example... Figure 11As shown, unit 1110 includes terminals p / n and n / p. Three circuit bridge arms (located at the top, middle, and bottom, respectively) are connected in parallel between terminals p / n and n / p. From terminal p / n to terminal n / p, the upper circuit bridge arm sequentially includes a first auxiliary switch S connected in series. 1A and the first capacitor C 1A The lower circuit bridge arm sequentially includes a second auxiliary switch S connected in series. 2A Second capacitor C 2A The middle circuit bridge arm sequentially includes the first main switch S connected in series. 1T Second main switch S 2T In this embodiment, switch S 1T and S 2T The sources are interconnected. A control signal (e.g., a PWM signal) is transmitted to switch S. 1A S 1T S 2A and S 2T The gate of the control unit 1110 can be used. In medium-voltage applications, multiple units 1110 composed of multiple low-voltage semiconductor devices are connected in series, wherein the terminal p / n of any unit 1110 is connected to the terminal n / p of the adjacent unit 1110.

[0126] Figure 12 Show Figure 8 Another example of the modular units 810_1, 810_2, ..., 810_N (i.e., unit 1210), unit 1210 has a four-quadrant unit structure. For example... Figure 12 As shown, unit 1210 includes terminals p / n connected to the first circuit loop 1211 and terminals n / p connected to the second circuit loop 1212. Figure 12 Unit 1210 in the middle is essentially the same as Figure 10 The same as unit 1010, but compared to unit 1010, in Figure 12 In unit 1210, the first circuit loop 1211 and the second circuit loop 1212 are also flipped or reversed to realize a four-quadrant device. The first circuit loop 1211 is located at the first main switch S. 1M With the first capacitor C 1A One node between them is connected to the second circuit loop 1212 located at the second main switch S. 2M With the second capacitor C 2A A node between them. Control signals (e.g., PWM signals) are transmitted to switch S. 1M S 1A S 2M and S 2AThe gate of the control unit 1210 can be used. In medium-voltage applications, multiple units 1210 composed of multiple low-voltage semiconductor devices are connected in series, wherein the terminal p / n of any unit 1210 is connected to the terminal n / p of the adjacent unit 1210.

[0127] Figure 13 Showing will Figure 11 The T-type four-quadrant unit structure is used in one application of Vienna rectifiers, where the Vienna rectifier is a unidirectional single-phase three-switch three-level PWM rectifier. This application can be viewed as a combination of a single-phase diode bridge arm and an integrated boost converter. For example... Figure 13 As shown, multiple Figure 11 The units 1110 are connected in a cascaded configuration to suit higher voltage applications.

[0128] Figure 14 Showing will Figure 9 The element 910, with its half-bridge two-quadrant unit structure, is used in one application of a typical phase bridge arm architecture. For example... Figure 14 As shown, the half-bridge arm 1400 includes an upper super switch or upper bridge arm (located between terminal SW and terminal P) and a lower super switch or lower bridge arm (located between terminal SW and terminal N). The upper super switch or upper bridge arm has multiple cascaded units 1410_1 to 1410_n connected in series, and the lower super switch or lower bridge arm has multiple cascaded units 1420_1 to 1420_n connected in series. In this embodiment, any one of the cascaded units 1410_1 to 1410_n and 1420_1 to 1420_n is connected to... Figure 9 The unit 910 is identical. In this case, all units are identical, with a delay time between their control sequences. This allows control over the total on and off times of the high-voltage device, reducing the output equivalent dv / dt. Controllable dv / dt facilitates the shaping of output harmonics (especially in the intermediate frequency range), which reduces the need for or space occupied by the output filter.

[0129] The half-bridge arm 1400 can be controlled in a quasi-two-level (Q2L) mode. In some embodiments, the upper arm between terminal SW and terminal P has four connected units, and the lower arm between terminal SW and terminal N has four connected units. The upper and lower arms are controlled by complementary signals. For example, when the upper arm's switch S... P1M When in the ON state, the lower bridge arm switch S N1M It is in the off state. Similarly, in each unit, switch S... PnM Control signals and switches S PnA The control signals are complementary, that is, when switch S PnA When in the off state, switch SPnM It is in the on state.

[0130] Figure 15A and Figure 15B exemplify Figure 14 The modulation strategy of the phase bridge arm architecture. In this embodiment, there are four units cascaded together in the upper bridge arm and four units cascaded together in the lower bridge arm. Figure 16 exemplify Figure 14 The waveforms of voltage, current, and gate signals in the phase bridge arm architecture are shown. For simplicity, Figure 16 Only the relevant waveforms of the two cascaded units in the upper arm and the two cascaded units in the lower arm are shown.

[0131] To achieve the delay time for each unit, such as Figure 15A and Figure 15B As shown, a delay time t needs to be inserted between the switching times of each unit. d For simplicity, only the switch S of the upper bridge arm is shown in the diagram. P1M S P2M S P3M and S P4M The control signal waveforms are P1M, P2M, P3M, and P4M. Due to a preset delay time, some units are turned on or off in the leading position, while others are turned on or off in the lagging position. The waveform of the switching node voltage Vsw is a quasi-two-level waveform.

[0132] Under specific load current polarity, the leading or lagging positions in the control timing will lead to uneven charging or discharging of energy stored in each unit, resulting in voltage imbalance among all series-connected super-switching units. To resolve the voltage imbalance caused by quasi-two-level operation, a rotating sequence can be implemented. For example... Figure 15A and Figure 15B As shown, in each switching cycle, the sequence counter counts from 0 to 3, and the lead and lag positions of these cascaded units change sequentially according to the value of the sequence counter, thereby ensuring uniform charging or discharging of each unit. The voltage of each unit needs to be sensed and its sensed value compared with a reference voltage. The reference voltage corresponding to the voltage of all units must be consistent to ensure modularity. The obtained voltage difference is fed into a voltage compensator, which adjusts the duty cycle of the control signal for each unit based on this voltage difference.

[0133] Figure 17 This invention illustrates a control algorithm according to an embodiment of the present invention. Figure 18 Showing the use of Figure 17 The balancing method of the control algorithm in [the document / process]. Please refer to [the document / reference]. Figure 17 and Figure 18In some embodiments, the quasi-two-level generation module 1710 is based on Figure 14 The PWM signal generation delay time t of the upper bridge arm switch d1 t d2 t d3 t d4 t d5 and t d6 (like Figure 15A and Figure 15B (As shown). The cyclic sequence module 1720 is based on the delay time t. d1 t d2 t d3 t d4 t d5 and t d6 A cyclic sequence of control signals P1M, P2M, P3M, and P4M is generated. Then, the control signals P1M, P2M, P3M, and P4M are transmitted to cells 1410_1 to 1410_4 of the half-bridge arm 1400. Furthermore, the voltage V of each cell is sensed. C and compare it with the reference voltage V C_ref A comparison is made, and the resulting voltage difference is transmitted to controller 1730 to generate a duty cycle difference value ΔD, thereby adjusting the duty cycle of the control signals for each unit. To achieve correct electrical performance, the output current polarity I also needs to be detected and applied. O (or I) out If V C Greater than V C_ref And I O If the value is greater than zero, then the duty cycle of the control signal received by the cyclic sequence module 1720 will be subtracted by ΔD. If V C Greater than V C_ref And I O If V is not greater than zero, then ΔD will be added to the duty cycle of the control signal received by the cyclic sequence module 1720. C Not greater than V C_ref And I O If the value is not greater than zero, then the duty cycle of the control signal received by the cyclic sequence module 1720 will be subtracted by ΔD. If V C Not greater than V C_ref And I O If the value is greater than zero, then ΔD will be added to the duty cycle of the control signal received by the cyclic sequence module 1720.

[0134] Figure 19 This illustrates a control algorithm according to another embodiment of the present invention. Figure 20 Showing the use of Figure 19The balancing method of the control algorithm in this embodiment utilizes a lead-lag sequence to balance the voltage of each unit, thus eliminating the need for a cyclic sequence. The voltages of all units are sensed and sorted sequentially to generate a sequence U. c1 ~U cn The polarity of the load current and the voltage value of the unit can be used to determine and adjust the control signal corresponding to each unit to be in the leading or lagging position.

[0135] Please see Figure 19 and Figure 20 The quasi-two-level generation module 1810 is based on... Figure 14 The PWM signal generation delay time t of the upper bridge arm switch d1 t d2 t d3 t d4 t d5 and t d6 (like Figure 15A and Figure 15B (As shown). Then, the sequence controller 1820 follows the sequence U. c1 ~U cn The control signals corresponding to each unit are generated and adjusted to lead or lag positions to balance the voltage of each unit. Therefore, cyclic sequence and duty cycle control are unnecessary. In this embodiment, the voltages of all units are sensed, sorted from largest to smallest, and a sequence U is generated. c1 ~U cn By means of the load current polarity I O (or I) out ), and determines whether the control signal corresponding to each unit is in the leading or lagging position based on the unit's voltage. If I O If I is greater than zero, the cell with the larger voltage will be ranked in the leading position; otherwise, if I is less than zero, the cell with the larger voltage will be ranked in the leading position. O If the value is less than or equal to 0, the cell with the larger voltage will be ranked in the lagging position.

[0136] Thanks to modular technology, the switching circuit impedance of each unit can be maintained exceptionally well, resulting in extremely low switching losses even in hard-switching applications. This invention provides a scalability to other applications (e.g., Figures 21 to 24 The modular construction scheme of the multilevel converter shown is illustrated.

[0137] To facilitate the explanation and definition of the technical content of this application, terms such as "substantially," "approximately," "slightly," and "relatively" are used to indicate an inherent degree of uncertainty, which may be caused by quantitative comparisons, numerical values, sensing, and other factors. These terms generally mean a deviation from a given value or range within 10%, 5%, 1%, or 0.5%, and that such deviation does not affect the basic function of the corresponding technical feature. Unless otherwise specifically stated, the numerical parameters stated in this application are values ​​that can be considered as specific values ​​or values ​​within their error range.

[0138] It should be noted that the above are merely preferred embodiments for illustrating this case, and this case is not limited to the described embodiments. The scope of this case is determined by the appended claims. Furthermore, this case may be modified in various ways by those skilled in the art, but all such modifications shall not depart from the protection sought by the appended claims.

Claims

1. A high-voltage device, comprising: Multiple modular units, each of which includes a first terminal, a second terminal, and a control terminal. The multiple modular units are connected in series, and the first end of any modular unit is connected to the second end of the adjacent modular unit. Each of the modular units comprises multiple low-voltage semiconductor devices and one or more low-voltage passive components; and A control unit is configured to send a control signal to the control terminal of each modular unit, wherein each control signal is offset by a corresponding delay time. The control unit includes a level generation module and a sequence controller. The level generation module generates the delay time based on the PWM signal of each modular unit, and the sequence controller generates the sequence position of the control signal of each modular unit based on the unit voltage of each modular unit and the polarity of the output current of the high-voltage device. The sequence controller is further configured to sort the multiple unit voltages of the plurality of modular units in a predetermined order, and sort the sequence position of the control signal corresponding to each modular unit in the predetermined order or its reverse order according to the polarity of the output current of the high-voltage device.

2. The high-voltage device as claimed in claim 1, wherein the one or more low-voltage passive components include a capacitor.

3. The high-voltage device of claim 1, wherein the plurality of low-voltage semiconductor devices comprises at least two power MOSFETs.

4. The high-voltage device as claimed in claim 1, wherein each of the modular units is a two-quadrant switch that allows bidirectional current flow.

5. The high-voltage device as claimed in claim 4, wherein the two-quadrant switch includes an active main switch, an active auxiliary switch and a capacitor, the active main switch, the active auxiliary switch and the capacitor are connected to form a circuit loop, wherein a first node between the active main switch and the active auxiliary switch is connected to the first end, and a second node between the active main switch and the capacitor is connected to the second end.

6. The high-voltage device as claimed in claim 4, wherein the two-quadrant switch includes a first circuit loop connected to the first end and a second circuit loop connected to the second end, wherein the first circuit loop includes a first active main switch, a first auxiliary switch and a first capacitor connected in series, the second circuit loop includes a second active main switch, a second auxiliary switch and a second capacitor connected in series, and a first node in the first circuit loop located between the first active main switch and the first capacitor is connected to a second node in the second circuit loop located between the second active main switch and the second capacitor.

7. The high-voltage device as claimed in claim 1, wherein each of the modular units is a four-quadrant switch.

8. The high-voltage device as claimed in claim 7, wherein the four-quadrant switch includes a first circuit bridge arm, a second circuit bridge arm, and a third circuit bridge arm connected in parallel between the first end and the second end, the first circuit bridge arm includes a first auxiliary switch and a first capacitor connected in series, the second circuit bridge arm includes a first main switch and a second main switch connected in series, and the third circuit bridge arm includes a second auxiliary switch and a second capacitor connected in series.

9. The high-voltage device as claimed in claim 8, wherein the sources of the first main switch and the second main switch are interconnected.

10. The high-voltage device of claim 7, wherein the four-quadrant switch includes a first circuit loop connected to the first end and a second circuit loop connected to the second end, wherein the first circuit loop includes a first active main switch, a first auxiliary switch and a first capacitor connected in series, the second circuit loop includes a second active main switch, a second auxiliary switch and a second capacitor connected in series, and a first node in the first circuit loop located between the first active main switch and the first capacitor is connected to a second node in the second circuit loop located between the second active main switch and the second capacitor.

11. A high-voltage half-bridge device, comprising: A first end, a second end, and a third end; An upper bridge arm is connected between the first end and the second end, wherein the upper bridge arm includes a plurality of first low-voltage modular units connected in a cascaded configuration; A lower bridge arm is connected between the first end and the third end, wherein the lower bridge arm includes a plurality of second low-voltage modular units connected in a cascaded configuration. The number of the first low-voltage modular unit and the number of the second low-voltage modular unit are equal; and A control unit is configured to send a control signal to the control terminal of each low-voltage modular unit, wherein each control signal is offset by a corresponding delay time. The control unit includes a level generation module and a sequence controller. The level generation module generates the delay time based on the PWM signal of each low-voltage modular unit, and the sequence controller generates the sequence position of the control signal of each low-voltage modular unit based on the unit voltage of each low-voltage modular unit and the polarity of the output current of the high-voltage half-bridge device. The sequence controller is further configured to sort the multiple unit voltages of the plurality of low-voltage modular units in a predetermined order, and sort the sequence position of the control signal corresponding to each low-voltage modular unit in the predetermined order or its reverse order according to the polarity of the output current of the high-voltage half-bridge device.

12. The high-voltage half-bridge device as claimed in claim 11, wherein the first low-voltage modular unit and the second low-voltage modular unit are both two-quadrant switches capable of bidirectional current flow.

13. A control method, based on controlling the high-voltage device of claim 1, the control method comprising: Transmit control signals to the control terminal of each modular unit, wherein each control signal is offset by a corresponding delay time; Sensing the unit voltage of each modular unit and the polarity of the output current of the high-voltage device; The delay time is generated based on the PWM signal of each modular unit; Based on the unit voltage and the polarity of the output current of each modular unit, the sequence position of the control signal for each modular unit is generated; and The control signal is output to each modular unit according to the sequence position in order to balance the voltage of multiple units in the multiple modular units; The step of generating the sequence position of the control signal for each modular unit based on the unit voltage and the polarity of the output current of each modular unit includes: The voltages of the multiple modular units are sorted in a predetermined order; Based on the polarity of the output current of the high-voltage device, the sequence positions of the control signals corresponding to each modular unit are sorted in a predetermined order or in reverse order.

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