Execution method shared by multiplication operations, system on chip, electronic device, and medium

Abstract

This application relates to the field of data processing technology, and discloses a method for executing multiplication operations, an on-chip system, an electronic device, and a medium. The electronic device includes a scalar processor and a vector processor. When the vector processor is configured to perform floating-point multiplication operations that do not possess vector characteristics, the scalar processor includes a scalar multiplication unit, which can be used to perform integer multiplication operations, and multiplication operations with the vector processor that do not include vectors. The method includes: acquiring data to be multiplied from the vector processor; sending the data to be multiplied from the vector processor to the scalar multiplication unit, and performing integer multiplication operations through the scalar multiplication unit to obtain the integer multiplication result; then sending the integer multiplication result to the vector processor for processing to obtain the final floating-point multiplication result. Based on the above scheme, the area occupied by the multiplier in the on-chip system can be effectively reduced.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to an execution method, system-on-a-chip, electronic device and medium for multiplication operations. Background Technology

[0002] Currently, such as Figure 1 As shown, a System-on-Chip (SOC) typically integrates a scalar processor and a vector processor. The scalar processor contains a scalar multiplication unit for performing integer multiplication operations and supports Single Instruction Multiple Data (SIMD) functionality. The vector processor contains a vector multiplication unit for performing integer vector multiplication and the multiplication portion of floating-point multiplication in the IEEE 754 standard. Both the vector multiplication unit and the scalar multiplication unit occupy a relatively large area, resulting in a large overall SOC area. Summary of the Invention

[0003] To address the aforementioned issues, embodiments of this application provide a multiplication operation-shared execution method, a system-on-a-chip, an electronic device, and a medium. The multiplication operation-shared execution method can also be referred to as a multiplication operation-shared execution method.

[0004] In a first aspect, embodiments of this application provide a method for executing multiplication operations in an electronic device. The electronic device includes a scalar processor and a vector processor. The scalar processor includes a scalar multiplication unit for performing integer multiplication operations. The vector processor is configured to perform floating-point multiplication operations that do not possess vector characteristics. The method includes: acquiring data to be multiplied in the vector processor; sending the data to be multiplied in the vector processor to the scalar multiplication unit and performing integer multiplication operations through the scalar multiplication unit to obtain an integer multiplication result; and sending the integer multiplication result to the vector processor for processing to obtain a floating-point result. The floating-point result is a floating-point result conforming to the IEEE 754 standard.

[0005] In some embodiments, the electronic device may include a system-on-a-chip (SoC), and the scalar processor and vector processor may be integrated into the SoC. Based on the above scheme, when the vector processor is configured to perform floating-point multiplication operations that do not have vector characteristics, the vector processor of the electronic device provided in this application embodiment may not have a vector multiplication unit, and only the scalar multiplication unit in the scalar processor may be retained, which can effectively reduce the area occupied by the multiplier in the SoC.

[0006] Furthermore, in the multiplication method provided in this application, when the vector processor processes the mantissa multiplication operation in floating-point multiplication, the data requiring integer multiplication can be sent to the scalar multiplication unit in the scalar processor. After the scalar multiplication unit obtains the operation result, it sends the result back to the vector processor for subsequent floating-point related processing calculations. Thus, floating-point multiplication operations conforming to the IEEE 754 standard can still be implemented without setting up a vector multiplication unit.

[0007] In one possible implementation of the first aspect described above, the vector processor includes a shift unit, an exponentiation processing unit, and a floating-point exception judgment unit. The step of sending the integer multiplication result to the vector processor for processing includes: sending the integer multiplication result to the shift unit for shift processing, the exponentiation processing unit performing exponentiation processing, and the floating-point exception judgment unit performing exception handling of the final floating-point result to obtain the floating-point operation result.

[0008] In one possible implementation of the first aspect described above, the vector processor does not include a vector multiplication unit.

[0009] In one possible implementation of the first aspect above, the method further includes: acquiring data to be multiplied in the scalar processor; sending the data to be multiplied in the scalar processor to the scalar multiplication unit, and performing integer multiplication through the scalar multiplication unit to obtain the integer multiplication result; and sending the integer multiplication result to a processing unit in the scalar processor, the processing unit including a register unit.

[0010] In one possible implementation of the first aspect described above, the floating-point multiplication operation includes half-precision floating-point multiplication, single-precision floating-point multiplication, and double-precision floating-point multiplication.

[0011] Secondly, embodiments of this application provide a method for executing multiplication operations in an electronic device. The electronic device includes a scalar processor and a vector processor. The vector processor includes a vector multiplication unit and is configured to perform floating-point multiplication operations with vector characteristics and integer multiplication operations with vector characteristics. The method includes: acquiring data to be multiplied in the scalar processor; sending the data to the vector multiplication unit and performing the corresponding multiplication operation through the vector multiplication unit to obtain the multiplication result; and sending the multiplication result to a processing unit in the scalar processor.

[0012] In some embodiments, the aforementioned electronic device may include a system-on-a-chip (SoC), and a scalar processor and a vector processor may be integrated into the SoC. Based on the above scheme, the vector processor is configured to perform integer multiplication and floating-point multiplication operations with vector characteristics. During the design of the multiplication unit, a scalar multiplication unit may not be configured; only a vector multiplication unit is configured. The vector multiplication unit performs integer multiplication operations in the scalar processor and sends the results to the next processing unit of the scalar processor for further processing. Thus, by removing the scalar multiplication unit, the area occupied by the multiplication unit on the SoC can be effectively reduced, thereby reducing the total area of ​​the SoC.

[0013] In one possible implementation of the second aspect described above, the processing unit includes a register unit. It is understood that the processing unit can also be other units. In this embodiment, the computation result of the vector processor can be sent to the corresponding processing unit of the scalar processor for corresponding processing based on computational requirements.

[0014] In one possible implementation of the second aspect described above, the scalar processor does not include a scalar multiplication unit.

[0015] In one possible implementation of the second aspect above, the method further includes: acquiring data to be multiplied in the vector processor; sending the data to be multiplied in the vector processor to the vector multiplication unit, and performing corresponding operations through the vector multiplication unit to obtain the operation result; and sending the operation result to a processing unit in the vector processor, the processing unit including a shift unit.

[0016] In one possible implementation of the second aspect described above, the floating-point multiplication operation includes single-precision floating-point multiplication, half-precision floating-point multiplication, and double-precision floating-point multiplication.

[0017] Thirdly, embodiments of this application provide an electronic device, which includes a scalar processor, a vector processor, and a bus control unit. The scalar processor includes a scalar multiplication unit for performing integer multiplication operations. The vector processor is configured to perform floating-point multiplication operations that do not have vector characteristics. The bus control unit is used to execute the execution method for multiplication operations mentioned in the first aspect.

[0018] Fourthly, embodiments of this application provide an electronic device, which includes a scalar processor, a vector processor, and a bus control unit. The vector processor includes a vector multiplication unit and is configured to perform floating-point multiplication operations with vector characteristics and integer multiplication operations with vector characteristics. The bus control unit is used to perform the execution method for multiplication operations mentioned in the second aspect.

[0019] Fifthly, embodiments of this application provide a system-on-a-chip (SoC) comprising a scalar processor, a vector processor, and a bus control unit. The scalar processor includes a scalar multiplication unit for performing integer multiplication operations. The vector processor is configured to perform floating-point multiplication operations that do not possess vector characteristics. The bus control unit is configured to execute the execution method for multiplication operations mentioned in the first aspect.

[0020] In a sixth aspect, embodiments of this application provide a system-on-a-chip, the system-on-a-chip including a scalar processor, a vector processor, and a bus control unit, the vector processor including a vector multiplication unit, the vector processor being configured to perform floating-point multiplication operations having vector characteristics and integer multiplication operations having vector characteristics; the bus control unit being used to perform the execution method common to multiplication operations mentioned in the second aspect.

[0021] In a seventh aspect, embodiments of this application provide an electronic device, including: a memory for storing instructions executed by one or more processors of the electronic device, and the processor being one of the one or more processors of the electronic device for executing the execution method for multiplication operations mentioned in the first or second aspect.

[0022] Eighthly, embodiments of this application provide a readable storage medium storing instructions that, when executed on an electronic device, cause the electronic device to perform the execution method commonly used for multiplication operations mentioned in the first or second aspect.

[0023] Ninthly, embodiments of this application provide a computer program product, including execution instructions, which, when executed on an electronic device, cause the electronic device to perform the execution method commonly used for multiplication operations mentioned in the first or second aspect. Attached Figure Description

[0024] Figure 1 According to some embodiments of this application, a schematic diagram of a system-on-a-chip is shown;

[0025] Figure 2 According to some embodiments of this application, a block diagram of a system-on-a-chip is shown;

[0026] Figure 3 According to some embodiments of this application, a schematic diagram of a system-on-a-chip is shown;

[0027] Figure 4 According to some embodiments of this application, a schematic diagram of a system-on-a-chip is shown;

[0028] Figure 5According to some embodiments of this application, a schematic diagram of a system-on-a-chip is shown.

[0029] Figure 6 According to some embodiments of this application, a flowchart of an execution method shared by multiplication operations is shown;

[0030] Figure 7 According to some embodiments of this application, a flowchart of an execution method shared by multiplication operations is shown;

[0031] Figure 8 According to some embodiments of this application, a schematic diagram of the structure of an electronic device is shown. Detailed Implementation

[0032] The illustrative embodiments of this application include, but are not limited to, a multiplication operation-shared execution method, a system-on-a-chip, an electronic device, and a medium.

[0033] To better understand the solutions in the embodiments of this application, some terms mentioned in the embodiments of this application will be explained first.

[0034] A vector processor is a parallel processor that performs vector-based parallel computations and primarily uses a pipelined architecture.

[0035] Vector multiplication units, the multiplication units in a vector processor, are divided into two categories according to their configuration. The first type of vector multiplication unit performs the integer multiplication operation within floating-point multiplication, which possesses vector characteristics. The second type of vector multiplication unit performs the integer multiplication operation within floating-point multiplication, which does not possess vector characteristics. Floating-point multiplication includes three parts: sign bit XOR, exponent addition, and mantissa multiplication. Mantissa multiplication includes integer multiplication and shift operations. In other words, the vector multiplication unit performs the integer multiplication part of mantissa multiplication.

[0036] Scalar processors are processors that perform non-vector operations and are primarily pipelined.

[0037] The scalar multiplication unit, the multiplication unit in a scalar processor, is used to perform regular integer multiplication.

[0038] As mentioned earlier, both vector multiplication units and scalar multiplication units occupy a large area in the system-on-a-chip, resulting in a large overall system-on-a-chip area.

[0039] To address the aforementioned issues, embodiments of this application provide a system-on-a-chip (SoC). When the SoC is configured to perform only conventional floating-point multiplication and conventional integer multiplication operations (which do not possess vector characteristics), i.e., when the vector processor is configured to perform only conventional floating-point multiplication operations (which do not possess vector characteristics), the SoC in this application does not include a vector multiplication unit in the vector processor, but only a scalar multiplication unit in the scalar processor.

[0040] It is understandable that the scalar multiplication unit in a scalar processor is generally used to perform the conventional integer multiplication operations mentioned above. Conventional floating-point multiplication operations, which lack vector characteristics, are generally performed by a vector processor. As mentioned earlier, floating-point multiplication operations without vector characteristics include three parts: sign bit XOR, exponent addition, and mantissa multiplication. Mantissa multiplication includes integer multiplication and shift operations. That is, the integer multiplication in mantissa multiplication is generally performed by the vector multiplication unit in the vector processor, while other floating-point multiplication operations are performed by other corresponding processing units in the vector processor.

[0041] In this embodiment, after removing the vector multiplication unit from the vector processor and retaining only the scalar multiplication unit in the scalar processor, when the vector processor processes the mantissa multiplication operation in floating-point multiplication, the data requiring integer multiplication can be sent to the scalar multiplication unit in the scalar processor. After the scalar multiplication unit obtains the result, it sends the result back to the vector processor for subsequent shift calculations. Thus, conventional floating-point multiplication operations conforming to the IEEE 754 standard can still be implemented without setting up a vector multiplication unit.

[0042] In some embodiments, the vector processor includes a shift unit, an exponentiation processing unit, and a floating-point exception judgment unit. After the scalar multiplication unit obtains the operation result, the integer multiplication operation result can be sent to the shift unit for shift processing, the exponentiation processing unit for exponentiation operation processing, and the floating-point exception judgment unit for exception handling of the final floating-point result to obtain the floating-point operation result.

[0043] Even after removing the vector multiplication unit from the vector processor and retaining only the scalar multiplication unit in the scalar processor, regular integer multiplication operations in the scalar processor are still handled by the scalar multiplication unit.

[0044] In other words, the on-chip system provided in this application embodiment uses scalar multiplication units to replace the function of the initial vector multiplication units, which can effectively reduce the number of multiplication units and thus reduce the area occupied by the multiplication units in the on-chip system.

[0045] Correspondingly, this application provides a common execution method for multiplication operations, used in the above-mentioned on-chip system, including: acquiring data to be multiplied during floating-point multiplication in the vector processor, sending the data to be multiplied to the scalar multiplication unit, performing integer multiplication in floating-point multiplication through the scalar multiplication unit, and sending the result to the shift unit of the vector processor for subsequent shift processing.

[0046] When the multiplication operation to be performed is an integer multiplication operation in a scalar processor, the data to be multiplied is sent to the scalar multiplication unit for operation, and the result of the scalar multiplication unit is sent to the next processing unit in the scalar processor for further processing. The next processing unit can be any unit such as a register unit. In this embodiment, the operation result of the scalar processor can be sent to the corresponding processing unit of the scalar processor for corresponding processing based on the computational requirements.

[0047] As mentioned earlier, the scalar multiplication unit can perform integer multiplication. Therefore, when performing the mantissa multiplication part of floating-point multiplication, such as 1.68 * 1.44, 1.68 and 1.44 can be sent to the scalar multiplication unit. The scalar multiplication unit performs the integer multiplication operation 168 * 144, and then the result 24192 is sent to the shift unit in the vector processor. The result is then shifted to the left by four decimal places to obtain the final result of 1.68 * 1.44, 2.4192.

[0048] In some embodiments, when the on-chip system is configured to perform vector multiplication, i.e., to perform both vector-based floating-point and integer multiplication, or when the vector processor is configured to perform either vector-based floating-point or integer multiplication, the on-chip system in this embodiment does not include a scalar multiplication unit in the scalar processor, but only a vector multiplication unit in the vector processor. The vector multiplication unit performs integer multiplication and sends the result to the corresponding processing unit of the scalar processor, such as a register unit, for further processing.

[0049] In this way, the scalar multiplication unit is removed and only the vector multiplication unit is set up. That is, the function of the initial two multiplication units is realized by using one multiplication unit, which can also effectively reduce the area occupied by the multiplication unit in the on-chip system.

[0050] Correspondingly, this application provides a common execution method for multiplication operations, used in the aforementioned on-chip system including a vector processor. The method includes acquiring data to be multiplied in a scalar processor, sending the data to be multiplied to a vector multiplication unit, and sending the result of the vector multiplication unit to a corresponding processing unit in the scalar processor, such as a register unit. If the multiplication operation is a floating-point multiplication or vector multiplication in the vector processor, the data to be multiplied is still sent to the vector multiplication unit for processing, and the result of the vector multiplication unit is sent to a subsequent processing unit of the multiplication unit in the vector processor. The subsequent processing unit can be a shift unit or other corresponding processing unit. In this application embodiment, the result of the vector processor's operation can be sent to the corresponding processing unit of the vector processor for corresponding processing based on computational requirements.

[0051] It is understandable that in some cases, the on-chip system required by the user is only used to handle integer multiplication and floating-point multiplication operations that do not have vector characteristics. In this case, the target configuration of the vector processor can be set to implement floating-point multiplication operations without vector characteristics. The design scheme of the multiplication unit can be based on this target configuration. For example, when designing the multiplication unit, vector multiplication units can be omitted, and only scalar multiplication units can be set. The scalar multiplication units can be used to implement integer multiplication operations in floating-point arithmetic, and subsequent operations can be sent to the post-processing unit. By removing the vector multiplication units, the area occupied by the multiplication units on the on-chip system can be effectively reduced, thereby reducing the total area of ​​the on-chip system.

[0052] In some embodiments, the user-required on-chip system needs to perform multiplications with vector characteristics, such as when the user needs to use the on-chip system for image recognition processing via neural networks. In this case, the target configuration of the vector processor can be set to perform integer and floating-point multiplication operations with vector characteristics. The design scheme of the multiplication unit can be based on this target configuration. For example, when designing the multiplication unit, scalar multiplication units can be omitted, and only vector multiplication units can be set. The vector multiplication units can perform integer multiplication operations, and the operation results can be sent to the next processing unit of the scalar processor for subsequent processing. By removing the scalar multiplication units, the area occupied by the multiplication units on the on-chip system can be effectively reduced, thereby reducing the total area of ​​the on-chip system.

[0053] Before introducing the detailed execution method for multiplication operations in this application, the on-chip system provided in the embodiments of this application will be introduced first.

[0054] like Figure 2 As shown, Figure 2 A block diagram of a SoC is shown. (e.g.) Figure 2As shown, the SoC includes: an interconnect unit 210 coupled to an application processor 220; a system proxy unit 230; a bus controller unit 240; an integrated memory controller unit 250; a group or one or more coprocessors 260, which may include integrated graphics logic, an image processor, an audio processor, and a video processor; and a memory unit 270, wherein the memory unit may include static random access memory (SRAM) units and direct memory access (DMA) units. In one embodiment, the coprocessor 260 includes a dedicated processor, such as, for example, a network or communication processor, a compression engine, a GPGPU, a high-throughput MIC processor, or an embedded processor. The SoC may also include a scalar processor 280 and a vector processor 290.

[0055] In some embodiments, the vector processor 290 includes a floating-point multiply-accumulate unit (MAC), wherein the floating-point multiply-accumulate unit is configured to perform single-precision and / or half-precision and / or double-precision floating-point multiplication operations that do not have vector characteristics in conjunction with a scalar multiplication unit. Figure 3 The diagram shows a partial structural schematic of the scalar processor 280 and the vector processor 290 of the system-on-a-chip. The floating-point multiply-accumulate unit of the vector processor 290 does not include a vector multiplication unit. The floating-point multiply-accumulate unit of the vector processor 290 may include a third register unit, a fourth register unit and a shift unit.

[0056] The scalar processor 280 includes an integer multiply-accumulate unit (MAC), which supports SIMD functionality. The MAC includes a first register unit, a second register unit, a scalar multiplication unit, a first selection module, and a fifth register unit. The first, second, third, and fourth register units receive data to be multiplied and send the data to be multiplied to the first selection module. The first selection module includes a first selection unit and a second selection unit.

[0057] The first selection unit is used to receive data from either the first or third register unit at the same time point, and the second selection unit is used to receive data from the second and fourth register units at the same time point. When the first and second selection units receive data from the first and second register units respectively, the bus controller unit 240 can determine that the multiplication operation type of the data to be multiplied is a regular integer multiplication. When the first and second selection units receive data from the third and fourth register units respectively, the bus controller unit 240 can determine that the multiplication operation type of the data to be multiplied is an integer multiplication operation within floating-point multiplication.

[0058] The scalar multiplication unit is used to send the result of the integer operation to the shift unit in the vector processor 290 for processing when the multiplication operation type of the data to be multiplied is integer multiplication in floating-point multiplication; and to send the operation result to the fifth register unit of the scalar processor 280 when the multiplication operation type of the data to be multiplied is regular integer multiplication.

[0059] The floating-point multiplication operations mentioned in the embodiments of this application include one or more combinations of single-precision floating-point multiplication operations, half-precision floating-point multiplication operations, or double-precision floating-point multiplication operations.

[0060] The bus controller unit 240 is used to execute the execution method for multiplication operations mentioned in the embodiments of this application. For example, it controls the first selection module to obtain the data to be multiplied in the vector processor, sends the data to be multiplied in the vector processor to the scalar multiplication unit, and controls the scalar multiplication unit to perform integer multiplication operations to obtain the integer multiplication result; it also controls the scalar multiplication unit to send the integer multiplication result to the vector processor for shift operations to obtain the operation result.

[0061] Figure 3 In the on-chip system shown, the vector multiplication unit has been removed, and only the scalar multiplication unit is provided. That is, one multiplication unit is used to implement the functions of the initial two multiplication units, which is relative to... Figure 4 The system-on-chip shown includes both vector and scalar multiplication units, which effectively reduces the area occupied by the multiplication units within the system-on-chip. This results in a smaller overall system-on-chip area.

[0062] In some embodiments, the vector processor 290 includes a floating-point multiply-accumulate unit and an integer multiply-accumulate unit, wherein the floating-point multiply-accumulate unit is configured to perform single-precision and / or half-precision and / or double-precision floating-point multiplication operations with vector characteristics. The integer multiply-accumulate unit can perform integer multiplication with vector characteristics as well as conventional integer multiplication without vector characteristics.

[0063] Figure 5 The diagram shows a partial structural schematic of the scalar processor 280 and vector processor 290 of the system-on-a-chip, as follows: Figure 5 As shown, both the floating-point multiply-accumulate unit and the integer multiply-accumulate unit in the vector processor 290 may include a third register unit, a fourth register unit, a second selection module, a vector multiplication unit, and a shift unit. The second selection module includes a third selection unit and a fourth selection unit.

[0064] The scalar processor 280 includes an integer multiply-accumulate unit (MAC), which supports SIMD functionality. For example... Figure 5As shown, the integer multiply-accumulate unit in the scalar processor 280 does not have a scalar multiplication unit. The integer multiply-accumulate unit of the scalar processor 280 includes a first register unit, a second register unit, and a fifth register unit.

[0065] The first register unit, the second register unit, the third register unit, and the fourth register unit are used to receive the data to be multiplied and send the data to be multiplied to the second selection module.

[0066] The second selection module sends the data to be multiplied to the vector multiplication unit. The third selection unit receives data from either the first or third register unit at the same time, and the fourth selection unit receives data from both the second and fourth register units at the same time. When the third and fourth selection units receive data from the first and second register units respectively, the bus controller unit 240 determines that the multiplication operation type is integer multiplication. When the third and fourth selection units receive data from the third and fourth register units respectively, the bus controller unit 240 determines that the multiplication operation type is floating-point multiplication or vector multiplication.

[0067] The vector multiplication unit is used to send the result of the integer operation to the fifth register unit in the scalar processor 280 when the data to be multiplied is a regular integer operation, that is, when the data to be multiplied comes from the scalar processor; and to send the result of the operation to the shift unit or other corresponding unit in the vector processor 290 when the multiplication operation type of the data to be multiplied is an integer multiplication operation with floating-point multiplication or a vector multiplication operation with vector characteristics.

[0068] The bus controller unit 240 is used to execute the execution method for multiplication operations mentioned in the embodiments of this application. For example, it controls the second selection module to obtain the data to be multiplied in the scalar processor, sends the data to be multiplied in the scalar processor to the vector multiplication unit, controls the vector multiplication unit to perform integer multiplication operations, obtains the integer multiplication result, and controls the vector multiplication unit to send the integer multiplication result to the corresponding processing unit in the scalar processor.

[0069] The above Figure 5 In the system-on-chip shown, the scalar multiplication unit has been removed, and only the vector multiplication unit has been set up. That is, one multiplication unit is used to realize the function of the initial two multiplication units, which can effectively reduce the area occupied by the multiplication unit in the system-on-chip.

[0070] The following is in conjunction with the above. Figure 2 and Figure 3The on-chip system shown here briefly introduces the common execution method for multiplication operations provided in the embodiments of this application. Specifically, it describes the common execution method for multiplication operations in on-chip systems that do not have vector multiplication units in the embodiments of this application. Figure 6 This illustration shows a flowchart of an execution method for shared multiplication operations according to an embodiment of this application. This shared multiplication operation execution method can be implemented by a method that does not include a vector multiplication unit. Figure 2 and Figure 3 The on-chip system execution shown can, in some embodiments, also be executed by the on-chip system's bus controller unit. For example... Figure 6 As shown, the common execution methods for multiplication operations can include:

[0071] 601: Retrieve data from the vector processor to be multiplied.

[0072] It is understood that when the target configuration of the on-chip system is only to satisfy the requirement of being able to perform floating-point multiplication and integer multiplication operations that do not have vector characteristics, the on-chip system in this embodiment does not set up a vector multiplication unit in the vector processor 290, but only sets up a scalar multiplication unit in the scalar processor 280.

[0073] The multiplication operations performed in a vector processor are generally floating-point multiplication operations. When it is necessary to perform mantissa multiplication in floating-point multiplication, the data that needs to be multiplied by integers can be sent to the scalar multiplication unit in the scalar processor.

[0074] It is understandable that floating-point multiplication can include single-precision and / or half-precision and / or double-precision floating-point multiplication operations.

[0075] 602: Send the data to be multiplied in the vector processor to the scalar multiplication unit for operation and obtain the result.

[0076] It is understandable that when the multiplication operation type is floating-point multiplication in the vector processor, the data to be multiplied in the vector processor is sent to the scalar multiplication unit, the integer multiplication operation in the floating-point multiplication is performed by the scalar multiplication unit, and the operation result is sent to the shift unit or other corresponding processing unit of the vector processor 290.

[0077] For example, when performing the mantissa multiplication operation of 1.68 * 1.44 in floating-point multiplication, 1.68 and 1.44 can be sent to the scalar multiplication unit, which performs integer multiplication 168 * 144. The result 24192 is then sent to the shift unit in the vector processor 290, where the result is shifted four decimal points to the left to obtain the final result 2.4192 of 1.68 * 1.44.

[0078] 603: Send the calculation result to the corresponding processing unit in the vector processor for further processing.

[0079] It is understood that, in the embodiments of this application, after obtaining the operation result of the scalar multiplication unit, the operation result can be sent back to the vector processor for subsequent processing, for example, to the shift unit in the vector processor for subsequent processing.

[0080] It is understood that during regular integer multiplication in a scalar processor, the data to be computed can still be sent to the scalar multiplication unit, and the output of the scalar multiplication unit can be sent to the corresponding processing unit of the scalar processor 280, such as the fifth register unit, for subsequent processing. It is also understood that in some embodiments, the processing unit connected to the scalar multiplication unit can be any other hardware configuration, such as an adder unit, a comparator, etc. In this embodiment, the on-chip system can send the output of the scalar multiplication unit to the corresponding processing unit of the scalar processor 280 for subsequent processing according to computational requirements.

[0081] Based on the above scheme, when the on-chip system is configured to only be able to perform floating-point multiplication and integer multiplication operations that do not have vector characteristics, the execution method for the multiplication operations provided in this application embodiment can realize the functions of the initial two multiplication units without setting up vector multiplication units, but only setting up scalar multiplication units in the scalar processor 280.

[0082] The following is in conjunction with the above. Figure 2 and Figure 5 The on-chip system shown here briefly introduces the common execution method for multiplication operations provided in the embodiments of this application. Specifically, it describes the common execution method for multiplication operations in on-chip systems that do not have a scalar multiplication unit, as illustrated in the embodiments of this application. Figure 7 This diagram illustrates a flowchart of a common execution method for multiplication operations according to an embodiment of this application. This common execution method for multiplication operations can be executed by an on-chip system (SoC), and in some embodiments, it can also be executed by the SoC's bus controller unit 240. For example... Figure 7 As shown, the common execution methods for multiplication operations can include:

[0083] 701: Retrieves the data to be multiplied in the scalar processor.

[0084] It is understood that when the on-chip system's vector processor 290 is configured to perform floating-point multiplication and integer multiplication operations with vector characteristics, the on-chip system in this embodiment does not include a scalar multiplication unit in the vector processor 290, but only a vector multiplication unit. It is also understood that when the on-chip system's vector processor 290 is configured to perform floating-point multiplication and integer multiplication operations with vector characteristics, the vector processor 290 can also perform conventional integer floating-point multiplication and integer multiplication operations.

[0085] 702: Send the data to be multiplied to the vector multiplication unit for operation and obtain the result.

[0086] Therefore, when the data to be multiplied by integers is obtained from the scalar processor, the data to be multiplied can be sent to the vector multiplication unit, and the result of the vector multiplication unit can be sent to the corresponding processing unit in the scalar processor 280 for subsequent processing, such as the fifth register unit.

[0087] 703: Send the calculation result to the corresponding processing unit in the scalar processor 280 for further processing.

[0088] It is understood that if the multiplication operation is a floating-point multiplication or vector multiplication operation in the vector processor, the data to be multiplied is still sent to the vector multiplication unit for processing, and the result of the vector multiplication unit is sent to the subsequent processing unit of the multiplication unit in the vector processor. The subsequent processing unit can be the shift unit or other corresponding processing unit mentioned in the embodiments of this application. In the embodiments of this application, the operation result of the vector processor can be sent to the corresponding processing unit of the vector processor for corresponding processing based on the computational requirements.

[0089] Based on the above scheme, when the on-chip system is configured to perform floating-point multiplication and integer multiplication operations with vector characteristics, the execution method for the multiplication operations provided in this embodiment can realize the functions of the initial two multiplication units without setting up scalar multiplication units, but only by setting up vector multiplication units in the vector processor 290.

[0090] It is understood that the system-on-a-chip provided in the embodiments of this application can be used in various electronic devices. The system-on-a-chip can be any processor such as a central processing unit (CPU), a video processing unit (VPU), or an image signal processing unit (ISP). That is, the design method of the multiplication unit and the execution method shared by the multiplication operation can be used in any processor such as CPU, VPU, or ISP.

[0091] It is understood that the above-described system-on-a-chip in this application embodiment can be used in various electronic devices such as mobile phones, computers, and tablets. The following description uses a mobile phone 10 as an example to illustrate the electronic device provided in this application embodiment.

[0092] like Figure 8 As shown, the mobile phone 10 may include a processor 110, a power module 140, a memory 180, a mobile communication module 130, a wireless communication module 120, a sensor module 190, an audio module 150, a camera 170, an interface module 160, buttons 101, and a display screen 102, etc.

[0093] It is understood that the structures illustrated in the embodiments of the present invention do not constitute a specific limitation on the mobile phone 10. In other embodiments of this application, the mobile phone 10 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0094] Processor 110 may include one or more processing units, such as processing modules or circuits of a Central Processing Unit (CPU), Graphics Processing Unit (GPU), Digital Signal Processor (DSP), Micro-programmed Control Unit (MCU), Artificial Intelligence (AI) processor, or Field Programmable Gate Array (FPGA). Different processing units may be independent devices or integrated into one or more processors. Processor 110 may include storage units for storing instructions and data. In some embodiments, the storage unit in processor 110 is a cache memory 180.

[0095] It is understood that the processor 110 can be the system-on-a-chip mentioned in the embodiments of this application. It can be used to execute the execution method shared by the multiplication operation mentioned in the embodiments of this application.

[0096] The power module 140 may include a power supply, a power management component, etc. The power supply may be a battery. The power management component manages the charging of the power supply and the power supply to other modules. In some embodiments, the power management component includes a charging management module and a power management module. The charging management module receives charging input from a charger; the power management module connects to the power supply and the processor 110. The power management module receives input from the power supply and / or the charging management module to supply power to the processor 110, the display 102, the camera 170, and the wireless communication module 120, etc.

[0097] The mobile communication module 130 may include, but is not limited to, an antenna, a power amplifier, a filter, and an LNA (Low Noise Amplifier). The mobile communication module 130 can provide wireless communication solutions, including 2G / 3G / 4G / 5G, for use on the mobile phone 10. The mobile communication module 130 can receive electromagnetic waves via the antenna, filter and amplify the received electromagnetic waves, and then transmit them to a modem processor for demodulation. The mobile communication module 130 can also amplify the signal modulated by the modem processor and convert it into electromagnetic waves for radiation via the antenna. In some embodiments, at least some functional modules of the mobile communication module 130 may be housed in the processor 110. In some embodiments, at least some functional modules of the mobile communication module 130 and at least some modules of the processor 110 may be housed in the same device. Wireless communication technologies can include Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Time-Division Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), Bluetooth (BT), Global Navigation Satellite System (GNSS), Wireless Local Area Networks (WLAN), Near Field Communication (NFC), Frequency Modulation (FM) and / or Field Communication (NFC), Infrared (IR) technology, etc.The GNSS may include the Global Positioning System (GPS), the Global Navigation Satellite System (GLONASS), the BeiDou Navigation Satellite System (BDS), the Quasi-Zenith Satellite System (QZSS), and / or satellite-based augmentation systems (SBAS).

[0098] The wireless communication module 120 may include an antenna, which enables the transmission and reception of electromagnetic waves. The wireless communication module 120 can provide solutions for wireless communication applications on the mobile phone 10, including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared (IR) technologies. The mobile phone 10 can communicate with networks and other devices through wireless communication technologies.

[0099] In some embodiments, the mobile communication module 130 and the wireless communication module 120 of the mobile phone 10 may also be located in the same module.

[0100] The display screen 102 is used to display human-computer interaction interfaces, images, videos, etc. The display screen 102 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a Mini LED, a MicroLED, a Micro-OLED, a quantum dot light-emitting diode (QLED), etc.

[0101] The sensor module 190 may include proximity sensors, pressure sensors, gyroscope sensors, barometric pressure sensors, magnetic sensors, accelerometers, distance sensors, fingerprint sensors, temperature sensors, touch sensors, ambient light sensors, bone conduction sensors, etc.

[0102] The audio module 150 is used to convert digital audio information into analog audio signals for output, or to convert analog audio input into digital audio signals. The audio module 150 can also be used for encoding and decoding audio signals. In some embodiments, the audio module 150 may be located in the processor 110, or some functional modules of the audio module 150 may be located in the processor 110. In some embodiments, the audio module 150 may include a speaker, a handset, a microphone, and a headphone jack.

[0103] Camera 170 is used to capture still images or videos. An object passes through the lens to generate an optical image that is projected onto a photosensitive element. The photosensitive element converts the light signal into an electrical signal, which is then passed to the ISP (Image Signal Processing) to be converted into a digital image signal. Mobile phone 10 can achieve its shooting function through the ISP, camera 170, video codec, GPU (Graphics Processing Unit), display 102, and application processor.

[0104] Interface module 160 includes an external memory interface, a universal serial bus (USB) interface, and a subscriber identification module (SIM) card interface. The external memory interface can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the mobile phone 10. The external memory card communicates with the processor 110 through the external memory interface to perform data storage. The USB interface is used for communication between the mobile phone 10 and other electronic devices. The SIM card interface is used to communicate with the SIM card installed in the mobile phone 10, for example, to read or write phone numbers stored in the SIM card.

[0105] In some embodiments, the mobile phone 10 further includes buttons 101, a motor, and indicators. The buttons 101 may include volume buttons, a power button, etc. The motor is used to generate a vibration effect in the mobile phone 10, for example, vibrating when the user's mobile phone 10 is called to prompt the user to answer the call. The indicators may include laser indicators, radio frequency indicators, LED indicators, etc.

[0106] This application provides an electronic device including a scalar processor, a vector processor, and a bus control unit. The scalar processor includes a scalar multiplication unit for performing integer multiplication operations. The vector processor is configured to perform floating-point multiplication operations that do not possess vector characteristics. The bus control unit is used to execute... Figure 6 The execution method shared by the multiplication operations mentioned in the text.

[0107] This application provides an electronic device including a scalar processor, a vector processor, and a bus control unit. The vector processor includes a vector multiplication unit and is configured to perform floating-point multiplication operations with vector characteristics and integer multiplication operations with vector characteristics. The bus control unit is used to perform... Figure 7 The execution method shared by the multiplication operations mentioned in the text.

[0108] This application provides a system-on-a-chip (SoC) comprising a scalar processor, a vector processor, and a bus control unit. The scalar processor includes a scalar multiplication unit for performing integer multiplication operations. The vector processor is configured to perform floating-point multiplication operations that do not possess vector characteristics. The bus control unit is used to execute... Figure 6 The execution method shared by the multiplication operations mentioned in the text.

[0109] This application provides a system-on-a-chip (SoC) comprising a scalar processor, a vector processor, and a bus control unit. The vector processor includes a vector multiplication unit and is configured to perform floating-point multiplication operations with vector characteristics and integer multiplication operations with vector characteristics. The bus control unit is used to perform... Figure 7 The execution method shared by the multiplication operations mentioned in the text.

[0110] This application provides an electronic device, including: a memory for storing instructions executed by one or more processors of the electronic device, and a processor, which is one of the one or more processors of the electronic device, for executing the execution method for multiplication operations mentioned in the embodiments of this application.

[0111] This application provides a readable storage medium storing instructions that, when executed on an electronic device, cause the electronic device to perform the execution method for multiplication operations mentioned in this application.

[0112] This application provides a computer program product, characterized in that it includes execution instructions, which, when executed on an electronic device, cause the electronic device to execute the execution method for multiplication operations mentioned in this application.

[0113] The embodiments disclosed in this application can be implemented in hardware, software, firmware, or a combination of these implementation methods. Embodiments of this application can be implemented as computer programs or program code executable on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0114] Program code can be applied to input instructions to execute the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

[0115] The program code can be implemented using a high-level procedural language or an object-oriented programming language to communicate with the processing system. Assembly language or machine language can also be used when needed. In fact, the mechanisms described in this application are not limited to any particular programming language. In either case, the language can be a compiled language or an interpreted language.

[0116] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored thereon on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed via a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form, including but not limited to floppy disks, optical disks, CD-ROMs, magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic cards or optical cards, flash memory, or tangible machine-readable storage for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in the form of electrical, optical, acoustic, or other propagation signals. Therefore, machine-readable media include any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine-readable (e.g., computer-readable) form.

[0117] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may be omitted or may be combined with other features.

[0118] It should be noted that all units / modules mentioned in the device embodiments of this application are logical units / modules. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important factor; the combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed in this application. Furthermore, to highlight the innovative aspects of this application, the above-described device embodiments of this application have not introduced units / modules that are not closely related to solving the technical problems proposed in this application. This does not mean that the above-described device embodiments do not contain other units / modules.

[0119] It should be noted that in the examples and description of this patent, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0120] Although this application has been illustrated and described with reference to certain preferred embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made thereto without departing from the scope of this application.

Claims

1. A method for executing multiplication operations, used in electronic devices, characterized in that, The electronic device includes a scalar processor, a vector processor, and a bus control unit. The scalar processor includes a scalar multiplication unit and a first selection module. The scalar multiplication unit is used to perform integer multiplication operations. The vector processor is configured to perform floating-point multiplication operations that do not have vector characteristics. The vector processor includes a third register unit and a fourth register unit. The vector processor does not include a vector multiplication unit. The method includes: The bus control unit determines that the first selection module has received data from the third register and the fourth register to be multiplied; The bus control unit controls the first selection module to send the data to be multiplied to the scalar multiplication unit, and performs integer multiplication through the scalar multiplication unit to obtain the integer multiplication result; The bus control unit controls the scalar multiplication unit to send the integer multiplication result to the vector processor for processing to obtain the floating-point operation result.

2. The method according to claim 1, characterized in that, The vector processor includes a shift unit, an exponentiation processing unit, and a floating-point exception handling unit. Sending the integer multiplication result to the vector processor for processing to obtain the floating-point operation result includes: The integer multiplication result is sent to the shift unit for shift processing, the exponentiation processing unit performs exponentiation processing on the multiplication of the two numbers, and the floating-point exception judgment unit performs exception processing on the final floating-point result to obtain the floating-point operation result.

3. The method according to claim 1 or 2, characterized in that, The scalar processor includes a first register unit and a second register unit; the method further includes: The bus control unit determines that the first selection module has received data from the first register and the second register to be multiplied; The bus control unit controls the first selection module to send the data to be multiplied to the scalar multiplication unit, and performs integer multiplication through the scalar multiplication unit to obtain the integer multiplication result; The bus control unit controls the scalar multiplication unit to send the integer multiplication result to the processing unit in the scalar processor, and the processing unit includes a register unit.

4. The method according to claim 1 or 2, characterized in that, The floating-point multiplication operation includes half-precision floating-point multiplication, single-precision floating-point multiplication, and double-precision floating-point multiplication.

5. A method for performing multiplication operations in an electronic device, characterized in that, The electronic device includes a scalar processor, a vector processor, and a bus control unit. The vector processor includes a vector multiplication unit and a second selection module. The vector processor is configured to perform floating-point multiplication operations with vector characteristics and integer multiplication operations with vector characteristics. The scalar processor includes a first register unit and a second register unit, but does not include a scalar multiplication unit. The method includes: The bus control unit determines that the second selection module has received data from the first register and the second register to be multiplied; The bus control unit controls the second selection module to send the data to the vector multiplication unit, and performs the corresponding multiplication operation through the vector multiplication unit to obtain the multiplication result; The bus control unit controls the vector multiplication unit to send the multiplication result to the processing unit in the scalar processor.

6. The method according to claim 5, characterized in that, The processing unit includes a register unit.

7. The method according to claim 5 or 6, characterized in that, The vector processor includes a third register unit and a fourth register unit; the method further includes: The bus control unit determines that the second selection module has received data from the third register and the fourth register to be multiplied; The bus control unit controls the second selection module to send the data to be multiplied to the vector multiplication unit, and performs the corresponding operation through the vector multiplication unit to obtain the operation result; The bus control unit controls the vector multiplication unit to send the operation result to the processing unit in the vector processor, and the processing unit includes a shift unit.

8. The method according to claim 5 or 6, characterized in that, The floating-point multiplication operation includes half-precision floating-point multiplication, single-precision floating-point multiplication, and double-precision floating-point multiplication.

9. An electronic device, characterized in that, The electronic device includes a scalar processor, a vector processor, and a bus control unit. The scalar processor includes a scalar multiplication unit for performing integer multiplication operations. The vector processor is configured to perform floating-point multiplication operations that do not have vector characteristics. The bus control unit is used to execute the execution method shared by the multiplication operation as described in any one of claims 1-4.

10. An electronic device, characterized in that, The electronic device includes a scalar processor, a vector processor, and a bus control unit. The vector processor includes a vector multiplication unit and is configured to perform floating-point multiplication operations with vector characteristics and integer multiplication operations with vector characteristics. The bus control unit is used to execute the execution method for multiplication operations as described in any one of claims 5-8.

11. A system-on-a-chip, characterized in that, The system-on-a-chip includes a scalar processor, a vector processor, and a bus control unit. The scalar processor includes a scalar multiplication unit for performing integer multiplication operations. The vector processor is configured to perform floating-point multiplication operations that do not have vector characteristics. The bus control unit is used to execute the execution method shared by the multiplication operation as described in any one of claims 1-4.

12. A system-on-a-chip, characterized in that, The system-on-a-chip includes a scalar processor, a vector processor, and a bus control unit. The vector processor includes a vector multiplication unit and is configured to perform floating-point multiplication operations with vector characteristics and integer multiplication operations with vector characteristics. The bus control unit is used to execute the execution method for multiplication operations as described in any one of claims 5-8.

13. An electronic device, characterized in that, include: A memory for storing instructions executed by one or more processors of the electronic device, wherein the processor is one of one or more processors of the electronic device for executing the execution method common to multiplication operations as described in any one of claims 1 to 4 or 5 to 8.

14. A readable storage medium, characterized in that, The readable storage medium stores instructions that, when executed on an electronic device, cause the electronic device to perform the execution method common to multiplication operations as described in any one of claims 1 to 4 or 5 to 8.

15. A computer program product, characterized in that, It includes execution instructions, which, when executed on an electronic device, cause the electronic device to perform the execution method common to multiplication operations as described in any one of claims 1 to 4 or 5 to 8.

Images