Memory co-management system and method

Abstract

The application provides a memory cooperative management system and method, physical storage spaces and virtual storage spaces are allocated on a memory, and are respectively divided into a plurality of physical storage units and a plurality of virtual storage units, wherein the size of each virtual storage unit is set as the maximum allowed packet length size. An address conversion table is constructed to store the corresponding relationship between the pointers of each physical storage unit and the pointers of each virtual storage unit, so as to realize the mapping conversion of both. In the scheme, the mapping of the virtual storage unit and the physical storage unit is realized by an address conversion controller, the splicing of the physical storage unit is realized by a hardware device, the CPU only needs to face the virtual storage unit, and the virtual storage unit set as the maximum allowed packet length size can meet the requirement of storing a complete packet. In this way, the memory management is released from the CPU, and the utilization rate of the storage space can be improved.

Description

Technical Field

[0001] This invention relates to the field of memory management technology, and more specifically, to a memory co-management system and method. Background Technology

[0002] The development of embedded technology places increasingly higher demands on data processing capabilities, leading to a significant increase in data interaction between on-chip CPUs (Central Processing Units) and other dedicated data processing units or peripherals. This data interaction is primarily implemented using Direct Memory Access (DMA). To further improve the overall system processing efficiency, DMA and the CPU should strive for zero-copy data exchange. This means that data written to memory by DMA can be directly read and written by the CPU at its address without needing to be copied to other addresses; conversely, data modified by the CPU can also be directly read by DMA at its address. A crucial operation in DMA is descriptor handling. The descriptor is a fundamental piece of information exchanged between the DMA controller and the CPU. When the CPU receives data, it requests the DMA to write the data to memory and update the information in the descriptor, including data type and length, to facilitate the CPU's subsequent reading and processing of the received data. When the CPU sends data, it requests the CPU to write the data to memory and mark the starting position and size of the data in memory in the descriptor. Then, the DMA controller reads the descriptor, uses this information to retrieve the data from memory, and sends it out. Throughout this process, the memory management mechanism significantly impacts the overall system processing efficiency. Because CPU processing is more complex and time-consuming than hardware logic processing, CPU processing efficiency is lower than hardware processing efficiency. Therefore, the less the CPU is involved in memory management, the higher the overall system processing efficiency, and vice versa. Thus, in the data interaction process described above, improving memory management efficiency is a crucial means of improving overall system processing efficiency.

[0003] In existing technologies, memory management is typically implemented in software, with the CPU handling the allocation and release of memory units. Current methods generally divide memory units into smaller, granular units. However, the data length of an Ethernet packet is variable, and the pre-allocated memory unit size may not be sufficient to store a complete Ethernet packet. In this case, the CPU needs to add extra processing logic based on information from the received descriptors to concatenate the data from multiple memory units into a single complete Ethernet packet before it can be processed correctly, consuming significant CPU processing time. Conversely, setting memory units according to the maximum packet length may lead to wasted storage resources.

[0004] Furthermore, existing technologies also employ methods that divide storage units into different sizes. In this approach, each storage unit has a fixed size and only a limited number of options are available. To add more options, more storage space must be allocated during initialization, significantly increasing the logical complexity of the chip design. Moreover, message lengths are random within a short period, making it impossible to accurately allocate the number and proportion of storage units of various sizes during system initialization. This can lead to situations where some storage units are exhausted while others remain largely unused, thus failing to improve storage space utilization. Summary of the Invention

[0005] This invention provides a memory co-management system and method that can free memory management from the CPU and significantly improve the utilization of storage space.

[0006] The embodiments of the present invention can be implemented as follows:

[0007] In a first aspect, the present invention provides a memory collaborative management system, including a CPU, a DMA, an address translation controller, and a memory, wherein the CPU and the DMA are interconnected and respectively connected to the address translation controller, and the address translation controller is connected to the memory via a system bus;

[0008] Physical storage space and virtual storage space are allocated on the memory. The physical storage space includes multiple physical storage units, and the virtual storage space includes multiple virtual storage units. The number of physical storage units and virtual storage units is the same, and the size of each virtual storage unit is set to the maximum allowed message length.

[0009] An address translation table is constructed in the address translation controller. The address translation table stores the correspondence between each physical memory unit pointer and each virtual memory unit pointer, so as to realize the mapping transformation between physical memory unit pointers and virtual memory unit pointers.

[0010] The CPU is used to read existing messages from the memory or write messages to be sent into the memory based on the obtained virtual memory unit pointer.

[0011] The DMA is used to write the received message into the corresponding physical storage unit or send the message already written into the corresponding physical storage unit based on the obtained physical storage unit pointer, and to release the physical storage unit after the message in the physical storage unit has been read or sent.

[0012] In an optional implementation, when receiving a message, the DMA is used to obtain the physical storage unit pointer required for the message to be received, and write the received message into the physical storage unit corresponding to the physical storage unit pointer, and write the virtual storage unit pointer corresponding to the physical storage unit pointer into the descriptor.

[0013] The CPU is used to read the descriptor to obtain the virtual memory unit pointer after detecting that the message reception is complete, obtain the physical memory unit pointer corresponding to the virtual memory unit pointer by looking up the address translation table, and read the written message from the physical memory unit corresponding to the physical memory unit pointer.

[0014] In an optional implementation, when receiving a message, the CPU is further configured to modify the flag bit in the descriptor after the message is read to notify that the DMA message has been read.

[0015] The DMA is also used to look up the address translation table based on the virtual memory cell pointer in the descriptor to obtain the physical memory cell pointer corresponding to the virtual memory cell pointer, and to release the physical memory cell corresponding to the physical memory cell pointer.

[0016] In an optional implementation, if the CPU is further used to edit the read message after it has finished reading the message, then the flag bit in the descriptor of the edited message is updated after the editing is completed to notify the DMA.

[0017] The DMA is also used to read the edited message according to the information in the descriptor, and after sending the edited message, to release the physical storage unit occupied by the edited message.

[0018] In an optional implementation, the physical memory cell pointers and virtual memory cell pointers that have a corresponding relationship have the same pointer number;

[0019] The DMA is used to write the physical storage unit pointers of the messages to the corresponding pointer numbers in the address translation table in sequence after the message reception is completed.

[0020] After reading the descriptor to obtain the virtual memory unit pointer, the CPU uses the address translation controller to subtract the base address of the virtual memory unit from the virtual memory unit pointer to obtain the pointer number, and then looks up the address translation table according to the pointer number to obtain the corresponding physical memory unit pointer.

[0021] In an optional implementation, when sending a message, the CPU, after completing the editing of the message to be sent, obtains the virtual memory unit pointer corresponding to the first physical memory unit pointer of the physical memory unit storing the message to be sent through the address translation controller.

[0022] The CPU is also used to write the message to be sent to the physical storage unit pointed to by the physical storage unit pointer corresponding to the acquired virtual storage unit pointer, and to write the virtual storage unit pointer to the descriptor to notify the DMA to complete the message writing;

[0023] The DMA is used to obtain the corresponding physical storage unit pointer according to the virtual storage unit pointer in the descriptor after detecting that there is a message to be sent, read the message to be sent from the physical storage unit pointed to by the physical storage unit pointer, and then send it.

[0024] In an optional implementation, the physical memory cell pointers and virtual memory cell pointers that have a corresponding relationship have the same pointer number;

[0025] The CPU, after obtaining the virtual memory unit pointer corresponding to the first physical memory unit pointer through the address translation controller, sequentially writes all physical memory unit pointers storing the physical memory unit to be sent into the corresponding pointer number in the address translation table.

[0026] The CPU is used to obtain a pointer number by subtracting its base address from the obtained virtual memory unit pointer, and to look up the address translation table based on the pointer number to obtain the corresponding physical memory unit pointer, and to write the message to be sent into the corresponding physical memory unit according to the order of the physical memory unit pointers.

[0027] The DMA is used to obtain a pointer number by subtracting the base address from the virtual memory cell pointer in the acquired descriptor, and to obtain a physical memory cell pointer by looking up the address translation table based on the pointer number. Then, it reads the message to be sent in sequence according to the physical memory cell pointer and sends it.

[0028] In an optional implementation, there is a one-to-one correspondence between the physical storage unit pointer and the virtual storage unit pointer.

[0029] In an optional implementation, all physical storage units are the same size, and all virtual storage units are the same size.

[0030] Secondly, the present invention provides a memory collaborative management method applied to the memory collaborative management system described in any one of the foregoing embodiments. The system includes a CPU, a DMA, an address translation controller, and a memory. The CPU and DMA are interconnected and respectively connected to the address translation controller. The address translation controller is connected to the memory via a system bus. The method includes:

[0031] Physical storage space and virtual storage space are allocated on the memory. The physical storage space includes multiple physical storage units, and the virtual storage space includes multiple virtual storage units. The number of physical storage units and virtual storage units is the same, and the size of each virtual storage unit is set to the maximum allowed message length.

[0032] An address translation table is constructed in the address translation controller. The address translation table stores the correspondence between each physical memory unit pointer and each virtual memory unit pointer, so as to realize the mapping transformation between physical memory unit pointers and virtual memory unit pointers.

[0033] The CPU reads existing messages from the memory or writes messages to be sent into the memory based on the obtained virtual memory unit pointer.

[0034] The DMA writes the received message to the corresponding physical storage unit or sends the message already written in the corresponding physical storage unit based on the obtained physical storage unit pointer, and releases the physical storage unit after all the messages in the physical storage unit have been read or sent.

[0035] The beneficial effects of the embodiments of the present invention include, for example:

[0036] This application provides a memory cooperative management system and method. Based on a traditional architecture, an address translation controller is added, and physical and virtual memory spaces are allocated on the memory, each divided into multiple physical memory units and multiple virtual memory units. The size of each virtual memory unit is set to the maximum allowed packet length. An address translation table is constructed in the address translation controller to store the correspondence between pointers to each physical memory unit and pointers to each virtual memory unit, enabling mapping and transformation between the two. The CPU can read and write packets based on the virtual memory unit pointers, while the DMA can write or send packets based on the physical memory unit pointers and release physical memory units.

[0037] In this solution, the mapping between virtual and physical storage units is achieved through an address translation controller. The splicing of physical storage units is implemented by hardware devices. The CPU only needs to interact with the virtual storage units, and the virtual storage units are set to a maximum allowed message length that can meet the requirement of storing a complete message. In this way, memory management is freed from the CPU, and the utilization rate of storage space is greatly improved. Attached Figure Description

[0038] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is one of the structural diagrams of a memory co-management system in the prior art;

[0040] Figure 2 This is the second schematic diagram of the structure of a memory collaborative management system in the prior art;

[0041] Figure 3 This is a schematic diagram of the structure of the memory collaborative management system provided in the embodiments of this application;

[0042] Figure 4 A schematic diagram of the physical storage space and virtual storage space provided in the embodiments of this application;

[0043] Figure 5 A flowchart of the memory collaborative management method provided in the embodiments of this application. Detailed Implementation

[0044] In existing technologies, there are two main processing methods to improve overall system processing efficiency. In the first method, memory management is implemented in software, with the CPU managing the entire memory. For example... Figure 1 As shown, the CPU includes a Memory Management Unit (MMU) which manages the entire memory space. The CPU pre-allocates multiple memory units (BUFs) in memory, and their physical addresses can be contiguous or non-contiguous. When the physical addresses are non-contiguous, the CPU's MMU can logically process them into logically contiguous addresses.

[0045] When the CPU receives data, it configures the available BufPtr (memory pointer) into the descriptor to be used by the DMA. Upon receiving data, the DMA controller writes the received data into the designated BUF according to the BufPtr in the descriptor. If the received data is large and the storage space in the descriptor is insufficient (i.e., the BUF size is insufficient to store the entire received data), the DMA controller needs to acquire more descriptors and BUFs to continue storing the data. When the DMA controller completes data reception, it updates the information in the descriptor, including the data type and the actual size of the received data, and finally notifies the CPU. The CPU then processes the received data according to the information in the descriptor and releases the occupied Buf after processing.

[0046] When the CPU sends data, it needs to acquire an available BufPtr, write the data to be sent into that Buf, and then inform the DMA controller of the data size and the corresponding BufPtr through the descriptor. The DMA controller reads the data to be sent from memory according to the BufPtr and other information in the descriptor, sends it to the designated target device, and finally updates the descriptor status and notifies the CPU. Once the CPU detects that the DMA operation is complete, it releases the occupied Buf.

[0047] like Figure 1 As shown, both the DMA controller and the CPU are connected to the memory via a bus. The CPU controls the address allocation of the entire memory, while the DMA controller operates on the CPU's instructions to read and write data in the memory.

[0048] In this approach, the CPU typically has an MMU and an IOMMU to manage memory. When initializing the BUF, it can be set at a finer granularity (such as 1KB size) and physically discontinuous addresses can be converted into logically contiguous addresses to facilitate cache coherency processing (cache coherency can improve the overall system performance).

[0049] However, as described above, during the data interaction between the CPU and the DMA controller, the allocation and release of buffers are handled by the CPU, consuming a significant amount of CPU time and resulting in low overall processing efficiency. When receiving data similar to Ethernet packets, because the length of an Ethernet packet is uncertain (generally a minimum of 64 bytes and a maximum of 16KB), the pre-allocated buffer size may not be sufficient to store a complete Ethernet packet. In this case, multiple descriptors and multiple buffers (each descriptor can only contain one buffer) must be used. The CPU is then required to add extra processing logic based on the information in the received descriptors to concatenate the data from multiple buffers into a complete Ethernet packet before it can be processed normally. This operation also consumes a significant amount of CPU time. If the CPU could guarantee that each buffer could store a complete Ethernet packet, it must be set according to the maximum packet length (i.e., 16KB). This means that even if a smaller packet is received, the entire 16KB buffer will still be used (because a buffer can only store a maximum of one packet). In real-world environments, the average length of an Ethernet packet is mostly between 1KB and 2KB. Therefore, setting the BUF size according to the maximum message length will inevitably waste a lot of memory resources.

[0050] In addition, in the second processing method, such as Figure 2 The diagram shows the addition of a memory management module, whose hardware logic manages the memory. During system initialization, the CPU first allocates a memory space for data reception and transmission, and this memory space is fixed to be managed only by the memory management module; other processing on the CPU cannot occupy it. This memory space is then divided into multiple BUFs of different sizes, such as 1KB, 2KB, 4KB, and 16KB, and their BufPtrs are grouped into multiple BPPs according to size. For example, BPP1 stores the BufPtr of a 1KB BUF, BPP2 stores the BufPtr of a 2KB BUF, BPP3 stores the BufPtr of a 4KB BUF, and BPP4 stores the BufPtr of a 16KB BUF.

[0051] When receiving data, the CPU only configures other fields in the descriptor; it no longer needs to actively acquire an available BufPtr and write it to the descriptor. When the DMA controller receives data, it selects a suitable BufPtr from the four BPPs based on the length of the received data via the memory management module. The received data is then written to the corresponding BUF of the BufPtr before updating the information in the descriptor (including the BufPtr and the actual length of the written data). Once the CPU detects that data reception is complete, it reads the descriptor and retrieves the specific data based on the BufPtr and other information. After processing the data, the CPU only needs to update the descriptor and notify the DMA controller; it no longer needs to actively release the BUF. Once the DMA controller detects that the CPU has finished processing, it completes the message reception process and releases the occupied BUF via the memory management module, writing the BufPtr back to the original BPP.

[0052] When sending data, the CPU needs to select a suitable BufPtr from the four BPPs (Block Pages) based on the length of the data to be sent (implemented by the memory management module), write the data to be sent into the corresponding BUF, update the descriptor information (including the BufPtr and the actual length of the data to be sent), and notify the DMA controller. The DMA controller then reads the data to be sent from the corresponding BUF based on the BufPtr and other information in the descriptor, completing the data transmission process. The DMA controller then updates its status, notifies the CPU, and automatically releases the BUF (i.e., rewrites the BufPtr into the original BPP) through the memory management module. At this point, the CPU no longer needs to perform the BUF release operation.

[0053] In this approach, the memory management module configures the DMA controller to complete the allocation and release of BUF, eliminating the CPU's processing steps, reducing CPU time usage, and improving the overall system processing efficiency.

[0054] However, in this approach, the size of each BUF is fixed, and only a limited number of options can be set (such as 1KB, 2KB, 4KB, and 16KB in the example above). To set more options, more storage space must be allocated during initialization, significantly increasing the logical complexity of the chip design. In real-world applications, while Ethernet packet lengths generally follow a proportional relationship in the long term, packet lengths are random in the short term. Therefore, it's impossible to accurately allocate the number and proportion of BUFs of different sizes during system initialization. This can lead to situations where some BUFs are exhausted while others remain largely unused, thus hindering efficient storage space utilization.

[0055] Based on the above research findings, existing processing methods all have many shortcomings. Therefore, this application provides a memory collaborative management scheme. In this scheme, an address translation controller is used to map virtual memory units to physical memory units. The splicing of physical memory units is implemented by hardware devices. The CPU only needs to interact with the virtual memory units, and the virtual memory units are set to a maximum allowed message length that can meet the requirement of storing a complete message. In this way, memory management is freed from the CPU, and the utilization rate of storage space is significantly improved.

[0056] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0057] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0058] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0059] It should be noted that, where there is no conflict, the features in the embodiments of the present invention can be combined with each other.

[0060] Please see Figure 3 The present application provides a memory collaborative management system, which includes a CPU, a DMA, an address translation controller, and a memory. The CPU and DMA are interconnected, and the CPU and DMA are respectively connected to the address translation controller, which is connected to the memory through a system bus.

[0061] Furthermore, in this embodiment, the memory co-management system also includes a memory management module connected between the CPU and the DMA. The memory management module can be used to manage the cell pointers of memory units.

[0062] In this embodiment, physical storage space and virtual storage space are allocated on the memory. The physical storage space includes multiple physical storage units, and the virtual storage space includes multiple virtual storage units. The number of physical storage units and virtual storage units is the same, and the size of each virtual storage unit is set to the maximum allowed message length. All physical storage units and all virtual storage units have the same size.

[0063] During system initialization, a large block of physical memory space, either contiguous or non-contiguous, is allocated in the memory. This physical memory space serves as the data storage space for the CPU and DMA, and other operations cannot occupy this address space. Correspondingly, a segment of virtual memory space is allocated at addresses visible to the CPU. This virtual memory space is visible to the CPU and can be read and written normally, but it is actually a virtual address space.

[0064] Taking Ethernet packet processing as an example, a contiguous 1MB physical address storage space can be initialized as physical storage space, denoted as storage space A. This physical storage space is then divided into 1K physical storage units (1KB * 1K = 1MB) of fixed size. The pointers to these 1K physical storage units are then written to the BPP (Browser Buffer Pointer) of the memory management module.

[0065] In addition, a virtual memory space, denoted as memory space B, is defined that is operable by the CPU. The size of the virtual memory space is larger than the size of the physical memory space. Furthermore, each virtual memory unit in the virtual memory space is guaranteed to be large enough to store a data segment of the maximum length. Taking Ethernet packet data as an example, the maximum packet data length is 16KB; therefore, the size of the virtual memory unit can be set to 16KB.

[0066] Each physical storage unit in the physical storage space has a corresponding virtual storage unit in the virtual storage space. In the example above, the virtual storage space should also contain 1K virtual storage units, and each virtual storage unit is 16KB in size, meaning the virtual storage space should be set to 16 times the size of the physical storage space.

[0067] The physical storage space sizes in the examples above are merely illustrative and are not limited in this embodiment. The specific size needs to be set according to the actual size of the system memory and the requirements of the specific application. For example, the physical storage space size is generally several hundred MB or more.

[0068] Furthermore, the size of each physical storage space is not limited to this and can be determined according to the specific application requirements. The smaller the granularity, the more storage unit pointers it manages and the more complex the logic, and vice versa.

[0069] The virtual storage space is divided into 16KB virtual storage units based on the fact that Ethernet packets typically do not exceed 16KB. The specific setting only needs to meet the maximum packet length requirement. The total size of the virtual storage space is determined by the granularity of the virtual and physical storage space division: Virtual storage space size = (Virtual storage space granularity / Physical storage space granularity) * Physical storage space size.

[0070] In this embodiment, although the virtual memory space is virtual, it occupies the actual address space accessible by the CPU. Most current CPUs support 64-bit address spaces, so although the virtual memory space is relatively large, it has virtually no impact on the CPU design.

[0071] In the examples above, the physical storage space is physically contiguous, but in actual use, it can be set to be non-contiguous. In this case, the memory co-management system also includes a memory management unit (MMU), which can convert the non-contiguous physical storage space into a contiguous address space before configuring it to correspond with the virtual storage space.

[0072] In this embodiment, an address translation table is constructed in the address translation controller. The address translation table stores the correspondence between each physical memory unit pointer and each virtual memory unit pointer, so as to realize the mapping transformation between physical memory unit pointers and virtual memory unit pointers.

[0073] Specifically, there is a one-to-one correspondence between virtual memory unit pointers and physical memory unit pointers. Each virtual memory unit pointer is then numbered and named the pointer number BUF_ID. Because the addresses of the current virtual memory space are contiguous, the virtual memory unit pointer and the pointer number are actually the same. The pointer number plus the base address of the virtual memory unit equals the virtual memory unit pointer. That is, the pointer number and the physical memory unit pointer also have a one-to-one correspondence. The address translation table uses the pointer number as an index to implement read and write operations.

[0074] In this embodiment, the memory collaborative management process mainly involves the data receiving process and the data sending process. Based on the above settings, the CPU can be used to read messages already stored in memory or write messages to be sent into memory based on the obtained virtual memory unit pointer.

[0075] DMA can be used to write received messages into the corresponding physical storage unit or send messages already written into the corresponding physical storage unit based on the obtained physical storage unit pointer, and release the physical storage unit after all messages in the physical storage unit have been read or sent.

[0076] In this solution, the mapping between virtual and physical storage units is achieved through an address translation controller. The splicing of physical storage units is implemented by hardware devices. The CPU only needs to interact with the virtual storage units, and the virtual storage units are set to a maximum allowed message length that can meet the requirement of storing a complete message. In this way, memory management is freed from the CPU, and the utilization rate of storage space is greatly improved.

[0077] The address translation settings in this embodiment will be described below first. In this embodiment, as... Figure 4 In the left-hand box, the physical storage units in the physical storage space can be named BUF_A, and there are a total of N units (the specific value of N depends on the actual application requirements, such as 1K in the example above). Each virtual storage unit in the virtual storage space can be named BUF_B, and there are also N units, such as... Figure 4 As shown in the right-hand box. Each BUF_B corresponds to one or more BUF_A, and the first BUF_A is the BUF_A in the physical storage space on the left side of the diagram. The BUF_A contained in each BUF_B are selected sequentially from the BPP by the memory management module, starting from the second one. The number of BUF_A contained in each BUF_B is determined by the actual size of the received or transmitted data. For example, when the DMA receives a 4KB Ethernet packet, the corresponding BUF_B should contain 4 BUF_A.

[0078] Based on the above, when receiving a message, DMA can be used to obtain the physical storage unit pointer required for the message to be received, write the received message into the physical storage unit corresponding to the physical storage unit pointer, and write the virtual storage unit pointer corresponding to the physical storage unit pointer into the descriptor.

[0079] The CPU can use this function to read the descriptor to obtain the virtual memory unit pointer after detecting that the message has been received, obtain the physical memory unit pointer corresponding to the virtual memory unit pointer by looking up the address translation table, and read the written message from the physical memory unit corresponding to the physical memory unit pointer.

[0080] As can be seen from the above, in this embodiment, the physical storage unit pointers and virtual storage unit pointers that have a corresponding relationship have the same pointer number.

[0081] DMA is used to write the physical storage unit pointers of the message to the corresponding pointer numbers in the address translation table in sequence after the message has been received.

[0082] Specifically, during message reception, the DMA terminates the current message reception operation after message reception is complete, for example, upon receiving the message end flag. The DMA sequentially writes the BufPtr_A (physical memory pointer) of the message to the corresponding BUF_ID (pointer number) position in the address translation table. That is, the BUF_ID corresponding to the written BufPtr_A can be used as an index to find the corresponding position in the address translation table, and writing BufPtr_A to the corresponding position indicates that the actual physical address of the BufPtr_B (virtual memory pointer) currently written to the descriptor is the BufPtr_A written to the address translation table.

[0083] When a single BUF_A is insufficient to store the entire received message, the DMA needs to obtain multiple BufPtr_A entries from the BPP and write the received message into the corresponding BUF_A. When writing the BufPtr_A entries into the address translation table, they are written sequentially according to the order of the multiple BUF_A entries, thus recording the order information of the multiple BufPtr_A entries to indicate that multiple BUF_A entries are currently in use.

[0084] The CPU can use the address translation controller to subtract the base address of the virtual memory unit from the virtual memory unit pointer after reading the descriptor to obtain the pointer number, and then look up the address translation table according to the pointer number to obtain the corresponding physical memory unit pointer.

[0085] Specifically, during message reception, when the CPU detects that message reception is complete, it obtains BufPtr_B by reading the descriptor information and initiates a message read request based on BufPtr_B. This message read request is processed by the address translation controller. First, it subtracts the base address of Buf_B from BufPtr_B to obtain BUF_ID. Then, it indexes the corresponding position in the address translation table according to BUF_ID to find all the BufPtr_A used to actually store the message data, along with their order information. Finally, the message read request is transformed into sequentially reading these BufPtr_A to obtain the received message data.

[0086] Although these BufPtr_A addresses may be physically discontinuous, the CPU operates on BufPtr_B. Therefore, for the CPU, it is still operating on a large, contiguous address space, and all cache coherency processing corresponding to the address can proceed normally without being affected.

[0087] Building upon the above, during message reception, the CPU also modifies flags in the descriptor after message reading is complete to notify the DMA that message reading is finished. The DMA also uses the virtual memory unit pointer in the descriptor to look up the corresponding physical memory unit pointer in the address translation table, and then releases the physical memory unit corresponding to the virtual memory unit pointer.

[0088] Specifically, after obtaining the descriptor updated by the CPU, the DMA calculates the BUF_ID based on the BufPtr_B in the descriptor through hardware logic, and indexes the corresponding position in the address translation table according to the BUF_ID to obtain the actual BufPtr_A occupied, and writes these BufPtr_A into the BPP for subsequent operation, that is, releases the BUF_A pointed to by BufPtr_A.

[0089] Furthermore, during message transmission, the CPU, after editing the message to be sent, obtains the virtual memory pointer corresponding to the first physical memory pointer of the physical memory unit storing the message through the address translation controller. The CPU also writes the message to be sent to the physical memory unit pointed to by the obtained virtual memory pointer, and writes the virtual memory pointer to the descriptor, completing the message writing process via DMA.

[0090] DMA is used to obtain the corresponding physical memory cell pointer based on the virtual memory cell pointer in the descriptor after detecting a message to be sent, read the message to be sent from the physical memory cell pointed to by the physical memory cell pointer, and then send it.

[0091] In the process described above where the CPU writes the message to be sent into the corresponding physical memory unit, the CPU, after obtaining the virtual memory unit pointer corresponding to the first physical memory unit pointer through the address translation controller, sequentially writes all the physical memory unit pointers storing the message to be sent into the corresponding pointer numbers in the address translation table. The CPU then uses the obtained virtual memory unit pointer minus its base address to obtain the pointer number, looks up the corresponding physical memory unit pointer in the address translation table based on the pointer number, and writes the message to be sent into the corresponding physical memory unit according to the order of the physical memory unit pointers.

[0092] In the process of DMA reading and sending the message to be sent, DMA obtains the pointer number by subtracting the base address from the virtual memory cell pointer in the obtained descriptor, and obtains the physical memory cell pointer by looking up the address translation table based on the pointer number. Then, it reads the message to be sent in sequence according to the physical memory cell pointer and sends it.

[0093] Specifically, during message transmission, the CPU first completes the editing of the message to be sent, and then sends an instruction to obtain sufficient physical memory units from the BPP to store the message data. After receiving the instruction, the address translation controller obtains one or more BufPtr_A according to the size of the physical memory units required by the CPU, sends the BufPtr_B corresponding to the first BufPtr_A to the CPU, and writes all BufPtr_A into the corresponding positions in the address translation table indexed by BUF_ID, while also recording their usage order.

[0094] The CPU performs a write operation based on the received BufPtr_B, writing the data of the message to be sent into memory. This write operation request is also first processed by the address translation controller. The BUF_ID is calculated based on BufPtr_B, then the corresponding position in the address translation table is located using the BUF_ID, and the corresponding BufPtr_A is sequentially swapped in, and the data of the message to be sent is written sequentially. After completing the write operation, the CPU writes BufPtr_B and other information of the message to be sent into the descriptor and notifies the DMA.

[0095] After the DMA detects a message to be sent, it initiates a read operation based on the BufPtr_B in the descriptor. This read request is first processed by the address translation controller, which retrieves all ButPtr_A and their order relationships from the virtual address translation table based on BufPtr_B. Then, the message data to be sent is actually read sequentially from memory and finally sent to the designated target device.

[0096] In addition, after the DMA finishes sending the message data, it releases the BufPtr_A it occupied, that is, writes it into BPP for use in subsequent operations.

[0097] In the process of memory collaborative management, in addition to the message receiving and sending processes mentioned above, a message forwarding process is also involved. The message forwarding process is essentially the process where, after message reception is completed, the CPU re-edits the message and then sends the re-edited message.

[0098] During message forwarding, the message receiving process is as described above and will not be repeated here. Based on this, if the CPU edits the message after reading it, it updates the flag bits in the descriptor of the edited message to notify the DMA. The DMA also reads the edited message based on the information in the descriptor, sends the edited message, and then releases the physical storage space occupied by the edited message.

[0099] Specifically, during message forwarding, the BUF cannot be released even after the received message data processing is complete. When the CPU needs to update the descriptor, it should indicate whether the BUF needs to be released. If it's normal processing, the hardware's BUF management logic needs to release the BUF according to the description information in the descriptor during the message receiving process. Otherwise, the BUF release process is not executed.

[0100] After the CPU finishes editing, it directly updates the message descriptor to notify the DMA to complete the message sending process and completes the BUF release operation normally.

[0101] Throughout this process, from the moment a message is received to its eventual retransmission, the buffer (BUF) remains occupied. This ensures that the message's storage location remains unchanged, reducing the CPU's need to copy message data; the message logic can be completed within its original location. This reduced CPU activity improves overall message forwarding efficiency.

[0102] The memory collaborative management scheme provided in this embodiment manages storage space through hardware logic, eliminating the need for the CPU to allocate and release storage units. It utilizes an address translation table in the address translation controller to handle address translation processes during DMA and CPU access. In the CPU-facing virtual storage space, each virtual storage unit is a relatively large unit capable of holding the maximum allowed data length. Even if physical addresses are not contiguous, multiple smaller physical storage units can be combined using the address translation table to accommodate large-scale storage needs. For the CPU, the resulting virtual storage unit represents a complete, contiguous address space. The CPU is unaware of the actual physical organization and therefore does not affect any operations performed on it, including read / write access and cache coherency handling. This effectively frees storage management from the CPU and improves storage space utilization.

[0103] Please see Figure 5 The memory collaborative management method provided in this application embodiment is implemented by the aforementioned memory collaborative management system and includes the following steps:

[0104] S101, allocate physical storage space and virtual storage space on the memory. The physical storage space includes multiple physical storage units, and the virtual storage space includes multiple virtual storage units. The number of physical storage units and virtual storage units is the same, and the size of each virtual storage unit is set to the maximum allowed message length.

[0105] S102, an address translation table is constructed in the address translation controller. The address translation table stores the correspondence between each physical memory unit pointer and each virtual memory unit pointer, so as to realize the mapping transformation between physical memory unit pointers and virtual memory unit pointers.

[0106] S103, the CPU reads the messages already stored in the memory or writes messages to be sent into the memory based on the obtained virtual memory unit pointer.

[0107] S104, the DMA writes the received message into the corresponding physical storage unit or sends the message already written into the corresponding physical storage unit based on the obtained physical storage unit pointer, and releases the physical storage unit after the message in the physical storage unit has been read or sent.

[0108] The memory collaborative management method provided in this embodiment can map virtual memory units and physical memory units through an address translation controller. The splicing of physical memory units is implemented by hardware devices. The CPU only needs to face the virtual memory units, and the virtual memory units are set to a maximum allowed packet length that can meet the requirement of storing a complete packet. In this way, memory management is freed from the CPU, and the utilization rate of storage space can be greatly improved.

[0109] It should be noted that the memory collaborative management method provided in this embodiment is implemented by the aforementioned memory collaborative management system and has the same or similar technical effects as the aforementioned memory collaborative management system. For any aspects not detailed in this embodiment, please refer to the corresponding parts in the above embodiments; these will not be repeated here.

[0110] In summary, the memory collaborative management system and method provided in this application add an address translation controller to the traditional architecture, and allocate physical and virtual storage space on the memory, dividing it into multiple physical storage units and multiple virtual storage units respectively. The size of each virtual storage unit is set to the maximum allowed packet length. An address translation table is constructed in the address translation controller to store the correspondence between pointers to each physical storage unit and pointers to each virtual storage unit, thereby realizing the mapping transformation between the two. The CPU can read and write packets based on the virtual storage unit pointers, while the DMA can write or send packets based on the physical storage unit pointers and release physical storage units.

[0111] In this solution, the mapping between virtual and physical storage units is achieved through an address translation controller. The splicing of physical storage units is implemented by hardware devices. The CPU only needs to interact with the virtual storage units, and the virtual storage units are set to a maximum allowed message length that can meet the requirement of storing a complete message. In this way, memory management is freed from the CPU, and the utilization rate of storage space is greatly improved.

[0112] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A memory collaborative management system, characterized in that, It includes a CPU, a DMA, an address translation controller, and a memory. The CPU and DMA are interconnected and are each connected to the address translation controller. The address translation controller is connected to the memory via a system bus. Physical storage space and virtual storage space are allocated on the memory. The physical storage space includes multiple physical storage units, and the virtual storage space includes multiple virtual storage units. The number of physical storage units and virtual storage units is the same, and the size of each virtual storage unit is set to the maximum allowed message length. An address translation table is constructed in the address translation controller. The address translation table stores the correspondence between each physical memory unit pointer and each virtual memory unit pointer, so as to realize the mapping transformation between physical memory unit pointers and virtual memory unit pointers. The CPU is used to read existing messages from the memory or write messages to be sent into the memory based on the obtained virtual memory unit pointer. The DMA is used to write the received message into the corresponding physical storage unit or send the message already written into the corresponding physical storage unit based on the obtained physical storage unit pointer, and to release the physical storage unit after the message in the physical storage unit has been read or sent. When receiving a message, the DMA is used to obtain the physical storage unit pointer required for the message to be received, write the received message into the physical storage unit corresponding to the physical storage unit pointer, and write the virtual storage unit pointer corresponding to the physical storage unit pointer into the descriptor. The CPU is used to read the descriptor to obtain the virtual memory unit pointer after detecting that the message reception is complete, obtain the physical memory unit pointer corresponding to the virtual memory unit pointer by looking up the address translation table, and read the written message from the physical memory unit corresponding to the physical memory unit pointer.

2. The memory collaborative management system according to claim 1, characterized in that, When receiving a message, the CPU is also used to modify the flag bits in the descriptor after the message is read to notify that the DMA message has been read. The DMA is also used to look up the address translation table based on the virtual memory cell pointer in the descriptor to obtain the physical memory cell pointer corresponding to the virtual memory cell pointer, and to release the physical memory cell corresponding to the physical memory cell pointer.

3. The memory collaborative management system according to claim 2, characterized in that, If, after the CPU has finished reading the message, the CPU is also used to edit the read message, then after the editing is completed, the flag bit in the descriptor of the edited message is updated to notify the DMA; The DMA is also used to read the edited message according to the information in the descriptor, and after sending the edited message, to release the physical storage unit occupied by the edited message.

4. The memory collaborative management system according to claim 1, characterized in that, Physical memory unit pointers and virtual memory unit pointers that have a corresponding relationship have the same pointer number; The DMA is used to write the physical storage unit pointers of the messages to the corresponding pointer numbers in the address translation table in sequence after the message reception is completed. After reading the descriptor to obtain the virtual memory unit pointer, the CPU uses the address translation controller to subtract the base address of the virtual memory unit from the virtual memory unit pointer to obtain the pointer number, and then looks up the address translation table according to the pointer number to obtain the corresponding physical memory unit pointer.

5. The memory collaborative management system according to claim 1, characterized in that, When sending a message, the CPU completes the editing of the message to be sent and then obtains the virtual memory unit pointer corresponding to the first physical memory unit pointer of the physical memory unit storing the message to be sent through the address translation controller. The CPU is also used to write the message to be sent to the physical storage unit pointed to by the physical storage unit pointer corresponding to the acquired virtual storage unit pointer, and to write the virtual storage unit pointer to the descriptor to notify the DMA to complete the message writing; The DMA is used to obtain the corresponding physical storage unit pointer according to the virtual storage unit pointer in the descriptor after detecting that there is a message to be sent, read the message to be sent from the physical storage unit pointed to by the physical storage unit pointer, and then send it.

6. The memory collaborative management system according to claim 5, characterized in that, Physical memory unit pointers and virtual memory unit pointers that have a corresponding relationship have the same pointer number; The CPU, after obtaining the virtual memory unit pointer corresponding to the first physical memory unit pointer through the address translation controller, sequentially writes all physical memory unit pointers storing the physical memory unit to be sent into the corresponding pointer number in the address translation table. The CPU is used to obtain a pointer number by subtracting its base address from the obtained virtual memory unit pointer, and to look up the address translation table based on the pointer number to obtain the corresponding physical memory unit pointer, and to write the message to be sent into the corresponding physical memory unit according to the order of the physical memory unit pointers. The DMA is used to obtain a pointer number by subtracting the base address from the virtual memory cell pointer in the acquired descriptor, and to obtain a physical memory cell pointer by looking up the address translation table based on the pointer number. Then, it reads the message to be sent in sequence according to the physical memory cell pointer and sends it.

7. The memory collaborative management system according to any one of claims 1-6, characterized in that, There is a one-to-one correspondence between the physical storage unit pointer and the virtual storage unit pointer.

8. The memory collaborative management system according to any one of claims 1-6, characterized in that, All physical storage units are the same size, and all virtual storage units are the same size.

9. A memory collaborative management method, characterized in that, A memory collaborative management system according to any one of claims 1-8, the system comprising a CPU, a DMA, an address translation controller, and a memory, wherein the CPU and DMA are interconnected and respectively connected to the address translation controller, and the address translation controller is connected to the memory via a system bus, the method comprising: Physical storage space and virtual storage space are allocated on the memory. The physical storage space includes multiple physical storage units, and the virtual storage space includes multiple virtual storage units. The number of physical storage units and virtual storage units is the same, and the size of each virtual storage unit is set to the maximum allowed message length. An address translation table is constructed in the address translation controller. The address translation table stores the correspondence between each physical memory unit pointer and each virtual memory unit pointer, so as to realize the mapping transformation between physical memory unit pointers and virtual memory unit pointers. The CPU reads existing messages from the memory or writes messages to be sent into the memory based on the obtained virtual memory unit pointer. The DMA writes the received message to the corresponding physical storage unit or sends the message already written in the corresponding physical storage unit based on the obtained physical storage unit pointer, and releases the physical storage unit after all the messages in the physical storage unit have been read or sent.

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