Data transceiving method, processor, electronic device, and computer system

Abstract

The present disclosure relates to the technical field of computer, and particularly relates to a data transceiving method, a processor, an electronic device and a computer system. The data transceiving method comprises the following steps: allocating a specified cache area for a specified thread in a cache, the specified thread is used for transceiving data through a network, the specified cache area is used for caching data with a write address in a specified buffer area, and the specified buffer area is established by the specified thread in a memory; receiving a write request, the write request comprises a write address in the specified buffer area and write data, the write data comprises data to be sent by the specified thread through the network or data received by the specified thread through the network; and for the received write request, write data in the write request is written into an address corresponding to the write address in the specified cache area.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, specifically to a data transmission and reception method, a processor, an electronic device, and a computer system. Background Technology

[0002] In recent years, data center network speeds have developed rapidly, from 25Gbps to 100Gbps, then to 200Gbps, with network bandwidth doubling every two years. 400Gbps networks are about to be commercially available. High-speed networks bring enormous memory bandwidth consumption. Sending and receiving data on a dual-port 200Gbps network requires nearly 80GBps of memory bandwidth. However, the memory modules used in servers widely deployed in data centers typically have a memory bandwidth capacity of around 100GBps. After deducting network memory access, the remaining memory bandwidth is insufficient to meet the needs of applications deployed on these servers.

[0003] Without upgrading the physical configuration of servers in the data center, the currently deployed servers will struggle to handle the massive memory bandwidth access required by high-speed networks. Upgrading the physical configuration, however, increases costs, including hardware expenses, electricity costs, cooling costs, and the associated costs of upgrading the Central Processing Unit (CPU). More importantly, the update cycle of network bandwidth is much shorter than the service life of data center server hardware, meaning that server hardware upgrades often lag behind the pace of network bandwidth updates. Therefore, simply relying on hardware upgrades cannot solve the problem of servers being unable to handle the massive memory bandwidth access required by high-speed networks. Summary of the Invention

[0004] To address the problems in the related technologies, embodiments of this disclosure provide a data transmission and reception method, a processor, an electronic device, and a computer system.

[0005] In a first aspect, this disclosure provides a data transmission and reception method, characterized in that it includes:

[0006] A specified cache area is allocated for a specified thread in the cache. The specified thread is used to send and receive data over the network. The specified cache area is used to cache data written to a specified buffer. The specified buffer is created in memory by the specified thread.

[0007] Receive a write request, the write request including the write address in the specified buffer and the write data, the write data including data that the specified thread wants to send through the network or data that the specified thread receives through the network;

[0008] For any received write request, the write data in the write request is written to the address corresponding to the write address in the specified cache area.

[0009] According to embodiments of this disclosure, wherein:

[0010] The specified cache area cannot be allocated to threads other than the specified thread;

[0011] The designated cache region is located in the L3 cache of the central processing unit and is smaller than the size of the L3 cache;

[0012] The specified buffer allows threads other than the specified thread to perform read and write operations, but does not allow threads other than the specified thread to perform operations other than read and write operations.

[0013] According to embodiments of this disclosure, the method further includes:

[0014] Receive a read request, the read request including the read address in the specified buffer;

[0015] For any received read request, read the corresponding data from the address corresponding to the read address in the specified cache area.

[0016] According to embodiments of this disclosure, wherein:

[0017] After reading the corresponding data from the specified cache area according to the read address in the read request, the specified thread is allowed to write data to the address in the specified cache area corresponding to the read address.

[0018] According to embodiments of this disclosure, wherein:

[0019] The designated buffer is a receive buffer used to store received data received over the network;

[0020] The designated buffer area is a receive buffer area corresponding to the receive buffer, used to cache data whose address is written to the receive buffer;

[0021] The allocation of a specified cache area for a specified thread includes:

[0022] According to the instruction to load the receive buffer into the cache, a receive buffer area corresponding to the receive buffer is allocated in the cache.

[0023] According to embodiments of this disclosure, wherein:

[0024] The receiving of write requests includes receiving write requests from the network interface card;

[0025] The write address includes the write address in the receive buffer;

[0026] The written data includes received data received via the network;

[0027] The step of writing the write data in the write request to the address corresponding to the write address in the specified cache area includes writing the received data to the address corresponding to the write address in the receive cache area.

[0028] According to embodiments of this disclosure, the method further includes:

[0029] Receive a read request from a specified storage device, the read request including the read address in the receive buffer;

[0030] According to the read request, the corresponding data is read from the address corresponding to the read address in the receive cache area and then into the designated storage device.

[0031] According to embodiments of this disclosure, wherein:

[0032] Receiving write requests from the network card includes receiving DMA write requests from the network card via the PCIe bus;

[0033] Receiving a read request from a designated storage device includes receiving a DMA read request from a network card via the PCIe bus.

[0034] According to embodiments of this disclosure, wherein:

[0035] The specified buffer is a transmission buffer used to store the data to be sent over the network;

[0036] The designated buffer area is a transmission buffer area corresponding to the transmission buffer, used to cache data whose address is written to the transmission buffer;

[0037] The allocation of a specified cache area for a specified thread includes:

[0038] According to the instruction to load the transmit buffer into the cache, a transmit buffer area corresponding to the transmit buffer is allocated in the cache.

[0039] According to embodiments of this disclosure, wherein:

[0040] The receiving of write requests includes receiving write requests from a specified storage device;

[0041] The write request is used for the write address in the send buffer;

[0042] The data to be written includes data to be sent over the network;

[0043] The step of writing the write data in the write request to the address corresponding to the write address in the specified cache area includes writing the send data to the address corresponding to the write address in the send cache area.

[0044] According to embodiments of this disclosure, the method further includes:

[0045] Receive a read request from the network card, the read request including the read address in the send buffer;

[0046] According to the read request, the corresponding data is read from the address corresponding to the read address in the send buffer area and then into the network card.

[0047] According to embodiments of this disclosure, wherein:

[0048] Receiving a write request from a specified storage device includes receiving a DMA write request from a specified storage device via the PCIe bus;

[0049] Receiving read requests from the network card includes receiving DMA read requests from the network card via the PCIe bus.

[0050] A second aspect of this disclosure provides a data transceiver apparatus, characterized in that it comprises:

[0051] The allocation module is configured to allocate a specified cache area in the cache for a specified thread, the specified thread being used to send and receive data over the network, the specified cache area being used to cache data written to a specified buffer, the specified buffer being established in memory by the specified thread;

[0052] The first receiving module is configured to receive write requests, the write requests including a write address and write data in the specified buffer, the write data including data to be sent by the specified thread through the network or data to be received by the specified thread through the network.

[0053] The write module is configured to, upon receiving a write request, write the write data in the write request to the address corresponding to the write address in the specified cache area.

[0054] According to embodiments of this disclosure, wherein:

[0055] The specified cache area cannot be allocated to threads other than the specified thread;

[0056] The designated cache region is located in the L3 cache of the central processing unit and is smaller than the size of the L3 cache;

[0057] The specified buffer allows threads other than the specified thread to perform read and write operations, but does not allow threads other than the specified thread to perform operations other than read and write operations.

[0058] According to embodiments of this disclosure, the apparatus further includes:

[0059] The second receiving module is configured to receive a read request, the read request including the read address in the specified buffer;

[0060] The read module is configured to read the corresponding data from the address corresponding to the read address in the specified cache area for any received read request.

[0061] According to embodiments of this disclosure, wherein:

[0062] After reading the corresponding data from the specified cache area according to the read address in the read request, the specified thread is allowed to write data to the address in the specified cache area corresponding to the read address.

[0063] According to embodiments of this disclosure, wherein:

[0064] The designated buffer is a receive buffer used to store received data received over the network;

[0065] The designated buffer area is a receive buffer area corresponding to the receive buffer, used to cache data whose address is written to the receive buffer;

[0066] The allocation of a specified cache area for a specified thread includes:

[0067] According to the instruction to load the receive buffer into the cache, a receive buffer area corresponding to the receive buffer is allocated in the cache.

[0068] According to embodiments of this disclosure, wherein:

[0069] The receiving of write requests includes receiving write requests from the network interface card;

[0070] The write address includes the write address in the receive buffer;

[0071] The written data includes received data received via the network;

[0072] The step of writing the write data in the write request to the address corresponding to the write address in the specified cache area includes writing the received data to the address corresponding to the write address in the receive cache area.

[0073] According to embodiments of this disclosure, wherein:

[0074] The second receiving module is configured to receive a read request from a specified storage device, the read request including a read address in the receiving buffer;

[0075] The reading module is configured to read corresponding data from the address corresponding to the reading address in the receiving cache area and to the designated storage device according to the reading request.

[0076] According to embodiments of this disclosure, wherein:

[0077] Receiving write requests from the network card includes receiving DMA write requests from the network card via the PCIe bus;

[0078] Receiving a read request from a designated storage device includes receiving a DMA read request from a network card via the PCIe bus.

[0079] According to embodiments of this disclosure, wherein:

[0080] The specified buffer is a transmission buffer used to store the data to be sent over the network;

[0081] The designated buffer area is a transmission buffer area corresponding to the transmission buffer, used to cache data whose address is written to the transmission buffer;

[0082] The allocation of a specified cache area for a specified thread includes:

[0083] According to the instruction to load the transmit buffer into the cache, a transmit buffer area corresponding to the transmit buffer is allocated in the cache.

[0084] According to embodiments of this disclosure, wherein:

[0085] The receiving of write requests includes receiving write requests from a specified storage device;

[0086] The write request is used for the write address in the send buffer;

[0087] The data to be written includes data to be sent over the network;

[0088] The step of writing the write data in the write request to the address corresponding to the write address in the specified cache area includes writing the send data to the address corresponding to the write address in the send cache area.

[0089] According to embodiments of this disclosure, wherein:

[0090] The second receiving module is configured to receive a read request from the network card, the read request including the read address in the sending buffer;

[0091] The reading module is configured to read corresponding data from the address corresponding to the reading address in the sending buffer area and put it into the network card according to the reading request.

[0092] According to embodiments of this disclosure, wherein:

[0093] Receiving a write request from a specified storage device includes receiving a DMA write request from a specified storage device via the PCIe bus;

[0094] Receiving read requests from the network card includes receiving DMA read requests from the network card via the PCIe bus.

[0095] A third aspect of this disclosure provides a processor, including a processor core, an integrated input / output module, and a cache, wherein:

[0096] The processor core allocates a specified cache area in the cache for a specified thread. The specified thread is used to send and receive data over the network. The specified cache area is used to cache data written to a specified buffer. The specified buffer is created in memory by the specified thread.

[0097] The integrated input / output module receives a write request, which includes a write address and write data in the specified buffer. The write data includes data that the specified thread wants to send through the network or data that the specified thread receives through the network.

[0098] For any write request received by the integrated input / output module, the cache writes the write data in the write request to the address corresponding to the write address in the specified cache area.

[0099] According to an embodiment of this disclosure, the designated cache area is not allowed to be allocated to threads other than the designated thread. The designated cache area is located in the L3 cache of the central processing unit and is smaller than the size of the L3 cache. The designated buffer allows threads other than the designated thread to perform read and write operations, but does not allow threads other than the designated thread to perform operations other than read and write operations.

[0100] According to an embodiment of this disclosure, the integrated input / output module receives a read request, the read request including a read address in the specified buffer. For any read request received by the integrated input / output module, the buffer reads the corresponding data from the address in the specified buffer area corresponding to the read address in the read request.

[0101] According to an embodiment of this disclosure, after reading the corresponding data from the specified cache region according to the read address in the read request, the operating system allows the specified thread to write data to the address in the specified cache region corresponding to the read address.

[0102] According to embodiments of this disclosure, the designated buffer is a receive buffer for storing received data received over the network; the designated cache area is a receive cache area corresponding to the receive buffer, used to cache data written to the receive buffer; the allocation of the designated cache area for a designated thread includes: allocating a receive cache area corresponding to the receive buffer in the cache according to an instruction to load the receive buffer into the cache.

[0103] According to embodiments of this disclosure, receiving a write request includes receiving a write request from a network interface card (NIC); the write address includes a write address in the receive buffer; the write data includes received data received via the network; and writing the write data in the write request to the address corresponding to the write address in the designated cache region includes writing the received data to the address corresponding to the write address in the receive cache region.

[0104] According to an embodiment of this disclosure, the integrated input / output module receives a read request from a designated storage device, the read request including a read address in the receive buffer; the cache reads corresponding data from the address corresponding to the read address in the receive buffer area to the designated storage device according to the read request.

[0105] According to embodiments of this disclosure, receiving a write request from the network card includes receiving a DMA write request from the network card via the PCIe bus using an integrated input / output module; receiving a read request from a designated storage device includes receiving a DMA read request from the network card via the PCIe bus using an integrated input / output module.

[0106] According to embodiments of this disclosure, the designated buffer is a transmission buffer used to store transmission data to be sent over the network; the designated cache area is a transmission cache area corresponding to the transmission buffer, used to cache data written to the address in the transmission buffer; the allocation of the designated cache area for a designated thread includes: allocating a transmission cache area corresponding to the transmission buffer in the cache according to an instruction to load the transmission buffer into the cache.

[0107] According to embodiments of this disclosure, receiving a write request includes receiving a write request from a specified storage device; the write request is for a write address in the send buffer; the write data includes send data to be sent over a network; and writing the write data in the write request to the address corresponding to the write address in the specified cache region includes writing the send data to the address corresponding to the write address in the send cache region.

[0108] According to embodiments of this disclosure, an integrated input / output module receives a read request from a network interface card (NIC), the read request including a read address in the transmit buffer. Based on the read request, the buffer reads corresponding data from the address corresponding to the read address in the transmit buffer region and stores it in the NIC.

[0109] According to embodiments of this disclosure, receiving a write request from a designated storage device includes receiving a DMA write request from the designated storage device via a PCIe bus; receiving a read request from a network interface card (NIC) includes receiving a DMA read request from the NIC via a PCIe bus.

[0110] A fourth aspect of this disclosure provides an electronic device including a processor, memory, a network interface card (NIC), and a designated storage device as described in the third aspect, wherein the processor is connected to the memory, the NIC, and the designated storage device.

[0111] The fifth aspect of this disclosure provides a computer system comprising a plurality of computers, each computer including a processor, memory, a network interface card (NIC), and a designated storage device as described in the third aspect, the processor being connected to the memory, the NIC, and the designated storage device.

[0112] According to the technical solution provided in the embodiments of this disclosure, by writing the data to be sent or received by a specified thread over the network into a specified cache area, it is not necessary to write the data to be sent or received by a specified thread over the network into a specified buffer in memory through the memory controller. This can significantly save the memory bandwidth consumption for data transmission and reception over the network. While meeting the high-speed network data transmission and reception requirements of the data center, it ensures that the server has sufficient memory bandwidth for the applications deployed on the server.

[0113] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0114] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:

[0115] Figure 1 A schematic diagram illustrating the principle of existing data transmission and reception methods is shown.

[0116] Figure 2 A schematic diagram of a data transmission and reception method according to an embodiment of the present disclosure is shown.

[0117] Figure 3 A flowchart illustrating a data transmission and reception method according to an embodiment of the present disclosure is shown.

[0118] Figure 4A structural block diagram of a data transceiver apparatus according to an embodiment of the present disclosure is shown.

[0119] Figure 5 A structural block diagram of a processor according to an embodiment of the present disclosure is shown.

[0120] Figure 6 A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown.

[0121] Figure 7 A schematic diagram of a computer system according to an embodiment of the present disclosure is shown. Detailed Implementation

[0122] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings to enable those skilled in the art to readily implement them. Furthermore, for clarity, portions unrelated to the description of exemplary embodiments have been omitted from the drawings.

[0123] In this disclosure, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of features, figures, steps, behaviors, components, parts or combinations thereof disclosed in this specification, and are not intended to exclude the possibility of the presence or addition of one or more other features, figures, steps, behaviors, components, parts or combinations thereof.

[0124] It should also be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0125] Cloud computing and big data have entered the digital infrastructure stage. The internet industry, from basic hardware to software services and application deployments, operates on the cloud. This cloud migration places extremely demanding requirements on the network service capabilities of cloud data centers. Currently, data center network speeds have been upgraded from 25Gbps to 100Gbps and 200Gbps, with 400Gbps networks already in the planning stages. The general pattern is that network bandwidth doubles every two years. However, the hardware configuration of data center servers has not kept pace with the development of network bandwidth. Sending and receiving data on a dual-port 200Gbps network requires nearly 80GBps of memory bandwidth, while the memory modules used in widely deployed servers in data centers typically have a memory bandwidth capacity of around 100GBps. After deducting network memory access, the remaining memory bandwidth is insufficient to meet the needs of applications deployed on the servers.

[0126] Specifically, high-speed data center networks typically use user-space network protocol stacks such as RDMA (Remote Direct Memory Access) or DPDK (Data Plane Development Kit) for communication. These user-space network protocol stacks can provide throughput of hundreds of Gbps and latency in the microsecond range. However, applications need to manage and maintain the network buffer used for sending and receiving data in user space. The network buffer is a memory area requested by the application from system memory. When sending data, the application places it in the network buffer. The CPU running the application submits the network buffer to the network card, which reads the data from the network buffer via DMA (Direct Memory Access), then sends it over the network and notifies the CPU of the application that the data transmission is complete. When receiving data, the application submits the network buffer to the network card. The network card receives the data over the network, writes the data back to the network buffer via DMA, and notifies the CPU of the application that the data reception is complete.

[0127] When sending and receiving data, the network interface card (NIC) needs to perform DMA writes or DMA reads on the network buffer via the PCIe bus to write received data to memory or read data to be sent from memory. Conversely, the hard drive uses DMA writes to write data to be sent via the NIC to memory, or DMA reads to read received data received by the NIC over the network from memory. When the NIC and hard drive read and write data to the network buffer, they must access the memory region through the memory controller, resulting in memory bandwidth consumption equal to the network bandwidth. This makes it difficult to meet the remaining memory bandwidth requirements of applications deployed on servers.

[0128] Figure 1 A schematic diagram illustrating the principle of existing data transmission and reception methods is shown.

[0129] like Figure 1 As shown, a designated thread runs on the CPU to send and receive data over the network. The designated thread requests a memory area in memory as a network buffer, which includes a receive buffer (RX Buffer) and a send buffer (TX Buffer).

[0130] When receiving data, the network card writes the received data to the RX Buffer via the memory controller, and the hard drive reads the received data from the RX Buffer via the memory controller to complete the persistent storage of the received data. When sending data, the hard drive first writes the data to be sent to the TX Buffer via the memory controller, and then the network card reads the data to be sent from the TX Buffer via the memory controller and sends it over the network.

[0131] Figure 2 A schematic diagram of a data transmission and reception method according to an embodiment of the present disclosure is shown.

[0132] like Figure 2 As shown, on the network receiving direction I / O path, a designated thread receiving data via the network allocates a memory region in memory as a network buffer, specifically a receive buffer (RX Buffer). According to embodiments of this disclosure, the designated thread can be an application thread based on RDMA or DPDK. Then, the RX Buffer is loaded into the CPU's Level 3 cache (LLC) using a CPU load instruction; that is, a designated cache region corresponding to the RX Buffer is allocated in the LLC for the designated thread, specifically a receive buffer region (rx buffer) used to cache data to be written to the RX Buffer. The cache can maintain the correspondence between addresses in the rx buffer and addresses in the RX Buffer.

[0133] The CPU sends a command to the network interface card (NIC) to receive data and sends metadata about the RX Buffer (e.g., RX Buffer physical address, length, access key, etc.) to the NIC. Upon receiving the data (hereinafter referred to as "received data"), the NIC parses the receive data command and the RX Buffer metadata to obtain the destination memory address for writing the received data. Then, it sends a DMA write request via the PCIe (Peripheral Component Interface Extend) bus. The DMA write request includes the write address in the RX Buffer and the data to be written (i.e., the received data). The buffer receives the DMA write request from the PCIe bus and, based on the correspondence between addresses in the RX Buffer and the addresses in the RX Buffer, writes the received data to the address corresponding to the write address in the RX Buffer.

[0134] Because the RX buffer is preloaded into the CPU's LLC, DMA write requests do not write to memory, but instead write the received data to the corresponding address in the RX buffer, saving the network card's memory bandwidth consumption in the receiving direction.

[0135] When it's necessary to store received data written to the rx buffer to a designated storage device, the CPU issues a read command to the designated storage device. In response, the designated storage device sends a DMA read request via the PCIe bus, which includes the read address in the RX buffer. The cache, upon receiving the DMA read request from the PCIe bus, responds by sending the data from the rx buffer corresponding to the read address, based on the address mapping between the rx buffer and the RX buffer. In this way, data received over the network can be stored in a designated storage device without directly reading or writing to memory, saving memory bandwidth consumption during storage device reads.

[0136] According to embodiments of this disclosure, the designated storage device may be, for example, a solid state disk (SSD), or other storage device capable of DMA access to LLC.

[0137] On the network transmit direction I / O path, the designated thread transmitting data over the network allocates a memory region in memory as a network buffer, specifically a TX buffer. According to embodiments of this disclosure, the designated thread can be an application thread based on RDMA or DPDK. Then, the TX buffer is loaded into the CPU's Level 3 cache (LLC) using a CPU load instruction; that is, a designated cache region corresponding to the TX buffer is allocated in the LLC for the designated thread, specifically a transmit buffer (tx buffer), used to cache data to be written to the TX buffer. The cache can maintain the correspondence between addresses in the tx buffer and addresses in the TX buffer.

[0138] The CPU sends a command to the specified storage device to read data. The specified storage device sends a DMA write request via the PCIe bus. The DMA write request includes the write address in the TX buffer and the data to be written (i.e., the data to be sent over the network). The buffer receives the DMA write request on the PCIe bus and, based on the correspondence between the addresses in the TX buffer and the addresses in the TX buffer, writes the data to be sent to the address corresponding to the write address in the TX buffer.

[0139] Because the TX buffer is preloaded into the CPU's LLC, DMA write requests do not write to memory, but instead write the data to the corresponding address in the TX buffer, saving memory bandwidth consumption for the specified storage device read direction.

[0140] Then, the CPU sends a data transmission command to the network card (NIC). In response, the NIC sends a DMA read request via the PCIe bus, which includes the read address in the TX buffer. The cache receives the DMA read request from the PCIe bus and, in response, sends the data corresponding to the read address in the TX buffer to the NIC, based on the address mapping between the TX buffer and the address in the TX buffer. The NIC encapsulates the data and sends it over the network. In this way, data to be sent over the network can be transferred from the cache to the NIC for transmission without directly reading or writing to memory, saving bandwidth consumption in the NIC's transmission direction.

[0141] Typically, CPU LLC has a bandwidth capacity of over 200GBps, far exceeding memory bandwidth and sufficient to meet current and future high-throughput access demands. This embodiment utilizes LLC to bypass memory for data transmission, effectively mitigating the memory bandwidth consumption of network data transmission and reception, and ensuring that other applications deployed on the server meet their memory bandwidth requirements.

[0142] Figure 3 A flowchart illustrating a data transmission and reception method according to an embodiment of the present disclosure is shown. Figure 3 As shown, the data transmission and reception method includes the following steps S301–S303:

[0143] In step S301, a specified cache area is allocated in the cache for a specified thread. The specified thread is used to send and receive data over the network. The specified cache area is used to cache data written to a specified buffer. The specified buffer is created in memory by the specified thread.

[0144] In step S302, a write request is received, the write request including the write address in the specified buffer and the write data, the write data including data to be sent by the specified thread through the network or data to be received by the specified thread through the network;

[0145] In step S303, for the received write request, the write data in the write request is written to the address corresponding to the write address in the specified cache area.

[0146] According to an embodiment of this disclosure, for any write request received by the cache, the write data in the write request is written to the address corresponding to the write address in the specified cache region.

[0147] The data transmission and reception method according to embodiments of this disclosure can be executed by an electronic device running a designated thread. The electronic device can be a computer or a server, and the designated thread is responsible for some or all of the data transmission and reception operations of the electronic device via a network. By writing the data to be sent or received by the designated thread over the network into a designated cache area, it is unnecessary to write the data to be sent or received by the designated thread over the network into a designated buffer in memory via a memory controller. This significantly reduces the memory bandwidth consumption for data transmission and reception over the network, meeting the high-speed network data transmission and reception requirements of data centers while ensuring sufficient memory bandwidth on the server for applications deployed on the server.

[0148] According to embodiments of this disclosure, the method further includes: receiving a read request, the read request including a read address in the specified buffer; and for any received read request, reading corresponding data from the address corresponding to the read address in the specified buffer area.

[0149] According to embodiments of this disclosure, by reading data to be sent over the network by a specified thread or data to be received over the network by a specified thread from a specified cache area, it is not necessary to read data to be sent over the network by a specified thread or data to be received over the network by a specified thread from a specified buffer in memory through the memory controller, which can further save the memory bandwidth consumption of data transmission and reception over the network.

[0150] According to embodiments of this disclosure, the addresses in both write and read requests are addresses in a specified buffer, and the cache maintains a mapping between addresses in the specified buffer and addresses in a specified cache region. Upon receiving a write request, the cache determines the address in the specified cache region corresponding to the address in the specified buffer and writes the data to that address in the specified cache region. Upon receiving a read request, the cache determines the address in the specified cache region corresponding to the address in the specified buffer and reads the data from that address in the specified cache region.

[0151] According to embodiments of this disclosure, the designated cache area is not allowed to be allocated to threads other than the designated thread; the designated cache area is located in the L3 cache of the central processing unit and is smaller than the size of the L3 cache; the designated buffer allows threads other than the designated thread to perform read and write operations, but does not allow threads other than the designated thread to perform operations other than read and write operations.

[0152] According to embodiments of this disclosure, threads running on all CPU cores in a CPU socket share the LLC of that CPU socket. A specific cache region allocated to a specific thread can be isolated from the cache regions of other threads using, for example, an existing CAT (cache allocation tool). This prevents the specified cache region from being allocated to other threads, which could lead to cache misses and additional memory accesses when the network card or specified storage device accesses the specified cache region. According to embodiments of this disclosure, a specified buffer is created by a specified thread, which declares it as a private object when creating the specified buffer. This allows the specified thread to perform read and write operations on the specified buffer, while threads other than the specified thread can only perform read and write operations on the specified buffer. Since the specified buffer allows read and write operations by threads other than the specified thread, the needs of other threads to quickly obtain, send, or receive data can be met. Simultaneously, since other threads cannot perform operations other than read and write operations on the specified buffer—for example, other threads cannot release or allocate memory space in the specified buffer—centralized management of the specified buffer by the specified thread can be achieved, ensuring that the address correspondence between the specified buffer and the specified cache region remains unchanged, thereby achieving efficient and stable data transmission and reception.

[0153] According to embodiments of this disclosure, by setting a specified cache area within an LLC and making it smaller than the size of the LLC, it can be ensured that both reading and writing of a specified buffer can be completed through the specified cache area.

[0154] According to an embodiment of this disclosure, after reading the corresponding data from the specified cache area according to the read address in the read request, the specified thread is allowed to write data to the address in the specified cache area corresponding to the read address.

[0155] For example, after reading received data from a specified cache area and storing it in a specified storage device, or after reading data to be sent from a specified cache area and sending it through the network card, a specified thread can be allowed to write data to the address in the specified cache area where the read data was originally stored (i.e., the address in the specified cache area corresponding to the read address). In this way, addresses in the specified cache area can be reused, ensuring that the size of the specified cache area is always within the LLC size and that the specified cache area is always maintained within the LLC. By controlling the size of the specified cache area and reusing it, access to memory from the network card or specified storage device can be completely transferred to access to the LLC with greater bandwidth, eliminating memory bandwidth consumption in high-speed network data transmission and reception scenarios and avoiding the generation of memory bandwidth bottlenecks.

[0156] According to embodiments of this disclosure, the designated buffer is a receive buffer for storing received data received over the network, for example, it may be... Figure 2 The RX Buffer shown.

[0157] According to embodiments of this disclosure, the designated buffer area is a receive buffer area corresponding to the receive buffer, used to buffer data whose address is written to the receive buffer, for example, it may be... Figure 2 The rx buffer shown.

[0158] According to an embodiment of this disclosure, allocating a specified cache region for a specified thread includes: allocating a receive cache region corresponding to the receive buffer in the cache according to an instruction to load the receive buffer into the cache.

[0159] For example, in Figure 2 In the process, according to the CPU load instruction that loads the RX Buffer into the cache, the corresponding rx buffer can be allocated in the cache. The cache maintains the address mapping between the RX Buffer and the rx buffer, so that when an access request for an address in the RX Buffer is received, it is converted into an access request for an address in the rx buffer and the corresponding access operation is performed.

[0160] According to embodiments of this disclosure, receiving a write request includes receiving a write request from a network interface card (NIC); the write address includes a write address in the receive buffer; the write data includes received data received via the network; and writing the write data in the write request to the address corresponding to the write address in the designated cache region includes writing the received data to the address corresponding to the write address in the receive cache region.

[0161] According to an embodiment of this disclosure, the method further includes: receiving a read request from a designated storage device, the read request including a read address in the receive buffer; and reading corresponding data from the address corresponding to the read address in the receive buffer region to the designated storage device according to the read request.

[0162] According to embodiments of this disclosure, receiving a write request from the network card includes receiving a DMA write request from the network card via a cache through the PCIe bus; receiving a read request from a specified storage device includes receiving a DMA read request from the network card via a cache through the PCIe bus.

[0163] For example, in Figure 2In this process, the cache receives DMA write requests from the network card via the PCIe bus. The write address in the DMA write request includes the write address in the RX Buffer, and the write data includes the received data. Based on the mapping between addresses in the RX Buffer and addresses in the RX Buffer, the cache converts the access to the write address into an access to the RX Buffer, and writes the received data to the address in the RX Buffer corresponding to the write address.

[0164] According to embodiments of this disclosure, the designated storage device may be, for example, an SSD. The cache receives a DMA read request from the designated storage device via the PCIe bus. The DMA read request includes a read address in the RX buffer. Based on the mapping between addresses in the RX buffer and addresses in the RX buffer, the cache translates the access to the read address into an access to the RX buffer, and reads data from the address in the RX buffer corresponding to the read address.

[0165] According to embodiments of this disclosure, by writing data received by a specified thread over the network from the network card to the receive buffer area, it is not necessary to write the data received by the specified thread over the network to the receive buffer in memory through the memory controller. This can significantly save the memory bandwidth consumption of data reception over the network, while meeting the high-speed network data transmission and reception requirements of the data center and ensuring that the server has sufficient memory bandwidth for the applications deployed on the server.

[0166] According to embodiments of this disclosure, data received by a specified thread via the network can be read from the receive buffer area through a specified storage device, without needing to read the data received by the specified thread via the network from the receive buffer in memory through the memory controller, which can further save the memory bandwidth consumption of data transmission and reception over the network.

[0167] According to embodiments of this disclosure, the designated buffer is a transmission buffer used to store transmission data to be sent over the network, for example, it may be... Figure 2 The TX Buffer shown.

[0168] According to embodiments of this disclosure, the designated buffer area is a transmission buffer area corresponding to the transmission buffer, used to cache data written to the address in the transmission buffer, for example, it may be... Figure 2 The tx buffer shown.

[0169] According to an embodiment of this disclosure, allocating a specified cache region for a specified thread includes: allocating a send cache region corresponding to the send buffer in the cache according to an instruction to load the send buffer into the cache.

[0170] For example, in Figure 2 In the process, according to the CPU load instruction that loads the TX Buffer into the cache, a tx buffer corresponding to the TX Buffer can be allocated in the cache. The cache maintains the address mapping between the TX Buffer and the tx buffer, so that when an access request for an address in the TX Buffer is received, it is converted into an access request for an address in the tx buffer and the corresponding access operation is performed.

[0171] According to embodiments of this disclosure, receiving a write request includes receiving a write request from a specified storage device; the write request is for a write address in the send buffer; the write data includes send data to be sent over a network; and writing the write data in the write request to the address corresponding to the write address in the specified cache region includes writing the send data to the address corresponding to the write address in the send cache region.

[0172] According to an embodiment of this disclosure, the method further includes: receiving a read request from a network interface card (NIC), the read request including a read address in the transmit buffer; and reading corresponding data from the address corresponding to the read address in the transmit buffer region to the NIC according to the read request.

[0173] According to embodiments of this disclosure, receiving a write request from a designated storage device includes receiving a DMA write request from the designated storage device via a PCIe bus; receiving a read request from a network interface card (NIC) includes receiving a DMA read request from the NIC via a PCIe bus.

[0174] For example, in Figure 2 In this embodiment of the present disclosure, the designated storage device may be, for example, an SSD. The cache receives a DMA write request from the designated storage device via the PCIe bus. The write address in the DMA write request includes the write address in the TX buffer, and the write data includes transmit data. Based on the mapping between addresses in the TX buffer and addresses in the TX buffer, the cache converts the access to the write address into an access to the TX buffer, and writes the transmit data to the address in the TX buffer corresponding to the write address.

[0175] The cache receives DMA read requests from the network card via the PCIe bus. These requests include the read address in the TX buffer. Based on the mapping between addresses in the TX buffer and addresses in the TX buffer, the cache translates the access to the read address into an access to the TX buffer, and reads the data from the address corresponding to the read address in the TX buffer.

[0176] According to embodiments of this disclosure, by writing the data to be sent by a specified thread over the network from a specified storage device to a send buffer area, it is not necessary to write the data to be sent by the specified thread over the network to a send buffer in memory through a memory controller. This can significantly save the memory bandwidth consumption for data transmission over the network. While meeting the high-speed network data transmission and reception requirements of the data center, it ensures that the server has sufficient memory bandwidth for the applications deployed on the server.

[0177] According to embodiments of this disclosure, data to be sent over the network by a specified thread can be read from the transmit buffer area via the network card, without having to read the data to be sent over the network by the specified thread from the transmit buffer in memory via the memory controller, which can further save the memory bandwidth consumption for data transmission and reception over the network.

[0178] Figure 4 A structural block diagram of a data transceiver apparatus according to an embodiment of the present disclosure is shown. The apparatus may be implemented as part or all of a processor (e.g., a CPU) through software, hardware, or a combination of both.

[0179] like Figure 4 As shown, the data transceiver device 400 includes an allocation module 410, a first receiving module 420, and a writing module 430.

[0180] The allocation module 410 is configured to allocate a specified cache area in the cache for a specified thread, the specified thread being used to send and receive data over the network, the specified cache area being used to cache data written to a specified buffer, the specified buffer being established in memory by the specified thread;

[0181] The first receiving module 420 is configured to receive a write request, the write request including a write address and write data in the specified buffer, the write data including data to be sent by the specified thread through the network or data to be received by the specified thread through the network.

[0182] The write module 430 is configured to, upon receiving a write request, write the write data in the write request to the address corresponding to the write address in the specified cache area.

[0183] According to embodiments of this disclosure, wherein:

[0184] The specified cache area cannot be allocated to threads other than the specified thread;

[0185] The designated cache region is located in the L3 cache of the central processing unit and is smaller than the size of the L3 cache;

[0186] The specified cache area allows the specified thread to perform read and write operations, and allows threads other than the specified thread to perform read operations.

[0187] According to embodiments of this disclosure, the device 400 further includes:

[0188] The second receiving module 440 is configured to receive a read request, the read request including the read address in the specified buffer;

[0189] The read module 450 is configured to read corresponding data from the address corresponding to the read address in the specified cache area for any received read request.

[0190] According to embodiments of this disclosure, wherein:

[0191] After reading the corresponding data from the specified cache area according to the read address in the read request, the specified thread is allowed to write data to the address in the specified cache area corresponding to the read address.

[0192] According to embodiments of this disclosure, wherein:

[0193] The designated buffer is a receive buffer used to store received data received over the network;

[0194] The designated buffer area is a receive buffer area corresponding to the receive buffer, used to cache data whose address is written to the receive buffer;

[0195] The allocation of a specified cache area for a specified thread includes:

[0196] According to the instruction to load the receive buffer into the cache, a receive buffer area corresponding to the receive buffer is allocated in the cache.

[0197] According to embodiments of this disclosure, wherein:

[0198] The receiving of write requests includes receiving write requests from the network interface card;

[0199] The write address includes the write address in the receive buffer;

[0200] The written data includes received data received via the network;

[0201] The step of writing the write data in the write request to the address corresponding to the write address in the specified cache area includes writing the received data to the address corresponding to the write address in the receive cache area.

[0202] According to embodiments of this disclosure, wherein:

[0203] The second receiving module 440 is configured to receive a read request from a specified storage device, the read request including a read address in the receiving buffer;

[0204] The read module 450 is configured to read corresponding data from the address corresponding to the read address in the receive cache area and to the designated storage device according to the read request.

[0205] According to embodiments of this disclosure, wherein:

[0206] Receiving write requests from the network card includes receiving DMA write requests from the network card via the PCIe bus;

[0207] Receiving a read request from a designated storage device includes receiving a DMA read request from a network card via the PCIe bus.

[0208] According to embodiments of this disclosure, wherein:

[0209] The specified buffer is a transmission buffer used to store the data to be sent over the network;

[0210] The designated buffer area is a transmission buffer area corresponding to the transmission buffer, used to cache data whose address is written to the transmission buffer;

[0211] The allocation of a specified cache area for a specified thread includes:

[0212] According to the instruction to load the transmit buffer into the cache, a transmit buffer area corresponding to the transmit buffer is allocated in the cache.

[0213] According to embodiments of this disclosure, wherein:

[0214] The receiving of write requests includes receiving write requests from a specified storage device;

[0215] The write request is used for the write address in the send buffer;

[0216] The data to be written includes data to be sent over the network;

[0217] The step of writing the write data in the write request to the address corresponding to the write address in the specified cache area includes writing the send data to the address corresponding to the write address in the send cache area.

[0218] According to embodiments of this disclosure, wherein:

[0219] The second receiving module 440 is configured to receive a read request from the network card, the read request including the read address in the sending buffer;

[0220] The reading module 450 is configured to read corresponding data from the address corresponding to the reading address in the sending buffer area and put it into the network card according to the reading request.

[0221] According to embodiments of this disclosure, wherein:

[0222] Receiving a write request from a specified storage device includes receiving a DMA write request from a specified storage device via the PCIe bus;

[0223] Receiving read requests from the network card includes receiving DMA read requests from the network card via the PCIe bus.

[0224] Figure 5 A structural block diagram of a processor according to an embodiment of the present disclosure is shown.

[0225] like Figure 5 As shown, a processor 500 includes at least one processor core 501, an integrated input / output module (IIO) 502, at least one integrated memory controller (IMC) 503, and at least one cache 504.

[0226] In this configuration, processor core 501 is connected to IIO 502, IIO 502 is connected to IMC 503, IMC 503 is connected to cache 504, and cache 504 is connected to both the processor and 501. According to embodiments of this disclosure, the connections can be direct or indirect, via other components.

[0227] According to an embodiment of this disclosure, the processor core 501 runs a designated thread for sending and receiving data over a network, and allocates a designated cache area for the designated thread in the cache according to a CPU load instruction. The designated thread is used for sending and receiving data over a network, and the designated cache area is used to cache data written to a designated buffer. The designated buffer is established in memory by the designated thread.

[0228] The IIO 502 receives a write request, which includes a write address in the specified buffer and write data. The write data includes data that the specified thread wants to send over the network or data that the specified thread receives over the network.

[0229] According to embodiments of this disclosure, IIO 502 forwards received DMA requests (including DMA write requests and DMA read requests) to IMC 503. If IMC 503 identifies a corresponding address in cache 504 for the memory address in the DMA request, it forwards the DMA request to cache 504. Since the specified buffer in this embodiment is loaded into cache 504, and the specified cache area is not allowed to be allocated to threads other than the specified thread, addresses in the specified buffer always have corresponding addresses in the specified cache area. Therefore, IMC 503 forwards any received read / write requests for addresses in the specified buffer to cache 504.

[0230] For any write request received by IIO 502, cache 504 writes the write data in the write request to the address corresponding to the write address in the specified cache area.

[0231] According to an embodiment of this disclosure, the designated cache area is not allowed to be allocated to threads other than the designated thread. The designated cache area is located in the L3 cache of the central processing unit and is smaller than the size of the L3 cache. The designated buffer allows threads other than the designated thread to perform read and write operations, but does not allow threads other than the designated thread to perform operations other than read and write operations.

[0232] According to an embodiment of this disclosure, the IIO 502 receives a read request, the read request including a read address in the specified buffer. For any read request received by the IIO 502, the cache 504 reads the corresponding data from the address in the specified cache area corresponding to the read address in the read request.

[0233] According to an embodiment of this disclosure, after reading the corresponding data from the specified cache region according to the read address in the read request, the operating system allows the specified thread to write data to the address in the specified cache region corresponding to the read address.

[0234] According to embodiments of this disclosure, the designated buffer is a receive buffer for storing received data received over the network; the designated cache area is a receive cache area corresponding to the receive buffer, used to cache data written to the receive buffer; the allocation of the designated cache area for a designated thread includes: allocating a receive cache area corresponding to the receive buffer in the cache according to an instruction to load the receive buffer into the cache.

[0235] According to embodiments of this disclosure, receiving a write request includes receiving a write request from a network interface card (NIC); the write address includes a write address in the receive buffer; the write data includes received data received via the network; and writing the write data in the write request to the address corresponding to the write address in the designated cache region includes writing the received data to the address corresponding to the write address in the receive cache region.

[0236] According to an embodiment of this disclosure, the IIO 502 receives a read request from a designated storage device, the read request including a read address in the receive buffer; the cache 504 reads corresponding data from the address corresponding to the read address in the receive cache area to the designated storage device according to the read request.

[0237] According to embodiments of this disclosure, receiving a write request from the network card includes IIO 502 receiving a DMA write request from the network card via the PCIe bus; receiving a read request from a specified storage device includes IIO 502 receiving a DMA read request from the network card via the PCIe bus.

[0238] According to embodiments of this disclosure, the designated buffer is a transmission buffer used to store transmission data to be sent over the network; the designated cache area is a transmission cache area corresponding to the transmission buffer, used to cache data written to the address in the transmission buffer; the allocation of the designated cache area for a designated thread includes: allocating a transmission cache area corresponding to the transmission buffer in the cache according to an instruction to load the transmission buffer into the cache.

[0239] According to embodiments of this disclosure, receiving a write request includes receiving a write request from a specified storage device; the write request is for a write address in the send buffer; the write data includes send data to be sent over a network; and writing the write data in the write request to the address corresponding to the write address in the specified cache region includes writing the send data to the address corresponding to the write address in the send cache region.

[0240] According to an embodiment of this disclosure, IIO 502 receives a read request from the network interface card (NIC), the read request including a read address in the transmit buffer. Buffer 504 reads corresponding data from the address corresponding to the read address in the transmit buffer region and stores it in the NIC according to the read request.

[0241] According to embodiments of this disclosure, receiving a write request from a designated storage device includes receiving a DMA write request from the designated storage device via a PCIe bus; receiving a read request from a network interface card (NIC) includes receiving a DMA read request from the NIC via a PCIe bus.

[0242] This disclosure also provides an electronic device, including a processor, memory, network interface card (NIC), and a designated storage device as described above, wherein the processor is connected to the memory, the NIC, and the designated storage device.

[0243] Figure 6 A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown.

[0244] like Figure 6 As shown, the electronic device includes a processor, memory, network card, and a designated storage device, wherein the processor is connected to the memory, the network card, and the designated storage device.

[0245] According to embodiments of this disclosure, the processor may be implemented as a processor including the data transceiver device 400 described above, or as a processor 500.

[0246] According to embodiments of this disclosure, the electronic device may be a server.

[0247] Figure 7 A schematic diagram of a computer system according to an embodiment of the present disclosure is shown.

[0248] like Figure 7 As shown, this disclosure also provides a computer system 700, including multiple computers 700-1, 700-2...700-N. Each computer includes a processor, memory, a network interface card (NIC), and a designated storage device. The processor is connected to the memory, the NIC, and the designated storage device. According to embodiments of this disclosure, the processor may be implemented as a processor including the data transceiver device 400 described above, or as a processor 500.

[0249] According to embodiments of this disclosure, the computer system may be a server system in a data center, and the computer may be a server in a data center.

[0250] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0251] The units or modules described in the embodiments of this disclosure can be implemented in software, programmable hardware, or dedicated hardware. The described units or modules can also be located in a processor, and the names of these units or modules do not necessarily constitute a limitation on the unit or module itself.

[0252] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

Claims

1. A data transmission and reception method, comprising: A specified cache area is allocated for a specified thread in the cache. The specified thread is used to send and receive data over the network. The specified cache area is used to cache data written to a specified buffer. The specified buffer is created in memory by the specified thread. Receive a write request, the write request including the write address in the specified buffer and the write data, the write data including data that the specified thread wants to send through the network or data that the specified thread receives through the network; For a received write request, according to the correspondence between the address in the specified buffer and the address in the specified cache area, the write data in the write request is written to the address corresponding to the write address in the specified cache area, so as to bypass the memory for data transmission and reception. The designated buffer is a receive buffer used to store received data received over the network; The designated buffer area is a receive buffer area corresponding to the receive buffer, used to cache data whose address is written to the receive buffer; The allocation of a specified cache area for a specified thread includes: According to the instruction to load the receive buffer into the cache, a receive buffer area corresponding to the receive buffer is allocated in the cache.

2. The method according to claim 1, wherein: The specified cache area cannot be allocated to threads other than the specified thread; The designated cache region is located in the L3 cache of the central processing unit and is smaller than the size of the L3 cache; The specified buffer allows threads other than the specified thread to perform read and write operations, but does not allow threads other than the specified thread to perform operations other than read and write operations.

3. The method according to claim 1, further comprising: Receive a read request, the read request including the read address in the specified buffer; For any received read request, read the corresponding data from the address corresponding to the read address in the specified cache area; After reading the corresponding data from the specified cache area according to the read address in the read request, the specified thread is allowed to write data to the address in the specified cache area corresponding to the read address.

4. The method according to claim 1, wherein: The receiving of write requests includes receiving write requests from the network interface card; The write address includes the write address in the receive buffer; The written data includes received data received via the network; The step of writing the write data in the write request to the address corresponding to the write address in the specified cache area includes writing the received data to the address corresponding to the write address in the receive cache area.

5. The method according to claim 4, further comprising: Receive a read request from a specified storage device, the read request including the read address in the receive buffer; According to the read request, the corresponding data is read from the address corresponding to the read address in the receive cache area and then into the designated storage device.

6. The method according to claim 5, wherein: Receiving write requests from the network card includes receiving DMA write requests from the network card via the PCIe bus; Receiving a read request from a designated storage device includes receiving a DMA read request from a network card via the PCIe bus.

7. The method according to claim 1, wherein: The specified buffer is a transmission buffer used to store the data to be sent over the network; The designated buffer area is a transmission buffer area corresponding to the transmission buffer, used to cache data whose address is written to the transmission buffer; The allocation of a specified cache area for a specified thread includes: According to the instruction to load the transmit buffer into the cache, a transmit buffer area corresponding to the transmit buffer is allocated in the cache.

8. The method according to claim 7, wherein: The receiving of write requests includes receiving write requests from a specified storage device; The write request is used for the write address in the send buffer; The data to be written includes data to be sent over the network; The step of writing the write data in the write request to the address corresponding to the write address in the specified cache area includes writing the send data to the address corresponding to the write address in the send cache area.

9. The method according to claim 8, further comprising: Receive a read request from the network card, the read request including the read address in the send buffer; According to the read request, the corresponding data is read from the address corresponding to the read address in the send buffer area and then into the network card.

10. The method according to claim 9, wherein: Receiving a write request from a specified storage device includes receiving a DMA write request from a specified storage device via the PCIe bus; Receiving read requests from the network card includes receiving DMA read requests from the network card via the PCIe bus.

11. A processor, comprising a processor core, an integrated input / output module, and a cache, wherein: The processor core allocates a specified cache area in the cache for a specified thread. The specified thread is used to send and receive data over the network. The specified cache area is used to cache data written to a specified buffer. The specified buffer is created in memory by the specified thread. The integrated input / output module receives a write request, which includes a write address and write data in the specified buffer. The write data includes data that the specified thread wants to send through the network or data that the specified thread receives through the network. For any write request received by the integrated input / output module, the cache writes the write data in the write request to the address corresponding to the write address in the specified cache area according to the correspondence between the address in the specified buffer and the address in the specified cache area, so as to bypass the memory for data transmission and reception. The designated buffer is a receive buffer used to store received data received over the network; The designated buffer area is a receive buffer area corresponding to the receive buffer, used to cache data whose address is written to the receive buffer; The allocation of a specified cache area for a specified thread includes: According to the instruction to load the receive buffer into the cache, a receive buffer area corresponding to the receive buffer is allocated in the cache.

12. An electronic device comprising a processor, memory, network interface card (NIC), and designated storage device as claimed in claim 11, wherein the processor is connected to the memory, the NIC, and the designated storage device.

13. A computer system comprising a plurality of computers, each computer including a processor, memory, network interface card (NIC), and a designated storage device as described in claim 11, wherein the processor is connected to the memory, the NIC, and the designated storage device.

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