A TLB configuration method suitable for a multi-core processor

Abstract

The present application relates to the field of computer data calculation, and specifically relates to an optimization mode of a processor in a virtual memory reading process.The present application is realized by the following technical scheme: a TLB configuration mode suitable for a multi-core processor, comprising the following steps: S01, a TLB arrangement step; the TLB is installed at a position of a common part of a memory access channel; S02, a TLB data format designation step; the table storage format of the TLB in the TLB is designated, the data format of the TLB table comprises segment number data and address difference value data, S03, a mode allocation step; S04, a table entry filling step; S05, a data use step; the present application aims to provide a TLB configuration mode suitable for a multi-core processor, in the state that the processor comprises multiple cores, the TLB construction cost is greatly reduced, and when the TLB segment table information is updated, the number of update filling tasks is effectively reduced, and the reading efficiency of the processor to the main memory is improved.

Description

Technical Field

[0001] This invention relates to the field of computer data computing, and more specifically to optimization methods for processors reading virtual main memory. Background Technology

[0002] Virtual main memory is a fundamental technology for main memory management. When ordinary main memory is insufficient for data processing, virtual main memory is used as an auxiliary storage component. In main memory management, as mentioned in the embedded database storage management method disclosed in Chinese patent document CN200710099762.1, common technologies include paging and segmentation, as well as a combination of both, called segmented paging.

[0003] Segmented memory management uses segmentation, dividing programs and related data into segments. Compared to paged memory management, where main memory is divided into pages of equal size, segmented memory management allows main memory to be divided into segments of varying lengths. Paging is invisible to the programmer, while segmentation is usually visible and dynamic, providing a convenient means for programmers to organize programs and data.

[0004] In multi-core data processing, different functions need to be called frequently, and each function has a different data size. Compared to page-based management, segment-based management is more suitable for this type of environment due to its flexibility in partition length.

[0005] Furthermore, segmented main memory management technology requires a segment table to translate between segmented virtual addresses and physical addresses. Because segments of varying sizes are used, there isn't a simple direct correspondence between virtual and physical addresses; calculations are needed based on information such as the segment number, offset, and segment length of the virtual address. Therefore, each virtual address access may trigger two main memory accesses: one to retrieve the corresponding segment table entry to calculate the physical address, and the other to retrieve the required data. This makes data retrieval complex and inefficient.

[0006] In this context, Chinese patent document CN202210535955.1 discloses a method, apparatus, and storage medium for TLB entry management. TLB stands for Translation Lookaside Buffet. It's a hardware component located on the processor, a special high-speed cache used to store recently used segment table entries. Therefore, when the processor core retrieves data, it doesn't need to perform two main memory accesses; instead, it first reads the segment table information from the TLB to obtain the physical address, and then directly retrieves the actual data from that address.

[0007] However, this solution still has certain drawbacks in multi-core processor applications. In existing technologies, each core requires a separate TLB. On the one hand, when the number of cores is large, such as hundreds or thousands of computing cores, an equal number of TLBs are needed, resulting in high hardware costs. On the other hand, as mentioned earlier, the TLB does not contain a complete segment table, but only the most recently used segment table entries. Therefore, when each TLB needs to update and populate new segment table information, the large number of TLBs also presents a problem of a huge number of update and population tasks, leading to high design complexity and slow operating efficiency. Summary of the Invention

[0008] The purpose of this invention is to provide a TLB configuration method suitable for multi-core processors. When the processor has multiple cores, the TLB construction cost is greatly reduced, and the number of update and fill tasks is effectively reduced when the TLB segment table information is updated, thereby improving the processor's read efficiency from main memory.

[0009] This invention is implemented according to the following technical solution: a TLB configuration method suitable for multi-core processors, comprising the following steps: S01, TLB layout steps; Install the TLB in the common part of the memory access path; S02, TLB data format specification steps; Specify the table storage format of the TLB in the TLB. The data format of the TLB table includes segment number data and address difference data. The segment number data and address difference data are used to determine the starting address of the physical address corresponding to the processor core calculation. S03, Mode Allocation Steps; The TLB table is divided into two modes: private segment and shared segment. The private segment is private to a certain core, and other cores cannot read or write data to this segment. The shared segment is shared by all cores, and all cores can read and write data to this segment. Each core is equipped with one private segment. S04, Table entry filling steps; When the read / write command issued by the core passes through the TLB, the TLB queries the corresponding segment table information in the main memory based on the virtual address information in the read / write command, and fills the segment table information into the TLB table. S05, Data Usage Steps; The TLB calculates the physical address corresponding to the read / write instruction based on the read / write instruction and the segment table information in the TLB table, and the read / write instruction accesses the data at that physical address in main memory.

[0010] As a preferred embodiment of the present invention, in S03, each core is equipped with only one dedicated private segment.

[0011] As a preferred embodiment of the present invention, the address difference exists in two's complement form, with the highest bit processed as a sign bit. The value of the sign bit, whether positive or negative, indicates the direction of the data difference.

[0012] As a preferred embodiment of the present invention, step S04 is implemented in pure hardware, through the circuit design of the TLB itself.

[0013] As a preferred embodiment of the present invention, step S04 is implemented by a combination of hardware and software, using the TLB's own circuitry and assembly language programming.

[0014] As a preferred embodiment of the present invention, in step S02, the table storage format of the TLB includes an offset data format and a segment length format. In step S05, the read / write instruction sent by the core to the TLB includes the offset of the instruction. When the offset is greater than the corresponding length data of the segment recorded in the TLB table, the read / write instruction is determined to be out of bounds, and the TLB issues an error message.

[0015] As a preferred embodiment of the present invention, in S02, the table storage format of the TLB includes an access permission information format, and in S05, the read / write instruction sent by the core to the TLB includes the specific action data of the instruction. When the specific action data contradicts the corresponding access permission of the segment recorded in the TLB table, the read / write instruction is determined to be unauthorized, and the TLB issues an error message.

[0016] As a preferred embodiment of the present invention, the access permissions include read permission, write permission, and execute permission.

[0017] As a preferred embodiment of the present invention, in S02, the table storage format of the TLB includes a valid bit format. When the valid bit of a segment table in the TLB table is marked as invalid, the core does not use the segment table information to calculate the corresponding physical address.

[0018] In summary, the present invention has the following beneficial effects: 1. Therefore, by setting the TLB in the common part of the memory access path, all read and write instructions of each core must go through the TLB. There is no need to set a separate TLB for each core, thus reducing hardware configuration costs.

[0019] 2. Due to the independent design that separates public and private segments, the segment table data corresponding to frequently used functions is located in the shared segment, so that the kernel can obtain it at the TLB without frequently reading and accessing the segment table information in main memory.

[0020] 3. Each core has its own dedicated private area, ensuring that its essential functions reside in the private area and are not overwritten by data from other cores. This avoids having to access main memory again after being overwritten, greatly improving access efficiency.

[0021] 4. Supports dynamic segment table loading using either pure hardware or a combination of hardware and software. When using a combination of hardware and software, hardware overhead can be significantly reduced.

[0022] 5. TLB includes over-authorization judgment, over-boundary judgment, and validity judgment, which further increases the stability and reliability of TLB operation. Attached Figure Description

[0023] Figure 1 This is a diagram illustrating the data format of a TLB table.

[0024] The present invention will now be described in further detail.

[0025] This specific embodiment is merely an explanation of the present invention and is not intended to limit the invention. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but such modifications are protected by patent law as long as they are within the scope of the claims of the present invention.

[0026] Example 1: A TLB configuration method suitable for multi-core processors. The process begins with S01, the TLB placement step. This step determines the physical installation location of the TLB. As mentioned above, the TLB is a hardware component; in this case, the TLB is installed in the common area of ​​the memory access path.

[0027] The memory access path refers to the data link between the processor core and main memory. This data link includes a common part and branch parts. The common part is the link that starts from main memory. There are no branches at this point, and all data exchanges between cores pass through this part. Next are the branch parts, where data reaches different cores through the links of each branch.

[0028] Therefore, the TLB is placed in the published section of the memory access path, ensuring that all read and write instructions from each core must pass through the TLB. It should be noted that, according to current chip design practices, it is common for memory access paths to share a common portion. In extreme cases where all memory access paths are independent and have no common portion, this technical solution is not suitable for that chip.

[0029] S02, TLB data format specification steps.

[0030] The purpose of the TLB (Transmission Block Table) is to translate the virtual addresses in instructions sent by the kernel into physical addresses, allowing the kernel to retrieve data from the corresponding physical addresses. In this case, the TLB data format must include two data formats: segment number and address difference. The segment number is the segment number of the virtual address, and the address difference is the difference between the physical address base address and the virtual address base address (DELTA), usually stored in two's complement form. The kernel can calculate the starting address of the physical address using these two data sets: the segment number and the address difference.

[0031] In practical applications, in order to identify addresses more conveniently and quickly, the highest bit of the address difference data is processed into a sign bit, that is, to indicate whether it is a positive or negative number, thereby indicating the direction of the data difference.

[0032] In this embodiment, as a preferred option, there are also three categories of data information. For example... Figure 1 As shown, there are also three data information categories: "valid bits," "segment length," and "access permissions." Their functions will be explained one by one below.

[0033] S03, Mode Allocation Steps.

[0034] In this step, the segment patterns of the TLB are allocated, divided into two types: private segments and shared segments. Private segments are private to a specific core, and other cores cannot read or write data to that segment. Shared segments, on the other hand, are shared by all cores, and all cores can read and write data to that segment.

[0035] The number of private and shared segments can be flexibly designed and specified by engineers based on specific application scenarios. However, the number of private segments must be guaranteed to be at least one per core, while the number of shared segments can be slightly more as needed to facilitate data storage.

[0036] In this embodiment, as a preferred option, the number of private segments is the same as the number of cores, so that each core has one and only one private segment. For example, in this embodiment, the number of cores is 16, so there are 16 private segments and 5-9 shared segments.

[0037] S04, Table entry filling steps.

[0038] As described above, the TLB table in the hardware can be viewed as a part of the segment table in main memory. For example, the TLB table is a "recently used segment table". Therefore, when power is first turned on, the TLB is empty, and data from the segment table is gradually imported during use, i.e., "table entry filling".

[0039] For example, if the kernel needs to call a function, it will generate a read / write instruction containing a virtual address. The TLB receives this instruction and looks up the segment table data in main memory. The TLB then stores this segment of data from the segment table into the TLB table, populating the entries.

[0040] At this point, the data segment has two possibilities: it can be a private segment or a shared segment. In practice, for commonly used data, such as functions frequently used by various kernels, the corresponding segment table data is populated in the shared segment segment table. For information more specific to each kernel, the corresponding segment table data is populated in the private segment segment table. In actual operation, determining which data segment is designated as a shared or private segment is automatically handled by operating systems like Linux and Unix, without requiring system administrators to write manual code.

[0041] It should be noted that in practical applications, table entry loading can be implemented through pure hardware or a combination of hardware and software. If implemented purely in hardware, it can be achieved through the TLB's own circuit design. If implemented using a combination of hardware and software, table entry loading is performed using the TLB's own circuitry in conjunction with assembly language.

[0042] S05, Data Usage Steps.

[0043] Each core processes data normally, calling functions or programs. A core sends read / write instructions to main memory, containing information about the virtual address of the function or program to be called. When this instruction passes through the TLB, the TLB calculates the actual physical address based on the information stored in the TLB table. The instruction then uses this physical address to read and write main memory data—that is, function data or program data—for normal use.

[0044] Specifically, as mentioned in S02 above, core 1 wants to read function A and has already found the starting address of function A's physical address in main memory in the TLB. The instruction itself records the offset data corresponding to each function. For example, if the offset of function A is 003, then core 1 can accurately and directly read function A based on its physical starting address and offset.

[0045] Furthermore, during the use of the TLB system, if the segment number corresponding to the function that a kernel wants to call already exists in the TLB table, it means that the segment table data has already been stored in the TLB table in step S04 above, which is considered a "hit". At this time, the data use in S05 can proceed normally. If there is a hit, step S04 above is repeated to load the segment table data from main memory into the TLB table.

[0046] As mentioned above, loading supports both pure hardware implementation and a combination of hardware and software. The specific steps are as follows: On the one hand, it supports traditional pure hardware dynamic segment table loading. In the event of a miss, the hardware automatically issues a memory access instruction to retrieve the corresponding entry from main memory, completes the loading, and performs address substitution again.

[0047] On the other hand, it supports dynamic segment table loading via a hardware-software collaborative approach. When a segment miss occurs, the hardware sends the exception to a kernel independent of the TLB table, where the operating system handles the exception. The operating system reads the exception information via I / O. This exception information, including the virtual address and hit status, is also stored in I / O registers. Based on the exception information, the operating system retrieves the corresponding entry from the segment table in main memory, imports it into the kernel running on the operating system, and then loads it into the TLB using I / O.

[0048] In this process, on the one hand, due to the independent design separating public and private segments, the segment table data corresponding to frequently used functions resides in the shared segment. This allows the kernel to obtain the data directly from the TLB, eliminating the need for frequent reads and accesses of segment table information from main memory. Furthermore, each kernel has its own dedicated private area, ensuring that its essential functions reside there, preventing data from being overwritten by other kernels and avoiding the need to access main memory again after overwriting, thus significantly improving access efficiency. On the other hand, because these functions reside in the shared portion of the memory access path, the number of TLBs required is greatly reduced, potentially requiring only one TLB, thus lowering the hardware implementation cost.

[0049] In this embodiment, as a preferred approach, boundary violation detection and unauthorized access detection are also supported.

[0050] As mentioned above, the data format in a TLB table is as follows: Figure 1 As shown, this includes the segment length. The segment length is the length of a segment in main memory. In step S05, the read / write instructions issued by the kernel include offset data. If the offset data is greater than the segment length data, it is determined to be out of bounds, and the TLB issues an error message.

[0051] Unauthorized judgment refers to, for example Figure 1 As shown, the TLB table information contains access permission information, which generally includes three types: readable, writable, and executable. In step S05, the read / write instructions sent by the kernel to the TLB contain specific action data. If this specific action contradicts the access permission, the TLB will deny the kernel access to that data.

[0052] For example, in the previous system detection, the system determined that function B was a Trojan program, so the access permission in the segment table field corresponding to function B was set to "non-executable". At some point later, kernel 3 issued a read / write instruction, which requested the call to function B, but the specific action data was "execute". At this point, the detection body (generally the operating system, i.e., LINUX or UNIX) determined that the read / write instruction was unauthorized and stopped its further execution.

[0053] like Figure 1 As shown, the TLB table also stores a "valid bit" flag, which indicates whether the segment table data is valid and usable. If the valid bit is marked as invalid, it is naturally unusable. This is because storage devices may experience errors at times, such as during malfunctions, power-on, or system crashes, resulting in incorrect segment number data, address differences, segment lengths, etc., in the segment table. In this embodiment, during data filling in S04, after each segment table data is correctly filled, the valid bit of that segment table data is set to valid to prevent the core from reading incorrect or invalid segment table data.

Claims

1. A TLB configuration method suitable for multi-core processors, characterized in that, The process includes the following steps: S01, TLB deployment step; installing the TLB in the common part of the memory access path; S02, TLB data format specification step; specifying the table storage format of the TLB, wherein the TLB table data format includes segment number data and address difference data, which are used to calculate the starting address of the physical address corresponding to the processor core; S03, mode allocation step; the TLB table is divided into two mode types: private segment and shared segment; the private segment is private to a certain core, and other cores cannot read or write data to this segment; the shared segment is shared by all cores, and all cores can read and write data to this segment. Read and write; each core is equipped with a corresponding private segment; the data stored in the shared segment includes functions frequently used by each core; the data stored in the private segment includes exclusive information for each core; S04, table filling step; when the read and write instructions issued by the core pass through the TLB, the TLB queries the corresponding segment table information in the main memory based on the virtual address information in the read and write instructions, and fills the segment table information into the TLB table; S05, data usage step; the TLB calculates the physical address corresponding to the read and write instructions based on the read and write instructions and the segment table information in the TLB table, and the read and write instructions access the data at that physical address in the main memory.

2. The TLB configuration method for multi-core processors according to claim 1, characterized in that: In S03, each core is equipped with only one dedicated private segment.

3. The TLB configuration method for multi-core processors according to claim 1, characterized in that: The address difference exists in two's complement form, with the highest bit processed as a sign bit. The value of the sign bit is either positive or negative, indicating the direction of the data difference.

4. The TLB configuration method for multi-core processors according to claim 1, characterized in that: Step S04 is implemented purely in hardware, through the circuit design of the TLB itself.

5. A TLB configuration method suitable for multi-core processors according to claim 1, characterized in that: Step S04 is implemented through a combination of hardware and software, using the TLB's own circuitry and assembly language programming.

6. The TLB configuration method for multi-core processors according to claim 1, characterized in that: In S02, the TLB's table storage format includes an offset data format and a segment length format. In S05, the read / write instruction sent by the core to the TLB includes the offset of the instruction. When the offset is greater than the corresponding length data of the segment recorded in the TLB table, the read / write instruction is determined to be out of bounds, and the TLB issues an error message.

7. A TLB configuration method suitable for multi-core processors according to claim 1, characterized in that: In S02, the TLB's table storage format includes access permission information format. In S05, the read / write instruction sent by the core to the TLB includes the specific action data of the instruction. When the specific action data contradicts the corresponding access permission recorded in the TLB table for that segment, the read / write instruction is determined to be unauthorized, and the TLB issues an error message.

8. A TLB configuration method suitable for multi-core processors according to claim 7, characterized in that: The access permissions include read permission, write permission, and execute permission.

9. A TLB configuration method suitable for multi-core processors according to claim 1, characterized in that: In S02, the TLB table storage format includes a valid bit format. When the valid bit of a segment table in the TLB table is marked as invalid, the core does not use the segment table information to calculate the corresponding physical address.

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