Bus routing method based on wiring area generation

Abstract

The application provides a bus wiring method based on a wiring area, which is used for bus wiring design of a PCB board. First, the starting pin groups are gathered together on the same bus of the same component and adjacent to each other, so as to improve the efficiency of subsequent wiring. Then, a wiring sequence priority queue of the bus is constructed to determine the wiring sequence of the bus. Then, a uniform grid is constructed according to the position of the starting pin group of the bus and the width of the bus, the A-star algorithm is used to search the path to the ending pin group, and the path is adjusted to obtain a more optimal wiring area. The wiring area of each bus is obtained through the iteration of the distribution of the wiring layer and the disconnection and redistribution. Finally, the final bus wiring result is obtained through detailed wiring design and right-angle removal. The application can improve the efficiency of bus wiring of the PCB board for general application scenarios.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology, and in particular to a bus routing method based on wiring area generation. Background Technology

[0002] A bus is a set of signal bits that connect two or more ends (pins) to transmit data or control signals. With the development of integrated circuit technology, the bus structures on multi-chip modules, I / O pins, and various memories on PCBs are becoming increasingly common. Manual routing is inefficient and increasingly difficult to meet routing needs. Therefore, efficient, high-pass-through-rate, and stable automatic bus routing algorithms have become urgently needed in the industry.

[0003] Traditional routing algorithms mainly focus on net-by-net routing, with little research on bus routing. Compared with bus routing, using net-by-net routing to route buses has the following problems: ① The bus routing topology cannot be kept consistent; ② The routing area is large, lacking compactness and wasting routing resources; ③ The length difference between nets under the same bus cannot be controlled within a certain range, affecting bus signal transmission; ④ Net-by-net routing is not conducive to dismantling and rerouting due to inconsistent net topologies.

[0004] In recent years, several typical bus routing solutions have emerged, mainly including the following: ① Bus ​​routing algorithms based on Directed Acyclic Graphs (DAGs): These algorithms use the LCS (Longest Common Subsequence) bus clustering algorithm to significantly reduce the number of buses, thereby reducing routing complexity; they use a DAG-based topology matching on-rail bus routing algorithm to find the shortest path for each bit of the bus in the DAG, and the resulting path satisfies topology matching constraints; and they use a teardown and rerouting method to reduce routing congestion and spacing conflicts. ② Bus routing algorithms based on multi-level frames: These algorithms can effectively solve practical problems such as minimum spacing and minimum linewidth on irregular track metal layers. The goal is to complete the routing of all buses, maintain the same topology for different bits of the bus, and optimize metrics such as bus line length, number of segments, and compactness. The algorithm mainly includes five steps: bus-based mesh graph (BGG) update, topology-aware path planning (TAP), bit tracking and allocation (TAB), track occupancy update, and teardown and rerouting (RR) scheme. ③ Boolean Satisfiability-Based Bus Routing Algorithm: This algorithm uses an efficient encoding method to encode constraints between objects into clauses and express them as topological Boolean expressions to determine the legality of a set of object spatial positions. Its efficient encoding method significantly reduces the number of clauses. Given a coordinate axis with several discrete positions {1,2,…,} and a set of objects {1,…,}, the SAT solver can be used to determine whether there exists a placement scheme that meets these constraints, and to provide a feasible solution, considering relative position constraints between objects, non-overlapping constraints between objects, and the constraint that all objects must have a place. ④ Bus Routing Algorithm Considering Line Length Matching: This algorithm optimizes routeability, line length, and length matching while simultaneously considering design constraints such as track resources and obstacles. The algorithm mainly includes layout plane partitioning, construction of overall routing diagram, track allocation of pin-access routing segments, using depth-first search (DFS) to search for candidate routing paths for each bus without detours, using breadth-first search (BFS) to detour routing for each failed bus in the previous stage, rerouting buses with spacing conflicts on pin-access routing segments, and minimum-maximum line length difference optimization.

[0005] These bus routing methods are based on routing track information, which is not available in general application scenarios. Moreover, these algorithms may result in long routing times and poor routing performance in certain specific scenarios. Summary of the Invention

[0006] This invention proposes a bus routing method for generating routing areas, which can improve the efficiency of PCB bus routing for general application scenarios.

[0007] The present invention adopts the following technical solution.

[0008] A bus routing method based on routing regions is used for PCB board bus routing design.

[0009] First, the starting pin groups are grouped together on the same boundary and adjacent buses of the same component to improve the efficiency of subsequent routing; then, a routing priority queue is built for the buses to determine the routing order of the buses.

[0010] Then, an evenly divided grid is constructed based on the starting pin group position and bus width of the bus. The path is found to the ending pin group using the A* algorithm. The path is adjusted to obtain a better routing area. The routing area of ​​each bus is obtained through the allocation of routing layers and the iteration of teardown and rerouting.

[0011] Finally, after detailed wiring design and right-angle removal, the final bus wiring result was obtained.

[0012] The method includes the following steps;

[0013] Step S1: Group multiple start and stop pin groups into one bus by multiple buses that are on the same component, have the same boundary, and are adjacent to each other;

[0014] Step S2: Construct a bus routing priority queue based on the bus width, the distance between the start and end pin groups, and custom parameters;

[0015] Step S3: For each bus, construct an evenly divided grid from the starting pin group according to the width determined by the bus width and spacing constraints, and use the A* algorithm to find the path to the ending pin group. Improve the path finding efficiency by constructing a coarse-grained grid.

[0016] Step S4: Maintain the initial path found by the A* algorithm through a series of turning points, and adjust the routing area path as much as possible to avoid affecting the routing of other buses.

[0017] Step S5: Change the layer of buses that cannot be routed or the segments of the path that intersect with other bus paths.

[0018] Step S6: For buses that cannot be routed even after changing layers, remove other buses affecting their routing on the selected layer, regenerate the routing area, and continue until all buses are routed.

[0019] Step S7: Perform detailed routing in the obtained bus routing area;

[0020] Step S8: Adjust all right-angled wiring paths to 135°.

[0021] In step S1, the bus aggregation method is as follows: multiple buses with start and stop pin groups located in the same component, on the same boundary and adjacent to each other are aggregated together and treated as a single bus for subsequent processing. By aggregating multiple buses into one bus, the number of buses to be deployed is reduced, and the bus width is increased by aggregating to increase the width of the evenly distributed grid, thereby improving the efficiency of evenly distributed grid construction and the pathfinding efficiency of the subsequent A* algorithm.

[0022] In step S2, a bus routing priority queue is constructed based on the number of bus nets, the distance between the start and end pin groups of the bus, and custom parameters. The bus priority Qbus is calculated as follows:

[0023] Q bus =α*N net +β*D pin +ω*C user Formula 1;

[0024] Where Nnet represents the number of bus nets, Dpin represents the distance between the start and end pin groups of the bus, and C is a custom value. user The parameters are user-defined, with α, β, and ω being preset fixed weights.

[0025] The specific method of step S3 is as follows: Construct an evenly divided grid for each bus. The grid width is determined by the bus width and spacing constraints of the starting pin group. Extend from the starting pin group to the entire PCB board. Select the grid with the largest overlap area with the ending pin group from the evenly divided grid as the ending grid for pathfinding. Use the A* pathfinding algorithm to obtain the shortest path from the starting grid to the ending grid. Add a penalty function for the distance of the path from the PCB board assembly to the heuristic function of the A* algorithm to reduce the impact of the penalty function on the heuristic function value. This ensures that the path is as short as possible while staying away from the PCB board assembly, and that the path reduces the impact on other bus routing.

[0026] If the bus width differs significantly from the PCB size and the difference exceeds a threshold, coarse-grained evenly divided grid pathfinding is used to improve the efficiency of the A* algorithm in searching paths. The previous evenly divided grid width is replaced by the coarse-grained evenly divided grid width. During the pathfinding process, the previously determined grid width is still used to determine whether a path with a fine-grained grid width is allowed to pass through the coarse-grained grid, thereby improving the path search efficiency of the A* algorithm and quickly obtaining the path from the starting pin group to the ending pin group.

[0027] The specific method for step S4 is as follows: The path finding path obtained by the A* algorithm in step S3 is maintained by a series of evenly divided grid turning grids, and the initial bus routing area is obtained by adjusting the position of the turning grids; the routing path adjustment in this step avoids the bus path from affecting other bus routing paths by adjusting the position of the turning points or adding or deleting turning points; the turning points are used to avoid the situation where the start and end paths are close to the component boundaries, causing other bus routing paths to be blocked and unable to be routed on the same layer; the turning point positions of the intermediate path segments are adjusted to avoid the situation where the intermediate path segments are close to the component boundaries.

[0028] The specific method of step S5 is as follows: each bus uses the layer where it escapes from the component as the initial layer allocation. When searching for the routing area, it determines whether to perform layer-changing routing based on the routing situation of the initial layer. After generating the routing area, the routing path segment that needs to be layer-changed is processed according to the overlap of the routing path with the routing path of other buses in this layer.

[0029] The specific method of step S6 is as follows: If, after step S5, there are still buses that cannot be routed by changing layers, and each layer is blocked by other buses that prevent them from being routed, then the problem is solved by disconnecting and rerouting. When disconnecting and rerouting, the wiring areas of other buses that affect the routing of the bus need to be removed in the layer that needs to be disconnected and rerouted, and the wiring areas are regenerated until all buses are routed.

[0030] The method in step S7 is as follows: perform detailed routing in the routing area determined for each bus, ensure that the net spacing and the distance between the net and the boundary of the routing area meet the spacing constraints during detailed routing, and determine whether the net order needs to be changed after changing layers in the middle of detailed routing.

[0031] In step S8, a right-angle removal operation is performed to adjust all right-angled net traces to 135° to reduce signal interference. Specifically, when routing, the distance between the corner removal point and the right-angle inflection point needs to be determined according to actual needs, so that the net traces will not cross with other net traces after the right angle removal, and the distance with other net traces can meet the spacing constraints of the layer.

[0032] This invention designs an automatic bus routing algorithm for general application scenarios to solve the PCB board bus routing problem, thereby improving the efficiency of PCB board bus routing. Its advantages are:

[0033] (1) Constructing a uniformly divided grid for each bus, and determining the grid width based on the bus width, although slightly increasing the construction cost compared to traditional one-time mapping, can accurately generate routing areas for each bus. Furthermore, one-time mapping, due to the difficulty in determining the grid granularity, can lead to unstable routing results, potentially resulting in significant differences in performance when dealing with bus routing on PCBs of different sizes. Simultaneously, constructing a coarse-grained uniformly divided grid can significantly reduce the construction time cost and greatly improve the pathfinding speed of the A* algorithm.

[0034] (2) The routing path adjustment is the core of the whole problem. This invention maintains the routing path of a bus through a series of turning points, which can be flexibly adjusted. It can not only solve the problem that the routing result of the A* algorithm may be close to the component boundary, causing other buses to be unable to be routed, but also make the routing area more concentrated through the path adjustment strategy, thus saving routing space and resources.

[0035] (3) The bus routing sequence priority strategy proposed in this invention determines the bus routing sequence based on a priority list that combines the number of bus nets, the distance between the start and end pin groups, and the custom weights. Due to the existence of custom weights, the bus routing sequence can be flexibly adjusted to achieve the effect of speeding up routing and optimizing routing results. Attached Figure Description

[0036] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0037] Appendix Figure 1 This is a flowchart illustrating the present invention;

[0038] Appendix Figure 2 This is a schematic diagram of constructing a uniformly divided grid;

[0039] Appendix Figure 3 This is a schematic diagram of constructing a coarse-grained mesh;

[0040] Appendix Figure 4 This is a schematic diagram of the wiring path before and after the path adjustment in step S4;

[0041] Appendix Figure 5 This is a schematic diagram of detailed wiring in the wiring area in step S7. Detailed Implementation

[0042] As shown in the figure, the bus routing method based on routing regions is used for PCB board bus routing design.

[0043] First, the starting pin groups are grouped together on the same boundary and adjacent buses of the same component to improve the efficiency of subsequent routing; then, a routing priority queue is built for the buses to determine the routing order of the buses.

[0044] Then, an evenly divided grid is constructed based on the starting pin group position and bus width of the bus. The path is found to the ending pin group using the A* algorithm. The path is adjusted to obtain a better routing area. The routing area of ​​each bus is obtained through the allocation of routing layers and the iteration of teardown and rerouting.

[0045] Finally, after detailed wiring design and right-angle removal, the final bus wiring result was obtained.

[0046] The method includes the following steps;

[0047] Step S1: Group multiple start and stop pin groups into one bus by multiple buses that are on the same component, have the same boundary, and are adjacent to each other;

[0048] Step S2: Construct a bus routing priority queue based on the bus width, the distance between the start and end pin groups, and custom parameters;

[0049] Step S3: For each bus, construct an evenly divided grid from the starting pin group according to the width determined by the bus width and spacing constraints, and use the A* algorithm to find the path to the ending pin group. Improve the path finding efficiency by constructing a coarse-grained grid.

[0050] Step S4: Maintain the initial path found by the A* algorithm through a series of turning points, and adjust the routing area path as much as possible to avoid affecting the routing of other buses.

[0051] Step S5: Change the layer of buses that cannot be routed or the segments of the path that intersect with other bus paths.

[0052] Step S6: For buses that cannot be routed even after changing layers, remove other buses affecting their routing on the selected layer, regenerate the routing area, and continue until all buses are routed.

[0053] Step S7: Perform detailed routing in the obtained bus routing area;

[0054] Step S8: Adjust all right-angled wiring paths to 135°.

[0055] In step S1, the bus aggregation method is as follows: multiple buses with start and stop pin groups located in the same component, on the same boundary and adjacent to each other are aggregated together and treated as a single bus for subsequent processing. By aggregating multiple buses into one bus, the number of buses to be deployed is reduced, and the bus width is increased by aggregating to increase the width of the evenly distributed grid, thereby improving the efficiency of evenly distributed grid construction and the pathfinding efficiency of the subsequent A* algorithm.

[0056] In step S2, a bus routing priority queue is constructed based on the number of bus nets, the distance between the start and end pin groups of the bus, and custom parameters. The bus priority Qbus is calculated as follows:

[0057] Q bus =α*N net +β*D pin +ω*C user Formula 1;

[0058] Where Nnet represents the number of bus nets, Dpin represents the distance between the start and end pin groups of the bus, and C is a custom value. user The parameters are user-defined, with α, β, and ω being preset fixed weights.

[0059] The specific method of step S3 is as follows: Construct an evenly divided grid for each bus. The grid width is determined by the bus width and spacing constraints of the starting pin group. Extend from the starting pin group to the entire PCB board. Select the grid with the largest overlap area with the ending pin group from the evenly divided grid as the ending grid for pathfinding. Use the A* pathfinding algorithm to obtain the shortest path from the starting grid to the ending grid. Add a penalty function for the distance of the path from the PCB board assembly to the heuristic function of the A* algorithm to reduce the impact of the penalty function on the heuristic function value. This ensures that the path is as short as possible while staying away from the PCB board assembly, and that the path reduces the impact on other bus routing.

[0060] If the bus width differs significantly from the PCB size and the difference exceeds a threshold, coarse-grained evenly divided grid pathfinding is used to improve the efficiency of the A* algorithm in searching paths. The previous evenly divided grid width is replaced by the coarse-grained evenly divided grid width. During the pathfinding process, the previously determined grid width is still used to determine whether a path with a fine-grained grid width is allowed to pass through the coarse-grained grid, thereby improving the path search efficiency of the A* algorithm and quickly obtaining the path from the starting pin group to the ending pin group.

[0061] The specific method for step S4 is as follows: The path finding path obtained by the A* algorithm in step S3 is maintained by a series of evenly divided grid turning grids, and the initial bus routing area is obtained by adjusting the position of the turning grids; the routing path adjustment in this step avoids the bus path from affecting other bus routing paths by adjusting the position of the turning points or adding or deleting turning points; the turning points are used to avoid the situation where the start and end paths are close to the component boundaries, causing other bus routing paths to be blocked and unable to be routed on the same layer; the turning point positions of the intermediate path segments are adjusted to avoid the situation where the intermediate path segments are close to the component boundaries.

[0062] The specific method of step S5 is as follows: each bus uses the layer where it escapes from the component as the initial layer allocation. When searching for the routing area, it determines whether to perform layer-changing routing based on the routing situation of the initial layer. After generating the routing area, the routing path segment that needs to be layer-changed is processed according to the overlap of the routing path with the routing path of other buses in this layer.

[0063] The specific method of step S6 is as follows: If, after step S5, there are still buses that cannot be routed by changing layers, and each layer is blocked by other buses that prevent them from being routed, then the problem is solved by disconnecting and rerouting. When disconnecting and rerouting, the wiring areas of other buses that affect the routing of the bus need to be removed in the layer that needs to be disconnected and rerouted, and the wiring areas are regenerated until all buses are routed.

[0064] The method in step S7 is as follows: perform detailed routing in the routing area determined for each bus, ensure that the net spacing and the distance between the net and the boundary of the routing area meet the spacing constraints during detailed routing, and determine whether the net order needs to be changed after changing layers in the middle of detailed routing.

[0065] In step S8, a right-angle removal operation is performed to adjust all right-angled net traces to 135° to reduce signal interference. Specifically, when routing, the distance between the corner removal point and the right-angle inflection point needs to be determined according to actual needs, so that the net traces will not cross with other net traces after the right angle removal, and the distance with other net traces can meet the spacing constraints of the layer.

Claims

1. A bus routing method based on routing area generation, used for PCB board bus routing design, characterized in that: First, the starting pin groups are grouped together on the same boundary and adjacent buses of the same component to improve the efficiency of subsequent routing; then, a routing priority queue is built for the buses to determine the routing order of the buses. Then, an evenly divided grid is constructed based on the starting pin group position and bus width of the bus. The path is found to the ending pin group using the A* algorithm. The path is adjusted to obtain a better routing area. The routing area of ​​each bus is obtained through the allocation of routing layers and the iteration of teardown and rerouting. Finally, after detailed routing design and right-angle removal, the final bus routing result was obtained; The method Includes the following steps; Step S1: Group multiple starting pin groups into one bus by multiple buses that are on the same component, have the same boundary, and are adjacent to each other; Step S2: Construct a bus routing priority queue based on the bus width, the distance between the start and end pin groups, and custom parameters; Step S3: For each bus, construct an evenly divided grid from the starting pin group according to the width determined by the bus width and spacing constraints, and use the A* algorithm to find the path to the ending pin group. Improve the path finding efficiency by constructing a coarse-grained grid. Step S4: Maintain the initial path found by the A* algorithm through a series of turning points, and avoid affecting the routing of other buses by adjusting the routing area path. Step S5: Change the layer of buses that cannot be routed or the segments of the path that intersect with other bus paths. Step S6: For buses that cannot be routed even after changing layers, remove other buses affecting their routing on the selected layer, regenerate the routing area, and continue until all buses are routed. Step S7: Perform detailed routing in the obtained bus routing area; Step S8: Adjust all right-angled wiring paths to 135°.

2. The bus routing method based on routing region generation according to claim 1, characterized in that: In step S1, the bus aggregation method is as follows: multiple buses with start and stop pin groups located in the same component, on the same boundary and adjacent to each other are aggregated together and treated as a single bus for subsequent processing. By aggregating multiple buses into one bus, the number of buses to be deployed is reduced, and the bus width is increased by aggregating to increase the width of the evenly distributed grid, thereby improving the efficiency of evenly distributed grid construction and the pathfinding efficiency of the subsequent A* algorithm.

3. The bus routing method based on routing region generation according to claim 1, characterized in that: In step S2, a bus routing priority queue is constructed based on the number of bus nets, the distance between the start and end pin groups of the bus, and custom parameters. The bus priority Qbus is calculated as follows: Formula 1; Where Nnet represents the number of bus nets, and Dpin represents the distance between the start and end pin groups of the bus (customizable). Allow users to customize parameters. These are preset fixed weights.

4. The bus routing method based on routing region generation according to claim 1, characterized in that: The specific method of step S3 is as follows: Construct an evenly divided grid for each bus. The grid width is determined by the bus width and spacing constraints of the starting pin group. Extend from the starting pin group to the entire PCB board. Select the grid with the largest overlap area with the ending pin group from the evenly divided grid as the ending grid for pathfinding. Use the A* pathfinding algorithm to obtain the shortest path from the starting grid to the ending grid. Add a penalty function for the distance of the path from the PCB board assembly to the heuristic function of the A* algorithm to reduce the impact of the penalty function on the heuristic function value. This ensures that the path is as short as possible while staying away from the PCB board assembly, and that the path reduces the impact on other bus routing. If the difference between the bus width and the PCB size is greater than a threshold, coarse-grained evenly divided grid pathfinding is used to improve the efficiency of the A* algorithm in searching for paths. The previous evenly divided grid width is replaced by the coarse-grained evenly divided grid width. During the pathfinding process, the previously determined grid width is still used to determine whether the path with the fine-grained grid width is allowed to pass through the coarse-grained grid, so as to improve the path search efficiency of the A* algorithm and quickly obtain the path from the starting pin group to the ending pin group.

5. The bus routing method based on routing region generation according to claim 4, characterized in that: The specific method for step S4 is as follows: The path finding path obtained by the A* algorithm in step S3 is maintained by a series of evenly divided grid turning grids, and the initial bus routing area is obtained by adjusting the position of the turning grids; the routing path adjustment in this step avoids the bus path from affecting other bus routing paths by adjusting the position of the turning points or adding or deleting turning points; the turning points are used to avoid the situation where the start and end paths are close to the component boundaries, causing other bus routing paths to be blocked and unable to be routed on the same layer; the turning point positions of the intermediate path segments are adjusted to avoid the situation where the intermediate path segments are close to the component boundaries.

6. The bus routing method based on routing region generation according to claim 1, characterized in that: The specific method of step S5 is as follows: each bus uses the layer where it escapes from the component as the initial layer allocation. When searching for the routing area, it determines whether to perform layer-changing routing based on the routing situation of the initial layer. After generating the routing area, the routing path segment that needs to be layer-changed is processed according to the overlap of the routing path with the routing path of other buses in this layer.

7. The bus routing method based on routing region generation according to claim 6, characterized in that: The specific method of step S6 is as follows: If, after step S5, there are still buses that cannot be routed by changing layers, and each layer is blocked by other buses that prevent them from being routed, then the problem is solved by disconnecting and rerouting. When disconnecting and rerouting, the wiring areas of other buses that affect the routing of the bus need to be removed in the layer that needs to be disconnected and rerouted, and the wiring areas are regenerated until all buses are routed.

8. The bus routing method based on routing region generation according to claim 1, characterized in that: The method in step S7 is as follows: perform detailed routing in the routing area determined for each bus, ensure that the net spacing and the distance between the net and the boundary of the routing area meet the spacing constraints during detailed routing, and determine whether the net order needs to be changed after changing layers in the middle of detailed routing.

9. The bus routing method based on routing region generation according to claim 1, characterized in that: In step S8, a right-angle removal operation is performed to adjust all right-angled net traces to 135° to reduce signal interference. Specifically, when routing, the distance between the corner removal point and the right-angle inflection point needs to be determined according to actual needs, so that the net traces will not cross with other net traces after the right angle removal, and the distance with other net traces can meet the spacing constraints of the layer.

Images