Display device

Abstract

Disclosed are display apparatuses. The display apparatus of the present invention includes a pixel unit including a plurality of first pixels displaying a first color and a data driver supplying a plurality of first data voltages to the plurality of first pixels. The data driver includes a first master gamma block including a plurality of first master amplifiers generating a plurality of first reference gamma voltages, a first slave gamma block generating a plurality of first gamma voltages by dividing the plurality of first reference gamma voltages, and a first decoder supplying some of the plurality of first gamma voltages as the plurality of first data voltages, and each of the plurality of first master amplifiers is enabled or disabled based on a maximum brightness of the pixel unit.

Description

[0001] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2021-0048083, filed on April 13, 2021, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This invention relates to display devices. Background Technology

[0003] With the development of information technology, the importance of display devices as the connection medium between users and information has been widely recognized. Accordingly, display devices such as liquid crystal displays, organic light-emitting diode displays, and the like are widely used in various fields.

[0004] Display devices typically include multiple pixels, and each pixel can display an image by emitting light based on a received data voltage. The data driver of the display device can pre-generate a gamma voltage corresponding to the brightness scheme and can provide a gamma voltage corresponding to the grayscale as a data voltage. Summary of the Invention

[0005] The embodiments of the present invention aim to provide a display device capable of reducing power consumption when generating gamma voltage.

[0006] An embodiment of the display device according to the present invention includes a pixel unit comprising a plurality of first pixels displaying a first color and a data driver supplying a plurality of first data voltages to the plurality of first pixels. In such an embodiment, the data driver includes a first master gamma block comprising a plurality of first master amplifiers generating a plurality of first reference gamma voltages, a first slave gamma block generating a plurality of first gamma voltages by dividing the plurality of first reference gamma voltages, and a first decoder providing some of the plurality of first gamma voltages as a plurality of first data voltages, wherein each of the plurality of first master amplifiers is enabled or disabled based on the maximum brightness of the pixel unit.

[0007] In one implementation, when the maximum brightness is set to a first maximum brightness, u of the plurality of first main amplifiers are enabled and the remaining first main amplifiers are disabled, where u is an integer greater than 0. In another implementation, when the maximum brightness is set to a second maximum brightness different from the first maximum brightness, v of the plurality of first main amplifiers are enabled and the remaining first main amplifiers are disabled, where v is an integer greater than u.

[0008] In an implementation, the second maximum brightness may be greater than the first maximum brightness.

[0009] In an implementation, the first master gamma block may further include a first multiplexer that provides an input voltage selected from at least one of a plurality of first master amplifiers based on a first gamma code applied thereto.

[0010] In one implementation, the first master gamma block may further include a second multiplexer that provides an input voltage selected from at least one of a plurality of first master amplifiers based on a second gamma code applied thereto.

[0011] In the implementation, the first gamma code under the first maximum brightness and the first gamma code under the second maximum brightness can be the same as each other, and the second gamma code under the first maximum brightness and the second gamma code under the second maximum brightness can be different from each other.

[0012] In one implementation, the input voltage provided by the second multiplexer at the first maximum brightness can be greater than the input voltage provided by the second multiplexer at the second maximum brightness.

[0013] In one embodiment, the display device may further include a memory storing a lookup table, and the lookup table may record the enabled or disabled state of each of a plurality of first main amplifiers corresponding to the level of maximum brightness.

[0014] In an implementation, the first slave gamma block may include a plurality of first slave amplifiers respectively connected to a plurality of first master amplifiers, and when one of the plurality of first master amplifiers is enabled or disabled, a corresponding one of the plurality of first slave amplifiers may be enabled or disabled together, and the corresponding one of the plurality of first slave amplifiers is connected to that one of the plurality of first master amplifiers.

[0015] In an embodiment, the display device may further include a memory storing a lookup table, and the lookup table may record the enabled or disabled state of each of a plurality of first main amplifiers and a plurality of first slave amplifiers corresponding to the level of maximum brightness.

[0016] In an embodiment, the display device may further include a timing controller containing a memory, wherein the timing controller may refer to a lookup table to provide enable / disable information corresponding to the level of maximum received brightness to a data driver, and each of the first main amplifier and the first slave amplifier may be enabled or disabled according to the enable / disable information.

[0017] In an embodiment, the display device may further include a memory storing a lookup table, and the lookup table may record the enabled or disabled state of each of the first master amplifier and the first slave amplifier corresponding to the gamma code level.

[0018] In an embodiment, the display device may further include a timing controller that provides gamma code corresponding to the level of maximum brightness received therefrom to a data driver, and the data driver may include a memory, and each of the first master amplifier and the first slave amplifier may be enabled or disabled with reference to the level of the gamma code and a lookup table.

[0019] In one embodiment, the pixel unit further includes a plurality of second pixels displaying a second color different from the first color, and a plurality of third pixels displaying a third color different from the first and second colors. In such an embodiment, a data driver can supply a plurality of second data voltages to a plurality of second pixels and a plurality of third data voltages to a plurality of third pixels, and the data driver may include a first sub-driver, a second sub-driver, and a third sub-driver. In such an embodiment, the first sub-driver may include a first master gamma block, a first slave gamma block, a second slave gamma block, a third slave gamma block, and a first decoder. In such an embodiment, the second slave gamma block can divide a plurality of second reference gamma voltages to generate a plurality of second gamma voltages, the third slave gamma block can divide a plurality of third reference gamma voltages to generate a plurality of third gamma voltages, and the first decoder can provide some of the plurality of second gamma voltages as a plurality of second data voltages and some of the plurality of third gamma voltages as a plurality of third data voltages.

[0020] In one implementation, the second sub-driver may include a second master gamma block, a fourth slave gamma block, a fifth slave gamma block, a sixth slave gamma block, and a second decoder. In this implementation, the second master gamma block may generate a plurality of second reference gamma voltages. In this implementation, the fourth slave gamma block may divide a plurality of first reference gamma voltages to generate a plurality of first gamma voltages, the fifth slave gamma block may divide a plurality of second reference gamma voltages to generate a plurality of second gamma voltages, and the sixth slave gamma block may divide a plurality of third reference gamma voltages to generate a plurality of third gamma voltages. In this implementation, the second decoder may provide some of the plurality of first gamma voltages as a plurality of first data voltages, some of the plurality of second gamma voltages as a plurality of second data voltages, and some of the plurality of third gamma voltages as a plurality of third data voltages.

[0021] In one implementation, the third sub-driver may include a third master gamma block, a seventh slave gamma block, an eighth slave gamma block, a ninth slave gamma block, and a third decoder. In such an implementation, the third master gamma block may generate multiple third reference gamma voltages. In such an implementation, the seventh slave gamma block may divide multiple first reference gamma voltages to generate multiple first gamma voltages, the eighth slave gamma block may divide multiple second reference gamma voltages to generate multiple second gamma voltages, and the ninth slave gamma block may divide multiple third reference gamma voltages to generate multiple third gamma voltages. In such an implementation, the third decoder may provide some of the multiple first gamma voltages as first data voltages, some of the multiple second gamma voltages as multiple second data voltages, and some of the multiple third gamma voltages as multiple third data voltages.

[0022] In one embodiment, the first sub-driver may further include a first output buffer that provides the output of the first decoder to the pixel unit. In such an embodiment, the second sub-driver may further include a second output buffer that provides the output of the second decoder to the pixel unit, and the third sub-driver may further include a third output buffer that provides the output of the third decoder to the pixel unit.

[0023] In an implementation, the data lines connected to the first output buffer, the data lines connected to the second output buffer, and the data lines connected to the third output buffer may be different from each other.

[0024] In one implementation, the pixels connected to the first output buffer, the pixels connected to the second output buffer, and the pixels connected to the third output buffer may be different from each other.

[0025] In one implementation, the first power input terminal of each of the first main amplifiers is connected to a switch, and each of the first main amplifiers can be disabled when the switch is off and enabled when the switch is on. Attached Figure Description

[0026] The above and other features of the present invention will become more apparent from a further detailed description of embodiments of the invention with reference to the accompanying drawings, in which:

[0027] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present invention;

[0028] Figure 2 This is a diagram illustrating pixels according to an embodiment of the present invention;

[0029] Figure 3 It is shown Figure 2 A diagram illustrating an implementation method for driving pixels;

[0030] Figure 4This is a diagram illustrating a data driver according to an embodiment of the present invention;

[0031] Figure 5A This is a diagram illustrating the master gamma block and slave gamma block according to an embodiment of the present invention;

[0032] Figure 5B yes Figure 5A A magnified view of the portion;

[0033] Figure 6 This is a diagram illustrating a sub-driver of a data driver according to an embodiment of the present invention;

[0034] Figures 7 to 10 This is a diagram illustrating a lookup table according to an embodiment of the present invention;

[0035] Figure 11 This is a diagram illustrating a display device according to an alternative embodiment of the present invention; and

[0036] Figure 12 This is a diagram illustrating a lookup table according to an alternative embodiment of the invention. Detailed Implementation

[0037] The invention will now be described more fully below with reference to the accompanying drawings, which illustrate various embodiments. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout this specification, similar reference numerals refer to similar elements.

[0038] It will be understood that when an element is referred to as being "on" another element, the element can be directly on the other element, or there can be an intermediary element between them. Conversely, when an element is referred to as being "directly" on another element, there is no intermediary element.

[0039] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, the first “element,” “component,” “area,” “layer,” or “part” discussed below can be referred to as a second element, component, area, layer, or part without departing from the teachings of this document.

[0040] The technical terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. Unless the context clearly indicates otherwise, the terms “a,” “an,” “the,” and “at least one,” as used herein, do not indicate a limitation of quantity and are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, “element” has the same meaning as “at least one element.” “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that when the terms “comprises” and / or “comprising” or “includes” and / or “including” are used in this specification, they indicate the presence of the stated features, areas, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, areas, integers, steps, operations, elements, components and / or clusters thereof.

[0041] Furthermore, relative terms such as “below” or “bottom” and “above” or “top” may be used herein to describe the relationship between one element and another as shown in the figures. It will be understood that, in addition to the orientations shown in the figures, the relative terms are also intended to cover different orientations of the device. For example, if a device in one of the figures is flipped, an element described as being “below” the other elements will subsequently be oriented “above” the other elements. Thus, the term “below” can cover both “below” and “above” orientations depending on the specific orientation of the figure. Similarly, if a device in one of the figures is flipped, an element described as being “below” or “below” the other elements will subsequently be oriented “above” the other elements. Thus, the term “below” or “below” can cover both “above” and “below” orientations.

[0042] Taking into account the errors associated with measurements and a particular number of measurements (i.e., limitations of the measurement system), the terms "about" or "approximately" as used herein include the stated values ​​and mean within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0043] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms, such as those defined in common dictionaries, shall be interpreted as having the same meaning as they have in the context of the relevant art and of this disclosure, and shall not be interpreted in an idealized or overly formal sense.

[0044] Furthermore, the size and thickness of each component shown in the figures are arbitrarily depicted for ease of description. Thicknesses may be exaggerated in the figures to clearly represent layers and regions. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of regions as shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For instance, regions shown or described as flat may generally have rough and / or non-linear characteristics. Additionally, sharp corners shown may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to show precise shapes of regions, nor are they intended to limit the scope of the claims.

[0045] Furthermore, in the description, the phrase "identical" can mean "substantially identical." That is, the phrase "identical" means sufficiently identical to convince a person skilled in the art that they are identical. In other expressions, "substantially" may be omitted.

[0046] In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0047] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present invention.

[0048] Reference Figure 1 According to an embodiment of the display device 10 of the present invention, it may include a timing controller 11, a data driver 12, a scan driver 13, an emission driver 14, and a pixel unit 15.

[0049] The timing controller 11 can receive grayscale GRAY1 and control signals for each input image (frame) from an external device, such as a processor.

[0050] Maximum brightness (DBV) can be the brightness information of light emitted from a pixel when it is set to maximum grayscale. In one embodiment, for example, maximum brightness (DBV) can be the brightness of white light generated when all pixels of pixel unit 15 emit light corresponding to white grayscale. The unit of brightness can be nits or candela per square meter (cd / m²). 2The maximum brightness (DBV) can be referred to as the display brightness value. The maximum brightness (DBV) can be manually set by the user's operation of the display device 10, or automatically set by an algorithm linked to an illuminance sensor or the like. In one embodiment, for example, the maximum value of the maximum brightness (DBV) can be approximately 1200 nits, and the minimum value can be approximately 4 nits. The maximum and minimum values ​​of the maximum brightness (DBV) can be set differently based on the product. Even when the grayscale values ​​are the same, the brightness of the light emitted by the pixels can vary or differ from each other because the data voltage changes according to the maximum brightness (DBV).

[0051] In one embodiment, timing controller 11 may provide grayscale GRAY2, generated by compensating for grayscale GRAY1, to data driver 12. In one embodiment, for example, the driving transistors and light-emitting elements of the pixels may have process variations and degradation variations. In one embodiment, timing controller 11 may generate grayscale GRAY2 by compensating for grayscale GRAY1 to compensate for at least one of such variations. In one embodiment, timing controller 11 may generate grayscale GRAY2 by spatially / temporally rendering grayscale GRAY1. In one embodiment, timing controller 11 may provide grayscale GRAY2, equivalent to grayscale GRAY1, to data driver 12.

[0052] The timing controller 11 can provide control signals suitable for each specification to the data driver 12, scan driver 13 and transmit driver 14 to display the input image.

[0053] In one implementation, the timing controller 11 may provide a gamma code GMCD to the data driver 12. In one implementation, for example, the timing controller 11 may provide a gamma code GMCD corresponding to the received maximum brightness (DBV) to the data driver 12. When the received maximum brightness (DBV) is high, the range of gamma voltages (the difference between the maximum and minimum gamma voltages) is set wide. Conversely, when the received maximum brightness (DBV) is low, the range of gamma voltages is set narrow. The gamma code GMCD may be a set value for such a range of gamma voltages.

[0054] In one implementation, timing controller 11 may provide enable / disable information EN / DIS to data driver 12. In one implementation, for example, timing controller 11 may include memory 11MEM, and memory 11MEM may store a lookup table. In one implementation, the enable or disable state of the main amplifier corresponding to the level of maximum brightness DBV may be recorded in the lookup table. In such an implementation, the enable / disable information EN / DIS may be an instruction for the enable or disable state of the main amplifier corresponding to the level of received maximum brightness DBV. In an alternative implementation, the enable or disable states of both the main amplifier and the slave amplifier corresponding to the level of maximum brightness DBV may be recorded in the lookup table. In such an implementation, the enable / disable information EN / DIS may be an instruction for the enable or disable state of both the main amplifier and the slave amplifier corresponding to the level of received maximum brightness DBV.

[0055] Pixel unit 15 may include multiple pixels. Multiple pixels can display the input image. Each pixel PXij can be connected to a corresponding data line, a corresponding scan line, and a corresponding emission line.

[0056] Pixel unit 15 may include a first pixel, a second pixel, and a third pixel. The first pixel may display a first color, the second pixel may display a second color, and the third pixel may display a third color. In one embodiment, for example, the first pixel may include a light-emitting element of the first color, the second pixel may include a light-emitting element of the second color, and the third pixel may include a light-emitting element of the third color. The first color, the second color, and the third color may be different from each other. In one embodiment, for example, the first color may be one of red, green, and blue. The second color may be one of red, green, and blue other than the first color. The third color may be one of red, green, and blue other than the first and second colors. In an alternative embodiment, the first to third colors may be magenta, cyan, and yellow.

[0057] Data driver 12 can use grayscale GRAY2, gamma code GMCD, and enable / disable information EN / DIS to generate data voltages to be provided to data lines DL1, DL2, DL3, ..., DLn. In one embodiment, for example, data driver 12 can sample grayscale using a clock signal and apply data voltages corresponding to grayscale to data lines DL1 through DLn on a pixel row basis (e.g., pixels connected to the same scan line), where n can be an integer greater than 0.

[0058] The data driver 12 can supply a first data voltage to a first pixel, a second data voltage to a second pixel, and a third data voltage to a third pixel.

[0059] The scan driver 13 can receive a clock signal, a scan start signal and similar signals from the timing controller 11, and generate scan signals to be provided to scan lines SL0, SL1, SL2, ... and SLm, where m can be an integer greater than 0.

[0060] Scan driver 13 can sequentially supply on-level scan signals to scan lines SL0 to SLm. Scan driver 13 may include scan stages configured as shift registers. Scan driver 13 can generate scan signals by sequentially transmitting on-level scan start signals to the next scan stage under the control of a clock signal.

[0061] Transmit driver 14 can receive clock signals, transmit stop signals, and similar signals from timing controller 11 to generate transmit signals to be provided to transmit lines EL1, EL2, EL3, ..., ELo, where Lo can be an integer greater than 0. In one embodiment, for example, transmit driver 14 can sequentially provide off-level transmit signals to transmit lines EL1 through ELo. In one embodiment, for example, the transmit stages of transmit driver 14 can be configured as shift registers, and transmit signals can be generated by sequentially transmitting off-level transmit stop signals to the next transmit stage under the control of a clock signal. In an alternative embodiment, transmit driver 14 can be omitted depending on the circuit configuration of pixel PXij.

[0062] Figure 2 This is a diagram illustrating pixels according to an embodiment of the present invention.

[0063] Reference Figure 2 The implementation of pixel PXij may include transistors T1, T2, T3, T4, T5, T6 and T7 (e.g., first transistor T1 to seventh transistor T7), storage capacitor Cst and light-emitting element LD.

[0064] For ease of description, an embodiment of the pixel PXij having a circuit structure composed of P-type transistors will be described in detail below. However, those skilled in the art can design a circuit composed of N-type transistors by changing the polarity of the voltage applied to the gate terminal. Similarly, those skilled in the art will be able to design a circuit composed of a combination of P-type and N-type transistors. A P-type transistor generally refers to a transistor in which the current increases when the voltage difference between the gate electrode and the source electrode increases in the negative direction. An N-type transistor generally refers to a transistor in which the current increases when the voltage difference between the gate electrode and the source electrode increases in the positive direction. Each of the transistors can be one of various types of transistors, such as thin-film transistors (“TFTs”), field-effect transistors (“FETs”), and bipolar junction transistors (“BJTs”).

[0065] The first transistor T1 may include a gate electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The first transistor T1 may be referred to as a driving transistor.

[0066] The second transistor T2 may include a gate electrode connected to the first scan line SL1, a first electrode connected to the data line DLj, and a second electrode connected to the second node N2. The second transistor T2 may be referred to as a scan transistor.

[0067] The third transistor T3 may include a gate electrode connected to the second scan line SL12, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. The third transistor T3 may be referred to as a diode-connected transistor.

[0068] The fourth transistor T4 may include a gate electrode connected to the third scan line SL13, a first electrode connected to the first node N1, and a second electrode connected to the initialization line INTL. The fourth transistor T4 may be referred to as a gate initialization transistor.

[0069] The fifth transistor T5 may include a gate electrode connected to the i-th emitter line ELi, a first electrode connected to the first power supply line ELVDDL, and a second electrode connected to the second node N2. The fifth transistor T5 may be referred to as an emitter transistor. In an alternative embodiment, the gate electrode of the fifth transistor T5 may be connected to another emitter line.

[0070] The sixth transistor T6 may include a gate electrode connected to the i-th emitter line ELi, a first electrode connected to the third node N3, and a second electrode connected to the anode of the light-emitting element LD. The sixth transistor T6 may be referred to as an emitter transistor. In an alternative embodiment, the gate electrode of the sixth transistor T6 may be connected to an emitter line different from the emitter line to which the gate electrode of the fifth transistor T5 is connected.

[0071] The seventh transistor T7 may include a gate electrode connected to the fourth scan line SL14, a first electrode connected to the initialization line INTL, and a second electrode connected to the anode of the light-emitting element LD. The seventh transistor T7 may be referred to as the light-emitting element initialization transistor.

[0072] The storage capacitor Cst may include a first electrode connected to the first power line ELVDDL and a second electrode connected to the first node N1.

[0073] The light-emitting element (LD) may include an anode connected to the second electrode of the sixth transistor T6 and a cathode connected to the second power line ELVSSL. In some embodiments, the LD may be a light-emitting diode (LED). In such embodiments, the LD may be an organic LED, an inorganic LED, a quantum dot / well LED, or the like. The LD may emit light of any one of a first color, a second color, and a third color. In some embodiments, a single LD is included in each pixel. However, in alternative embodiments, multiple LDs may be provided in each pixel. In such embodiments, multiple LDs may be connected in series, in parallel, or in a combination of series and parallel.

[0074] A first power supply voltage may be applied to a first power line ELVDDL, a second power supply voltage may be applied to a second power line ELVSSL, and an initialization voltage may be applied to an initialization line INTL. In one embodiment, for example, the first power supply voltage may be greater than the second power supply voltage. In one embodiment, for example, the initialization voltage may be equal to or greater than the second power supply voltage. In one embodiment, for example, the initialization voltage may correspond to the smallest data voltage among the data voltages to be provided. In an alternative embodiment, the magnitude of the initialization voltage may be smaller than the magnitude of the data voltages that can be provided.

[0075] Figure 3 It is shown Figure 2 A diagram illustrating an implementation of the pixel driving method.

[0076] For ease of description, the following will describe in detail an implementation where the first scan line SLi1, the second scan line SLi2, and the fourth scan line SLi4 are each the i-th scan line, and the third scan line SLi3 is the (i-1)-th scan line. However, according to alternative embodiments, the first scan line SLi1, the second scan line SLi2, the third scan line SLi3, and the fourth scan line SLi4 may have various different connection relationships. In one alternative embodiment, for example, the fourth scan line SLi4 may be the (i-1)-th scan line or the (i+1)-th scan line.

[0077] In the implementation method, such as Figure 3 As shown, the data voltage DATA(i-1)j for the (i-1)th pixel in the j-th pixel column can be applied to the data line DLj, and the on-level (logic low) scan signal can be applied to the third scan line SLi3.

[0078] In this case, since the off-level (logic high level) scan signal is applied to the first scan line SLi1 and the second scan line SLi2, the second transistor T2 can be in the off state, and the data voltage DATA(i-1)j for the (i-1)th pixel in the j-th pixel column can be effectively prevented from being written into the pixel PXij.

[0079] In this configuration, since the fourth transistor T4 is in the ON state, the first node N1 can be connected to the initialization line INTL, allowing the voltage of the first node N1 to be initialized. Because a turn-off level transmit signal is applied to the transmit line ELi, the fifth transistor T5 and the sixth transistor T6 can be in the OFF state, effectively preventing unwanted light emission from the light-emitting element LD due to the application of the initialization voltage.

[0080] In such an implementation, such as Figure 3 As shown, the data voltage DATAij for the i-th pixel PXij in the j-th pixel column can be applied to the data line DLj, and a scan signal with an on-level can be applied to the first scan line SLi1 and the second scan line SLi2. Therefore, the second transistor T2, the first transistor T1, and the third transistor T3 can be turned on, and the data line DLj and the first node N1 can be electrically connected to each other. Therefore, the compensation voltage obtained by subtracting the threshold voltage of the first transistor T1 from the data voltage DATAij can be applied to the second electrode of the storage capacitor Cst (i.e., the first node N1), and the storage capacitor Cst can maintain a voltage corresponding to the difference between the first power supply voltage and the compensation voltage. This period can be referred to as the threshold voltage compensation period.

[0081] In such an implementation, when the fourth scan line SLi4 is the i-th scan line, since the seventh transistor T7 is in the on state, the anode of the light-emitting element LD and the initialization line INTL can be connected to each other, and the light-emitting element LD can be initialized with the amount of charge corresponding to the voltage difference between the initialization voltage and the second power supply voltage.

[0082] Subsequently, when a transmit signal at the conduction level is applied to the transmit line ELi, the fifth transistor T5 and the sixth transistor T6 can be turned on. Therefore, a drive current path can be formed through the first power line ELVDDL, the fifth transistor T5, the first transistor T1, the sixth transistor T6, the light-emitting element LD, and the second power line ELVSSL.

[0083] The amount of drive current flowing through the first and second electrodes of the first transistor T1 can be adjusted based on the voltage held in the storage capacitor Cst. The light-emitting element LD can emit light with a brightness corresponding to the amount of drive current. The light-emitting element LD can emit light until a turn-off level emission signal is applied to the emission line ELi.

[0084] Figure 4 This is a diagram illustrating a data driver according to an embodiment of the present invention.

[0085] Reference Figure 4 According to an embodiment of the data driver 12 of the present invention, a first sub-driver 121, a second sub-driver 122 and a third sub-driver 123 may be included.

[0086] The first sub-driver 121 may include a first master gamma block 1210, a first slave gamma block 1211, a second slave gamma block 1212, a third slave gamma block 1213, a first decoder 121dc, and a first output buffer 121bf.

[0087] The first master gamma block 1210 can generate a first reference gamma voltage. In an embodiment, the first master gamma block 1210 may not generate a second reference gamma voltage and a third reference gamma voltage. Therefore, in such an embodiment, the first sub-driver 121 can receive a second reference gamma voltage from the second master gamma block 1220 of the second sub-driver 122, and can receive a third reference gamma voltage from the third master gamma block 1230 of the third sub-driver 123. The first slave gamma block 1211 can divide a plurality of first reference gamma voltages to generate a plurality of first gamma voltages. The second slave gamma block 1212 can divide a plurality of second reference gamma voltages to generate a plurality of second gamma voltages. The third slave gamma block 1213 can divide a plurality of third reference gamma voltages to generate a plurality of third gamma voltages.

[0088] The first reference gamma voltage, the first gamma voltage, and the first data voltage can be voltages used for a first pixel. The second reference gamma voltage, the second gamma voltage, and the second data voltage can be voltages used for a second pixel. The third reference gamma voltage, the third gamma voltage, and the third data voltage can be voltages used for a third pixel. The second slave gamma block 1212 can receive the second reference gamma voltage from the second master gamma block 1220 of the second sub-driver 122. The third slave gamma block 1213 can receive the third reference gamma voltage from the third master gamma block 1230 of the third sub-driver 123. In such an implementation, each of the first sub-driver 121, the second sub-driver 122, and the third sub-driver 123 may include a master gamma block for a single color, thereby reducing configuration costs.

[0089] The first decoder 121dc can provide some of the first gamma voltages provided by the first gamma block 1211 as the first data voltage, some of the second gamma voltages provided by the second gamma block 1212 as the second data voltage, and some of the third gamma voltages provided by the third gamma block 1213 as the third data voltage.

[0090] The first output buffer 121bf can provide the output of the first decoder 121dc to the pixel unit 15. In one embodiment, for example, the first output buffer 121bf can be connected to data lines DL1, DL2, DL3, ... and DLp. The data lines DL1, DL2, DL3, ... and DLp can be connected to a portion of the first pixel, a portion of the second pixel, and a portion of the third pixel.

[0091] The second sub-driver 122 may include a second master gamma block 1220, a fourth slave gamma block 1221, a fifth slave gamma block 1222, a sixth slave gamma block 1223, a second decoder 122dc, and a second output buffer 122bf.

[0092] The second master gamma block 1220 can generate a second reference gamma voltage. In an embodiment, the second master gamma block 1220 may not generate a first reference gamma voltage and a third reference gamma voltage. Therefore, in such an embodiment, the second sub-driver 122 can receive a first reference gamma voltage from the first master gamma block 1210 of the first sub-driver 121, and can receive a third reference gamma voltage from the third master gamma block 1230 of the third sub-driver 123. The fourth slave gamma block 1221 can divide a plurality of first reference gamma voltages to generate a plurality of first gamma voltages. The fifth slave gamma block 1222 can divide a plurality of second reference gamma voltages to generate a plurality of second gamma voltages. The sixth slave gamma block 1223 can divide a plurality of third reference gamma voltages to generate a plurality of third gamma voltages.

[0093] The fourth slave gamma block 1221 may receive a first reference gamma voltage from the first master gamma block 1210 of the first sub-driver 121. The sixth slave gamma block 1223 may receive a third reference gamma voltage from the third master gamma block 1230 of the third sub-driver 123. In such an implementation, each of the first sub-driver 121, the second sub-driver 122, and the third sub-driver 123 may include a master gamma block for a single color, thereby reducing configuration costs.

[0094] The second decoder 122dc can provide some of the first gamma voltages provided by the fourth gamma block 1221 as the first data voltage, some of the second gamma voltages provided by the fifth gamma block 1222 as the second data voltage, and some of the third gamma voltages provided by the sixth gamma block 1223 as the third data voltage.

[0095] The second output buffer 122bf can provide the output of the second decoder 122dc to the pixel unit 15. In one embodiment, for example, the second output buffer 122bf can be connected to data lines DL(p+1), DL(p+2), DL(p+3), ... and DLq. The data lines DL(p+1), DL(p+2), DL(p+3), ... and DLq can be connected to another portion of the first pixel, another portion of the second pixel, and another portion of the third pixel.

[0096] The third sub-driver 123 may include a third master gamma block 1230, a seventh slave gamma block 1231, an eighth slave gamma block 1232, a ninth slave gamma block 1233, a third decoder 123dc, and a third output buffer 123bf.

[0097] The third master gamma block 1230 can generate a third reference gamma voltage. In an embodiment, the third master gamma block 1230 may not generate a first reference gamma voltage or a second reference gamma voltage. Therefore, in such an embodiment, the third sub-driver 123 can receive a first reference gamma voltage from the first master gamma block 1210 of the first sub-driver 121, and can receive a second reference gamma voltage from the second master gamma block 1220 of the second sub-driver 122. The seventh slave gamma block 1231 can divide a plurality of first reference gamma voltages to generate a plurality of first gamma voltages. The eighth slave gamma block 1232 can divide a plurality of second reference gamma voltages to generate a plurality of second gamma voltages. The ninth slave gamma block 1233 can divide a plurality of third reference gamma voltages to generate a plurality of third gamma voltages.

[0098] The seventh slave gamma block 1231 may receive a first reference gamma voltage from the first master gamma block 1210 of the first sub-driver 121. The eighth slave gamma block 1232 may receive a second reference gamma voltage from the second master gamma block 1220 of the second sub-driver 122. In such an implementation, each of the first sub-driver 121, the second sub-driver 122, and the third sub-driver 123 may include a master gamma block for a single color, thereby reducing configuration costs.

[0099] The third decoder 123dc can provide some of the first gamma voltages provided by the seventh gamma block 1231 as the first data voltage, some of the second gamma voltages provided by the eighth gamma block 1232 as the second data voltage, and some of the third gamma voltages provided by the ninth gamma block 1233 as the third data voltage.

[0100] The third output buffer 123bf can provide the output of the third decoder 123dc to the pixel unit 15. In one embodiment, for example, the third output buffer 123bf can be connected to data lines DL(q+1), DL(q+2), DL(q+3), ... and DLn. The data lines DL(q+1), DL(q+2), DL(q+3), ... and DLn can be connected to another portion of the first pixel, another portion of the second pixel, and another portion of the third pixel.

[0101] The data lines DL1, DL2, DL3, ..., DLp connected to the first output buffer 121bf, the data lines DL(p+1), DL(p+2), DL(p+3), ..., DLq connected to the second output buffer 122bf, and the data lines DL(q+1), DL(q+2), DL(q+3), ..., DLn connected to the third output buffer 123bf can be different from each other. Here, p can be an integer greater than 0, and q can be an integer greater than p and less than n. The pixels connected to the first output buffer 121bf, the pixels connected to the second output buffer 122bf, and the pixels connected to the third output buffer 123bf can be different from each other. According to the embodiment, each of the first sub-driver 121, the second sub-driver 122, and the third sub-driver 123 can supply data voltage to a different region (pixel) of the pixel unit 15. Therefore, even when the pixel unit 15 has a large display area, the RC delay of the data voltage can be reduced.

[0102] In the implementation method, such as Figure 4 As shown, data driver 12 may include multiple sub-drivers (e.g., a first sub-driver 121, a second sub-driver 122, and a third sub-driver 123). In such an embodiment, the multiple sub-drivers (e.g., the first sub-driver 121, the second sub-driver 122, and the third sub-driver 123) may each be defined by a different integrated circuit (“IC”) chip. In such an embodiment, data driver 12 may include four or more sub-drivers. In an alternative embodiment, data driver 12 may be configured as a single driver, i.e., a single IC.

[0103] Figure 5A This is a diagram illustrating the master gamma block and slave gamma block according to an embodiment of the present invention, and Figure 5B yes Figure 5A A magnified view of the portion.

[0104] exist Figure 5AFor ease of explanation and description, only the first master gamma block 1210 and the first slave gamma block 1211 of the first sub-driver 121 embodiment are shown. Since the configurations of the fourth slave gamma block 1221 and the seventh slave gamma block 1231 are substantially the same as those of the first slave gamma block 1211, any repeated detailed descriptions thereof will be omitted.

[0105] In one embodiment, the first main gamma block 1210 may include first main amplifiers MG1, MG2, MG3, MG4, MG5, MG6, MG7, MG8, MG9, and MG10 (e.g., first main amplifiers MG1 to tenth main amplifiers MG10) that generate first reference gamma voltages V0, V1, V255, V511, V767, V1023, V1279, V1525, V1791, and V2047, respectively. In such an embodiment, the first main gamma block 1210 may include auxiliary amplifiers AA1, AA2, AA3, and AA4, multiplexers MUX1, MUX2, and MUX3, and a first resistor string RS1 and a tenth resistor string RS10.

[0106] The auxiliary amplifier AA1 can receive a high voltage VREF_H and output a first reference voltage VREG1. In such an amplifier, as... Figure 5A As shown, the inverting terminal can be connected to the output terminal (negative feedback), the non-inverting terminal can receive the input voltage, and the output terminal can output the output voltage. Any repeated detailed descriptions of the terminal connections will be omitted below. The auxiliary amplifier AA2 can receive a low voltage VREF_L and output a second reference voltage VREF1.

[0107] One end of the first resistor string RS1 can receive a first reference voltage VREG1, and the other end of the first resistor string RS1 can receive a second reference voltage VREF1. The first resistor string RS1 may include multiple resistors connected in series with each other.

[0108] The first multiplexer MUX1 may provide an input voltage selected from at least one of the first main amplifiers MG1 to MG10 based on a first gamma code GMCD1 received therefrom or applied thereto. In one embodiment, for example, the first multiplexer MUX1 may receive the voltage of a specific node in the first resistor string RS1 based on the first gamma code GMCD1 and provide the received voltage to the second first main amplifier MG2.

[0109] The second multiplexer MUX2 can provide an input voltage selected from at least one of the first main amplifiers MG1 to MG10 based on a second gamma code GMCD2 received therefrom or applied thereto. In one embodiment, for example, the second multiplexer MUX2 can receive the voltage of a specific node in the first resistor string RS1 based on the second gamma code GMCD2 and provide the received voltage to the tenth first main amplifier MG10.

[0110] The third multiplexer MUX3 can provide an input voltage selected from at least one of the first main amplifiers MG1 to MG10 based on the received third gamma code GMCD3. In one embodiment, for example, the third multiplexer MUX3 can receive the voltage of a specific node in the first resistor string RS1 based on the third gamma code GMCD3 and provide the received voltage to the first main amplifier MG1.

[0111] In one implementation, the voltage VGMA_H provided by the third multiplexer MUX3 may be greater than the voltage provided by the first multiplexer MUX1. In another implementation, the voltage provided by the first multiplexer MUX1 may be greater than the voltage VGMA_L provided by the second multiplexer MUX2. In yet another implementation, the third gamma code GMCD3 may be greater than the first gamma code GMCD1, and the first gamma code GMCD1 may be greater than the second gamma code GMCD2.

[0112] The timing controller 11 can be based on the received maximum brightness DBV (refer to...) Figure 1 A second gamma code GMCD2 is provided differently. In this case, the first gamma code GMCD1 and the third gamma code GMCD3 can remain constant, independent of the received maximum brightness DBV. In one embodiment, for example, when the second maximum brightness is greater than the first maximum brightness, the first gamma code GMCD1 under the first maximum brightness and the first gamma code GMCD2 under the second maximum brightness can be the same as each other. In this case, the second gamma code GMCD2 under the first maximum brightness and the second gamma code GMCD2 under the second maximum brightness can be different from each other. The input voltage VGMA_L provided by the second multiplexer MUX2 under the first maximum brightness can be greater than the input voltage VGMA_L provided by the second multiplexer MUX2 under the second maximum brightness. Therefore, as the maximum brightness DBV is set larger, the difference between the minimum voltage V2047 and the maximum voltage V0 among the first reference gamma voltages V0 to V2047 can increase. Furthermore, as the maximum luminance DBV is set smaller, the difference between the minimum voltage V2047 and the maximum voltage V0 among the first reference gamma voltages V0 to V2047 can be reduced.

[0113] The first main amplifier MG1 can receive an input voltage VGMA_H and output a first reference gamma voltage V0. When the gain is 1, the first main amplifier MG1 can operate as a unit buffer. The related description will be omitted below.

[0114] The second primary amplifier MG2 can receive input voltage from the first multiplexer MUX1 and output the first reference gamma voltage V1.

[0115] One end of the tenth resistor string RS10 can be connected to the output terminal of the auxiliary amplifier AA3, and the other end of the tenth resistor string RS10 can be connected to the output terminal of the auxiliary amplifier AA4. The tenth resistor string RS10 may include multiple resistors connected in series with each other.

[0116] The third first main amplifier MG3, the fourth first main amplifier MG4, the fifth first main amplifier MG5, the sixth first main amplifier MG6, the seventh first main amplifier MG7, the eighth first main amplifier MG8, and the ninth first main amplifier MG9 can each receive input voltage from one node of the tenth resistor series RS10, and output the corresponding first reference gamma voltages V255, V511, V767, V1023, V1279, V1525, and V1791.

[0117] The tenth main amplifier MG10 can receive the input voltage VGMA_L from the second multiplexer MUX2 and output the corresponding first reference gamma voltage V2047.

[0118] The first slave gamma block 1211 may include first slave amplifiers SG1, SG2, SG3, SG4, SG5, SG6, SG7, SG8, ​​SG9 and SG10, each of the first slave amplifiers SG1, SG2, SG3, SG4, SG5, SG6, SG7, SG8, ​​SG9 and SG10 having an input terminal connected to the output terminal of a corresponding one of the first master amplifiers MG1 to MG10 of the first master gamma block 1211. The first output voltages (e.g., first gamma voltages) V0, V1, V255, V511, V767, V1023, V1279, V1525, V1791, and V2047 of the first amplifiers SG1 to SG10 may be the same as the corresponding output voltages (e.g., first reference gamma voltages) V0, V1, V255, V511, V767, V1023, V1279, V1525, V1791, and V2047 of the first main amplifiers MG1 to MG10.

[0119] The first slave gamma block 1211 may further include a second resistor string RS2, a third resistor string RS3, a fourth resistor string RS4, a fifth resistor string RS5, a sixth resistor string RS6, a seventh resistor string RS7, an eighth resistor string RS8, and a ninth resistor string RS9. Each of these resistor strings is connected to the output terminal of an adjacent first slave amplifier among the first slave amplifiers SG1 to SG10. In one embodiment, for example, the second resistor string RS2 may be connected to the output terminal of a second first slave amplifier SG2 and a third first slave amplifier SG3.

[0120] The first gamma block 1211 can provide a first gamma voltage at an intermediate node of the second resistor string RS2 to the ninth resistor string RS9. In one embodiment, for example, the second resistor string RS2 can divide a first reference gamma voltage V1 and a first reference gamma voltage V255 to provide first gamma voltages V2 to V254. The third resistor string RS3 can divide a first reference gamma voltage V255 and a first reference gamma voltage V511 to provide first gamma voltages V256 to V510. The fourth resistor string RS4 can divide a first reference gamma voltage V511 and a first reference gamma voltage V767 to provide first gamma voltages V512 to V766. The fifth resistor string RS5 can divide a first reference gamma voltage V767 and a first reference gamma voltage V1023 to provide first gamma voltages V768 to V1022. The sixth resistor string RS6 divides the first reference gamma voltage V1023 and the first reference gamma voltage V1279 to provide the first gamma voltage V1024 to V1278. The seventh resistor string RS7 divides the first reference gamma voltage V1279 and the first reference gamma voltage V1525 to provide the first gamma voltage V1280 to V1524. The eighth resistor string RS8 divides the first reference gamma voltage V1525 and the first reference gamma voltage V1791 to provide the first gamma voltage V1526 to V1790. The ninth resistor string RS9 divides the first reference gamma voltage V1791 and the first reference gamma voltage V2047 to provide the first gamma voltage V1792 to V2046.

[0121] exist Figure 5BThe image shows an enlarged view of an embodiment of the ninth first main amplifier MG9. In one embodiment, for example, the ninth first main amplifier MG9 may include a non-inverting input terminal tvp, an inverting input terminal tvn, an output terminal tvo, a first power input terminal tvcc, and a second power input terminal tvee. The range of the output voltage that can be output to the output terminal tvo may be greater than a second voltage applied to the second power input terminal tvee and less than a first voltage applied to the first power input terminal tvcc.

[0122] In one implementation, switch SW9 may be connected to the first power input terminal tvcc of the ninth first main amplifier MG9. The ninth first main amplifier MG9 may be disabled when switch SW9 is off and enabled when switch SW9 is on. In an alternative implementation, switch SW9 may be connected to the second power input terminal tvee of the ninth first main amplifier MG9.

[0123] Switch SW9 can be configured according to the enabled / disabled information EN / DIS (see reference). Figure 1 The switch is turned on or off based on the sub-information EN / DIS9 in the switch. According to the implementation, the other first main amplifiers MG1 to MG8 and MG10 can also be connected to the switch in a manner similar to the ninth first main amplifier MG9, and can be enabled or disabled based on the enable / disable information EN / DIS.

[0124] In an implementation, the first secondary amplifiers SG1 to SG10 may also be connected to a switch in a manner similar to the ninth primary amplifier MG9, and may be enabled or disabled based on the enable / disable information EN / DIS.

[0125] In the implementation, as described above, the timing controller 11 may refer to the memory 11MEM (reference memory 11). Figure 1 The lookup table provides enable / disable information EN / DIS corresponding to the level of the received maximum brightness DBV to the data driver 12. The first main amplifiers MG1 to MG10 and the first slave amplifiers SG1 to SG10 can be enabled or disabled based on the enable / disable information EN / DIS.

[0126] In one implementation, when the first master amplifiers MG1 to MG10 are enabled or disabled, the connected first slave amplifiers SG1 to SG10 can also be enabled or disabled. In one implementation, for example, when the third first master amplifier MG3 is enabled, the third first slave amplifier SG3 can be enabled, and when the third first master amplifier MG3 is disabled, the third first slave amplifier SG3 can be disabled.

[0127] In this implementation, auxiliary amplifiers AA1, AA2, AA3, and AA4 can be selectively configured and can be excluded from the configuration of the first main gamma block 1210 if not needed. In this implementation, the third multiplexer MUX3 can be selectively configured and can be excluded from the configuration of the first main gamma block 1210 if not needed. In this implementation, with the third multiplexer MUX3 excluded, the first reference gamma voltages V1 to V2047 can be output.

[0128] Since the relationship and configuration between the second master gamma block 1220 and the second slave gamma block 1212, the fifth slave gamma block 1222 and the eighth slave gamma block 1232 can be basically the same as Figure 5A Those are the same, so any repeated detailed descriptions will be omitted. However, in an implementation, the gamma code received by the second master gamma block 1220 may be different from the first gamma code GMCD1, the second gamma code GMCD2, and the third gamma code GMCD3 received by the first master gamma block 1210.

[0129] Since the relationship and configuration between the third master gamma block 1230 and the third slave gamma block 1213, the sixth slave gamma block 1223 and the ninth slave gamma block 1233 can be basically the same as Figure 5A Those are the same, therefore any repeated detailed descriptions will be omitted. However, in an implementation, the gamma code received by the third master gamma block 1230 may be different from the first gamma code GMCD1, the second gamma code GMCD2, and the third gamma code GMCD3 received by the first master gamma block 1210. In such an implementation, the gamma code received by the third master gamma block 1230 may be different from the gamma code received by the second master gamma block 1220.

[0130] The range of gamma voltage corresponding to a color can be changed by altering the gamma code for that color. Therefore, white balance and the balance for the color of interest can be precisely adjusted.

[0131] Figure 6 This is a diagram illustrating a sub-driver of a data driver according to an embodiment of the present invention.

[0132] Reference Figure 6 The relationship between the first slave gamma block 1211, the first decoder 121dc, and the first output buffer 121bf in the first sub-driver 121 will be described. Since the relationships between the other slave gamma blocks, decoders, and output buffers are also essentially the same... Figure 6 The ones shown are the same, so any repeated detailed descriptions will be omitted.

[0133] In one implementation, the first gamma voltages V1 to V2047 provided by the first gamma block 1211 can have linear voltages at each step. In one implementation, for example, the slope between the first gamma voltage V1 in the first step and the first gamma voltage V2 in the second step can be the same as the slope between the first gamma voltage V2046 in the 2046th step and the first gamma voltage V2047 in the 2047th step.

[0134] The first decoder 121dc can provide one of the first gamma voltages V1 to V2047 as a corresponding first data voltage based on the received grayscale. In one embodiment, for example, when receiving the grayscale GRAYij for pixel PXij, the first decoder 121dc can provide the first gamma voltage corresponding to the grayscale GRAYij as the first data voltage DATAij.

[0135] In one implementation, for example, the range (number) of grayscale values ​​G1 to G255 may be smaller than the range (number) of first gamma voltages V1 to V2047. The first decoder 121dc may output a first data voltage DATAij corresponding to the grayscale value GRAYij, to correspond to a set gamma curve (e.g., 1.8 gamma, 2.0 gamma, 2.2 gamma, and similar curves). In such an implementation, the first data voltage DATAij provided by the first decoder 121dc may have a non-linear voltage at each step of the grayscale value.

[0136] The first output buffer 121bf can output the received first data voltage DATAij to the pixel PXij via the data line DLj. In this embodiment, the pixel PXij may be the first pixel. Although not shown, the first output buffer 121bf may include multiple output amplifiers. Similar to the master amplifier and slave amplifier described above, the output amplifiers can operate as unit buffers.

[0137] Figures 7 to 10 This is a diagram illustrating a lookup table (LUT) according to an embodiment of the present invention.

[0138] Reference Figure 7, the memory 11MEM can store a first lookup table LUT1 corresponding to the level 000h of the maximum brightness DBV, a second lookup table LUT2 when the level of the maximum brightness DBV falls within the range (000h<DBV<DBV1), a third lookup table LUT3 when the level of the maximum brightness DBV falls within the range (DBV1<DBV<DBV2), a fourth lookup table LUT4 when the level of the maximum brightness DBV falls within the range (DBV2<DBV<DBV3), a fifth lookup table LUT5 when the level of the maximum brightness DBV falls within the range (DBV3<DBV<DBV4), a sixth lookup table LUT6 when the level of the maximum brightness DBV falls within the range (DBV4<DBV<DBV5), a seventh lookup table LUT7 when the level of the maximum brightness DBV falls within the range (DBV5<DBV<DBV6), an eighth lookup table LUT8 when the level of the maximum brightness DBV falls within the range (DBV6<DBV<DBV7), a ninth lookup table LUT9 when the level of the maximum brightness DBV falls within the range (DBV7<DBV<DBV8), and a tenth lookup table LUT10 when the level of the maximum brightness DBV falls within the range (DBV8<DBV<FFFh).

[0139] in Figure 8 , the configuration of an embodiment of the tenth lookup table LUT10 is shown. With reference to Figure 7 , the tenth lookup table LUT10 can correspond to the case where the level of the maximum brightness DBV is the highest. In this case, all of the first master amplifiers MG1 to MG10 and the first slave amplifiers SG1 to SG10 can be in an enabled state.

[0140] in Figure 9 , the configuration of an embodiment of the fifth lookup table LUT5 is shown. With reference to Figure 7 , the corresponding maximum brightness DBV level of the fifth lookup table LUT5 can be lower than the corresponding maximum brightness DBV level of the tenth lookup table LUT10. In this case, among the first master amplifiers MG1 to MG10, v master amplifiers (e.g., MG1, MG3, MG5, MG7, MG9 and MG10) can be enabled, and the remaining master amplifiers (e.g., MG2, MG4, MG6 and MG8) can be disabled, where v can be 6. In such an embodiment, among the first slave amplifiers SG1 to SG10, v first slave amplifiers (e.g., SG1, SG3, SG5, SG7, SG9 and SG10) can be enabled, and the remaining first slave amplifiers (e.g., SG2, SG4, SG6 and SG8) can be disabled.

[0141] in Figure 10 , the configuration of an embodiment of the second lookup table LUT2 is shown. With reference to Figure 7, the level of the maximum display brightness value (DBV) corresponding to the second lookup table LUT2 can be lower than the level of the maximum DBV corresponding to the fifth lookup table LUT5. In this case, among the first main amplifiers MG1 to MG10, u first main amplifiers (e.g., MG1, MG5, MG8 and MG10) can be enabled, and the remaining first main amplifiers (e.g., MG2, MG3, MG4, MG6, MG7 and MG9) can be disabled, where u can be 4. In such an embodiment, among the first slave amplifiers SG1 to SG10, u first slave amplifiers (e.g., SG1, SG5, SG8 and SG10) can be enabled, and the remaining first slave amplifiers (e.g., SG2, SG3, SG4, SG6, SG7 and SG9) can be disabled.

[0142] According to an embodiment, when the maximum DBV is set to a first maximum brightness (e.g., 000h < DBV < DBV1), among the first main amplifiers MG1 to MG10, u first main amplifiers (e.g., 4 first main amplifiers) can be enabled, and the remaining first main amplifiers can be disabled, where u can be an integer greater than 0. In such an embodiment, when the maximum DBV is set to a second maximum brightness different from the first maximum brightness (DBV3 < DBV < DBV4), among the first main amplifiers MG1 to MG10, v first main amplifiers (e.g., 6 first main amplifiers) can be enabled, and the remaining first main amplifiers can be disabled, where v can be an integer greater than u. In such an embodiment, the second maximum brightness can be greater than the first maximum brightness.

[0143] According to an embodiment, when the maximum DBV is set to a first maximum brightness (e.g., 000h < DBV < DBV1), among the first slave amplifiers SG1 to SG10, u first slave amplifiers (e.g., 4 first slave amplifiers) can be enabled, and the remaining first slave amplifiers can be disabled, where u can be an integer greater than 0. In such an embodiment, when the maximum DBV is set to a second maximum brightness different from the first maximum brightness (DBV3 < DBV < DBV4), among the first slave amplifiers SG1 to SG10, v first slave amplifiers (e.g., 6 first slave amplifiers) can be enabled, and the remaining first slave amplifiers can be disabled, where v can be an integer greater than u. In such an embodiment, the second maximum brightness can be greater than the first maximum brightness.

[0144] According to an embodiment, when the maximum brightness DBV is set to a first maximum brightness (e.g., 000h<DBV<DBV1), u first master amplifiers among the first master amplifiers MG1 to MG10 and u first slave amplifiers among the first slave amplifiers SG1 to SG10 may be enabled, and the remaining first master amplifiers and the remaining first slave amplifiers may be disabled, wherein u may be an integer greater than 0. In such an embodiment, when the maximum brightness DBV is set to a second maximum brightness different from the first maximum brightness (e.g., DBV3<DBV<DBV4), v first master amplifiers among the first master amplifiers MG1 to MG10 and v first slave amplifiers among the first slave amplifiers SG1 to SG10 may be enabled, and the remaining first master amplifiers and the remaining first slave amplifiers may be disabled, wherein v may be an integer greater than u. In such an embodiment, the second maximum brightness may be greater than the first maximum brightness.

[0145] According to an embodiment, the lower the set maximum brightness DBV is, the more master amplifiers or slave amplifiers are disabled, so that power consumption can be reduced.

[0146] When all master amplifiers and all slave amplifiers are enabled, when the maximum brightness DBV is relatively high, the voltage difference between adjacent reference gamma voltages can be defined as a first difference. In this case, when the maximum brightness DBV is relatively low, the voltage difference between adjacent reference gamma voltages can be defined as a second difference. The second difference may be smaller than the first difference. According to an embodiment of the present invention, some master amplifiers and some slave amplifiers may be disabled until the second difference reaches the first difference. Therefore, according to an embodiment of the present invention, while the charging rate (e.g., slew rate) of the gamma voltage is similarly maintained at all maximum brightness DBV levels, the power consumption can be reduced as the maximum brightness DBV decreases. Here, for example, charging of the gamma voltage refers to charging of each node in the resistor string RS2 to RS9 of the first slave gamma block 1211 (refer to Figure 5A ) for charging each node in the resistor string RS2 to RS9.

[0147] Figure 11 It is a diagram illustrating a display device according to an alternative embodiment of the present invention.

[0148] Except that the data driver 12 includes a memory 12MEM, Figure 11 the embodiment of the display device 10' may be substantially the same as the embodiment of the display device 10 described above with reference to Figure 1 described above. Figure 11 the same or similar elements shown in are marked with the same reference numerals as those used above to describe the embodiment of the display device shown in Figure 1 above, and any repeated detailed description thereof will be omitted or simplified hereinafter.

[0149] In an embodiment, as shown in Figure 11 As shown in, the timing controller 11 may not provide the enable / disable information EN / DIS. In such an embodiment, the timing controller 11 may provide a gamma code GMCD corresponding to the level of the received maximum brightness DBV to the data driver 12.

[0150] The memory 12MEM may store a lookup table. The enable or disable states of the main amplifier and the slave amplifier corresponding to the level of the gamma code GMCD may be recorded in the lookup table.

[0151] The data driver 12 may include the memory 12MEM, and may enable or disable the main amplifier and the slave amplifier with reference to the level of the received gamma code GMCD and the lookup table.

[0152] Figure 12 is a diagram showing a lookup table according to an alternative embodiment of the present invention.

[0153] In an embodiment, the level of the gamma code GMCD referenced by the lookup tables LUT1 to LUT10 may refer to the level of the second gamma code GMCD2.

[0154] With reference to Figure 12 , the memory 12MEM may store a first lookup table LUT1 corresponding to the level 000h of the second gamma code GMCD2, a second lookup table LUT2 for when the level of the second gamma code GMCD2 falls within the range (000h<GMCD2<GMCD2_1), a third lookup table LUT3 for when the level of the second gamma code GMCD2 falls within the range (GMCD2_1<GMCD2<GMCD2_2), a fourth lookup table LUT4 for when the level of the second gamma code GMCD2 falls within the range (GMCD2_2<GMCD2<GMCD2_3), a fifth lookup table LUT5 for when the level of the second gamma code GMCD2 falls within the range (GMCD2_3<GMCD2<GMCD2_4), a sixth lookup table LUT6 for when the level of the second gamma code GMCD2 falls within the range (GMCD2_4<GMCD2<GMCD2_5), a seventh lookup table LUT7 for when the level of the second gamma code GMCD2 falls within the range (GMCD2_5<GMCD2<GMCD2_6), an eighth lookup table LUT8 for when the level of the second gamma code GMCD2 falls within the range (GMCD2_6<GMCD2<GMCD2_7), a ninth lookup table LUT9 for when the level of the second gamma code GMCD2 falls within the range (GMCD2_7<GMCD2<GMCD2_8), and a tenth lookup table LUT10 for when the level of the second gamma code GMCD2 falls within the range (GMCD2_8<GMCD2<GMCD2_9).

[0155] Since the internal configuration of lookup tables LUT1 to LUT10 of memory 12MEM can be compared with the internal configuration of lookup tables LUT1 to LUT10 of memory 11MEM (refer to...) Figure 8 , Figure 9 and Figure 10 Since they are the same, any repeated detailed descriptions will be omitted.

[0156] In embodiments of the present invention, as described herein, the display device may have reduced power consumption when generating gamma voltage.

[0157] This invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

[0158] Although the invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A display device, comprising: A pixel unit, the pixel unit comprising a plurality of first pixels displaying a first color; as well as A data driver that supplies multiple first data voltages to the multiple first pixels. The data driver includes: The first master gamma block includes a plurality of first master amplifiers that generate a plurality of first reference gamma voltages; A first slave gamma block, wherein the first slave gamma block generates a plurality of first gamma voltages by dividing the plurality of first reference gamma voltages; and A first decoder provides some of the plurality of first gamma voltages as the plurality of first data voltages, and Each of the plurality of first main amplifiers is enabled or disabled based on the maximum brightness of the pixel unit. Specifically, when the maximum brightness is set to a first maximum brightness, u of the plurality of first main amplifiers are enabled and the remaining first main amplifiers are disabled, where u is an integer greater than 0. When the maximum brightness is set to a second maximum brightness that is different from the first maximum brightness, v of the plurality of first main amplifiers are enabled and the remaining first main amplifiers are disabled, where v is an integer greater than u.

2. The display device according to claim 1, wherein, The second maximum brightness is greater than the first maximum brightness.

3. The display device according to claim 2, wherein, The first master gamma block further includes a first multiplexer that provides an input voltage selected from at least one of the plurality of first master amplifiers based on a first gamma code applied to the first multiplexer.

4. The display device according to claim 3, wherein, The first master gamma block further includes a second multiplexer, which provides an input voltage selected from at least one of the plurality of first master amplifiers based on a second gamma code applied to the second multiplexer.

5. The display device according to claim 4, wherein, The first gamma code under the first maximum brightness and the first gamma code under the second maximum brightness are the same as each other, and The second gamma code under the first maximum brightness and the second gamma code under the second maximum brightness are different from each other.

6. The display device according to claim 5, wherein, The input voltage provided by the second multiplexer at the first maximum brightness is greater than the input voltage provided by the second multiplexer at the second maximum brightness.

7. The display device according to claim 1, further comprising: The memory stores lookup tables. The lookup table records the enabled or disabled state of each of the plurality of first main amplifiers corresponding to the level of maximum brightness.

8. The display device according to claim 1, wherein, The first slave gamma block includes a plurality of first slave amplifiers respectively connected to the plurality of first master amplifiers, and When one of the plurality of first master amplifiers is enabled or disabled, the corresponding first slave amplifier among the plurality of first slave amplifiers connected to the first master amplifier is also enabled or disabled.

9. The display device according to claim 8, further comprising: The memory stores lookup tables. The lookup table records the enabled or disabled state of each of the plurality of first main amplifiers and the plurality of first slave amplifiers corresponding to the level of the maximum brightness.

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