Systems for controlling temperature in memory and methods for controlling temperature in HBM

Abstract

A system includes: a high-bandwidth memory (HBM) comprising: a first sensing unit configured to generate one or more first ambient signals corresponding to a first transistor in a first memory cell; and a second sensing unit configured to generate one or more second ambient signals corresponding to a second transistor in a second memory cell; and a differential dynamic voltage and frequency scaling (DDVFS) device configured to perform the following operations for a first group of memory cells including the first memory cells: (1) controlling the temperature of the first group by adjusting one or more first transistor temperature effects (TTA) based on one or more first ambient signals, and (2) controlling the temperature of a second group of memory cells including the second memory cells by adjusting one or more second TTA parameters based on one or more second ambient signals. Embodiments of this application provide a system for controlling temperature in a memory and a method for controlling temperature in an HBM.

Description

Technical Field

[0001] Embodiments of this application relate to systems for controlling temperature in a memory and methods for controlling temperature in an HBM. Background Technology

[0002] An integrated circuit (“IC”) comprises one or more semiconductor devices. One way to represent a semiconductor device is using a planar diagram called a layout diagram. Summary of the Invention

[0003] In some embodiments, the system (for controlling temperature in the memory) includes: a high-bandwidth memory (HBM) including core dies disposed in a stack, each core die including a bank, and each bank including memory cells, the HBM further including: a first sensing unit configured to generate one or more first ambient signals corresponding to at least a first transistor of at least one of the corresponding memory cells; a second sensing unit configured to generate one or more second ambient signals corresponding to at least a second transistor of at least a corresponding memory cell; and a differential dynamic voltage and frequency scaling (DDVFS) device configured to perform the following operations: for a first set of one or more memory cells including the first memory cells, controlling the temperature of the first set by adjusting one or more first set transistor temperature effect (TTA) parameters of the first set based on one or more first ambient signals; for a second set of one or more memory cells including the second memory cells, controlling the temperature of the second set by adjusting one or more second TTA parameters of the second set based on one or more second ambient signals.

[0004] In some embodiments, a system (for controlling temperature in a memory) includes: a high-bandwidth memory (HBM) including core dies disposed in a stack, each core die including a library, and each library including a memory cell, the HBM further including: a first sensing unit configured to sense a first temperature corresponding to at least a first transistor of at least a first memory cell; and a second sensing unit configured to sense a second temperature corresponding to at least a second transistor of at least a second memory cell; and a differential dynamic voltage and frequency scaling (DDVFS) device configured to perform the following operations: for a first group of one or more memory cells including the first memory cell, controlling the temperature of the first group by adjusting one or more first transistor temperature influence (TTA) parameters of the first group based on the first temperature; and for a second group of one or more memory cells including the second memory cell, controlling the temperature of the second group by adjusting one or more second TTA parameters of the second group based on the second temperature.

[0005] In some embodiments, a method for controlling the temperature in a high-bandwidth memory (HBM) includes core dies arranged in a stack, each core die including a library, and each library including a memory cell, the HBM further including at least first and second sensing units correspondingly arranged within the core dies, the method comprising: receiving a first threshold voltage from a first sensing unit arranged within the HBM, the first threshold voltage corresponding to at least a first transistor in a corresponding at least first memory cell; receiving a second threshold voltage from a second sensing unit arranged within the HBM, the second threshold voltage corresponding to at least a second transistor in a corresponding at least second memory cell; for a first group of one or more memory cells including the first memory cell, controlling the temperature of the first group by adjusting one or more first transistor temperature influence (TTA) parameters of the first group based on the first threshold voltage; for a second group of one or more memory cells including the second memory cell, controlling the temperature of the second group by adjusting one or more second TTA parameters of the second group based on the second threshold voltage. Embodiments of this application provide a differential thermal throttling method and system for memory. Attached Figure Description

[0006] When with attachment Figure 1 When reading this document, the following detailed description is the best way to understand all aspects of this disclosure. It is worth noting that, in accordance with industry standard practice, the various parts are not drawn to scale. In fact, the dimensions of the various parts can be increased or decreased arbitrarily for clarity of discussion.

[0007] Figure 1 This is a block diagram of a semiconductor device according to some embodiments.

[0008] Figure 2A This is a cross-sectional view of a semiconductor device according to some embodiments.

[0009] Figure 2B This is a three-quarter perspective view of HBM based on some embodiments.

[0010] Figures 2C-2E This is a corresponding block diagram of a corresponding sensing unit according to some embodiments.

[0011] Figures 3A-3D This is a block diagram of the corresponding HBM according to some embodiments.

[0012] Figures 4A-4G This is a block diagram of a corresponding DDVFS device according to some embodiments.

[0013] Figures 5A-5B This is a circuit diagram of a corresponding temperature sensor according to some embodiments.

[0014] Figures 6A-6CThis is a circuit diagram of a corresponding threshold voltage detector according to some embodiments.

[0015] Figures 7A-7E These are corresponding flowcharts based on some embodiments.

[0016] Figures 7F-7I The embodiments are shown in more detail below. Figure 7A The corresponding flowchart for the boxes.

[0017] Figure 8 This is a flowchart of a method for manufacturing a semiconductor device according to some embodiments.

[0018] Figure 9 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0019] Figure 10 This is a block diagram of an integrated circuit (IC) manufacturing system and its associated IC manufacturing process according to some embodiments. Detailed Implementation

[0020] The following disclosure provides numerous different embodiments or examples for implementing various components of the described subject matter. Specific examples of elements and arrangements are described below to simplify this description. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where additional components may be formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, to facilitate the description of one element or component relative to another as shown in the figure, spatially related terms such as "below," "under," "below," "above," and "above" may be used here. In addition to the directions depicted in the figure, spatially relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein will be interpreted accordingly.

[0022] In some embodiments, high-bandwidth memory (HBM) comprises a stack of core dies / chips / ICs, such as dynamic random access memory (DRAM) core dies and differentiated DVFS devices, where DVFS is an acronym for Dynamic Voltage and Frequency Scaling (DVFS). The core die library includes sensing units (each including a temperature sensor and / or a threshold voltage detector). Typically, frequent read or write activity to memory cells within a core die increases the temperature of the memory cells. Unrestricted / uncontrolled increases in temperature can lead to thermal runaway. When the temperature of a memory cell within a core die exceeds its maximum permissible temperature, the values ​​of the data bits stored in the memory cell are susceptible to corruption, for example, due to increased leakage. According to another approach, a technique called monolithic DVFS is used to prevent overheating in the HBM. Monolithic DVFS technology, according to another approach, monitors the temperature in each core die of the HBM. When any part of a core chip exceeds its permissible temperature, the monolithic DVFS technology reduces the clock speed of all bit cells across all core chips, where the clock speed is reduced by decreasing the frequency of the clock supplied to all cores. According to another approach, monolithic DVFS technology is described as monolithic type thermal throttling because the same clock is provided to all bit cells of all core dies, thus treating HMB as if HMB were monolithic. That is, HMB is not handled in the case of different parts that represent different aspects.

[0023] However, typically only a small portion of a given core die exceeds its allowable temperature. As a result, monolithic thermal throttling according to another approach not only cools a small portion of the given core die but also unnecessarily cools most of the given core die and the rest of the other core dies, leading to an unnecessary reduction in the performance of most of the given core chip and the rest of the other core chips – a wasteful and inefficient approach. Compared to monolithic thermal throttling, differentiated thermal throttling in some embodiments, such as bank-wide, group-wide, channel-wide, and core-wide, is more refined in terms of the portion of HBM to be temperature-controlled, thus resulting in less waste and higher efficiency.

[0024] Figure 1 This is a block diagram of a semiconductor device 100 according to at least one embodiment of the present disclosure.

[0025] exist Figure 1In this embodiment, semiconductor device 100 includes, among other things, a processor 102 and a high-bandwidth memory (HBM) 104 operably coupled together via a bus 106. In some embodiments, semiconductor device 100 is a system-in-package (SIP) type semiconductor device. In some embodiments, semiconductor device 100 is a computer-in-memory (CIM) system. An example of semiconductor device 102 is shown in... Figure 2A As shown in the figure.

[0026] Figure 2A This is a cross-sectional view of a semiconductor device 200 according to some embodiments.

[0027] More specifically, semiconductor device 200 is a SIP-type semiconductor device. SIP 200 includes a processor 202 and an HBM 204 operably coupled together via bus 206. SIP 200 is... Figure 1 An example of a semiconductor device 100. In some embodiments, SIP 200 is a computer in memory (CIM) system. Processor 202 is Figure 1 Example of processor 102. HBM204 is Figure 1 An example of HBM 104. Bus 206 is... Figure 1 Examples of bus 106. In some embodiments, processor 202 is a central processing unit (CPU). In some embodiments, processor 202 is a graphics processing unit (GPU). In some embodiments, processor 202 is a vision processing unit (VPU). In some embodiments, processor 202 is a general-purpose graphics processing unit (GPGPU).

[0028] exist Figure 2A In this embodiment, SIP 200 also includes an interposer structure 208 and a printed circuit board (PCB) 210. The interposer structure 208 is formed over the PCB 210. The interposer 208 is formed of a semiconductor, such as silicon. The interposer 208 includes portions containing signal lines 206 and portions containing signal lines 216. In some embodiments, signals on the bus 208 communicate internally with respect to the SIP 200. Therefore, in such embodiments, the signal lines of the SIP 200 are described as internal SIP signal lines. In some embodiments, signals on at least some of the signal lines 216 communicate externally with respect to the SIP 200. Therefore, in such embodiments, the signal lines of the SIP 200 are generally described as external-SIP signal lines, although not every signal line 216 must carry signals communicating externally with respect to the SIP 200.

[0029] exist Figure 2AIn this embodiment, HBM 204 includes a stack 214 of four core dies 218(1), 218(2), 218(3), and 218(4). In some embodiments, HBM 204 includes a buffer die below the stack 214. Figure 2B In some embodiments, the stack 214 includes two, three, five, or more core dies. The HBM 204 also includes one or more differential dynamic voltage and frequency scaling (DDVFS) devices (see...). Figures 3A-3D ).

[0030] Figure 2B This is a three-quarter perspective view of HBM 204 according to some embodiments.

[0031] exist Figure 2B In the HBM 204, each of the core dies 218(1)-218(4) includes a memory cell MC, which are arranged / organized into two channels of eight libraries B0-B7. Each channel is arranged into two groups of libraries. Therefore, the HBM 204 includes eight channels 222(0)-222(7). More specifically, core die 218(0) is arranged in channels 222(0) and 222(1); core die 218(1) is arranged in channels 222(2) and 222(3); core die 218(2) is arranged in channels 222(4) and 222(5); and core die 218(3) is arranged in channels 222(6) and 222(7).

[0032] Furthermore, correspondingly, for example, core die 218(3) includes four groups of libraries. More specifically, channel 222(6) of core die 218(3) includes: group 224(0) consisting of libraries B0-B3; and group 222(4) consisting of libraries B4-B7. Channel 222(7) of core die 218(3) includes: group 224(1) consisting of libraries B0-B3; and group 222(3) consisting of libraries B4-B7. Relative to Figure 2B As shown on the X-axis, group 224(2) is located to the left of channel 222(6), and group 224(0) is located to the right of channel 222(6). Similarly, group 224(3) is located to the left of channel 222(7), and group 224(1) is located to the right of channel 222(7). In some embodiments, groups 224(2) and 224(3) are referred to as the left group, and groups 224(0) and 224(1) are referred to as the right group.

[0033] In some embodiments, one or more, but fewer than all, aggregates in a bank in HBM are called a lot. In some embodiments, one or more, but fewer than all, aggregates in a group in HBM are called a batch. In some embodiments, one or more, but fewer than all, aggregates in a channel in HBM are called a bundle. In some embodiments, one or more, but fewer than all, aggregates in a core die in HBM are called a collection.

[0034] exist Figure 2B In addition, HBM 204 also includes arrays 226(1) and 226(2) of through-silicon vias (TSVs) 228, and arrays 230(1) and 230(2) of TSVs 232. Relative to the X-axis, arrays 226(1) and 230(1) are located between the left and right groups of each of the channels 222(6) of core die 218(3), the channel 222(4) of core die 218(2), the channel 222(2) of core die 218(1), and the channel 222(0) of core die 218(0). Similarly, arrays 226(2) and 230(2) are located between the left and right groups of each of the channels 222(7) of core die 218(3), the channel 222(6) of core die 218(2), the channel 222(3) of core die 218(1), and the channel 222(1) of core die 218(0).

[0035] Compared to Figure 2B As shown on the Y-axis, array 230(1) is located between array 226(1) and array 230(2). Similarly, array 230(2) is located between array 226(2) and array 230(1).

[0036] In some embodiments, the TSV 228 of array 226(1) provides power system (PS) voltage to even-numbered channels 222(0), 222(2), 222(4) and 222(6), and the TSV 228 of array 226(2) transmits the PS voltage to odd-numbered channels 222(1), 222(3), 222(5) and 222(7).

[0037] In some embodiments, the TSV 232 of array 230(1) transmits input / output (I / O) signals and / or control signals to even-numbered channels 222(0), 222(2), 222(4) and TSV 222(6), and the TSV 230 of array 232(2) transmits I / O signals and / or control signals to odd-numbered channels 222(1), 222(3), 222(5) and 222(7).

[0038] exist Figure 2BIn this configuration, the memory cells MC in each of libraries B0-B7 are arranged in an array. Each memory cell MC is a dynamic random access memory (DRAM) cell. In some embodiments, the memory cell MC is a memory cell of a different type than a DRAM cell.

[0039] like Figure 2B As shown in the exploded diagram 223, each memory cell MC includes a capacitor C1 and a first field-effect transistor (FET) FET1. The capacitor C1 is used to store data voltages, such as bit values. That is, the capacitor C1 stores a voltage representing logic 0, i.e., bit 0, or a voltage representing logic 1, i.e., bit 1. The transistor FET1 is a switch used to transfer the data voltage to the capacitor C1. In the exploded diagram 223, the DRAM cell MC is presented in the i-th row and j-th column of the array. Therefore, the switch FET1 is electrically coupled between the i-th bit line B(i) and the first terminal of the capacitor C1, while the second terminal of the capacitor C1 is electrically coupled to a low system voltage, such as ground, in contrast to a high system voltage, VDD. In some embodiments, ground is VSS. The gate electrode of the switch FET1 is electrically coupled to the j-th row-enable line RE(j). When the switch FET1 is turned on by a signal on the row-enable line RE(j), the capacitor C1 is electrically coupled to the bit line BL(i).

[0040] exist Figure 2B In the library, each of B0-B7 includes the corresponding sensing units S0-S7 (see...). Figures 2C-2D For example, the library B0 of group 224(0) of channel 222(6) of core die 218(3) includes sensing units S0. Physically / spatially, sensing units S0-S7 are located close to their corresponding libraries B0-B7. Each of sensing units S0-S7 generates environmental information, such as temperature and / or threshold voltage. Since sensing units S0-S7 are close to their corresponding libraries B0-B7, the environmental information generated by sensing units S0-S7 is considered to represent all memory cells MC in their corresponding libraries B0-B7. For example, since the sensing unit S2 of the group 224(0) of channel 226(6) of core die 218(3) is close to the group 224(0) of channel 226(6) of core die 218(3), the environmental information generated by the sensing unit S2 of the group 224(0) of channel 226(6) of core die 218(3) is considered to represent all memory cells MC in the group 224(0) of channel 226(6) of core die 218(3).

[0041] like Figure 2BAs shown: Relative to the Y-axis, sensing units S0-S7 are centered within their respective libraries B0-B7; relative to the X-axis, sensing units S0-S7 are located to the right of their respective libraries B0-B7. In some embodiments, relative to both the X-axis and Y-axis, sensing units S0-S7 are centered within their respective libraries B0-B7. In some embodiments, relative to both the X-axis and Y-axis, sensing units S0-S7 are located in positions other than those described above.

[0042] To simplify the explanation, Figure 2B Not all components of the HBM 204 are shown. Furthermore, for the sake of simplicity, Figure 2B Not all components shown in HMB 204 are labeled. For example, in Figure 2B In addition, the HBM 204 also includes one or more DDVFS devices (see [link]). Figures 3A-3D In some embodiments, each of the core dies 218(0)-218(3) includes one or more DDVFS devices. In some embodiments, one or more DDVFS devices are located in the buffer die 212.

[0043] In some embodiments, the HBM 204 conforms to standard JESD-235, which is defined by a standards-setting organization called the Joint Electronic Devices Engineering Committee (JEDEC). In some embodiments, the HBM 204 conforms to standard JESD-235A, which is defined by JEDEC. In some embodiments, the HBM 204 conforms to the HMB standard defined by another standards-setting organization. For example, details of typical HBMs (although excluding, for example, the sensor S0-S7 and DDVFS devices disclosed herein) can be found in U.S. Patent No. 10,180,906, granted January 15, 2019, and U.S. Pre-Publication No. 20210024798, published August 12, 2021, the entire contents of which are incorporated herein by reference.

[0044] Figures 2C-2E This is a block diagram of the corresponding sensing unit according to some embodiments.

[0045] Figure 2C The sensing unit 235C is Figure 2B Examples of each of the sensing units S0-S7. Therefore, sensing unit 235C in... Figure 2C It is also marked as "Sx".

[0046] exist Figure 2C In this context, sensing unit 235C includes a temperature sensor 236 and a threshold voltage sensor 238. Temperature sensor 236 (see...) Figures 5A-5BThe temperature sensor 236 is configured to sense temperature and output a signal T representing the sensed temperature. Since the temperature sensor 236 is near the first given instance of a storage cell MC in a given library, the signal T is considered to represent the temperature of all instances of storage cells MC in the given library. The temperature signal T is an example of an ambient signal. Threshold voltage detector 238 (see...) Figures 6A-6C The system is configured to detect a threshold voltage and output a signal Vt representing the sensed threshold voltage. Since the temperature sensor 236 is close to a given instance of transistor FET1 in a second given instance of the memory cell MC in a given library, the signal Vt is considered to represent the threshold voltage of all instances of transistor FET1 in all instances of the memory cell MC in the given library. The threshold voltage Vt is an example of an ambient signal. In some embodiments, the first given instance of the memory cell MC in the given library is the same as the second given instance of the memory cell MC in the given library.

[0047] In some embodiments, Figure 2C The sensing unit 235C includes a temperature sensor 236 but does not include a threshold voltage sensor 238. Such an embodiment... Figure 2D The sensor unit is shown as 235D.

[0048] In some embodiments, Figure 2C The sensing unit 235C includes a threshold voltage sensor 238 but does not include a temperature sensor 236. Such an embodiment... Figure 2E The sensor unit is shown as 235E.

[0049] Figures 3A-3D This is a block diagram of the corresponding HBM according to some embodiments.

[0050] corresponding Figures 3A-3D Each of HBM 304A, 304B, 304C and 304D is Figure 2B An example of HBM 204.

[0051] In some respects, Figures 3A-3D Is with Figure 2B The simplified representation of the corresponding HBM 304A-304D compared to HBM 204. However, in some aspects, compared to Figure 2B Compared to HBM 204, Figures 3A-3D This is a more detailed representation of HBM 304A-304D.

[0052] exist Figure 3A and Figures 3C-3D In the HBM 304A, 304C, and 304D, each includes: a core die 218(x); a channel 222(x); a library Bx; and a sensing unit 235C. The core die 218(x) is... Figure 2BExamples of each of the core die 218(0)-218(3). Channel 228(x) is Figure 2B Examples of each of channels 222(0)-222(7). Library Bx is Figure 2B Examples for each of libraries B0-B7. Figure 3B In HBM 304B, libraries B_α, B_β, B_γ, and B_δ are included. When libraries B_α, B_β, B_γ, and B_δ are included in the left-hand group 224(x), they correspond to libraries B4-B7. When libraries B_α, B_β, B_γ, and B_δ are included in the right-hand group 224(x), they correspond to libraries B0-B3.

[0053] exist Figures 3A-3D In addition, each of the corresponding HBM 304A, 304B, 304C, and 304D also includes Differential Dynamic Voltage and Frequency Scaling (DDVFS) 340 (see [link]). Figures 4A-4G ).exist Figures 3A-3D In each of them, the DDVFS device 340 is included in the core die 218(x). In some embodiments, the core die 218(x) includes multiple instances of the DDVFS device 340.

[0054] In some embodiments, one or more instances of the DDVFS device 340 are located in a buffer die ( Figure 2B In some embodiments, one or more instances of the DDVFS device 340 are located in a buffer die, rather than in a corresponding instance of the core die 218(x). Figure 2B In some embodiments, one or more instances of the DDVFS device 340 are located in the processor 202. Figure 2A In some embodiments, one or more instances of the DDVFS device 340, other than those in the corresponding instance of the core die 218(x), are located in the processor 202 ( Figure 2A In some embodiments, one or more instances of the DDVFS device 340 are located in locations other than those described above.

[0055] exist Figures 3A-3D In the configuration, each of the corresponding HBM 304A-304D is arranged such that the DDVFS device 340 receives: a temperature sensor 236 from the sensing unit 235C (see...). Figures 5A-5BThe temperature T of the storage cell MC in the library Bx is considered to represent the temperature of all instances of the storage cell MC in the library Bx, as the temperature sensor 236 is close to a given instance of transistor FET1 in a second given instance of the storage cell MC in the library Bx. The threshold voltage Vt from the threshold voltage detector 238 of the sensing unit 235C is also considered to represent the threshold voltage of all instances of transistor FET1 in all instances of the storage cell MC in the library Bx, as the temperature sensor 236 is close to a given instance of transistor FET1 in a second given instance of the storage cell MC in the library Bx. In some embodiments, the first given instance of the storage cell MC in the library Bx is the same as the second given instance of the storage cell MC in the library Bx.

[0056] exist Figures 3A-3D In each of them, the DDVFS device 340 is configured to regulate: the local clock signal (see...) Figures 4A-4G Based on temperature T and / or threshold voltage Vt; and / or based on temperature T and / or threshold voltage Vt, regulate the local power supply (PS) voltage (see Figures 4A-4G Each of the local clock signal and the local PS voltage is an example of a transistor temperature effect (TTA) parameter. By adjusting the local clock signal and / or the local PS voltage, the DDVFS device adaptively adjusts / controls the memory cell MC (see [link to relevant documentation]). Figure 2B The temperature of the corresponding instance.

[0057] Typically, to reduce temperature, the DDVFS device 340 reduces the frequency of the local clock signal and / or the value of the local PS voltage. Generally, reducing the frequency of the local clock signal and / or the value of the local PS voltage also tends to reduce the performance of the memory cell MC that receives the local clock signal and / or the local PS voltage. Conversely, when the current temperature is below the maximum permissible temperature, allowing the temperature of the memory cell MC that receives the local clock signal and / or the local PS voltage to rise safely, the performance of the memory cell MC that receives the local clock signal and / or the local PS voltage is typically improved by increasing the frequency of the local clock signal and / or the value of the local PS voltage through the DDVFS 340. According to another approach of DVFS technology using monolithic thermal throttling, the same clock signal is provided to all bit cells of all core dies. According to this other approach, the HMB is treated as monolithic, i.e., not as comprising different parts exhibiting different characteristics, and the frequency of the clock signal is increased only when the temperature of all parts of all core dies in the HMB can rise safely. However, typically, the portion of a given core die exceeding the permissible temperature is only a small portion of that given core die. As a result, while monolithic thermal throttling according to the alternative approach cools a small portion of a given core die, it also unnecessarily prevents most of the given core die and the rest of the core chip from experiencing a safe temperature rise associated with increases in clock signal frequency and PS voltage signal value. This leads to an unnecessarily degraded performance of most of the given core chip and the rest of the core chip, resulting in both waste and inefficiency. Compared to monolithic thermal throttling, the HBM 304A (library range, discussed below), HBM 304B (group range, discussed below), HBM 304C (channel range, discussed below), and HBM 304D (core range, discussed below) are more refined in terms of the portion of HBM to be cooled, thus resulting in less waste and higher efficiency.

[0058] As discussed in more detail below, Figures 3A-3D They differ from each other, for example, in which components of the corresponding HBM 304A-304D are configured to receive local clock signals and / or local voltages from the DDVFS device 340, and in how many instances of the sensing unit 235C transmit temperature T and / or threshold voltage Vt to the DDVFS device 340.

[0059] Specific direction Figure 3A The HBM 304A is configured such that each instance of library Bx receives a local clock signal and a local power supply voltage from the corresponding instance of DDVFS device 340. Therefore, the HBM 304A is configured such that each instance of sensing unit 235C (i.e., each library Bx) transmits temperature T and threshold voltage Vt to DDVFS device 340. This is because each instance of library Bx receives a local clock signal and a local power supply voltage from the corresponding instance of DDVFS device 340. Figure 3A The local clock signal and local power supply voltage of the DDVFS device 340 in the middle, so in Figure 3A The local clock signal is labeled CLK_bnk, and the local PS voltage is labeled PSV_bnk. Each of the signals CLK_bnk and PSV_bnk is an example of a TTA parameter.

[0060] Figure 3A The context of the adjective "local" is library-specific, or described as library-by-library. Therefore, the arrangement of the HBM 304A results in library-wide temperature regulation between corresponding memory cells (not shown) in each instance of library Bx; that is, the HBM 304A arrangement results in library-wide differentiated thermal throttling. This library-wide differentiated thermal throttling contrasts with the overall thermal throttling of other methods. According to the alternative approach of DVFS technology, monolithic thermal throttling is used, i.e., providing the same clock signal to all bit cells of all core dies, thus treating the HMB as monolithic according to the alternative approach, i.e., not treating the HBM as comprising different parts with different performance. However, typically, only a few parts of a given core die exceed the allowable temperature. As a result, monolithic thermal throttling according to the alternative approach not only cools a few parts of a given core die but also unnecessarily cools most of the given core die and the rest of the other core dies, leading to an unnecessarily reduced performance of most of the given core die and the rest of the other core dies, which is wasteful and inefficient. Compared to overall thermal throttling, which is an alternative approach, the HBM 304A's library-range differentiated thermal throttling is more refined in terms of the portion of HBM that needs to control temperature (e.g., cooling), resulting in less waste and greater efficiency.

[0061] Specific direction Figure 3B The HBM 304B is configured such that each instance of group 224(x) receives a local clock signal and a local power supply voltage from the corresponding instance of DDVFS device 340. Therefore, each of libraries B_a, B_β, B_γ, and B_δ in group 224(x) receives the same local clock signal and the same local power supply voltage from DDVFS device 340. Thus, the HBM 304B is configured such that sensing unit 235C of one of libraries B_α, B_β, B_γ, and B_δ transmits temperature T and threshold voltage Vt to DDVFS device 340. Figure 3B In this diagram, library B_γ is shown as transmitting temperature T and threshold voltage Vt to DDVFS device 340. In some embodiments (not shown), one of libraries B_α, B_β, and B_δ transmits temperature T and threshold voltage Vt to DDVFS device 340 instead of library B_γ. This is because each instance of group 224(x) receives from... Figure 3BThe local clock signal and local power supply voltage of the DDVFS device 340 in the group 224(x) are received from each of the libraries B_α, B_β, B_γ and B_δ. Figure 3B The DDVFS device 340 in the middle has the same local clock signal and the same local power supply voltage. Figure 3B In this context, the local clock signal is labeled CLK_grp and the local PS voltage is labeled PSV_grp. Each of the signals CLK_grp and PSV_grp is an example of a TTA parameter.

[0062] Figure 3B The context of the adjective "local" is group-specific, or described as group-by-group. Therefore, the arrangement of the HBM 304B results in group-wide temperature regulation between corresponding memory cells (not shown) in each instance of group 224(x), i.e., the HBM 304B arrangement provides group-wide differentiated thermal throttling. This group-wide differentiated thermal throttling contrasts with the monolithic thermal throttling of other methods. Compared to monolithic thermal throttling of other methods, the group-wide differentiated thermal throttling of the HBM 304B is more refined in relation to the portion of the HBM to be cooled, resulting in less waste and greater efficiency.

[0063] about Figure 3B Because the HBM 304B is configured such that one of the sensing units 235C of libraries B_a, B_β, B_γ, and B_δ transmits the temperature T and threshold voltage Vt to the DDVFS device 340, in some embodiments (not shown), at least, but not all, of libraries B_α, B_β, B_γ, and B_δ in a given instance of group 224(x) includes the corresponding sensing unit 245C.

[0064] Specific direction Figure 3C The HBM 304C is configured such that each instance of channel 222(x) receives a local clock signal and a local power supply voltage from the corresponding instance of DDVFS device 340. Therefore, each instance of group 224(x) in channel 222(x), and each corresponding instance of library Bx in channel 222(x), receives the same local clock signal and the same local power supply voltage from DDVFS device 340. Thus, the HBM 304C is configured such that sensing unit 235C of one of library Bx in one of group 224(x) transmits temperature T and threshold voltage Vt to DDVFS device 340. Because each instance of channel 222(x) receives a local clock signal and the same local power supply voltage from the corresponding instance of DDVFS device 340. Figure 3C The local clock signal and local power supply voltage of the DDVFS device 340 in the middle are... Figure 3CIn this context, the local clock signal is labeled CLK_chan and the local PS voltage is labeled PSV_chan. Each of the signals CLK_chan and PSV_chan is an example of a TTA parameter.

[0065] Figure 3C The context of the adjective "local" is channel-specific, or described as channel-by-channel. Therefore, the arrangement of the HBM304C results in channel-range regulation of the corresponding temperature between memory cells (not shown) in each instance of channel 222(x), i.e., the HBM 304C arrangement provides channel-range type differential thermal throttling. This channel-range differential thermal throttling contrasts with monolithic thermal throttling methods. Compared to monolithic thermal throttling of another approach, the channel-range differential thermal throttling of the HBM 304C is more refined in terms of the portion of the HBM to be cooled, resulting in less waste and higher efficiency.

[0066] about Figure 3C Since the HBM 304C is configured such that the sensing unit 235C of one of the libraries Bx in one of the groups 224(x) transmits the temperature T and threshold voltage Vt to the DDVFS device 340, in some embodiments (not shown), not every instance of the group 224(x) in a given instance of the channel 222(x), nor every instance of the library Bx in a given instance of the channel 222(x), includes the corresponding sensing unit 245C.

[0067] Specific direction Figure 3D The HBM 304D is configured such that each instance of core die 218(x) receives a local clock signal and a local power supply voltage from a corresponding instance of DDVFS device 340. Therefore, each instance of channel 222(x) in core die 218(x), and consequently each corresponding instance of group 224(x) in core die 218(x), and consequently each corresponding instance of library Bx in core die 218(x), receives the same local clock signal and the same local power supply voltage from DDVFS device 340. Therefore, the HBM 304D is configured such that a sensing unit 235C of library Bx in group 224(x) of channel 222(x) in one of core die 218(x) transmits temperature T and threshold voltage Vt to DDVFS device 340. Because each instance of core die 218(x) receives a local clock signal and a local power supply voltage from a corresponding instance of DDVFS device 340, the HBM 304D transmits the same local clock signal and the same local power supply voltage from DDVFS device 340. Figure 3D The local clock signal and local power supply voltage of the DDVFS device 340 in the middle are... Figure 3D In this context, the local clock signal is labeled CLK_core and the local PS voltage is labeled PSV_core. Each of the signals CLK_core and PSV_core is an example of a TTA parameter.

[0068] Figure 3D The context of the adjective "local" is core-specific, or described as core-by-core. Therefore, the arrangement of the HBM304D results in core-range regulation of the corresponding temperature between memory cells (not shown) in each instance of the core die 218(x), i.e., the HBM 304D arrangement provides core-range type differential thermal throttling. This core-range differential thermal throttling contrasts with monolithic thermal throttling methods. Compared to monolithic thermal throttling, the core-range differential thermal throttling of the HBM 304D is more refined in terms of the portion of the HBM to be cooled, resulting in less waste and greater efficiency.

[0069] about Figure 3D Because the HBM 304D is configured such that the sensing unit 235C of one of the groups 224(x) in one of the channels 222(x) in one of the core die 218(x) transmits the temperature T and threshold voltage Vt to the DDVFS device 340, in some embodiments (not shown), not every instance of the channel 222(x) in a given instance of the core die 218(x), nor every instance of the group 224(x) in a given instance of the channel 222(x), nor every instance of the group Bx in a given instance of the channel 222(x) includes the corresponding sensing unit 245C.

[0070] about Figures 3A-3B In some embodiments (not shown), each of the corresponding HBM 304A-304D includes Figure 2D The sensing unit is 235D instead of Figure 2C The sensing unit 235C. To recap, the sensing unit 235D includes a temperature sensor 236 but not a threshold voltage sensor 238. Therefore, in such an embodiment, the corresponding HBM 304A-304D (see...) Figure 4B , Figure 4C and Figure 4F Each of the DDVFS devices is arranged such that the DDVFS device 340 receives only the temperature T from the temperature sensor 236.

[0071] about Figures 3A-3B In some embodiments (not shown), each of the corresponding HBM 304A-304D includes Figure 2E The sensing unit is 235E instead of Figure 2C The sensing unit 235C. To recap, the sensing unit 235E includes a threshold voltage sensor 238 but not a temperature sensor 236. Therefore, in such an embodiment, the corresponding HBM 304A-304D (see...) Figure 4D , Figure 4E and Figure 4GEach of the DDVFS devices is arranged such that the DDVFS device 340 receives only the threshold voltage Vt from the temperature sensor 236.

[0072] Figures 4A-4G This is a block diagram of the corresponding DDVFS devices 442A-442G according to some embodiments.

[0073] exist Figures 4A-4G In the context, each of the corresponding DDVFS devices 442A-442G is... Figures 3A-3D Example of a DDVFS device 340.

[0074] exist Figure 4A In this DDVFS device 442A, there are: a temperature comparator 444; a threshold voltage comparator 446; a controller 448A; a clock generator 454; and a PS voltage (PSV) generator 456. The controller 448A includes a clock regulator 450 and a PS voltage regulator 452.

[0075] Temperature comparator 444 is configured to receive from Figures 3A-3D The temperature T of the temperature sensor 236 with sensing unit 235C, and the corresponding... Figures 3A-3D The maximum permissible temperature signal MAX_temp for any instance of the HBM 304A-304D memory cell MC. Temperature comparator 444 is also configured to: perform a first comparison by comparing temperature T with temperature reference MAX_temp; and derive a first output signal representing the result of the first temperature comparison, wherein the first output signal indicates which is larger, temperature T or temperature reference MAX_temp.

[0076] Temperature comparator 444 is also configured to receive a response. Figures 3A-3D The signal MOD_temp indicates the moderate temperature of any instance of the HBM 304A-304D memory cell MC. If the temperature T is less than MAX_temp, the increase in temperature T can be caused by... Figures 3A-3D Instances of memory cells MC that receive the corresponding local clock signal and / or local PS voltage are safely adapted. Generally, the performance of instances of memory cells MC that receive the corresponding local clock signal and / or local PS voltage is improved by increasing the frequency of the corresponding local clock signal and / or increasing the value of the corresponding local PS voltage through DDVFS 340. Therefore, temperature comparator 444 is also configured to: perform a second comparison by comparing temperature T with temperature reference MOD_temp; and derive a second output signal representing the result of the second temperature comparison, wherein the second output signal indicates which is larger, temperature T or temperature reference MOD_temp.

[0077] Threshold voltage comparator 446 is configured to receive from Figures 3A-3DThe threshold voltage Vt of the threshold voltage detector 238 of the sensing unit 235C, and the corresponding Figures 3A-3D The minimum permissible threshold voltage signal MIN_Vt for any instance of the HBM 304A-304D transistor FET1 (and therefore any instance of the memory cell MC).

[0078] The threshold voltage comparator 446 is also configured to: compare the threshold voltage Vt with a voltage reference MIN_Vt; and to produce an output signal representing the result of the voltage comparison, wherein the output signal indicates which is larger, the threshold voltage Vt or the voltage reference MIN_Vt.

[0079] exist Figure 4A In this configuration, controller 448A is configured to receive first and second temperature comparison results from temperature comparator 444 and voltage comparison results from threshold voltage comparator 446. More specifically, each of the PS voltage regulator 452 and clock regulator 450 of controller 448A is configured to receive first and second temperature comparison results from temperature comparator 444 and voltage comparison results from threshold voltage comparator 446.

[0080] The clock regulator 450 (and therefore the controller 448A) is configured to increase or decrease the frequency of the local clock signal based on the first and second temperature comparison results from the temperature comparator 444 and / or the voltage comparison results from the threshold voltage comparator 446.

[0081] The local clock signal CLK_local is Figure 3A CLK_bnk, Figure 3B CLK_grp, Figure 3C CLK_chan or Figure 3D Examples include CLK_core, etc. More specifically, clock regulator 450 is configured to generate control signals CLK_up and CLK_down, thereby controlling CLK generator 454 to increase or decrease the frequency of the local clock signal CLK_local accordingly.

[0082] Signals CLK_up and CLK_down are mutually exclusive. In some embodiments, when control signal CLK_up is high (indicating that the frequency of the local clock signal CLK_local will increase), control signal CLK_down is low (indicating that the local clock frequency signal CLK_local will not decrease). Conversely, when control signal CLK_up is low (indicating that the frequency of the local clock signal CLK_local will not increase), control signal CLK_down is high (indicating that the frequency of the local clock signal CLK_local will decrease). In some embodiments (not shown), clock regulator 450 outputs a single control signal to CLK generator 454 instead of control signals CLK_up and CLK_down. In such embodiments, the single control signal has a level corresponding to whether the frequency of the local clock signal CLK_local is to be increased or decreased.

[0083] In some embodiments, when the first temperature comparison result indicates that the temperature T is higher than MAX_temp, the clock regulator 450 outputs a low-level control signal CLK_up and a high-level control signal CLK_down. This combination of levels of the control signals CLK_up and CLK_down causes the CLK generator 454 to change, i.e., reduce the frequency of the local clock signal CLK_local.

[0084] In some embodiments, when the first voltage comparison result indicates that the threshold voltage is lower than MIN_Vt, the clock regulator 450 outputs a low-level control signal CLK_up and a high-level control signal CLK_down. This combination of levels of the control signals CLK_up and CLK_down causes the CLK generator 454 to change, i.e., reduce the value of the local PS voltage PSV_local.

[0085] In some embodiments, when a first temperature comparison result indicates that temperature T is lower than MAX_temp and a second temperature comparison result indicates that temperature T is lower than MOD_temp, the clock regulator 450 outputs a high-level control signal CLK_up and a low-level control signal CLK_down. This combination of the states of the control signals CLK_up and CLK_down causes the CLK generator 454 to change, that is, to increase the frequency of the local clock signal CLK_local to the maximum allowed value.

[0086] The PS voltage regulator 452 (and therefore the controller 448A) is configured to increase or decrease the value of the local PS voltage PSV_local based on the first and second temperature comparison results from the temperature comparator 444 and / or the voltage comparison result from the threshold voltage comparator 446. The local PS voltage PSV_local is... Figure 3APSV_bnk, Figure 3B PSV_grp, Figure 3C PSV_chan or Figure 3D Examples include PSV_core, etc. More specifically, the PS voltage regulator 452 is configured to generate control signals PSV_up and PSV_down, thereby controlling the PSV generator 456 to increase or decrease the value of the local PS voltage PSV_local accordingly.

[0087] Signals PSV_up and PSV_down are mutually exclusive. In some embodiments, when signal PSV_up is high (indicating an increase in the value of the local PS voltage PSV_local), signal PSV_down is low (indicating that the value of the local PS voltage PSV_local will not decrease). Conversely, when signal PSV_down is high (indicating a decrease in the value of the local PS voltage PSV_local), signal PSV_up is low (indicating that the value of the local PS voltage PSV_local will not increase). In some embodiments (not shown), the PS voltage regulator 452 outputs a single control signal to the PSV generator 456 instead of control signals PSV_up and PSV_down. In such embodiments, the single control signal has a level that correspondingly indicates whether the value of the local PS voltage PSV_local is to be increased or decreased.

[0088] In some embodiments, when the first voltage comparison result indicates that the threshold voltage Vt is lower than MIN_Vt, the PSV regulator 452 outputs a low-level control signal PSV_up and a high-level control signal PSV_down. This combination of the levels of the control signals PSV_up and PSV_down causes the PSV generator 456 to change, i.e., reduce the value of the local PS voltage PSV_local.

[0089] In some embodiments, when the first temperature comparison result indicates that the temperature T is higher than MAX_temp, the PSV regulator 452 outputs a low-level control signal PSV_up and a high-level control signal PSV_down. This combination of the levels of the control signals PSV_up and PSV_down causes the PSV generator 456 to change, i.e., reduce the value of the local PS voltage PSV_local.

[0090] Optionally, in some embodiments, the DDVFS 442A is configured with a feedback loop (shown as a dashed line, i.e., a broken line) that feeds back the frequency ω of the local clock signal CLK_local to the clock conditioner 450. In such embodiments, the clock conditioner 450 (and therefore the controller 448A) is configured to increase or decrease the frequency of the local clock signal CLK_local by the CLK generator 454, based in part on (A) the feedback value of the local clock signal CLK_local and (B) the first and second temperature comparison results from the temperature comparator 444 and / or the voltage comparison result from the threshold voltage comparator 446.

[0091] Optionally, in some embodiments, the DDVFS 442A is configured with a feedback loop (shown as a dashed line, i.e., a broken line) that feeds back the value of PSV_local to the PS voltage regulator 452. In such embodiments, the PS voltage regulator 452 (and therefore the controller 448A) is configured to increase or decrease the value of the local PS voltage PSV_local by the PSV generator 456, in part based on (A) the feedback value of the local PSV voltage PSV_local and (B) the first and second temperature comparison results from the temperature comparator 444 and / or the voltage comparison result from the threshold voltage comparator 446.

[0092] In some embodiments, Figure 4A The DDVFS device 442A includes a temperature comparator 444 but does not include a threshold voltage comparator 446. Such an embodiment in... Figure 4B , Figure 4C and Figure 4F The corresponding DDVFS devices 442B, 442C and 442F are shown in the figure.

[0093] In some embodiments, Figure 4B The DDVFS device 442B, and more specifically, the controller 445B, includes a clock regulator 450 but does not include a PS voltage regulator 452. Such an embodiment is shown as... Figure 4C The DDVFS device 442C. In some embodiments, Figure 4B The DDVFS device 442B, and more specifically, the controller 445B, includes a PS voltage regulator 452 but not a clock regulator 450. Such an embodiment is shown as... Figure 4F The DDVFS device 442F.

[0094] In some embodiments, Figure 4A The DDVFS device 442A includes a threshold voltage comparator 446 but does not include a temperature comparator 444. Such an embodiment in... Figure 4D , Figure 4E and picture Figure 4GThe corresponding DDVFS devices are shown in the diagram as 442D, 442E, and 442G.

[0095] In some embodiments, Figure 4D The DDVFS device 442D, and more specifically, the controller 445D, includes a PS voltage regulator 452 but not a clock regulator 450. Such an embodiment is shown as... Figure 4E The DDVFS device 442E. In some embodiments, Figure 4D The DDVFS device 442D, and more specifically, the controller 445D, includes a clock regulator 450 but does not include a PS voltage regulator 452. Such an embodiment is shown as... Figure 4G The DDVFS device 442G.

[0096] Figures 5A-5B This is a circuit diagram of the corresponding temperature sensors 522A-522B according to some embodiments.

[0097] Each of the temperature sensors 522A-522B includes a bias current generator 558, a bipolar junction transistor (BJT), and a readout circuit 560. The bias current generator 558 is electrically coupled to node ndl. Details of a typical bias current generator can be found, for example, in U.S. Patent No. 8,183,910, granted May 22, 2012 (A circuit for a device under test includes: a first node for receiving a first voltage independent of temperature; a second node for receiving a second voltage corresponding to a circuit parameter; and a comparator for providing an output current corresponding to a comparison of the voltages at the first and second nodes; wherein the circuit parameter is selected from a group consisting of a transistor threshold voltage, a transistor saturation current, and an amount proportional to temperature. An integrated circuit includes: a logic circuit defining a function; and a test macro circuit including: a first circuit element, A semiconductor wafer process monitoring circuit includes: a first circuit for receiving a first current to provide a predetermined voltage at a first node; a second circuit for providing a voltage corresponding to a circuit parameter to a second node; and a comparator for providing an output current corresponding to a comparison of the voltages at the first node and the second node; wherein the circuit parameter is selected from a group consisting of a transistor threshold voltage, a transistor saturation current, and an amount proportional to temperature. A semiconductor wafer process monitoring circuit includes: a plurality of integrated circuit wafers fabricated on the semiconductor wafer; a dicing region separated from the integrated circuit wafers; and at least one device under test circuitry, including: a first circuit element for providing a predetermined voltage at a first node. A second circuit element for providing a voltage corresponding to a circuit parameter to a second node; and a comparator for providing a comparison output current corresponding to the voltages of the first and second nodes; wherein the circuit parameter is selected from the group consisting of a transistor threshold voltage, a transistor saturation current, and a number of proportional temperatures. (or U.S. Patent No. 9,166,067, granted October 20, 2015 (A bandgap reference circuit comprising: a current mirror based on an error amplifier coupled between a first power node and a pair of intermediate voltage nodes; a pair of matching diodes for providing a current proportional to absolute temperature (PTAT), the pair of matching diodes comprising: a first and a second...) A first intermediate voltage node and a second power supply node are connected between a pair of intermediate voltage nodes; and a second diode is connected in series with a resistor located between the second intermediate voltage node and the second power supply node of the pair of intermediate voltage nodes, wherein each diode is formed in a p-type substrate and includes one or more unit cells, each unit cell including: an n-well in which a SiGe compound contact region is formed; a p-well formed around the n-well; and an N+ implantation region formed in the n-well and spaced apart from the SiGe compound contact region, wherein a PN diode heterojunction is formed between the n-well and the SiGe compound contact region. (The entire contents of each patent are incorporated herein by reference.)The readout circuit 560 is electrically coupled to node nd1 and configured to generate temperature T. In some embodiments, the readout circuit 560 includes a buffer circuit.

[0098] exist Figure 5A In this configuration, transistor BJT1 is an NPN type BJT electrically coupled between node nd1 and a low system voltage (e.g., ground), contrasting with a high system voltage VDD. In some embodiments, ground is VSS. Transistor BJT1 has a diode configuration in which the base terminal of BJT1 is electrically coupled to the collector terminal, i.e., node nd1.

[0099] exist Figure 5B In this configuration, transistor BJT2 is a PNP type BJT, electrically coupled between node ndl and ground. Transistor BJT2 has a diode configuration, allowing the base terminal of BJT2 to be electrically coupled to the emitter terminal, i.e., to ground.

[0100] Figures 6A-6C This is a circuit diagram of the corresponding threshold voltage detectors 622A-622C according to some embodiments.

[0101] Each threshold voltage detector 622A-622C includes a temperature-to-absolute-temperature (PTAT) current generator 564 and one or more field-effect transistors (FETs). The PTAT current generator 564 is electrically coupled to node nd2. In some embodiments (not shown), each of the voltage detectors 622A-622C includes temperature-to-absolute-temperature (CTAT) circuitry. Details of a typical PTAT current generator can be found, for example, in U.S. Patent No. 8,183,910, granted May 22, 2012, or U.S. Patent No. 9,166,067, granted October 20, 2015, the entire contents of which are incorporated herein by reference.

[0102] exist Figure 6A In this embodiment, the threshold voltage detector 638A includes a transistor FET2, which is an N-type FET transistor and is electrically coupled between node nd2 and a low system voltage, such as ground, opposite to the high system voltage VDD. In some embodiments, ground is VSS. The transistor FET2 has a diode configuration in which the gate terminal of FET2 is electrically coupled to the drain terminal, i.e., connected to node nd2. The signal on node nd2 represents the threshold voltage Vt.

[0103] exist Figure 6B In this design, the threshold voltage detector 638B includes a transistor FET3, which is a P-type FET transistor electrically coupled between node nd2 and ground. The transistor FET3 has a diode configuration, where the gate terminal of FET3 is electrically coupled to the drain terminal, i.e., ground. The signal at node nd2 represents the threshold voltage Vt.

[0104] about Figure 6C The threshold voltage detector 638C is a combination of threshold voltage detectors 638a and 638B. More specifically, the threshold voltage detector 638C includes... Figure 6A FET2 and Figure 6B FET3. In Figure 6C In the diagram, FET2, configured with a diode, is electrically coupled between nodes nd2 and nd3, while FET3, also configured with a diode, is electrically coupled between node nd3 and ground. The signal at node nd2 represents the threshold voltage Vt.

[0105] Figures 7A-7E The corresponding flowcharts 700A-700E are based on some embodiments.

[0106] More specifically, flowcharts 700A-700E correspond to differentiated thermal throttling methods for high-bandwidth memory (HBM). Examples of HBMs include... Figure 2B HBM 204, corresponding Figures 3A-3D HBM 204A-304D, etc. Flowchart 700A includes blocks 702A, 704A, and 706A.

[0107] In block 702A, first and second instances of temperature signals and / or first and second instances of threshold voltage signals are received from each of the first and second sensing units correspondingly arranged in the core die. The first and second instances of temperature signals and the first and second instances of threshold voltage signals are associated with first and second transistors in corresponding first and second memory cells of corresponding first and second libraries of the corresponding core die.

[0108] Regarding box 702A, examples of the first and second sensing units are: Figure 2C Examples of sensing unit 235C, etc., where sensing unit 235C is Figure 2B Examples of each instance of the sensing units S0-S7. Examples of the first and second temperature signals are provided by... Figure 2C A corresponding example of the temperature T generated by the temperature sensor 236, in a corresponding example of the sensing unit 235C, etc. Examples of the first and second threshold voltage signals are generated in a corresponding example of the sensing unit 235C, etc. Figure 2C A corresponding instance of the threshold voltage detector 238 generates a corresponding instance of the threshold voltage Vt. Examples of the first and second transistors in the corresponding first and second memory cells of the corresponding core die are... Figure 2B The corresponding first and second instances of the corresponding first and second memory cells MC of the corresponding core die 218(0)-218(3) library B0-B7. From box 702A, the process proceeds to box 704A.

[0109] In block 704A, the first clock and / or first PS voltage of one or more memory cells in the first group are adjusted accordingly based on a first temperature (see block 702A) and / or a first threshold voltage (see block 702A). The first group consists of one or more corresponding libraries of HBM. Such adjustment thereby changes the corresponding temperature in one or more memory cells of the first group. In some embodiments, both the first clock and the first PS voltage of one or more memory cells in the first group are adjusted. In some embodiments, the first clock and / or the first PS voltage are adjusted based on the first temperature and the first threshold voltage. In some embodiments, the first clock and / or the first PS voltage are adjusted based only on the first temperature. In some embodiments, the first clock and / or the first PS voltage are adjusted based only on the first threshold voltage.

[0110] Regarding box 704A, examples of adjusting the first clock include decreasing or increasing the frequency of the first clock. Examples of adjusting the first PS voltage include decreasing the value / amplitude of the first PS voltage. Examples of changing the temperature in the memory cell include decreasing or increasing the temperature of the memory cell. Examples of the first clock include... Figures 4A-4D The local clock signal CLK_local in each Figure 3A The local clock signal CLK_bnk in Figure 3B The local clock signal CLK_grp in Figure 3C The local clock signal CLK_chan in Figure 3D The first instance of the local clock signal CLK_core, etc. Examples of the first PS voltage include... Figures 4A-4D The local PS voltage PSV_local in each Figure 3A The local PS voltage PSV_bnk in Figure 3B The local PS voltage PSV_grp in Figure 3C The local PS voltage PSV_chan in Figure 3D The first instance of the local PS voltage PSV_core, etc. From box 704A, the process proceeds to box 706A.

[0111] In block 706A, the second clock or second PS voltage of one or more memory cells in the second group is adjusted accordingly based on a second temperature (see block 702A) and / or a second threshold voltage (see block 702A). The second group consists of one or more corresponding libraries of HBM. Such adjustment thereby changes the corresponding temperature in one or more memory cells of the second group. In some embodiments, the first and second groups do not overlap with each other in terms of membership. In some embodiments, the second clock and / or second PS voltage is adjusted based on the second temperature and the second threshold voltage. In some embodiments, the second clock and / or second PS voltage is adjusted only based on the second temperature. In some embodiments, the second clock and / or second PS voltage is adjusted only based on the second threshold voltage.

[0112] Regarding box 706A, examples of adjusting the second clock include decreasing or increasing the frequency of the second clock. Examples of adjusting the second PS voltage include decreasing the value / amplitude of the second PS voltage. Examples of changing the temperature in the memory cell include decreasing or increasing the temperature of the memory cell. Examples of the second clock include... Figures 4A-4D The local clock signal CLK_local in each Figure 3A The local clock signal CLK_bnk in Figure 3B The local clock signal CLK_grp in Figure 3C The local clock signal CLK_chan in Figure 3D The second instance of the local clock signal CLK_core, etc. Examples of the second PS voltage include... Figures 4A-4D The local PS voltage PSV_local in each Figure 3A The local PS voltage PSV_bnk in Figure 3B The local PS voltage PSV_grp in Figure 3C Local PS voltage PSV_chan, local PS voltage Figure 3D The second instance of PSV_core, etc.

[0113] Turn now Figure 7B Flowchart 700B is a library-range type of differentiated thermal throttling for HBM. An example of HBM is... Figure 3A HBM 304A.

[0114] exist Figure 7B In this process, flowchart 700B includes blocks 702B, 704B, and 706B. Flowchart 700B presents a scheme in which a first group of one or more storage units in HBM is included in at least a first copy of one or more libraries in HBM, and a second group of one or more storage units is included in at least a second copy of one or more libraries in HBM. In terms of membership, in some embodiments, the first and second copies do not overlap with each other.

[0115] Box 702B is similar to box 702A, which is already on top of it. Figure 7A As discussed in the context. In block 702B, from each of the first and second sensing units, first and second instances of temperature signals and / or first and second instances of threshold voltage signals are received. The first and second instances of temperature signals and the first and second instances of threshold voltage signals are associated with first and second transistors in corresponding first and second memory cells corresponding to corresponding first and second copies of one or more libraries. From block 702B, the process proceeds to block 704B.

[0116] Box 704B is similar to box 704A, the latter already has it on top. Figure 7A As discussed in the context. In block 704B, the first clock and / or first PS voltage of one or more memory cells in the first library are adjusted accordingly based on a first temperature (see block 702B) and / or a first threshold voltage (see block 702B). Such adjustment thereby achieves library-range adjustment of the corresponding temperature in one or more memory cells of the first library. In some embodiments, both the first clock and the first PS voltage of the first library are adjusted. An example of library-range adjustment is... Figure 3A The arrangement of the DDVFS device 340 in the HBM 304A. In some embodiments, the first clock and / or the first PS voltage are adjusted based on a first temperature and a first threshold voltage. In some embodiments, the first clock and / or the first PS voltage are adjusted based only on the first temperature. In some embodiments, the first clock and / or the first PS voltage are adjusted based only on the first threshold voltage. From block 704B, the process proceeds to block 706B.

[0117] Box 706B is similar to box 706A, the latter already... Figure 7A As discussed above in the context of [the previous discussion], in block 706B, the second clock and / or second PS voltage of one or more memory cells in the second library are adjusted accordingly based on a second temperature (see block 702B) and / or a second threshold voltage (see block 702B). Such adjustment thus achieves library-wide adjustment of the corresponding temperature range in one or more memory cells of the second library. In some embodiments, both the second clock and the second PS voltage of one or more memory cells in the second library are adjusted. An example of library-wide adjustment is... Figure 3A The arrangement of the DDVFS device 340 in the HBM 304A. In some embodiments, the second clock and / or the second PS voltage are adjusted based on a second temperature and a second threshold voltage. In some embodiments, the second clock and / or the second PS voltage are adjusted based only on the second temperature. In some embodiments, the second clock and / or the second PS voltage are adjusted based only on the second threshold voltage.

[0118] Turn now Figure 7CFlowchart 700C illustrates differentiated thermal throttling of the group-range type of HBM. An example of HBM is... Figure 3B HBM 304B.

[0119] exist Figure 7C In this process, flowchart 700C includes blocks 702C, 704C, and 706C. Flowchart 700C presents a scheme in which a first group of one or more memory cells in HBM is included in at least a first batch of one or more groups of HBM, and a second group of one or more memory cells is included in at least a second batch of one or more groups of HBM. In terms of membership, in some embodiments, the first and second batches do not overlap with each other.

[0120] Box 702C is similar to box 702B, which is already on top of it. Figure 7B As discussed in the context. In block 702C, first and second instances of temperature signals and / or first and second instances of threshold voltage signals are received from each of the first and second sensing units. The first and second instances of temperature signals and the first and second instances of threshold voltage signals are associated with first and second transistors in corresponding first and second memory cells of corresponding first and second batches. From block 702C, the process proceeds to block 704C.

[0121] Box 704C is similar to box 704B, which is already on top. Figure 7B As discussed in the context of [previous discussion], in block 704C, the first clock and / or first PS voltage of one or more memory cells in the first group are adjusted accordingly based on a first temperature (see block 702C) and / or a first threshold voltage (see block 702C). Such adjustment thus achieves group-range adjustment of the corresponding temperature in one or more memory cells of the first group. In some embodiments, both the first clock and the first PS voltage of the first group are adjusted. An example of group-range adjustment is [example of adjustment]. Figure 3B The arrangement of the DDVFS device 340 in the HBM 304B. In some embodiments, the first clock and / or the first PS voltage are adjusted based on a first temperature and a first threshold voltage. In some embodiments, the first clock and / or the first PS voltage are adjusted based only on the first temperature. In some embodiments, the first clock and / or the first PS voltage are adjusted based only on the first threshold voltage. From block 704C, the process proceeds to block 706C.

[0122] Box 706C is similar to box 706B, which is already on top of it. Figure 7BAs discussed in the context. In block 706C, the second clock and / or second PS voltage of one or more memory cells in the second group are adjusted accordingly based on a second temperature (see block 702C) and / or a second threshold voltage (see block 702C). Such adjustment thus achieves group-range regulation of the corresponding temperature in one or more memory cells of the second batch. In some embodiments, both the second clock and the second PS voltage of one or more memory cells in the second group are adjusted. An example of group-range regulation is... Figure 3B The arrangement of the DDVFS device 340 in the HBM304B. In some embodiments, the second clock and / or the second PS voltage are adjusted based on a second temperature and a second threshold voltage. In some embodiments, the second clock and / or the second PS voltage are adjusted based only on the second temperature. In some embodiments, the second clock and / or the second PS voltage are adjusted based only on the second threshold voltage.

[0123] Turn now Figure 7D Flowchart 700D illustrates differentiated thermal throttling for HBM channel range types. An example of an HBM is... Figure 3C HBM 304C.

[0124] exist Figure 7D In this process, flowchart 700D includes blocks 702D, 704D, and 706D. Flowchart 700D presents a scheme in which a first group of one or more memory cells in the HBM is included in at least a first bundle of one or more channels of the HBM, and a second group of one or more memory cells is included in at least a second bundle of one or more channels of the HBM. In terms of membership, in some embodiments, the first and second bundles do not overlap with each other.

[0125] Box 702D is similar to box 702B, which is already on top. Figure 7C As discussed in the context. In block 702D, first and second instances of temperature signals and / or first and second instances of threshold voltage signals are received from each of the first and second sensing units. The first and second instances of temperature signals and the first and second instances of threshold voltage signals are associated with first and second transistors in corresponding first and second memory cells of corresponding first and second bundles of corresponding one or more channels. From block 702D, the process proceeds to block 704D.

[0126] Box 704D is similar to box 704B, which is already on top of it. Figure 7CAs discussed in the context of [previous discussion], in block 704D, the first clock and / or first PS voltage of one or more memory cells in the first channel are adjusted accordingly based on a first temperature (see block 702D) and / or a first threshold voltage (see block 702D). Such adjustment thereby achieves channel range adjustment for corresponding temperatures in one or more memory cells of the first bundle. In some embodiments, both the first clock and the first PS voltage of the first channel are adjusted. An example of channel range adjustment is [example of channel range adjustment]. Figure 3C The arrangement of the DDVFS device 340 in the HBM 304C. In some embodiments, the first clock and / or the first PS voltage are adjusted based on a first temperature and a first threshold voltage. In some embodiments, the first clock and / or the first PS voltage are adjusted based only on the first temperature. In some embodiments, the first clock and / or the first PS voltage are adjusted based only on the first threshold voltage. From block 704D, the process proceeds to block 706D.

[0127] Box 706D is similar to box 706B, which is already on top of it. Figure 7C As discussed in the context of [previous discussion], in block 706D, the second clock and / or second PS voltage of one or more memory cells in the second channel are adjusted accordingly based on a second temperature (see block 702D) and / or a second threshold voltage (see block 702D). Such adjustment thereby achieves channel range adjustment for corresponding temperatures in one or more memory cells of the second channel. In some embodiments, both the second clock and the second PS voltage of one or more memory cells in the second channel are adjusted. An example of channel range adjustment is... Figure 3C The arrangement of the DDVFS device 340 in the HBM 304C. In some embodiments, the second clock and / or the second PS voltage are adjusted based on a second temperature and a second threshold voltage. In some embodiments, the second clock and / or the second PS voltage are adjusted based only on the second temperature. In some embodiments, the second clock and / or the second PS voltage are adjusted based only on the second threshold voltage.

[0128] Turn now Figure 7E Flowchart 700E represents the differentiated thermal throttling of HBM's core die range types. An example of HBM is... Figure 3D HBM 304D.

[0129] exist Figure 7E In this process, flowchart 700E includes blocks 702E, 704E, and 706E. Flowchart 700E illustrates a scheme in which a first group of one or more memory cells in an HBM is included in at least a first set of one or more core dies of the HBM, and a second group of one or more memory cells is included in at least a second set of one or more core dies of the HBM. In terms of membership, in some embodiments, the first and second sets do not overlap with each other.

[0130] Box 702E is similar to box 702B, which already has it on top. Figure 7D As discussed in the context. In block 702E, from each of the first and second sensing units, first and second instances of temperature signals and / or first and second instances of threshold voltage signals are received. The first and second instances of temperature signals and the first and second instances of threshold voltage signals are associated with first and second transistors in corresponding first and second memory cells of corresponding first and second sets of corresponding one or more core dies. From block 702E, the process proceeds to block 704E.

[0131] Box 704E is similar to box 704B, which is already on top. Figure 7D As discussed in the context of [previous discussion], in block 704E, the first clock and / or first PS voltage of one or more memory cells in the first core die are adjusted accordingly based on a first temperature (see block 702E) and / or a first threshold voltage (see block 702E). Such adjustment thereby achieves adjustment of the core die range for a corresponding temperature in one or more memory cells of the first set. In some embodiments, both the first clock and the first PS voltage of the first core die are adjusted. An example of core die range adjustment is... Figure 3D The arrangement of the DDVFS device 340 in the HBM 304D. In some embodiments, the first clock and / or the first PS voltage are adjusted based on a first temperature and a first threshold voltage. In some embodiments, the first clock and / or the first PS voltage are adjusted based only on the first temperature. In some embodiments, the first clock and / or the first PS voltage are adjusted based only on the first threshold voltage. From block 704E, the process proceeds to block 706E.

[0132] Box 706E is similar to box 706B, which already has a box on top. Figure 7D As discussed in the context of [previous discussion], in block 706E, the second clock and / or second PS voltage of one or more memory cells in the second core die are adjusted accordingly based on a second temperature (see block 702E) and / or a second threshold voltage (see block 702E). Such adjustment thereby achieves adjustment of the core die range for a corresponding temperature in one or more memory cells of the second set. In some embodiments, both the second clock and the second PS voltage of one or more memory cells in the second core die are adjusted. An example of core die range adjustment is [example of core die range adjustment]. Figure 3D The arrangement of the DDVFS device 340 in the HBM 304D. In some embodiments, the second clock and / or the second PS voltage are adjusted based on a second temperature and a second threshold voltage. In some embodiments, the second clock and / or the second PS voltage are adjusted based only on the second temperature. In some embodiments, the second clock and / or the second PS voltage are adjusted based only on the second threshold voltage.

[0133] Figure 7F The flowcharts of blocks 704A and 706A are shown in more detail according to some embodiments.

[0134] exist Figure 7F In the middle, frame 704A includes frames 730-734, and frame 706A includes frames 736-740.

[0135] In box 730, a first temperature is compared with a first temperature reference, yielding a first temperature comparison result. The first temperature reference represents the highest temperature. An example of a first temperature reference is... Figures 4A-4C and Figure 4F Temperature reference MAX_temp, etc. An example of comparing the first temperature with the first temperature reference is provided by... Figures 4A-4C and Figure 4F Temperature comparator 444 performs comparisons, etc. From box 730, the process proceeds to box 732.

[0136] In box 732, the frequency of the first clock is changed based on the first temperature comparison result (see box 730). An example of such a change is to decrease the frequency of the first clock, for example, as... Figures 4A-4C The coordinated operation of the clock regulator 450 and the CLK generator 454, etc. From block 732, the process proceeds to block 734.

[0137] In box 734, the value of the first PS voltage is changed based on the first temperature comparison result (see box 730). An example of this change is to decrease the value / amplitude of the first PS voltage, for example, as... Figures 4A-4B and Figure 4F The coordinated operation of the PSV regulator 452 and PSV generator 456, etc. From box 734, the process proceeds to box 736 in box 706A.

[0138] In box 736, the second temperature is compared with a first temperature reference, resulting in a second temperature comparison result. An example of comparing the second temperature with a second temperature reference is provided by... Figure 4A -picture Figure 4C Temperature comparator 444 performs comparisons, etc. From box 736, the process proceeds to box 738.

[0139] In box 738, the frequency of the second clock is changed based on the result of the first temperature comparison (see box 736). An example of such a change is to decrease the frequency of the second clock, for example, as... Figures 4A-4C The coordinated operation of the clock regulator 450 and the CLK generator 454, etc. From block 738, the process proceeds to block 740.

[0140] In box 740, the value of the second PS voltage is changed based on the second temperature comparison result (see box 736). An example of this change is to decrease the value / amplitude of the second PS voltage, for example, as... Figures 4A-4B and Figure 4F Coordinated operation of PSV regulator 452 and PSV generator 456, etc.

[0141] Figure 7G The flowcharts of blocks 704A and 706A are shown in more detail according to some embodiments.

[0142] exist Figure 7G In the middle, frame 704A includes frames 750-754 and frame 706A includes frames 756-760.

[0143] At box 750, the first threshold voltage is compared with a first voltage reference, yielding a first voltage comparison result. The first voltage reference represents the minimum threshold voltage. An example of the first voltage reference is... Figure 4A , Figures 4D-4E and Figure 4G The voltage reference is MIN_Vt. An example of comparing the first voltage to the first voltage reference is given by... Figure 4A , Figures 4C-4D and Figure 4G The threshold voltage comparator 446 performs comparisons, etc. From block 750, the process proceeds to block 752.

[0144] In box 752, the frequency of the first clock is changed based on the result of the first voltage comparison (see box 750). An example of such a change is to decrease the frequency of the first clock, for example, as... Figure 4A , Figure 4D and Figure 4G The coordinated operation of the clock regulator 450 and the CLK generator 454, etc. From block 752, the process proceeds to block 754.

[0145] In box 754, the value of the first PS voltage is changed based on the comparison result of the first threshold voltage (see box 750). An example of this change is to decrease the value / amplitude of the first PS voltage, for example, as... Figure 4A and Figures 4D-4E The coordinated operation of the PSV regulator 452 and PSV generator 456, etc. From box 754, the process proceeds to box 756 in box 706A.

[0146] In box 756, the second threshold voltage is compared with a first threshold voltage reference, resulting in a second threshold voltage comparison result. An example of comparing the second threshold voltage with a second threshold voltage reference is provided by... Figures 4A-4C and Figure 4F The threshold voltage comparator 444 performs comparisons, etc. From block 756, the process proceeds to block 758.

[0147] In box 758, the frequency of the second clock is changed based on the comparison result of the second threshold voltage (see box 756). An example of such a change is to decrease the frequency of the second clock, for example, as... Figure 4A, Figure 4D and Figure 4G The coordinated operation of the clock regulator 450 and the CLK generator 454, etc. From box 758, the process proceeds to box 760.

[0148] In box 760, the value of the second PS voltage is changed based on the comparison result of the second threshold voltage (see box 756). An example of this change is to decrease the value / amplitude of the second PS voltage, for example, as... Figure 4A and Figures 4D-4E Coordinated operation of PSV regulator 452 and PSV generator 456, etc.

[0149] Figure 7H The flowcharts of blocks 704A and 706A are shown in more detail according to some embodiments.

[0150] exist Figure 7H In the middle, frame 704A includes frames 770-774, and frame 706A includes frames 776-780.

[0151] In box 770, a first temperature is compared to a second temperature reference, resulting in a third temperature comparison. The second temperature reference represents a moderate temperature. An example of a second temperature reference is... Figures 4A-4C and Figure 4F Temperature references such as MOD_temp. An example of comparing a first temperature with a second temperature reference is provided by... Figures 4A-4C and Figure 4F Temperature comparator 444 performs comparisons, etc. From box 770, the process proceeds to box 772.

[0152] In box 772, the frequency of the first clock is changed based on the third temperature comparison result (see box 770). More specifically, in box 772, the frequency of the first clock is increased. An example of this change is increasing the frequency of the first clock, for example, as... Figures 4A-4C The coordinated operation of the clock regulator 450 and the CLK generator 454, etc. From block 772, the process proceeds to block 774.

[0153] In box 774, the value of the first PS voltage is changed based on the third temperature comparison result (see box 770). More specifically, the value of the first PS voltage is increased at box 774. An example of this change is increasing the value / amplitude of the first PS voltage, for example, as... Figures 4A-4B and Figure 4F The coordinated operation of the PSV regulator 452 and PSV generator 456, etc. From box 774, the process proceeds to box 776 in box 706A.

[0154] In box 776, the second temperature is compared with a second temperature reference, resulting in a fourth temperature comparison. An example of comparing the second temperature with the second temperature reference is provided by... Figures 4A-4Cand Figure 4F Temperature comparator 444 performs comparisons, etc. From box 776, the process proceeds to box 778.

[0155] In box 778, the frequency of the second clock is changed based on the fourth temperature comparison result (see box 776). More specifically, the frequency of the second clock is increased at box 778. An example of this change is increasing the frequency of the second clock, for example, as... Figures 4A-4C The coordinated operation of the clock regulator 450 and the CLK generator 454, etc. From box 778, the process proceeds to box 780.

[0156] In box 780, the value of the second PS voltage is changed based on the fourth temperature comparison result (see box 776). More specifically, the value of the second PS voltage is increased at box 780. An example of this change is increasing the value / amplitude of the second PS voltage, for example, as... Figures 4A-4B and Figure 4F Coordinated operation of PSV regulator 452 and PSV generator 456, etc.

[0157] Figure 7I The flowcharts of blocks 704A and 706A are shown in more detail according to some embodiments.

[0158] exist Figure 7I In the middle, frame 704A includes frames 790-794, and frame 706A includes frames 796-799.

[0159] In box 790, it is determined whether all members of the first group, such as storage units MC, are idle. If so (i.e., when all members of the first group are idle / sleeping), the process proceeds to box 792. In some embodiments, HBM, for example... Figures 2A-2B The HBM 204 is included in Internet of Things (IoT) devices. It is common for IoT devices to be idle most of the time.

[0160] In box 792, when all members of the first group are idle, the frequency of the first clock is decreased. An example of this change is decreasing the frequency of the first clock, for example, as... Figures 4A-4C The clock regulator 450 and CLK generator 454 are coordinated in operation. From box 792, the process proceeds to box 794.

[0161] In box 794, decrease the value of the first PS voltage. An example of this change is decreasing the value / amplitude of the first PS voltage, for example, as... Figures 4A-4B and Figure 4F The coordinated operation of the PSV regulator 452 and PSV generator 456. From box 794, the process proceeds to box 796 in box 706A.

[0162] In box 796, determine whether all members of the second group, such as storage units MC, are idle. If so (i.e., when all members of the second group are idle), the process proceeds to box 798.

[0163] In box 798, the frequency of the second clock is reduced. An example of this change is reducing the frequency of the second clock, for example, as... Figures 4A-4C The coordinated operation of the clock regulator 450 and the CLK generator 454, etc. From box 798, the process proceeds to box 799.

[0164] In box 799, decrease the value of the second PS voltage. An example of this change is decreasing the value / amplitude of the second PS voltage, for example, as... Figures 4A-4B and Figure 4F Coordinated operation of PSV regulator 452 and PSV generator 456, etc.

[0165] Alternatively, in some embodiments, box 792 is not included, and the flow proceeds from box 790 to box 794. Alternatively, in some embodiments, box 794 is not included.

[0166] Alternatively, in some embodiments, box 798 is not included, and the flow proceeds from box 796 to box 799. Alternatively, in some embodiments, box 799 is not included.

[0167] In some embodiments, the values ​​of the first and second PS voltages are reduced to approximately zero. In such embodiments, although the first and second PS voltages are set to approximately zero, the corresponding devices receiving the first and second PS voltages enjoy a power consumption reduction of approximately 99%.

[0168] In some embodiments, the values ​​of the first and second PS voltages are reduced to the minimum operating voltage, i.e., the minimum voltage at which the HBM will operate correctly / reliably. In such embodiments, although the first and second PS voltages are set to the minimum operating voltages, the corresponding devices receiving the first and second PS voltages enjoy a power consumption reduction of approximately 1%.

[0169] Figure 8 This is a flowchart of a method 800 for manufacturing a semiconductor device according to some embodiments.

[0170] According to some embodiments, method 800 is implementable, for example, using EDA system 900 ( Figure 9 (discussed below) and integrated circuit (IC) manufacturing system 1000 ( Figure 10 (Discussed below). Examples of semiconductor devices that can be manufactured according to method 800 include... Figure 1 Semiconductor devices 100, semiconductor devices corresponding to various layout diagrams disclosed herein, etc.

[0171] exist Figure 8In method 800, blocks 802-804 are included. In block 802, a layout diagram is generated, which includes, for example, [details omitted]. Figure 1 The layout of one or more semiconductor devices, such as those disclosed herein, wherein the semiconductor devices are implementations of systems such as those described herein. According to some embodiments, for example, an EDA system 900 is used. Figure 9 (Discussed below) Implementation of box 802.

[0172] More specifically, block 802 includes generating a shape corresponding to a structure in a semiconductor device, thereby obtaining a layout diagram for manufacturing the semiconductor device. From block 802, the process proceeds to block 804.

[0173] In box 804, based on the layout diagram, at least one of the following is performed: (A) performing one or more photolithographic exposures; or (B) fabricating one or more semiconductor masks; or (C) fabricating one or more components in a layer of a semiconductor device. See below. Figure 10 The discussion.

[0174] Figure 9 This is a block diagram of an electronic design automation (EDA) system 900 according to some embodiments.

[0175] In some embodiments, EDA system 900 includes an Automatic Placement and Routing (APR) system. According to some embodiments, the design layout methods described herein represent wiring arrangements according to one or more embodiments, for example, achievable using EDA system 900.

[0176] In some embodiments, the EDA system 900 is a general-purpose computing device including a hardware processor 902 and a non-transitory computer-readable storage medium 904. The storage medium 904 (in addition) encodes (i.e. stores) computer program code 906, which is a set of executable instructions. Execution of the instructions 906 by the hardware processor 902 (at least partially) represents an EDA tool that implements some or all of the methods described herein according to one or more embodiments (hereinafter, the processes and / or methods mentioned).

[0177] Processor 902 is electrically coupled to computer-readable storage medium 904 via bus 908. Processor 902 is also electrically coupled to I / O interface 910 via bus 908. Network interface 912 is also electrically connected to processor 902 via bus 908. Network interface 912 is connected to network 914, enabling processor 902 and computer-readable storage medium 904 to be connected to external components via network 914. Processor 902 is configured to execute computer program code 906 encoded in computer-readable storage medium 904 so that system 900 can be used to perform part or all of the process and / or method. In one or more embodiments, processor 902 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0178] In one or more embodiments, the computer-readable storage medium 904 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 904 includes semiconductor or solid-state memory, magnetic tape, removable computer floppy disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 904 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video optical disc (DVD).

[0179] In one or more embodiments, storage medium 904 stores computer program code 906 configured to enable system 900 [where such execution (at least partially) represents an EDA tool] to perform part or all of the process and / or method. In one or more embodiments, storage medium 904 also stores information that facilitates the execution of part or all of the process and / or method. In one or more embodiments, storage medium 904 stores a standard library 907 comprising the standard units disclosed herein. In one or more embodiments, storage medium 904 stores one or more layout diagrams 909 corresponding to one or more layout diagrams disclosed herein.

[0180] EDA system 900 includes an I / O interface 910. The I / O interface 910 is coupled to external circuitry. In one or more embodiments, the I / O interface 910 includes a keyboard, buttons, a mouse, a trackball, a trackpad, a touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 902.

[0181] EDA system 900 also includes a network interface 912 coupled to processor 902. Network interface 912 allows system 900 to communicate with one or more other computer systems connected to network 914. Network interface 912 includes a wireless network interface, such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, some or all of the mentioned processes and / or methods are implemented in two or more systems 900.

[0182] System 900 is configured to receive information via I / O interface 910. The information received via I / O interface 910 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing, provided by processor 902. The information is transmitted to processor 902 via bus 908. EDA system 900 is configured to receive UI-related information via I / O interface 910. This information is stored as a user interface (UI) in computer-readable medium 904 942.

[0183] In some embodiments, some or all of the processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, some or all of the processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, some or all of the processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application as part of an EDA tool. In some embodiments, some or all of the processes and / or methods are implemented as a software application used by an EDA system 900. In some embodiments, the layout diagram including standard cells is obtained using, for example, from CADENCEDESIGN SYSTEMS, Inc. It is generated by tools or other suitable layout diagram generation tools.

[0184] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or storage units (such as one or more optical discs, such as DVDs), magnetic disks (such as hard disks), semiconductor memories (such as ROM, RAM, memory cards), etc.

[0185] Figure 10This is a block diagram of an integrated circuit (IC) manufacturing system 1000 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 1000 is used to manufacture at least one of: (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0186] exist Figure 10 In this IC manufacturing system 1000, entities interact with each other throughout the design, development, and manufacturing cycles, such as design room 1020, mask room 1030, and IC fab 1050, and / or a series / services related to the manufacture of IC devices 1060. The entities in system 1000 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design room 1020, mask room 1030, and IC fab 1050 are owned by a single, larger company. In some embodiments, two or more of design room 1020, mask room 1030, and IC fab 1050 coexist in a shared facility and use shared resources.

[0187] Design studio (or design team) 1020 generates IC design layout 1022. IC design layout 1022 includes various geometric patterns designed for IC device 1060. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 1060 to be manufactured. These layers combine to form various IC components. For example, portions of IC design layout 1022 include various IC components (e.g., active regions, gate electrodes, source electrodes, and drain electrodes) to be formed in a semiconductor substrate (e.g., a silicon wafer), metal lines or vias for interlayer interconnects, openings for bonding pads, and various material layers disposed on the semiconductor substrate. Design studio 1020 implements appropriate design procedures to form IC design layout 1022. These procedures include one or more of logic design, physical design, or place-and-route. IC design layout 1022 is presented in one or more data files containing geometric pattern information. For example, IC design layout 1022 can be expressed in GDSII or DFII file format.

[0188] Mask chamber 1030 includes mask data preparation 1032 and mask fabrication 1044. Mask chamber 1030 uses an IC design layout 1022 to fabricate one or more masks 1045 for fabricating various layers of an IC device 1060 according to the IC design layout 1022. Mask chamber 1030 performs mask data preparation 1032, in which the IC design layout 1022 is converted into a representative data file (“RDF”). Mask data preparation 1032 provides the RDF to mask fabrication 1044. Mask fabrication 1044 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (mask) 1045 or a semiconductor wafer 1053. The IC design layout 1022 is manipulated by mask data preparation 1032 to conform to the specific characteristics of the mask writer and / or the requirements of IC Fab 1050. Figure 10 In this embodiment, mask data preparation 1032 and mask manufacturing 1044 are shown as separate elements. In some embodiments, mask data preparation 1032 and mask manufacturing 1044 may be collectively referred to as mask data preparation.

[0189] In some embodiments, mask data preparation 1032 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other process effects. OPC adjusts the IC design layout (Figure 1022). In some embodiments, mask data preparation 1032 includes further resolution enhancement techniques (RET), such as off-axis illumination, subresolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, treating OPC as an inverse imaging problem.

[0190] In some embodiments, mask data preparation 1032 includes a mask rule checker (MRC) that checks an IC design layout 1022 that has undergone a process in an OPC with a set of mask creation rules. These rules include certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in the semiconductor manufacturing process, etc. In some embodiments, the MRC modifies the IC design layout 1022 to compensate for constraints during mask fabrication 1044, which can undo some modifications performed by the OPC to satisfy the mask creation rules.

[0191] In some embodiments, mask data preparation 1032 includes a lithography process inspection (LPC) simulating a process to be performed by an IC vendor 1050 to manufacture an IC device 1060. The LPC simulates this process based on the IC design layout 1022 to create a simulated manufactured device, such as the IC device 1060. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and combinations thereof. In some embodiments, after the simulated manufactured device has been created by the LPC, if the shape of the simulated device is not close enough to meet design rules, the OPC and / or MRC are repeated to further refine the IC design layout 1022.

[0192] It should be understood that the above description of mask data preparation 1032 has been simplified for clarity. In some embodiments, mask data preparation 1032 includes additional features, such as modifying the logic operations (LOPs) of the IC design layout 1022 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1022 during mask data preparation 1032 can be performed in various different sequences.

[0193] Following mask data preparation 1032 and during mask fabrication 1044, a mask 1045 or a set of masks 1045 is fabricated based on a modified IC design layout 1022. In some embodiments, mask fabrication 1044 includes performing one or more photolithographic exposure layouts 1022 based on the IC design. In some embodiments, a pattern is formed on the mask (photomask or photomask plate) 1045 using an electron beam (e-beam) or a plurality of e-beams based on the modified IC design layout 1022. The mask 1045 can be formed using various techniques. In some embodiments, a binary technique is used to form the mask 1045. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam (e.g., an ultraviolet (UV) beam) is used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer; the radiation beam is blocked by the opaque regions and transmits through the transparent regions. In one example, a binary mask version of mask 1045 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on opaque regions of the binary mask. In another example, mask 1045 is formed using a phase-shifting technique. In a phase-shifting mask (PSM) version of mask 1045, various components in a pattern formed on the phase-shifting mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase-shifting mask can be attenuated PSM or alternating PSM. The mask produced by mask fabrication 1044 is used in a variety of processes. For example, such a mask is used in ion implantation processes to form various doped regions in semiconductor wafer 1053, in etching processes to form various etched regions in semiconductor wafer 1053, and / or in other suitable processes.

[0194] IC manufacturer 1050 includes wafer fabrication 1052. IC manufacturer 1050 is an IC manufacturing business that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC manufacturer 1050 is a semiconductor foundry. For example, there may be one manufacturing facility for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility may provide back-end manufacturing of IC products for interconnection and packaging (back-end process (BEOL) manufacturing), and a third manufacturing plant may provide other services for the foundry business.

[0195] IC fab 1050 includes manufacturing tool 1052 configured to perform various manufacturing operations on semiconductor wafer 1053 to manufacture IC device 1060 according to a mask (e.g., mask 1045). In various embodiments, manufacturing tool 1052 includes one or more of a wafer stepper, ion implanter, photoresist coater, process chamber such as a CVD chamber or LPCVD furnace, CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of implementing one or more suitable manufacturing processes as discussed herein.

[0196] IC fab 1050 uses mask 1045, fabricated by mask chamber 1030, to fabricate IC device 1060. Therefore, IC fab 1050 uses IC layout pattern 1022 at least indirectly to fabricate IC device 1060. In some embodiments, semiconductor wafer 1053 is fabricated by IC fab 1050 using mask 1045 to form IC device 1060. In some embodiments, IC fabrication includes performing one or more photolithographic exposures based at least indirectly on IC layout pattern 1022. Semiconductor wafer 1053 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 1053 also includes one or more of various doped regions, dielectric components, multilevel interconnects, etc. (formed in subsequent fabrication steps).

[0197] Regarding integrated circuit (IC) manufacturing systems (e.g., Figure 10 Details of the system 1000 and the associated IC manufacturing process can be found, for example, in U.S. Patent No. 9,256,709, granted February 9, 2016; Pre-Grant Publication No. 20150278429, published October 1, 2015; U.S. Pre-Grant Publication No. 20140040838, published February 6, 2014; and U.S. Patent No. 7,260,442, granted August 21, 2007, the entire contents of which are incorporated herein by reference.

[0198] For example, in U.S. Patent No. 9,256,709, an IC design layout is generated in a design room (or design team). The IC design layout includes various geometric patterns designed for an IC device. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various components of the IC device to be manufactured. The various layers combine to form various IC functions. For example, portions of the IC design layout include various IC components such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for forming pads in the semiconductor. These openings will be formed on a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. The design room performs appropriate design processes to form the IC design layout. These design processes may include logic design, physical design, and / or placement and routing. The IC design layout is presented in one or more data files containing geometric pattern information. A mask room uses the IC design layout to fabricate one or more masks, which are used to fabricate the various layers of the IC device according to the IC design layout. The mask room performs mask data preparation, in which the IC design layout is converted into a form that can be physically written by a mask writer. The design layout prepared by mask data preparation is modified to conform to a specific mask manufacturer and / or mask vendor before fabrication. In this embodiment, mask data preparation and mask fabrication are illustrated as separate elements; however, they can be collectively referred to as mask data preparation. Mask data preparation typically includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other processing effects. Mask data preparation may include other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. Mask data preparation 132 also includes a mask rule checker (MRC), which uses a set of mask creation rules to check the IC design layout that has already been processed in the OPC. These mask creation rules may include some geometric and connectivity constraints to ensure sufficient margin.

[0199] For example, in U.S. Patent Publication No. 20150278429, in one embodiment, the IC manufacturing system may employ maskless lithography techniques, such as electron beam lithography or optical maskless lithography. In such a system, mask fabrication is bypassed, and the IC design layout is modified through data preparation suitable for wafer processing using a specific maskless lithography technique. The data preparation modifies the design layout to suit subsequent operations within the IC manufacturing system. The result of the data preparation is represented by one or more data files, such as files in GDSII or DFII file formats. The one or more data files include information on geometric patterns, such as polygons representing the primary design pattern and / or auxiliary components. In this embodiment, the one or more data files also include auxiliary data generated by the data preparation. This auxiliary data will be used to enhance various operations of the IC manufacturing system, such as mask fabrication performed in the mask chamber and wafer exposure performed by the IC manufacturer.

[0200] For example, in Pre-License No. 20140040838, the IC design layout is presented in one or more data files containing geometric pattern information. In one example, the IC design layout is represented in the “GDS” format known in the art. In alternative embodiments, the IC design layout may be transferred between components in an IC manufacturing system in alternative file formats such as DFII, CIF, OASIS, or any other suitable file type. The IC design layout 300 includes various geometric patterns representing components of an integrated circuit. For example, the IC design layout may include primary IC components such as active regions, gate electrodes, source and drain electrodes, metal lines, interlayer interconnect vias, and openings for forming pads in the semiconductor, the openings being formed on a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. The IC design layout may also include auxiliary components, such as those for imaging effects, processing enhancement and / or mask recognition information.

[0201] For example, in U.S. Patent No. 7,260,442, a mask manufacturing system includes: a processing tool for processing a mask; a metrology tool connected to the processing tool for inspecting the mask and obtaining inspection results; and a controller coupled to the processing tool and the metrology tool for generating a manufacturing model of the processing tool and calibrating the manufacturing model based on equipment data, material data, and the mask inspection results. The mask manufacturing system may include at least one processing tool, a metrology tool, a controller, a database, and a manufacturing execution system. The processing tool may be an exposure tool, a developer, an etcher, or a photoresist stripper. The metrology tool performs post-etch or post-stripping inspections and obtains post-etch or post-stripping inspection results, respectively. The controller provides operation-to-operation control for the processing tool, including feedforward and feedback control. The controller receives post-etch or post-stripping inspection results from the metrology tool and retrieves device and material data from the database. The controller, connected to the manufacturing execution system, generates a manufacturing model of the processing tool and calibrates the manufacturing model based on equipment data, material data, and the mask inspection results. The controller also monitors the operating conditions of the processing tool and adjusts the manufacturing model of the processing tool during processing.

[0202] In some embodiments, the system (for controlling temperature in the memory) includes: a high-bandwidth memory (HBM) including core dies disposed in a stack, each core die including a bank, and each bank including memory cells, the HBM further including: a first sensing unit configured to generate one or more first ambient signals corresponding to at least a first transistor of at least one of the corresponding memory cells; a second sensing unit configured to generate one or more second ambient signals corresponding to at least a second transistor of at least a corresponding memory cell; and a differential dynamic voltage and frequency scaling (DDVFS) device configured to perform the following operations: for a first set of one or more memory cells including the first memory cells, controlling the temperature of the first set by adjusting one or more first set transistor temperature effect (TTA) parameters of the first set based on one or more first ambient signals; for a second set of one or more memory cells including the second memory cells, controlling the temperature of the second set by adjusting one or more second TTA parameters of the second set based on one or more second ambient signals.

[0203] In some embodiments, the first group and the second group do not overlap in terms of membership. In some embodiments, the first sensing unit is further configured to sense a first temperature or detect a first threshold voltage corresponding to at least a first transistor of at least one of the corresponding memory cells of the first group; the second sensing unit is further configured to sense a second temperature or detect a second threshold voltage associated with first and second transistors of at least one of the corresponding memory cells of the second group; one or more first ambient signals include the first temperature or the first threshold voltage; one or more second ambient signals include the second temperature or the second threshold voltage; one or more first TTA parameters include a first clock or a first power supply (PS) voltage; one or more second TTA parameters include a second clock or a second PS voltage; the DDVFS device is also configured to perform the following operations: adjust the first clock or the first PS voltage based on the first temperature or the first threshold voltage, and adjust the second clock or the second PS voltage based on the second temperature or the second threshold voltage. In some embodiments, a first group of one or more memory cells is contained in at least a first lot of one or more libraries; a second group of one or more memory cells is contained in at least a second lot of one or more libraries; in terms of membership, the first lot and the second lot do not overlap with each other; the DDVFS device is also configured to perform the following operations: adjusting a first clock or a first PS voltage of the first lot to cause adjustment of a first library range of corresponding temperatures in the memory cells of the first lot; and adjusting a second clock or a second PS voltage of the second lot to cause adjustment of a second library range of corresponding temperatures in the memory cells of the second lot.

[0204] In some embodiments, the HBM libraries are arranged in a group; a first group of one or more memory cells is contained within at least a first block of one or more of the group; a second group of one or more memory cells is contained within at least a second block of one or more of the group; in terms of membership, the first and second blocks do not overlap with each other; the DDVFS device is also configured to perform the following operations: adjusting a first clock or a first PS voltage of the first block to cause adjustment of a first group range of temperature in the memory cells of the group of the first block; and adjusting a second clock or a second PS voltage of the second block to cause adjustment of a second group range of temperature in the memory cells of the group of the second block. In some embodiments, each of the core dies of the HBM is arranged in a channel; a first group of one or more memory cells is contained in at least a first bundle of one or more channels; a second group of one or more memory cells is contained in at least a second bundle of one or more channels; in terms of membership, the first and second bundles do not overlap with each other; the DDVFS device is further configured to perform the following operations: adjusting a first clock or a first PS voltage of the first bundle, causing adjustment of a first channel range of temperature in the memory cells of the channel of the first bundle; and adjusting a second clock or a second PS voltage of the second bundle, causing adjustment of a second channel range of temperature in the memory cells of the channel of the second bundle. In some embodiments, a first group of one or more memory cells is contained within a first collection of one or more core dies; a second group of one or more memory cells is contained within a second collection of one or more core dies; in terms of membership, the first and second collections do not overlap with each other; the DDVFS device is further configured to perform the following operations: adjusting a first clock or a first PS voltage of the first collection, causing adjustment of a first core die range of temperature in the memory cells of the core dies of the first collection; and adjusting a second clock or a second PS voltage of the second collection, causing adjustment of a second core range of temperature in the memory cells of the core dies of the second collection.

[0205] In some embodiments, the DDVFS device includes a controller configured to perform the following operations: changing the frequency of a first clock based on a first temperature from a first sensing unit, or changing the value of a first PS voltage based on a second temperature from the first sensing unit; changing the frequency of a second clock based on a second temperature from a second sensing unit, or changing the value of a second PS voltage based on a second temperature from a second sensing unit. In embodiments, the DDVFS device further includes a temperature comparator configured to perform the following operations: comparing a first temperature with a first temperature reference representing a highest temperature to obtain a first temperature comparison result, and comparing a second temperature with the first temperature reference to obtain a second temperature comparison result; the controller is also configured to perform the following operations: executing scenario (A), including changing the frequency of the first clock based on the first temperature comparison result and changing the frequency of the second clock based on the second temperature comparison result; or executing scheme (B), including changing the value of the first PS voltage based on the first temperature comparison result or changing the value of the second PS voltage based on the second temperature comparison result.

[0206] In some embodiments, the temperature comparator is further configured to perform the following operations: compare a first temperature with a second temperature reference representing a moderate temperature to obtain a third temperature comparison result; and compare a second temperature with a second temperature reference to generate a fourth temperature comparison result; when the third temperature comparison result indicates that the first temperature is lower than the second temperature reference, the controller is further configured to perform the following operations: increase the frequency of a first clock or increase the value of a first PS voltage. Furthermore, when the second temperature comparison result indicates that the second temperature is lower than the second temperature reference, the controller is further configured to perform the following operations: increase the frequency of a second clock or increase the value of a second PS voltage. In some embodiments, the DDVFS device further includes a threshold voltage comparator configured to perform the following operations: compare a first threshold voltage with a voltage reference representing a minimum threshold voltage to obtain a first voltage comparison result, and compare a second threshold voltage with a voltage reference to obtain a second voltage comparison result; the controller is further configured to perform the following operations: execute scenario (A), including changing the frequency of the first clock based on the first voltage comparison result and changing the frequency of the second clock based on the second voltage comparison result; or execute scenario (B), including changing the value of the first PS voltage based on the first voltage comparison result or changing the value of the second PS voltage based on the second voltage comparison result. In some embodiments, when all members of the first group are idle, the controller is configured to perform the following operations: reduce the frequency of the first clock or reduce the value of the first PS voltage; and when all members of the second group are idle, the controller is configured to perform the following operations: reduce the frequency of the second clock or reduce the value of the second PS voltage.

[0207] In some embodiments, each of the first sensing unit and the second sensing unit includes: a bias current generator electrically coupled to a first node; a diode-configured transistor electrically coupled between the first node and a ground voltage; and a readout circuit electrically coupled to the first node and correspondingly outputting a first or second temperature. In some embodiments, each of the first sensing unit and the second sensing unit includes: a PTAT current generator electrically coupled to the first node; and a diode-configured transistor electrically coupled between the first node and a ground voltage; wherein the voltage at the first node corresponds to a first or second threshold voltage.

[0208] In some embodiments, a system (for controlling temperature in a memory) includes: a high-bandwidth memory (HBM) including core dies disposed in a stack, each core die including a library, and each library including a memory cell, the HBM further including: a first sensing unit configured to sense a first temperature corresponding to at least a first transistor of at least a first memory cell; and a second sensing unit configured to sense a second temperature corresponding to at least a second transistor of at least a second memory cell; and a differential dynamic voltage and frequency scaling (DDVFS) device configured to perform the following operations: for a first group of one or more memory cells including the first memory cell, controlling the temperature of the first group by adjusting one or more first transistor temperature influence (TTA) parameters of the first group based on the first temperature; and for a second group of one or more memory cells including the second memory cell, controlling the temperature of the second group by adjusting one or more second TTA parameters of the second group based on the second temperature.

[0209] In some embodiments, one or more first TTA parameters include a first clock or a first power supply (PS) voltage; one or more second TTA parameters include a second clock or a second PS voltage; and the DDVFS device further includes: a temperature comparator configured to perform the following operations: compare a first temperature with a first temperature reference representing a maximum temperature to obtain a first temperature comparison result, and compare a second temperature with the first temperature reference to obtain a second temperature comparison result; the DDVFS device is also configured to perform the following steps: performing scenario (A), including changing the frequency of the first clock based on the first temperature comparison result, and changing the frequency of the second clock based on the second temperature comparison result; or performing scheme (B), including changing the value of the first PS voltage based on the first temperature comparison result, or changing the value of the second PS voltage based on the second temperature comparison result. In some embodiments, when the first temperature is lower than a second temperature reference representing a moderate temperature, the DDVFS device is further configured to perform the following operations: increase the frequency of the first clock, or increase the value of the first PS voltage; and when the second temperature is lower than a second reference temperature, the DDVFS device is further configured to perform the following operations: increase the frequency of the second clock, or increase the value of the second PS voltage. In some embodiments, one or more first TTA parameters include a first clock or a first power supply (PS) voltage; one or more second TTA parameters include a second clock or a second PS voltage; when all members of the first set are idle, the DDVFS device is further configured to perform the following operations: reduce the frequency of the first clock or reduce the value of the first PS voltage. Furthermore, when all members of the second set are idle, the DDVFS device is also configured to perform the following operations: reduce the frequency of the second clock or decrease the value of the second PS voltage.

[0210] In some embodiments, a method for controlling temperature in a high-bandwidth memory (HBM) includes core dies arranged in a stack, each core die including a library and each library including a memory cell, the HBM further including at least first and second sensing units correspondingly arranged within the core dies, the method comprising: receiving a first threshold voltage from a first sensing unit arranged within the HBM, the first threshold voltage corresponding to at least a first transistor in a corresponding at least first memory cell; receiving a second threshold voltage from a second sensing unit arranged within the HBM, the second threshold voltage corresponding to at least a second transistor in a corresponding at least second memory cell; for a first group of one or more memory cells including the first memory cell, controlling the temperature of the first group by adjusting one or more first transistor temperature effect (TTA) parameters of the first group based on the first threshold voltage; for a second group of one or more memory cells including the second memory cell, controlling the temperature of the second group by adjusting one or more second TTA parameters of the second group based on the second threshold voltage.

[0211] In some embodiments, one or more first TTA parameters include a first clock or a first power supply (PS) voltage, one or more second TTA parameters include a second clock or a second PS voltage, and the method further includes: comparing a first threshold voltage with a first voltage reference representing a minimum threshold voltage to obtain a first voltage comparison result; comparing a second threshold voltage with the first voltage reference to obtain a second voltage comparison result; performing scenario (A), including changing the frequency of the first clock based on the first voltage comparison result and changing the frequency of the second clock based on the second voltage comparison result; or performing scenario (B), including changing the value of the first PS voltage based on the first voltage comparison result or changing the value of the second PS voltage based on the second voltage comparison result.

[0212] Those skilled in the art should readily understand that the embodiments of the present invention achieve one or more of the advantages described above. After reading the foregoing specification, those skilled in the art will be able to make various changes, equivalent substitutions, and other embodiments of the invention as broadly described. Therefore, the scope of protection shown above is defined only by inclusion in the appended claims and their equivalents.

Claims

1. A system for controlling the temperature in a memory, the system comprising: A high-bandwidth memory includes core dies arranged in a stack, each core die including a library, and each library including a memory cell, the high-bandwidth memory further including: A first sensing unit is configured to generate one or more first ambient signals corresponding to at least a first transistor in at least one of the memory cells, the one or more first ambient signals including a first temperature or a first threshold voltage; and The second sensing unit is configured to generate one or more second ambient signals corresponding to at least the second transistor in the memory cell; and Differential dynamic voltage and frequency scaling devices are configured to perform the following operations: For a first group of one or more memory cells including a first memory cell, the temperature of the first group is controlled by adjusting one or more first transistor temperature-affecting parameters of the first group based on the one or more first environmental signals, the one or more first transistor temperature-affecting parameters including a first power supply voltage; and For a second group of one or more memory cells including a second memory cell, the temperature of the second group is controlled by adjusting one or more second transistor temperature influence parameters of the second group based on the one or more second environmental signals. The first sensing unit is further configured to sense a first temperature or detect a first threshold voltage corresponding to at least one of the first transistors in the first group of memory cells. The differential dynamic voltage and frequency scaling device is also configured to adjust the first power supply voltage based on the first temperature or the first threshold voltage.

2. The system according to claim 1, wherein: The storage cells in the first group and the storage cells in the second group do not overlap.

3. The system according to claim 1, wherein: The second sensing unit is further configured to sense a second temperature or detect a second threshold voltage associated with a first transistor and a second transistor of at least one of the corresponding memory cells of the second group; The one or more second environmental signals include a second temperature or a second threshold voltage; The temperature-affected parameters of the one or more first transistors include a first clock; The temperature-affected parameters of the one or more second transistors include a second clock or a second power supply voltage; and The differential dynamic voltage and frequency scaling device is also configured to perform the following operations: The first clock is adjusted based on the first temperature or the first threshold voltage; and Adjust the second clock or the second power supply voltage based on the second temperature or the second threshold voltage.

4. The system according to claim 3, wherein: The first group of one or more of the storage units is contained in at least the first copy of one or more of the library; The second group of one or more of the storage units is contained in at least a second copy of one or more of the library; The first and second storage units do not overlap. as well as The differential dynamic voltage and frequency scaling device is also configured to perform the following operations: Adjusting the first power supply voltage or the first clock of the first copy causes a first adjustment of the temperature range of the corresponding storage unit in the first copy of the library. and Adjusting the second power supply voltage or the second clock of the second copy causes a second adjustment of the temperature range of the corresponding storage unit in the second copy of the library.

5. The system according to claim 3, wherein: The libraries of the high-bandwidth memory are arranged in a group; The first group of one or more of the storage cells is contained within at least one frame of one or more of the group; The second group of one or more of the storage cells is contained within at least one second frame of the group; The storage cells in the first frame and the storage cells in the second frame do not overlap with each other; as well as The differential dynamic voltage and frequency scaling device is also configured to perform the following operations: Adjusting the first clock or the first power supply voltage of the first frame causes a first group range of temperature adjustment in the storage cells of the first frame. and Adjusting the second clock or the second power supply voltage of the second frame causes a second range of temperature adjustment within the storage cells of the second frame.

6. The system according to claim 3, wherein: Each of the core dies of the high-bandwidth memory is arranged in a channel; The first group of one or more of the storage units is contained in at least the first bundle of one or more of the channels; The second group of one or more of the storage cells is contained in at least the second bundle of one or more of the channels; The storage cells of the first bundle and the storage cells of the second bundle do not overlap with each other; as well as The differential dynamic voltage and frequency scaling device is also configured to perform the following operations: Adjusting the first clock or the first power supply voltage of the first beam causes the temperature in the storage cell of the channel of the first beam to be adjusted within a first channel range. and Adjusting the second clock or the second power supply voltage of the second beam causes the temperature of the second channel range in the storage cell of the channel of the second beam to be adjusted.

7. The system according to claim 3, wherein: The first group of one or more of the memory cells is included in the first set of one or more of the core die; The second group of one or more of the memory cells is contained within the second set of one or more of the core die; The storage units of the first set and the storage units of the second set do not overlap with each other; as well as The differential dynamic voltage and frequency scaling device is also configured to perform the following operations: Adjusting the first clock or the first power supply voltage of the first set causes the temperature of the first core die range in the memory cell of the first set to be adjusted. and Adjusting the second clock or the second power supply voltage of the second set causes the temperature range of the second core die in the memory cell of the second set to be adjusted.

8. The system according to claim 3, wherein, The differential dynamic voltage and frequency scaling device includes: The controller is configured to perform the following operations: The frequency of the first clock is changed based on the first temperature from the first sensing unit; or The value of the first power supply voltage is changed based on the second temperature from the first sensing unit; and The frequency of the second clock is changed based on the second temperature from the second sensing unit; or The value of the second power supply voltage is changed based on the second temperature from the second sensing unit.

9. The system according to claim 8, wherein: The differential dynamic voltage and frequency scaling device further includes: The temperature comparator is configured to perform the following operations: The first temperature is compared with a first temperature reference representing the highest temperature to obtain a first temperature comparison result; and The second temperature is compared with the first temperature reference to obtain the second temperature comparison result; and The controller is also configured to perform the following operations: Execution scenario (A) includes: The frequency of the first clock is changed based on the first temperature comparison result; and The frequency of the second clock is changed based on the second temperature comparison result; or Execution scenario (B) includes: The value of the first power supply voltage is changed based on the first temperature comparison result; or The value of the second power supply voltage is changed based on the second temperature comparison result.

10. The system according to claim 9, wherein: The temperature comparator is also configured to perform the following operations: The first temperature is compared with a second temperature reference representing a moderate temperature to obtain a third temperature comparison result; and The second temperature is compared with the second temperature reference to obtain the fourth temperature comparison result; When the third temperature comparison result indicates that the first temperature is lower than the second temperature reference, the controller is further configured to perform the following operations: Increase the frequency of the first clock; or Increase the value of the first power supply voltage; and When the second temperature comparison result indicates that the second temperature is lower than the second temperature reference, the controller is further configured to perform the following operations: Increase the frequency of the second clock; or Increase the value of the second power supply voltage.

11. The system according to claim 8, wherein: The differential dynamic voltage and frequency scaling device further includes: The threshold voltage comparator is configured to perform the following operations: The first threshold voltage is compared with a voltage reference representing the minimum threshold voltage to obtain a first voltage comparison result; and The second threshold voltage is compared with the voltage reference to obtain a second voltage comparison result; and The controller is also configured to perform the following operations: Execution scenario (A) includes: The frequency of the first clock is changed based on the first voltage comparison result; and The frequency of the second clock is changed based on the result of the second voltage comparison; or Execution scenario (B) includes: The value of the first power supply voltage is changed based on the first voltage comparison result; or The value of the second power supply voltage is changed based on the second voltage comparison result.

12. The system according to claim 8, wherein: When all storage units in the first group are idle, the controller is configured to perform the following operations: Reduce the frequency of the first clock; or Reduce the value of the first power supply voltage; and When all storage units in the second group are idle, the controller is configured to perform the following operations: Reduce the frequency of the second clock; or Decrease the value of the second voltage.

13. The system according to claim 3, wherein, Each of the first sensing unit and the second sensing unit includes: Bias current generator, electrically coupled to the first node; A diode is configured to connect a transistor, electrically coupled between the first node and ground voltage; and The readout circuit is electrically coupled to the first node and configured accordingly to output the first temperature or the second temperature.

14. The system according to claim 3, wherein, Each of the first sensing unit and the second sensing unit includes: A temperature-to-absolute (PTAT) current generator is electrically coupled to the first node; A diode is configured to connect a transistor, electrically coupled between the first node and ground voltage; and The voltage at the first node corresponds to either the first threshold voltage or the second threshold voltage.

15. A system for controlling the temperature in a memory, the system comprising: High-bandwidth memory (HBM) includes core dies arranged in a stack, each core die including a library, and each library including a memory cell, the high-bandwidth memory further including: A first sensing unit is configured to sense a first temperature corresponding to at least one first transistor of the memory cell; and The second sensing unit is configured to sense a second temperature corresponding to at least a second transistor of the corresponding second memory cell; and Differential dynamic voltage and frequency scaling devices are configured to perform the following operations: For a first group of one or more memory cells including a first memory cell, the temperature of the first group is controlled by adjusting one or more first transistor temperature-influencing parameters of the first group based on the first temperature, the one or more first transistor temperature-influencing parameters including a first power supply voltage; and For a second group of one or more memory cells including a second memory cell, the temperature of the second group is controlled by adjusting one or more second transistor temperature influence parameters of the second group based on the second temperature. The differential dynamic voltage and frequency scaling device further includes a temperature comparator configured to compare the first temperature with a first temperature reference representing the highest temperature to obtain a first temperature comparison result. The differential dynamic voltage and frequency scaling device is further configured to change the value of the first power supply voltage based on the first temperature comparison result.

16. The system according to claim 15, wherein: The temperature-affected parameters of the one or more first transistors include a first clock; The temperature-affected parameters of the one or more second transistors include a second clock or a second power supply voltage; and The temperature comparator is further configured to compare the second temperature with the first temperature reference to obtain a second temperature comparison result; as well as The differential dynamic voltage and frequency scaling device is also configured to perform the following operations: Execution scenario (A) includes: The frequency of the first clock is changed based on the first temperature comparison result; and The frequency of the second clock is changed based on the second temperature comparison result; or Execution scenario (B) includes: The value of the second power supply voltage is changed based on the second temperature comparison result.

17. The system according to claim 16, wherein: When the first temperature is lower than a second temperature reference representing a moderate temperature, the differential dynamic voltage and frequency scaling device is also configured to perform the following operations: Increase the frequency of the first clock; or Increase the value of the first power supply voltage; and When the second temperature is lower than the second temperature reference, the differential dynamic voltage and frequency scaling device is also configured to perform the following operations: Increase the frequency of the second clock; or Increase the value of the second power supply voltage.

18. The system according to claim 16, wherein: The temperature-affected parameters of the one or more first transistors include a first clock or a first power supply voltage; The temperature-affected parameters of the one or more second transistors include a second clock or a second power supply voltage; When all memory cells in the first group are idle, the differential dynamic voltage and frequency scaling device is also configured to perform the following operations: Reduce the frequency of the first clock; or Reduce the value of the first power supply voltage; and When all memory cells in the second group are idle, the differential dynamic voltage and frequency scaling device is also configured to perform the following operations: Reduce the frequency of the second clock; or Reduce the value of the second power supply voltage.

19. A method for controlling temperature in a high-bandwidth memory (HBM), the method comprising core dies disposed in a stack, each core die including a library, and each library including a memory cell, the high-bandwidth memory further including at least a first sensing unit and a second sensing unit correspondingly disposed within the core dies, the method comprising: A first threshold voltage is received from a first sensing unit disposed within the high-bandwidth memory, the first threshold voltage corresponding to at least a first transistor in at least the first of the corresponding memory cells. A second threshold voltage is received from a second sensing unit disposed within the high-bandwidth memory, the second threshold voltage corresponding to at least a second transistor in at least a second of the memory cells; For a first group of one or more memory cells including a first memory cell, the temperature of the first group is controlled by adjusting one or more first transistor temperature influence parameters of the first group based on the first threshold voltage; as well as For a second group of one or more memory cells including a second memory cell, the temperature of the second group is controlled by adjusting one or more second transistor temperature influence parameters of the second group based on the second threshold voltage.

20. The method of claim 19, wherein: The temperature-affected parameters of the one or more first transistors include a first clock or a first power supply voltage; The temperature-affected parameters of the one or more second transistors include a second clock or a second power supply voltage; as well as The method further includes: The first threshold voltage is compared with a first voltage reference representing the minimum threshold voltage to obtain the first voltage comparison result; The second threshold voltage is compared with the first voltage reference to obtain a second voltage comparison result; and Execution scenario (A) includes: The frequency of the first clock is changed based on the first voltage comparison result; and The frequency of the second clock is changed based on the result of the second voltage comparison; or Execution scenario (B) includes: Change the value of the first power supply voltage based on the first voltage comparison result; or The value of the second power supply voltage is changed based on the second voltage comparison result.

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