Data pre-processing (DPP) mode supporting both normal programming and early cache release programming (ECRP)

Abstract

Memory devices and methods for data pre-processing for program operations are disclosed herein. In an aspect, a memory device includes N data latches configured to store data and a controller coupled to the N data latches. The controller is configured to receive data including a plurality of data units and store the data units in the N data latches, wherein each data unit includes N bits. The processor is further configured to convert the data units based on a first table and a second table and program a cell of the memory device based on the converted data units. The first table and the second table include N rows and 2 N columns of bits, and the bits from the 2 N‑1 +2column to the 2 N column in the Nth row of the second table are the same. The present disclosure relates to a data pre-processing (DPP) mode that supports both normal program and early cache release program (ECRP).

Description

Technical Field

[0001] This specification relates to memory devices and methods for data preprocessing. Specifically, these memory devices and methods improve the efficiency of programming operations. Background Technology

[0002] A flash memory chip can receive data to be written into its memory cells. In some aspects, the flash memory chip stores this data in a page buffer. For example, a page buffer may include one or more data latches, each of which can store one page of data. In some aspects, the memory cells of the flash memory chip are also referred to as cells of the flash memory chip.

[0003] In some aspects, the received data comprises one or more data units, each corresponding to a cell in the flash memory chip. The controller of the flash memory chip programs one or more data units into their corresponding cells by controlling the voltage level applied to the cells. Based on the binary code included in one or more data units, the controller programs the cells to different voltage levels.

[0004] In some aspects, the controller also verifies whether a group of units has been successfully programmed. For example, the controller determines the group of units and the target voltage level corresponding to that group of data units. The controller then checks whether the group of units meets the voltage requirement corresponding to that target voltage level.

[0005] In some aspects, controllers perform normal programming when selecting one or more data units to be written to their corresponding cells. For example, a controller might select a set of data units that have "0" in their first and second bits, regardless of the values ​​of the other bits. However, normal programming can cause the controller to incorrectly select data units.

[0006] In some implementations, one or more data units are stored in one or more data latches on a flash memory chip. The controller may release one or more data latches before all or all of the data units are programmed. However, the controller may release one or more data latches later than an early release requirement that could lead to a system error. Summary of the Invention

[0007] Some aspects of this disclosure relate to memory devices and methods for data preprocessing. For example, memory devices and methods are provided to improve the efficiency of programming operations.

[0008] Some aspects of this disclosure provide a flash memory chip including a page buffer. The flash memory chip can receive data to be written into cells of the flash memory chip. In some aspects, the cells of the flash memory chip are also referred to as memory cells of the flash memory chip. The flash memory chip can store received data into the page buffer. In some aspects, the page buffer includes one or more data latches. For example, the page buffer may include three data latches: lower page (LP), middle page (MP), and upper page (UP). In such a case, the received data may include one or more data units, each data unit including three bits stored respectively in the three data latches. In other words, the first bit of the data unit is stored in LP, the second bit of the data unit is stored in MP, and the third bit of the data unit is stored in UP.

[0009] In some aspects, the controller of a flash memory chip converts data units into different patterns before programming the cells. For example, the controller can convert data units based on a first table and a second table. The first and second tables can be 3×8 binary tables. The controller can determine that a data unit matches a column in the first table and convert that data unit into the binary code of the corresponding column in the second table. For example, the data unit includes the binary code (010). The controller determines that the second column of the first table also includes the binary code (010). In such a case, the controller then retrieves a second binary code, for example, (001), from the second column of the second table and converts the data unit into that second binary code, for example, (001).

[0010] In some aspects, the controller programs one or more data units into their corresponding cells by applying a voltage level to the cells. Based on the binary code included in the one or more data units, the controller programs the cells to different voltage levels. In some aspects, the controller programs the cells at voltage levels in a batch manner. For example, since the voltage level depends on the binary code included in the data unit, the controller determines that a group of data units in one or more data units all include a binary code, for example, (010). The controller determines the voltage level corresponding to that binary code and a group of cells corresponding to that group of data units. The controller then encodes that group of cells to that voltage level.

[0011] In some aspects, the controller also verifies whether the group of units has been successfully programmed. Similarly, the controller verifies units with the same voltage level in batches. For example, the controller selects the group of data units that includes the binary code (e.g., (010)). The controller then determines the voltage level corresponding to the binary code and the group of units corresponding to the group of data units. Finally, the controller checks whether the group of units meets the voltage requirement corresponding to the voltage level. The voltage requirement can be the voltage level itself or a percentage of the voltage level. For example, the voltage level can be 1V. The voltage requirement can be 1V or 0.9V, which is 90% of the voltage level.

[0012] In some aspects, the controller selects a group of data units based on the presence of "0"s in the data units. For example, to select a data unit containing binary code (010), the controller selects the data unit with "0"s in its first and third bits. In some aspects, it may be more efficient for the controller to search for "0"s instead of "1". For example, the controller can select the group of data units in a shorter amount of time by searching for 0s. After the group of data units has been verified, the controller converts the group of data units to all "1"s, for example, binary code (111). In this case, the group of data units no longer contains "0"s and is therefore no longer selected. In other words, the controller will no longer verify the group of units corresponding to the group of data units in future verifications.

[0013] It is also worth noting that when selecting data units including binary code (010), a second set of data units with binary code (000) is also selected. This is because binary code (000) also has "0" in its first and third bits. In such a case, the unit corresponding to the second set of data units can be verified using the voltage requirement. However, this may be undesirable because the second set of data units can correspond to a second voltage requirement higher than the voltage requirement. Therefore, the unit corresponding to the second set of data units can pass verification even with a voltage lower than the second voltage requirement and higher than the voltage requirement. In other words, the unit corresponding to the second set of data units may pass verification incorrectly. To avoid such a situation, as explained in more detail below, data preprocessing can be designed in a way that the second set of data units with binary code (000) is programmed and verified before the set of data units with binary code (010). Therefore, after the unit corresponding to the second set of data units is verified, the second set of data units is converted to (111) and will no longer be programmed and verified.

[0014] In some respects, the controller can release one or more data latches in the page buffer before all data units have been written into their corresponding cells. For example, two data latches may suffice when only two sets of data units need to be programmed and verified. These two sets of data units may have binary codes (011) and (101), respectively. Therefore, the third bit of both sets of data units is "1" and is not necessary for selecting either set. In such a case, the controller can release the data latch storing the third bit, for example, the UP latch. The UP latch can then be used to receive additional data for further programming operations, thus improving efficiency. In some respects, as explained in more detail below, the second table may affect when the controller can release the data latches.

[0015] This invention is provided merely to illustrate some aspects to provide an understanding of the subject matter described herein. Accordingly, the features described above are merely illustrative and should not be construed as narrowing the scope or spirit of the subject matter of this disclosure. Other features, aspects, and advantages of this disclosure will become apparent from the following detailed description, drawings, and claims. Attached Figure Description

[0016] The accompanying drawings are incorporated herein and form part of the specification.

[0017] Figure 1 An example system of a storage system having NAND flash memory according to aspects of this disclosure is shown.

[0018] Figure 2 An example circuit diagram of a memory array according to aspects of this disclosure is shown.

[0019] Figure 3 An example threshold voltage distribution of a NAND flash memory according to aspects of this disclosure is shown.

[0020] Figure 4 An example of data preprocessing (DPP) using normal programming is shown according to aspects of this disclosure.

[0021] Figure 5 An example of data preprocessing using an early release operation according to aspects of this disclosure is shown.

[0022] Figure 6 An example of data preprocessing using both normal programming and early release operations, according to aspects of this disclosure, is shown.

[0023] Figure 7 An example of an early release operation at level 5 according to aspects of this disclosure is shown.

[0024] Figure 8 An example of an early release operation at level 6 according to aspects of this disclosure is shown.

[0025] Figure 9 An example of an early release operation at level 7 according to aspects of this disclosure is shown.

[0026] Figure 10 An example method for performing programming operations using preprocessing according to aspects of this disclosure is shown.

[0027] Figure 11 It is an example computer system for implementing some aspects or one or more parts of this disclosure.

[0028] The features and advantages of the invention will become more apparent from the specific embodiments described below, taken in conjunction with the accompanying drawings, in which similar reference numerals consistently denote corresponding elements. In the drawings, similar reference numerals generally indicate identical, functionally similar, and / or structurally similar elements.

[0029] Various aspects of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0030] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will also be apparent to those skilled in the art that this disclosure can be used for a variety of other applications.

[0031] Note that references to "an embodiment," "embodiment," "example embodiment," "some aspects," etc., in this specification indicate that the described embodiment may include specific features, structures, or characteristics, but each embodiment need not necessarily include specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in combination with other aspects will be within the knowledge of those skilled in the art.

[0032] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0033] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter for a component or process step, set during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. The range of values ​​may arise due to minor variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a value of a given quantity that can vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" can indicate a value of a given quantity that varies, for example, within 10% to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0034] Figure 1 A storage system 100 according to some aspects of this disclosure is illustrated. The storage system 100 may also be referred to as a solid-state drive (SSD) 100, which includes NAND flash memory 118 and a host controller 104. The SSD 100 can communicate with a host computer 102 via the host controller 104, wherein the host controller 104 can be connected to the NAND flash memory 118 via a memory channel 106. In some aspects, the SSD 100 may have more than one NAND flash memory 118, and each NAND flash memory 118 may be managed by the host controller 104. In some aspects, the host controller 104 includes one or more processors.

[0035] The host computer 102 sends data to be stored in the SSD 100 or retrieves data by reading from the SSD 100. The host controller 104 can process I / O requests received from the host computer 102, ensure data integrity and efficient storage, and manage the NAND flash memory 118. The memory channel 106 can provide data and control communication between the host controller 104 and the NAND flash memory 118 via a data bus.

[0036] NAND flash memory 118 (e.g., "flash memory", "NAND flash", or "NAND") can be a memory chip (package), a memory die, or any part of a memory die, and may include one or more memory surfaces 120, each memory surface 120 including multiple memory blocks 122. The same and concurrent operations can occur at each memory surface 120. A memory block 122, which may be megabytes (MB) in size, is the minimum size for performing an erase operation. Figure 1 As shown, the exemplary NAND flash memory 118 includes four memory surfaces 120, and each memory surface 120 includes six memory blocks 122. Each memory block 122 may include multiple memory cells, wherein each memory cell can be addressed via interconnects such as bit lines and word lines. The bit lines and word lines may be arranged vertically (e.g., in rows and columns, respectively) to form an array of metal lines. Figure 1 In this disclosure, the directions of the bit lines and word lines are indicated as "BL" and "WL". The memory block 122 is also referred to as a "memory array" or "array". A memory array is the core area in a memory device that performs storage functions.

[0037] The NAND flash memory 118 also includes a peripheral region 124, which is the region surrounding the memory surface 120. The peripheral region 124 contains digital, analog, and / or mixed-signal circuitry (e.g., page buffer 110, row decoder 108, column decoder 112, peripheral circuitry 114, and sense amplifier 116) to support the functionality of the memory array. The peripheral circuitry 114 includes active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., which will be apparent to those skilled in the art.

[0038] It should be noted that Figure 1 The layout of the electronic components in the SSD 100 and NAND flash memory 118 is shown as an example only. The SSD 100 and NAND flash memory 118 may have other layouts and may include additional components. For example, the NAND flash memory 118 may also include a high-voltage charge pump, I / O circuitry, etc. The SSD 100 may also include firmware, a data scrambler, etc.

[0039] Figure 2An example circuit diagram 200 of a memory block 122 according to some aspects of this disclosure is shown. The example circuit diagram 200 includes a plurality of memory strings 202, each memory string 202 having a plurality of memory cells 210. Each memory string 202 also includes at least one field-effect transistor (e.g., MOSFET) controlled at each end by a lower select gate (LSG) 204 and a top select gate (TSG) 206, respectively. These two corresponding transistors are referred to as lower select transistor 204-T and top select transistor 206-T. Memory cells 210 may be controlled by a control gate 208, which may be connected to a word line of the example circuit diagram 200. The drain terminal of the top select transistor 206-T may be connected to a bit line 212, and the source terminal of the lower select transistor 204-T may be connected to an array common source (ACS) 214. The array common source 214 may be shared by the memory strings 202 throughout the memory block and is also referred to as a common source line.

[0040] In some aspects, example circuit diagram 200 may be formed based on floating gate technology. In some aspects, example circuit diagram 200 may be formed based on charge trapping technology. Charge trapping-based NAND flash memory can provide high storage density and high inherent reliability. It stores data or logic states (e.g., the threshold voltage V of memory cell 210). th The amount depends on the amount of charge trapped within the storage layer. In some aspects, the NAND flash memory 118 can be a three-dimensional (3D) memory device, and the example circuit diagram 200 can be a 3D memory array in which memory cells 210 can be stacked vertically on top of each other.

[0041] In NAND flash memory, read and write operations can be performed in memory pages 216 that include all memory cells 210 sharing the same word line. In NAND memory, memory cells 210 can be in an erase state ER or a programmable state P1. Initially, all memory cells 210 in example circuit schematic 200 can be reset to the erase state ER, which is logic "1", by implementing a negative voltage difference between the control gate 208 of the memory cell and the source terminal (e.g., array common source 214), thereby removing all trapped electronic charge in the storage layer of the memory cell 210. This negative voltage difference can be initiated, for example, by setting the control gate 208 of the memory cell 210 to ground and applying a high positive voltage to the array common source 214. At the erase state ER ("state ER"), the threshold voltage V of the memory cell 210... thIt can be reset to the lowest value and can be measured or sensed at bit line 212.

[0042] During programming (i.e., writing), the programming voltage V pgm (For example, a positive voltage pulse between 10V and 30V) can be applied to the control gate 208, such that electronic charge (e.g., electrons) can be injected into the storage layer of the memory cell 210, thereby increasing the threshold voltage V of the memory cell 210. th Therefore, memory cell 210 is programmed to state P1.

[0043] NAND flash memory can be configured to operate in single-level cell (SLC) mode. To increase storage capacity, NAND flash memory can also be configured to operate in multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC) mode, or a combination of these modes. In SLC mode, the memory cell stores "1" bit and has two logical states ("states"), namely states ER and P1. In MLC mode, the memory cell stores 2 bits and has four states, namely states ER, P1, P2, and P3. In TLC mode, the memory cell stores 3 bits and has eight states, namely states ER and P1–P7. In QLC mode, the memory cell stores 4 bits and has 16 states.

[0044] Figure 3 The threshold voltage V of a NAND flash memory programmed in three-cell (TLC) mode according to some aspects of this disclosure is shown. th Distribution. Due to various variations, each state of a memory cell includes a certain range of threshold voltages V. th (x-axis), where the threshold voltage V for each state. th The distribution can be represented by a probability density (y-axis). In some aspects, the eight TLC states can be programmed using an incremental step pulse programming (ISPP) scheme, where the step pulse V is increased. step And make the programming voltage V pgm The threshold voltage increases incrementally. Accordingly, the eight TLC states can be programmed from state P1 with the lowest threshold voltage to state P7 with the highest threshold voltage.

[0045] In some aspects, to improve programming speed, the same memory page 216 ( Figure 2Memory cells sharing the same word line (i.e., the same control gate 208) are programmed. A verification read can be performed after each ISPP pulse. In some aspects, further programming of memory cells that have reached a target state (i.e., the target threshold voltage) can be prevented by controlling TSG 206 and / or LSG 204. In some aspects, further programming of memory cells can also be prevented by increasing the voltage on the corresponding bit line.

[0046] After programming, one or more reference voltages V can be used to read the voltage. R1 -V R7 Verification was performed on eight TLC states ER and P1-P7. This was achieved by applying a read reference voltage V to the control gate of the target memory cell. R1 -V R7 One or more voltages in the data can determine the threshold voltage V of the memory cell. th The range. For example, to verify whether the target memory cell 340 is in state ER, the read reference voltage V can be used. R1 If the target memory cell is in state ER, then the threshold voltage V of the target memory cell is... th Below the reading reference voltage V R1 The target memory cell can be turned on and form a conductive path in the channel. If the target memory cell is in any of states P1-P7, then the threshold voltage V of the target memory cell... th Higher than the reading reference voltage V R1 This shuts down the target memory cell. The threshold voltage V of the target memory cell can be verified by measuring or sensing the current through the target memory cell at the corresponding bit line. th Or state.

[0047] As described above, to determine the two states ER and P1 stored in SLC mode, it is only necessary to read the reference voltage V. R1 To determine the four states ER and P1-P3 in MLC mode, the reference voltage V can be read. R1 V R2 and V R3 To determine the eight states ER and P1-P7 of the TLC mode, the reference voltage V can be read. R1 -V R7 For example, in TLC mode, the threshold voltage of state ER is lower than V. R1 And the threshold voltage of state P7 is higher than V. R7 Wherein, the threshold voltage of state P1 is between V R1 With V R2 Between these points, states P2-P6 can be similarly determined.

[0048] In some aspects, to improve read and program speeds, multiple memory pages (“physical pages”) can be read or programmed simultaneously. In MLC, TLC, or QLC modes, each memory page can be read or programmed based on one or more logical pages. For example, in a TLC mode with 3 bits per memory cell, a memory page can be programmed based on three logical pages, such as the next page, the middle page, and the previous page.

[0049] Figure 4 An example of data preprocessing (DPP) using normal programming, according to aspects of this disclosure, is shown. (The remaining text appears to be incomplete and requires further context.) Figure 1 , Figure 2 and Figure 11 To describe the components Figure 4 Example 400 can be provided by a storage system (e.g., Figure 1 The storage system 100) executes. Example 400 can also be executed by... Figure 11 The computer system 1100 is used to execute this method. However, Example 400 is not limited to the specific aspects depicted in these figures, and other systems can be used to execute the method, as will be understood by those skilled in the art. It should be appreciated that not all operations may be required, and it may not be necessary to use the same system as the computer system 1100. Figure 4 These operations are performed in the same order as shown.

[0050] In some aspects, as described above, a flash memory chip (e.g., storage system 100) can receive data to be written into cells of the flash memory chip. In some aspects, a cell of the flash memory chip is also referred to as a memory cell of the flash memory chip. The received data may include one or more data units. Prior to programming operations, the controller of the flash memory chip converts one or more data units based on tables 402 and 404. For example, a data unit may include binary code (010). The controller determines that the fifth column of table 402 includes binary code (010). Then, the controller determines that the fifth column of table 404 includes binary code (001) and converts the data unit into binary code (001).

[0051] In some aspects, the controller performs programming operations after converting data units. Table 404 also serves as a lookup table for programming and verification operations. In some aspects, each column of Table 404 corresponds to a voltage level. For example, column 1 corresponds to LV0, which is also known as the erase state voltage level. Column 2 corresponds to LV1. In some aspects, LV0 to LV7, corresponding to columns 1 to 8, are in ascending order. For example, LV7 has the highest voltage level, and LV0 has the lowest voltage level. In some aspects, LV0 corresponds to... Figure 3The ER, and LV1 to LV7 correspond to Figure 3 P1 through P7, as described above. In some aspects, the controller programs the cells corresponding to the data units based on the voltage levels determined by Table 404. For example, a data unit including binary code (010) matches column 4 of Table 404. Therefore, the controller programs the cell corresponding to that data unit until that cell reaches LV3 voltage.

[0052] In some aspects, the data unit corresponds to the cell based on its position in the data latch. As described above, a page buffer, such as page buffer 110, may include one or more data latches. For example, the page buffer here includes three data latches: LP, MP, and UP, also known as D1 latch, D2 latch, and DC latch. Each of the one or more data units includes three bits stored in LP, MP, and UP, respectively. The controller can determine that the data unit occupies a position in each of LP, MP, and UP, for example, the 10th bit, and determine the cell corresponding to that position. The controller then configures the voltage to be applied to the cell to be an LV3 voltage.

[0053] In some aspects, the controller programs units in batches via voltage levels. For example, the controller can program units to LV1 voltage. The controller selects a first set of data units including binary code (000). Then, the controller locates the first set of units corresponding to the first set of data units based on their position in the data latch. Finally, the controller programs the first set of units to LV1 voltage. In some aspects, after programming the first set of units, the controller verifies the first set of units. For example, the controller selects a first set of data units including binary code (000) and locates the first set of units. Then, the controller checks whether the first set of units meets a first voltage requirement. In some aspects, the first voltage requirement can be LV1 voltage or a certain percentage of LV1 voltage. For example, LV1 voltage can be -1.4V. The first voltage requirement can be -1.4V or slightly lower than LV1 voltage, -1.5V. Similarly, LV2 voltage can be -0.4V, and the second voltage requirement can be -0.4V or slightly lower than LV2 voltage, -0.5V. The LV3 voltage can be 0.4V, and the third voltage requirement can be 0.4V or 0.36V, which is 90% of the LV3 voltage. LV3-LV7 voltages correspond to voltage requirements in a similar manner. If the first group of units meets the first voltage requirement, the controller converts the first group of data units into binary code (111).

[0054] In some aspects, the controller programs and verifies the cells in batches, from lower voltage levels to higher voltage levels. For example, the controller starts batch programming from LV1 because LV0 corresponds to the erase state. After programming the first group of cells, the controller converts the first group of data units into binary code (111) and begins programming the second group of cells corresponding to LV2. For example, the controller selects the second group of data units with binary code (100) and then selects the second group of cells based on the second group of data units.

[0055] In some aspects, the controller selects data by choosing 0. For example, when selecting a second set of data units including binary code (100), the controller checks whether the data unit contains "0" in its second and third bits. It can be seen that the first set of data units would also be selected because it includes binary code (000), which also contains "0" in its second and third bits. However, since the controller has previously converted the first set of data units to binary code (111) after verifying them, the first set of data units will no longer be selected, thus avoiding selection errors. In some aspects, selecting data units by choosing 0, as described above, is called normal programming. Normal programming can improve the efficiency of selection because selecting "0" is easier than selecting "1".

[0056] For proper programming to be performed, the data unit corresponding to the higher voltage has a subset of the "0" bits corresponding to the lower voltage data unit. For example, based on Table 404, column 3 has "0" bits located in both the MP and UP rows. Therefore, the set of "0" bits for column 3 is {MP row, UP row}. Thus, for later columns (e.g., columns 4-8), the set of "0" bits within both the MP and UP rows is a subset of {MP row, UP row}. In other words, columns 4-8 do not include "0" bits located in either the MP or UP rows. For example, with regard to column 5, only the MP row includes "0" bits. Therefore, the set of "0" bits in the MP and UP rows of column 5 is {MP row}, which is a subset of {MP row, UP row}. In this way, when the controller selects a data unit with "0" bits located in the MP and UP rows (second and third bits), the data unit corresponding to column 4-8 will not be selected.

[0057] In some aspects, the controller can release the data latch before all data units are programmed and verified. For example, the controller can release the UP (DC latch) data latch before LV7 data units are programmed and verified. In some aspects, after verifying LV5 units, the controller converts the corresponding data units into binary code (111). In this case, the received data units include three binary codes: (111), (011), and (101). This is because all data units, except those corresponding to (011) and (101), are verified and converted into binary code (111). In the case of only three possible binary codes, the controller can distinguish them using bits in the LP and MP data latches. For example, to select a data unit corresponding to LV6 or (011), the controller can select the data unit using a "0" in the LP row. Similarly, the controller can select a data unit corresponding to LV7 or (101) by selecting a "0" in the MP row. Therefore, the controller can release the UP data latch, which can be used to store newly received data. However, applying Table 404, the earliest time the controller can release the UP data latch is after the LV5 cell has been programmed and verified. This may not meet the Early Cache Release Program (ECRP) requirement, which requires the UP data latch to be released before the LV5 cell has been programmed and verified.

[0058] Figure 5 An example of a DPP employing an early release operation according to aspects of this disclosure is shown. (The remaining text appears to be incomplete and requires further context.) Figure 1 , Figure 2 and Figure 11 To describe the components Figure 5 Example 500 can be provided by a storage system (e.g., Figure 1 The storage system 100) executes. Example 500 can also be executed by... Figure 11 The computer system 1100 is used to execute this method. However, Example 500 is not limited to the specific aspects depicted in these figures, and other systems can be used to execute the method, as will be understood by those skilled in the art. It should be recognized that not all operations may be required, and it may not be necessary to use the same system as the computer system 1100. Figure 5 These operations are performed in the same order as shown.

[0059] In some aspects, as described above, a flash memory chip (e.g., storage system 100) receives data to be written into cells of the flash memory chip. Prior to the programming operation, the controller of the flash memory chip converts one or more data units based on Tables 502 and 504. The controller then programs and verifies the cells using voltage levels from LV1 to LV7. In some aspects, after programming and verifying a cell at LV4, the received data unit includes four binary codes: (111), (000), (100), and (010). Data units corresponding to LV1 through LV4 are converted to binary code (111) after verification. Data units corresponding to LV0 initially include binary code (111). Data units at LV5, LV6, and LV7 correspond to binary codes (000), (100), and (010). With only four possible binary codes, the controller can use bits in the LP and MP data latches to distinguish data units at different voltage levels; that is, 2 bits correspond to the four possibilities. For example, to select the data unit corresponding to LV5 or (000), the controller can select the data unit using "0" from both the LP and MP rows. Similarly, the controller can select the data unit corresponding to LV6 or (100) by selecting "0" from the MP row. Therefore, the controller can release the UP data latch after LV4, which satisfies the ECRP requirements.

[0060] On the other hand, applying Table 504 prevents the controller from performing normal programming. For example, when selecting the LV2 data unit, the controller selects "0" in the MP row. Besides the LV2 data unit, the controller might also select LV5 and LV6 data units. In this case, the controller programs and verifies the LV5 and LV6 units as having the LV2 voltage level, which will result in an error. Furthermore, after verifying the LV5 and LV6 units, the controller converts the LV5 and LV6 data units into binary code (111), and therefore the error will not be detected through verification.

[0061] Figure 6 An example of data preprocessing using both normal programming and early release operations, according to aspects of this disclosure, is shown. (The remaining text appears to be incomplete and possibly contains errors.) Figure 1 , Figure 2 and Figure 11 To describe the components Figure 6 Example 600 can be provided by a storage system (e.g., Figure 1 The storage system 100) executes. Example 600 can also be executed by... Figure 11The computer system 1100 is used to execute this method. However, Example 600 is not limited to the specific aspects depicted in these figures, and other systems can be used to execute the method, as will be understood by those skilled in the art. It should be appreciated that not all operations may be required, and it may not be necessary to use a computer system 1100 to execute this method. Figure 6 These operations are performed in the same order as shown.

[0062] In some aspects, as described above, a flash memory chip (e.g., storage system 100) receives data to be written into cells of the flash memory chip. Prior to the programming operation, the controller of the flash memory chip converts one or more data units based on Tables 602 and 604. Above this, the controller programs and verifies the cells using voltage levels from LV1 to LV7. In some aspects, after programming and verifying the LV4 cell, the received data unit includes four binary codes: (111), (001), (101), and (011). Data units corresponding to LV1 through LV4 are converted to binary code (111) after verification. Data units corresponding to LV0 initially include binary code (111). Data units for LV5, LV6, and LV7 correspond to binary codes (001), (101), and (011). In the case of only four possible binary codes, the controller can distinguish them using bits in the LP and MP data latches; that is, 2 bits correspond to the four possibilities. For example, to select the data unit corresponding to LV5 or (001), the controller can select the data unit by using "0" in either the LP line or the MP line. Similarly, the controller can select the data unit corresponding to LV6 or (101) by selecting "0" in the MP line. Therefore, the controller can release the UP data latch after LV4, which satisfies the ECRP requirement.

[0063] On the other hand, by applying Table 604, the controller can also perform normal programming. For example, when selecting the data unit for LV2, the controller selects "0" in both the MP and UP rows. Data units for LV3 through LV7 are not selected because none of them include "0" in either the MP or UP rows. Therefore, applying Table 604 in programming and verification operations satisfies both ECRP requirements and normal programming.

[0064] Figure 7 An example of an early release operation at level 5 according to aspects of this disclosure is shown. (This can be discussed regarding...) Figure 1 , Figure 2 and Figure 11 To describe the components Figure 7 Example 700 can be provided by a storage system (e.g., Figure 1 The storage system 100) executes. Example 700 can also be executed by... Figure 11The computer system 1100 is used to execute this method. However, Example 700 is not limited to the specific aspects depicted in these figures, and other systems can be used to execute the method, as will be understood by those skilled in the art. It should be appreciated that not all operations may be required, and it may not be necessary to use a computer system 1100 to execute this method. Figure 7 These operations are performed in the same order as shown.

[0065] In some aspects, by applying Table 604, the controller can release the DC latch after verifying the LV4 cell. The controller stores newly received data (e.g., data from the next LP data latch) into the DC latch. In some aspects, the controller first receives data from the LP data latch, then receives data from the MP data latch, and finally receives data from the UP data latch.

[0066] As described above, the controller selects "0" from latches D1 and D2 to program and verify the LV5, LV6, and LV7 units. For example, the controller selects the LV5 data unit, which includes "0" in both latches D1 and D2. The LV6 and LV7 data units are not selected because they include "0" in either latch D1 or latch D2, rather than in both.

[0067] In some aspects, the flash memory chip (e.g., memory system 100) also includes a DS data latch. In other words, each data unit in the received data unit may also include a fourth bit. Except for the LV0 data unit, the DS data latch initially includes a "0" bit for each data unit in the received data unit. After the cell corresponding to the data unit is verified, the controller converts the corresponding portion of the DS data latch to 1. In some aspects, when programming a cell, the controller selects the data unit based on the DS data latch instead of the D1 data latch (LP), D2 data latch (MP), and DC data latch (UP). For example, when programming an LV1 cell, the controller selects the data unit with a "0" in the DS data latch and applies an LV1 voltage to the corresponding cell. In this case, cells LV2 through LV7 are also programmed and LV1 voltages are applied. However, when verifying an LV1 cell, the controller selects based on the D1 data latch (LP), D2 data latch (MP), and DC data latch (UP). As mentioned above, cells LV2 through LV7 will not be verified. After a cell LV1 is verified, the bit in the DS latch corresponding to the LV1 data unit is converted to 1. In another example, when programming a cell LV2, the controller selects the data unit with a "0" in the DS data latch and applies the LV2 voltage to the corresponding cell. In this case, cells LV3 through LV7 are also programmed and LV2 voltages are applied. However, the previously programmed and verified LV1 cells are programmed here, thus avoiding the application of a higher LV2 voltage to the lower-voltage LV1 cells.

[0068] Figure 8 An example of an early release operation at level 6 according to aspects of this disclosure is shown. (The following is a possible interpretation:) Figure 1 , Figure 2 and Figure 11 To describe the components Figure 8 Example 800 can be provided by a storage system (e.g., Figure 1 The storage system 100) executes. Example 800 can also be executed by... Figure 11 The computer system 1100 is used to execute this method. However, example 800 is not limited to the specific aspects depicted in these figures, and other systems can be used to execute the method, as will be understood by those skilled in the art. It should be recognized that all operations may be required and may not be performed in accordance with... Figure 8 These operations are performed in the same order as shown.

[0069] In some aspects, by applying Table 604, the controller further releases the D1 latch after verifying the LV5 cell. The controller moves the data from the next LP data latch into the newly released D1 latch. The controller also stores newly received data (e.g., data from the next MP data latch) in the DC latch. In some aspects, the controller first stores the newly received data in the DC latch and then moves it sequentially into the D1 and D2 latches.

[0070] In some cases, since only one data latch is available, the controller selects a "0" in the D2 latch to program and verify the LV6 unit. For example, if the controller selects a data unit that includes a "0" in the D2 latch, then LV7 data units will not be selected because they include a "1" in the D2 latch.

[0071] Figure 9 An example of an early release operation at level 7 according to aspects of this disclosure is shown. (The following is a possible interpretation:) Figure 1 , Figure 2 and Figure 11 To describe the components Figure 9 Example 900 can be provided by a storage system (e.g., Figure 1 The storage system 100) executes. Example 900 can also be executed by... Figure 11 The computer system 1100 is used to execute this method. However, Example 900 is not limited to the specific aspects depicted in these figures, and other systems can be used to execute the method, as will be understood by those skilled in the art. It should be appreciated that not all operations may be required, and it may not be necessary to use a computer system 1100 to execute this method. Figure 9 These operations are performed in the same order as shown.

[0072] In some aspects, by applying Table 604, the controller further releases the D2 latch after verifying the LV6 unit. The controller moves the data from the next MP data latch into the newly released D2 latch. The controller also stores newly received data (e.g., data from the next UP data latch) in the DC latch. In this case, the data unit for further operation is received and stored.

[0073] In some aspects, since D2 is also released, the controller selects the LV7 data unit based on the DS data latch in both programming and verification operations. As described above, the controller toggles the corresponding bit of the DS data latch after verifying the unit. Since the LV7 unit is neither programmed nor verified, the corresponding bit of the DS data latch is "0", and the controller selects the LV7 data unit based on this bit.

[0074] Figure 10An example method for programming operations using preprocessing according to aspects of this disclosure is shown. For convenience and not limitation, further details can be found regarding... Figure 1 , Figure 2 and Figure 11 To describe the components Figure 10 Example method 1000 can be provided by a storage system (e.g., Figure 1 The storage system 100) executes the method. Example method 1000 can also be executed by... Figure 11 The example method 1000 is executed using computer system 1100. However, the example method 1000 is not limited to the specific aspects depicted in these figures, and other systems can be used to execute the method, as will be understood by those skilled in the art. It should be recognized that not all operations may be required, and it may not be necessary to use a computer system 1100. Figure 10 These operations are performed in the same order as shown.

[0075] At 1002, a flash memory chip (e.g., storage system 100) receives data to be written to cells of the flash memory chip. The received data includes one or more data units, each of which includes one or more bits. A controller (e.g., host controller 104) stores the data units into a page buffer (e.g., page buffer 110). The page buffer may include one or more data latches. For example, the page buffer may include three data latches. Correspondingly, each of the one or more data units includes three bits stored in the three data latches respectively.

[0076] At position 1004, the controller is based on the first table and the second table (e.g., Figure 6 The controller converts one or more received data units (using Tables 602 and 604). For example, the controller determines that a data unit matches a column in the first table and then converts that data unit into the binary code of the corresponding column in the second table.

[0077] At 1006, the controller programs the cells of the flash memory chip based on the converted data. In some aspects, the controller programs one cell at a time, from lower voltage levels to higher voltage levels. For example, referring to Table 604, the controller may first program the cells of LV1. Specifically, the controller selects the first set of data units corresponding to LV1, i.e., the data unit including (000). The controller then locates the cell of LV1 and applies the ISPP voltage until the cell reaches the LV1 voltage level. After that, control moves to 1008 before programming cells of other voltage levels. In some aspects, since LV0 corresponds to the erase state, the cells of LV0 are skipped.

[0078] At point 1008, the controller verifies the cells programmed in point 1006. For example, after programming an LV1 cell, the controller checks whether the LV1 cell meets the LV1 voltage requirement. The LV1 voltage requirement can be the LV1 voltage level or a certain percentage of the LV1 voltage level. The controller also measures the number of cells that do not meet the LV1 voltage requirement.

[0079] At 1010, the controller determines whether the verification of the cell programmed in 1006 was successful. For example, if the number of failed cells exceeds a certain threshold, the controller can determine that the verification was unsuccessful. In such a case, control moves back to 1006, and the controller reprograms the cell, for example, the LV1 cell. Otherwise, the controller determines that the verification was successful, and control moves to 1012.

[0080] At 1012, the controller determines whether it is possible to release the latch. For example, referring to Table 604, if the cell successfully verified in 1010 is an LV4 cell, then the controller can determine that the DC latch can be released. If the cell successfully verified in 1010 is an LV5 cell, then the controller can also determine that the D1 latch can be released. If the cell successfully verified in 1010 is an LV6 cell, then the controller can also determine that the D2 latch can be released. In any of these cases, control moves to 1016.

[0081] At 1016, the controller releases the data latch, such as a DC latch, D1 latch, or D2 latch. Control then returns to 1006, and the controller programs the cell for the next voltage level.

[0082] Returning to reference 1012, if the controller determines that it is impossible to release the data latch, then control moves to 1014.

[0083] At 1014, the controller determines whether the programming operation is complete. For example, the controller may determine that the unit successfully verified in 1010 is an LV7 unit. In this case, it is impossible to release the data latch because all data latches have been released. However, since the LV7 unit was the last one programmed, the controller has completed the programming of the received data unit and the programming operation is complete. In this case, control moves to 1018, and the programming operation ends.

[0084] Returning to reference 1014, the controller can determine that the programming operation is incomplete. For example, the cell successfully verified in 1010 might be an LV2 cell. Therefore, it is too early to release the data latch, and more cells need to be programmed. In such a case, control moves to 1006, and the controller continues programming cells at the next voltage level (e.g., cells with LV3).

[0085] For example, one or more computer systems can be used (e.g., Figure 11 The computer system 1100 shown herein implements various aspects. The computer system 1100 may be capable of performing the functions described herein (e.g., Figure 1 The computer system 1100 is any known computer with a storage system 1106. The computer system 1100 includes one or more processors (also known as central processing units or CPUs), such as processor 1104. Processor 1104 is connected to communication infrastructure 1106 (e.g., a bus). The computer system 1100 also includes one or more user input / output devices 1103, such as monitors, keyboards, pointing devices, etc., which communicate with communication infrastructure 1106 via one or more user input / output interfaces 1102. The computer system 1100 also includes main memory or primary memory 1108, such as random access memory (RAM). Main memory 1108 may include one or more levels of cache. Main memory 1108 has control logic (e.g., computer software) and / or data stored therein.

[0086] Computer system 1100 may also include one or more auxiliary storage devices or memories 1110. Auxiliary memory 1110 may include, for example, a hard disk drive 1112 and / or a removable storage device or drive 1114. Removable storage drive 1114 may be a floppy disk drive, tape drive, compact disk drive, optical storage device, tape backup device and / or any other storage device / drive.

[0087] Removable storage drive 1114 can interact with removable storage unit 1118. Removable storage unit 1118 includes a computer-usable or readable storage device having computer software (control logic) and / or data stored thereon. Removable storage unit 1118 can be a floppy disk, magnetic tape, compact disc, DVD, optical storage disc, and / or any other computer data storage device. Removable storage drive 1114 reads from and / or writes to removable storage unit 1118 in a known manner.

[0088] According to some aspects, auxiliary storage 1110 may include other mechanisms, measures, or other means for allowing computer programs and / or other instructions and / or data to be accessed by computer system 1100. Such mechanisms, measures, or other means may include, for example, removable storage unit 1122 and interface 1120. Examples of removable storage unit 1122 and interface 1120 may include a program cartridge and cartridge interface (e.g., found in video game devices), a removable memory chip (e.g., EPROM or PROM) and associated socket, a memory stick and USB port, a memory card and associated memory card slot, and / or any other removable storage unit and associated interface.

[0089] Computer system 1100 may also include a communication or network interface 1124. Communication interface 1124 enables computer system 1100 to communicate and interact with any combination of remote devices, remote networks, remote entities, etc. (identified individually and uniformly by reference numeral 1128). For example, communication interface 1124 may allow computer system 1100 to communicate with remote device 1128 via communication path 1126, which may be wired and / or wireless, and may include any combination of LAN, WAN, Internet, etc. Control logic and / or data may be transferred to and from computer system 1100 via communication path 1126.

[0090] The operations described in the foregoing aspects can be implemented in a wide variety of configurations and architectures. Therefore, some or all of the operations described in the foregoing aspects can be performed in hardware, in software, or both. In some aspects, a tangible, non-transitory means or article of manufacture includes, as also referred to herein as a computer program product or program storage device, a tangible, non-transitory computer-usable or readable medium having control logic (software) stored thereon. This means or article of manufacture includes, but is not limited to, computer system 1100, main memory 1108, secondary memory 1110, and removable storage units 1118, 1122, and tangible articles embodying any combination thereof. Such control logic, when executed by one or more data processing devices (e.g., computer system 1100), causes such data processing devices to perform the operations described herein.

[0091] Based on the teachings contained in this disclosure, those skilled in the art (one or more) will clearly understand how to use... Figure 11 The various aspects of this disclosure may be made and used using data processing devices, computer systems, and / or computer architectures other than those shown herein. In particular, the various aspects may be operated using software, hardware, and / or operating system implementations other than those described herein.

[0092] In summary, this disclosure describes various aspects of memory storage systems and methods for implementing them.

[0093] Some aspects of this disclosure provide a memory device including N data latches configured to store data and a controller coupled to the N data latches. The controller is configured to receive data comprising multiple data units and store the data units in the N data latches, wherein each data unit comprises N rows, and each of the N rows contains one bit. The processor is further configured to convert the data units based on the first table and the second table, and to program cells of the memory device based on the converted data units. The first table and the second table comprise N rows and 2 bits. N The position of the column, and in the Nth row of the second table from the 2nd... N- N+1 column to the 2nd N The columns have the same position. The second table also includes column L, which contains K numbers of "0"s in one or more rows. Column M of the second table contains one or more rows containing fewer than K numbers of 0, where L is less than M.

[0094] Some aspects of this disclosure relate to the memory device, wherein, in order to convert data units, the controller is further configured to determine that one of a plurality of data units matches a bit in the first column of a first table, and convert the data unit into a bit in the first column of a second table.

[0095] Some aspects of this disclosure relate to the memory device, wherein the columns of the second table correspond to the respective voltage levels.

[0096] Some aspects of this disclosure relate to the memory device, wherein, in order to store data units in N data latches, the controller is further configured to store the J-th bit of each data unit in the J-th data latch.

[0097] Some aspects of this disclosure relate to the memory device, wherein, in order to program the cells of the memory device based on the converted data units, the controller is further configured to: determine that one or more data units in the converted data units match a target column of a second table; determine a target voltage level corresponding to the target column; determine one or more cells in the memory device corresponding to the one or more data units; and apply the target voltage level to the one or more cells.

[0098] Some aspects of this disclosure relate to the memory device, wherein the controller is further configured to verify one or more cells, the controller being configured to: determine that a set of rows of the target column of the second table contains “0” bits; determine one or more data units based on the set of rows; determine one or more cells based on the one or more data units; verify that the voltage level of the one or more cells is higher than a voltage requirement; and convert one or more rows of the one or more data units into “1” bits based on the set of rows.

[0099] Some aspects of this disclosure relate to the memory device, wherein the controller is further configured to: determine that the target column is the second of the second table. N-1 +1 column; and release the Nth data latch of the memory device.

[0100] Some aspects of this disclosure provide a method for operating a memory device, the method comprising: receiving data comprising a plurality of data units, wherein each data unit comprises N bits; storing the data units in N data latches; converting the data units based on the first table and the second table; and programming cells of the memory device based on the converted data units. The first table and the second table comprise N rows and 2... N The position of the column, and in the Nth row of the second table from the 2nd... N -N+1 column to the 2nd N The columns have the same position. The second table also includes column L, which contains K numbers of "0"s in one or more rows. Column M of the second table contains one or more rows containing fewer than K numbers of 0, where L is less than M.

[0101] Some aspects of this disclosure provide a method for operating a memory device, wherein converting data units further includes: determining that one of a plurality of data units matches a bit in the first column of a first table; and converting the data unit into a bit in the first column of a second table.

[0102] Some aspects of this disclosure provide methods for operating a memory device, wherein columns of a second table correspond to corresponding voltage levels.

[0103] Some aspects of this disclosure provide a method for operating a memory device, wherein storing data units in N data latches further includes storing the J-th bit of each data unit in the J-th data latch.

[0104] Some aspects of this disclosure provide a method for operating a memory device, wherein programming the cells of the memory device based on converted data units further includes: determining that one or more data units in the converted data units match a target column of a second table; determining a target voltage level corresponding to the target column; determining one or more cells in the memory device that correspond to the one or more data units; and applying the target voltage level to the one or more cells.

[0105] Some aspects of this disclosure provide a method for operating a memory device, the method further comprising verifying one or more cells by: determining that a set of rows of the target column of a second table contains “0” bits; determining one or more data units based on the set of rows; determining one or more cells based on the one or more data units; verifying that the voltage level of the one or more cells is higher than a voltage requirement; and converting one or more rows of the one or more data units into “1” bits based on the set of rows.

[0106] Some aspects of this disclosure provide a method for operating a memory device, the method further comprising: determining that the target column is the second column of a second table. N-1 +1 column; and release the Nth data latch of the memory device.

[0107] Some aspects of this disclosure provide a non-transitory computer-readable medium (CRM) including instructions that, when executed by one or more processors of a memory device, cause the memory device to perform operations including: receiving data comprising a plurality of data units, wherein each data unit comprises N bits; storing the data units in N data latches; converting the data units based on a first table and a second table; and programming cells of the memory device based on the converted data units. The first table and the second table comprise N rows and 2... N The position of the column, and in the Nth row of the second table from the 2nd... N -N+1 column to the 2nd N The columns have the same position. The second table also includes column L, which contains K numbers of "0"s in one or more rows. Column M of the second table contains one or more rows containing fewer than K numbers of 0, where L is less than M.

[0108] Some aspects of this disclosure provide the non-transient CRM, wherein converting data units further includes: determining that one of a plurality of data units matches a bit in the I-th column of a first table; and converting the data unit into a bit in the I-th column of a second table.

[0109] Some aspects of this disclosure provide for the non-transient CRM, wherein the columns of the second table correspond to the respective voltage levels.

[0110] Some aspects of this disclosure provide the non-transient CRM, wherein storing data units in N data latches further includes storing the J-th bit of each data unit in the J-th data latch.

[0111] Some aspects of this disclosure provide the non-transient CRM, wherein programming the cells of the memory device based on the converted data units further includes: determining that one or more data units in the converted data units match a target column of a second table; determining a target voltage level corresponding to the target column; determining one or more cells in the memory device corresponding to the one or more data units; and applying the target voltage level to the one or more cells.

[0112] Some aspects of this disclosure provide the non-transient CRM, wherein the operation further includes verifying one or more cells by: determining that a set of rows of the target column of the second table contains “0” bits; determining one or more data units based on the set of rows; determining one or more cells based on the one or more data units; verifying that the voltage level of one or more cells is higher than a voltage requirement; and converting one or more rows of one or more data units into “1” bits based on the set of rows.

[0113] Some aspects of this disclosure provide for this non-transient CRM, wherein the operation further includes: determining that the target column is the second column of the second table. N-1 +1 column; and release the Nth data latch of the memory device.

[0114] The summary and abstract sections may set forth one or more exemplary aspects of this disclosure as conceived by the inventors, but not all of them, and are therefore not intended to limit this disclosure and the appended claims in any way.

[0115] Although this disclosure has been described herein with reference to exemplary aspects for exemplary fields and applications, it should be understood that this disclosure is not limited thereto. Other aspects and modifications thereof are also possible and are within the scope and spirit of this disclosure. For example, without limiting the generality of this paragraph, the aspects are not limited to the software, hardware, firmware, and / or entities shown in the figures and / or described herein. Furthermore, the aspects (whether or not explicitly described herein) have significant utility for fields and applications beyond the examples described herein.

[0116] This document has described various aspects using functional building blocks that illustrate implementations of the specified functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined. Alternative boundaries can be defined, provided that the specified functions and relationships (or their equivalents) are performed appropriately. Furthermore, alternative aspects may use a different order of execution for functional blocks, steps, operations, methods, etc., than those described herein.

[0117] In this document, references to “an aspect,” “aspect,” “example aspect,” or similar phrases indicate that the described aspect may include a particular feature, structure, or characteristic, but not every aspect may include that particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same aspect. Moreover, when a particular feature, structure, or characteristic is described in conjunction with an aspect, incorporating such a feature, structure, or characteristic into other aspects (whether or not it is explicitly mentioned or described herein) is within the knowledge of one or more people skilled in the art.

[0118] The breadth and scope of this disclosure should not be limited by any of the exemplary aspects described above, but only by the following claims and their equivalents.

Claims

1. A memory device, comprising: N data latches are configured to store data; as well as The controller, coupled to the N data latches, is configured to: Receive data consisting of multiple data units, where each data unit consists of N bits; The data units are stored in the N data latches; The data units are converted based on the first and second tables; and The memory device cells are programmed based on the converted data units. The first table and the second table each contain N rows and 2... N The position of the column; In the second table, from row N, starting from row 2 N-1 +2 columns to the 2nd N The columns have the same position; In this table, one or more rows in column L contain K numbers of "0". Wherein, the row or more rows in the Mth column of the second table contain less than K "0"s. Where L and M are positive integers, L is less than M, and L is greater than or equal to 2. Where N is a positive integer greater than 2.

2. The memory device according to claim 1, wherein, In order to convert the data units, the controller is also configured to: Determine that one of the plurality of data units matches a bit in the I-th column of the first table; and Convert the data unit into the bit of the I column of the second table.

3. The memory device according to claim 1, wherein, The columns of the second table correspond to a set of corresponding voltage levels.

4. The memory device according to claim 1, wherein, In order to store the data units in the N data latches, the controller is further configured to: The J-th bit of each data unit in the data unit is stored in the J-th data latch.

5. The memory device according to claim 1, wherein, In order to program the cells of the memory device based on the converted data units, the controller is further configured to: Determine one or more data units among the transformed data units that match the target column of the second table; Determine the target voltage level corresponding to the target column; Determine one or more cells in the memory device that correspond to the one or more data units; as well as The one or more units are programmed to the target voltage level.

6. The memory device of claim 5, wherein, The controller is also configured to verify the one or more units, the controller being configured to: Determine that a set of rows in the target column of the second table contains "0" bits; The one or more data units are determined based on the set of rows; The one or more units are determined based on the one or more data units; Verify that the voltage level of one or more units is higher than the voltage requirement; as well as Based on the set of rows, convert one or more rows of the one or more data units into "1" bits.

7. The memory device according to claim 6, wherein, The controller is also configured to: determining that the target column is the 2 N-1 +1 column of the second table; and Release the Nth data latch of the memory device.

8. A method for operating a memory device, comprising: Receive data consisting of multiple data units, where each data unit consists of N bits; The data units are stored in N data latches; The data units are converted based on the first and second tables; and The memory device cells are programmed based on the converted data units. wherein the first table and the second table include N rows and 2 N columns of bits; wherein the bits in the 2nd N-1 column to the 2nd N column of the Nth row of the second table are identical; In this table, one or more rows in column L contain K numbers of "0". Wherein, the row or more rows in the Mth column of the second table contain less than K "0"s. Where L and M are positive integers, L is less than M, and L is greater than or equal to 2. Where N is a positive integer greater than 2.

9. The method of claim 8, wherein, Converting the data units also includes: Determine that one of the plurality of data units matches a bit in the I-th column of the first table; and Convert the data unit into the bit of the I column of the second table.

10. The method of claim 8, wherein, The columns of the second table correspond to a set of voltage levels.

11. The method of claim 8, wherein, Storing the data units in the N data latches also includes: The J-th bit of each data unit in the data unit is stored in the J-th data latch.

12. The method of claim 8, wherein, Programming the cells of the memory device based on the converted data units further includes: Determine one or more data units among the transformed data units that match the target column of the second table; Determine the target voltage level corresponding to the target column; Determine one or more cells in the memory device that correspond to the one or more data units; and The one or more units are programmed to the target voltage level.

13. The method of claim 12, further comprising verifying the one or more units by: Determine that a set of rows in the target column of the second table contains "0" bits; The one or more data units are determined based on the set of rows; The one or more units are determined based on the one or more data units; Verify that the voltage level of one or more units is higher than the voltage requirement; as well as Based on the set of rows, convert one or more rows of the one or more data units into "1" bits.

14. The method of claim 13, further comprising: determining that the target column is the 2 N-1 +1 column; as well as Release the Nth data latch of the memory device.

15. A non-transitory computer-readable medium (CRM) including instructions that, when executed by one or more processors of a memory device, cause the memory device to perform operations, the operations including: Receive data consisting of multiple data units, where each data unit consists of N bits; The data units are stored in N data latches; The data units are converted based on the first and second tables; and The memory device cells are programmed based on the converted data units. The first table and the second table each contain N rows and 2... N The position of the column; In the second table, from row N, starting from row 2 N-1 +2 columns to the 2nd N The columns have the same position; In this table, one or more rows in column L contain K numbers of "0". Wherein, the row or more rows in the Mth column of the second table contain less than K "0"s. Where L and M are positive integers, L is less than M, and L is greater than or equal to 2. Where N is a positive integer greater than 2.

16. The non-transitory computer-readable medium according to claim 15, wherein, Converting the data units also includes: Determine that one of the plurality of data units matches a bit in the I-th column of the first table; and Convert the data unit into the bit of the I column of the second table.

17. The non-transitory computer-readable medium according to claim 15, wherein, Storing the data units in the N data latches also includes: The J-th bit of each data unit in the data unit is stored in the J-th data latch.

18. The non-transitory computer-readable medium according to claim 15, wherein, Programming the cells of the memory device based on the converted data units further includes: Determine one or more data units among the transformed data units that match the target column of the second table; Determine the target voltage level corresponding to the target column; Determine one or more cells in the memory device that correspond to the one or more data units; and The one or more units are programmed to the target voltage level.

19. The non-transitory computer-readable medium according to claim 18, wherein, The operation also includes verifying the one or more units through the following operations: Determine that a set of rows in the target column of the second table contains "0" bits; The one or more data units are determined based on the set of rows; The one or more units are determined based on the one or more data units; Verify that the voltage level of one or more units is higher than a threshold. as well as Based on the set of rows, convert one or more rows of the one or more data units into "1" bits.

20. The non-transitory computer-readable medium according to claim 19, wherein, The operation also includes: The target column is determined to be the second column of the second table. N-1 +1 column; and Release the Nth data latch of the memory device.

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