A chip packaging method and a packaged chip

Abstract

This application discloses a chip packaging method and a packaged chip. The chip packaging method includes: providing a carrier board and a chip; wherein, one side surface of the chip is provided with chip pads; attaching the side surface of the chip away from the chip pads to at least one side surface of the carrier board; performing a primary encapsulation of the chip using a molding compound, exposing the chip pads; forming a first copper layer on the surface of the chip pads; performing a secondary encapsulation of the chip using a molding compound, exposing the first copper layer; and forming fan-out pads on the surface of the first copper layer to complete the chip packaging. This method reduces damage to the chip pads.

Description

Technical Field

[0001] This application relates to the field of circuit board technology, and in particular to a chip packaging method and a packaged chip. Background Technology

[0002] As electronic devices become increasingly integrated, the semiconductor packaging field has proposed System-in-Package (SIP), a technology that encapsulates the chip and substrate together.

[0003] As electronic products become smaller, more integrated, and more widespread, the chips used inside these products are also becoming smaller. FOPLP (Fan-Out Package) technology, as an advanced packaging method, is being widely used in chip packaging.

[0004] However, the current FOPLP packaging technology still involves packaging the chip as a whole board, then slotting the chip pads to expose them, and then creating pins on the surface of the chip pads to bring them out. This method of packaging the chip can easily damage the pads on the chip surface and is not conducive to the soldering of small chips and small pads. The alignment requirements of the chip pads are very high during the soldering process. Summary of the Invention

[0005] This application proposes a chip packaging method and a packaged chip to reduce damage to the chip pads.

[0006] To address the aforementioned technical problems, this application provides a chip packaging method, the packaging method comprising:

[0007] A carrier board and a chip are provided; wherein, one side surface of the chip is provided with chip pads; the side surface of the chip away from the chip pads is attached to at least one side surface of the carrier board; the chip is encapsulated using molding compound, exposing the chip pads; a first copper layer is formed on the surface of the chip pads; the chip is encapsulated using molding compound again, exposing the first copper layer; fan-out pads are formed on the surface of the first copper layer to complete the encapsulation of the chip.

[0008] Preferably, the step of forming a first copper layer on the surface of the chip pad includes: electroplating the first copper layer on the molding compound and the surface of the chip pad using a full-board electroplating process; and etching the first copper layer using a pattern etching process to retain the first copper layer on the surface of the chip pad.

[0009] Preferably, the step of forming a fan-out pad on the surface of the first copper layer includes: electroplating a second copper layer on the molding compound and the surface of the first copper layer using a full-board electroplating process; and etching the second copper layer using a pattern etching process, retaining the surface of the first copper layer and the surrounding second copper layer to form the fan-out pad.

[0010] Preferably, the thickness of the first copper layer is 20 micrometers and the thickness of the second copper layer is 35 micrometers.

[0011] Preferably, the step of encapsulating the chip with molding compound and exposing the chip pads includes: filling the surface of the chip with molding compound to form a first molding layer at the same height as the chip pads, so that the chip pads are exposed.

[0012] Preferably, the step of using molding compound to perform secondary encapsulation of the chip and expose the first copper layer includes: using the molding compound to perform secondary filling of the chip and forming a second molding layer with the same height as the first copper layer, so that the first copper layer is exposed.

[0013] Preferably, before the step of attaching the side surface of the chip away from the chip pads to at least one side surface of the carrier board, the method includes: laminating a copper foil layer on the surface of the carrier board; wherein the copper foil layer has a thickness of 1 ounce; the step of attaching the side surface of the chip away from the chip pads to at least one side surface of the carrier board includes: soldering the chip to the copper foil layer on the surface of the carrier board using silver paste.

[0014] Preferably, the step of attaching the side surface of the chip away from the chip pad to at least one side surface of the carrier includes: attaching the chip to opposite sides of the carrier respectively; after the step of creating fan-out pads on the chip pad surface to complete the chip packaging, the step includes: separating the carrier from the middle using a board separation process to form two packaged chips.

[0015] To address the aforementioned technical problems, this application provides a packaged chip, comprising: a carrier board; a chip, one side surface of which is provided with chip pads, and the side surface of the chip away from the chip pads being soldered to at least one side surface of the carrier board; a first molding compound layer covering the surface of the chip and exposing the chip pads; a second molding compound layer covering the surface of the first molding compound layer; and fan-out pads, including a first copper layer and a second copper layer, the first copper layer covering the surface of the chip pads and the second copper layer covering the surface of the first copper layer.

[0016] Preferably, the second copper layer covers the surface of the first copper layer and a portion of the surface of the second molding layer.

[0017] The beneficial effects of this application are as follows: by attaching the side of the chip away from the chip pad to the surface of the carrier board, the chip is encapsulated once using molding compound to expose the chip pad, and a first copper layer is formed on the surface of the chip pad. The chip is then encapsulated a second time using molding compound to expose the first copper layer, and fan-out pads are formed on the surface of the first copper layer to complete the chip encapsulation. The chip pads on the chip surface are transferred to the surface of the encapsulation component through the fan-out pads, thereby leading out the chip pads. This avoids damage to the chip pads caused by slotting the chip pad surface through windowing / slotting processes, and is beneficial for the fabrication of small chips and small pads. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic flowchart of an embodiment of the chip packaging method of this application;

[0020] Figure 2 This is a flowchart illustrating another embodiment of the chip packaging method of this application;

[0021] Figure 3a This is a schematic diagram of the structure of one embodiment of the carrier plate of this application;

[0022] Figure 3b for Figure 2 S22 is a structural schematic diagram of an embodiment;

[0023] Figure 3c for Figure 2 S23 is a structural schematic diagram of an embodiment;

[0024] Figure 3d for Figure 2 S24 is a structural schematic diagram of one embodiment;

[0025] Figure 3e for Figure 2 A schematic diagram of the structure of embodiment S25;

[0026] Figure 3f for Figure 2 S26 is a structural schematic diagram of an embodiment;

[0027] Figure 3g for Figure 2 S27 is a structural schematic diagram of one embodiment;

[0028] Figure 3h for Figure 2 S28 is a structural schematic diagram of one embodiment;

[0029] Figure 4 This is a schematic diagram of the structure of a packaged chip according to an embodiment of this application;

[0030] Figure 5 This is a schematic diagram of another embodiment of the packaged chip in this application. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0032] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the application. The singular forms “a,” “said,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless otherwise clearly indicated above. “Multiple” generally includes at least two, but does not exclude the inclusion of at least one.

[0033] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0034] It should be understood that the terms "comprising," "including," or any other variations used herein are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0035] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0036] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in every place in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0037] This application provides a chip packaging method; please refer to [link / reference]. Figure 1 , Figure 1 This is a schematic flowchart of an embodiment of the chip packaging method of this application. Figure 1 As shown, the chip packaging method includes:

[0038] S11: Provides carrier board and chip.

[0039] In this embodiment, the carrier board is a PCB board. Specifically, the carrier board is manufactured using the FOPLP process, and the internal copper thickness variation of the carrier board is relatively small.

[0040] In this embodiment, the chip is a diode. The chip's pads are disposed on a single layer of the chip's surface. For example, the chip surface may include two chip pads located on the same side of the chip's surface.

[0041] S12: Attach the side of the chip away from the chip pads to at least one side of the carrier board.

[0042] In one embodiment, a chip is attached to one side surface of a carrier board. In another embodiment, two chips are attached to opposite sides of the carrier board, and the chips on opposite sides of the carrier board are encapsulated simultaneously.

[0043] The process preceding S12 includes: laminating a copper foil layer onto the surface of a carrier board; and then attaching a chip to the surface of the copper foil layer. Specifically, the chip is soldered to the copper foil layer on the surface of the carrier board using silver paste. In this embodiment, the thickness of the copper foil layer is 1 ounce.

[0044] S13: The chip is encapsulated using molding compound, exposing the chip pads on the chip surface.

[0045] Specifically, a molding compound is used to fill the surface of the chip, forming a first molding layer at the same height as the chip pads, thus exposing the chip pads on the chip surface. The chip surface includes the four peripheral surfaces of the chip. In this embodiment, the periphery of the chip is encapsulated first to cover all surfaces of the chip, exposing only the chip pads on the chip surface.

[0046] Compared to traditional windowing / grooving processes that can easily damage the chip by creating grooves on the chip pad surface and are unsuitable for fabricating small chips with small pads (as the pads are small and easily drilled through during the grooving process, leading to chip damage), this embodiment reduces the risk of chip pad damage caused by grooving by filling the chip surface with molding compound to form a molding layer at the same height as the chip pads, thus exposing the chip pads on the chip surface.

[0047] S14: Create the first copper layer on the surface of the chip pad.

[0048] In this embodiment, the thickness of the first copper layer is 20 micrometers. In other embodiments, the thickness of the first copper layer can also be designed according to actual needs, and is not limited here.

[0049] Specifically, this includes: electroplating a first copper layer on the surface of the molding compound and the chip pads using a full-board electroplating process, wherein the first copper layer covers the entire surface of the molding compound and the chip pads; and then etching the first copper layer covering the surface of the molding compound using a pattern etching process, while retaining the first copper layer on the surface of the chip pads.

[0050] S15: The chip is repackaged using molding compound, exposing the first copper layer.

[0051] Specifically, a second molding compound is used to fill the surface and surrounding area of ​​the chip to form a second molding layer with the same height as the first copper layer, exposing the first copper layer on the surface of the chip pads.

[0052] In this embodiment, the chip is encapsulated a second time to thicken the encapsulation layer on the chip surface, making the chip encapsulation more robust.

[0053] S16: Create fan-out pads on the surface of the first copper layer to complete the chip packaging.

[0054] Specifically, this involves: electroplating a second copper layer onto the surfaces of the molding compound and the first copper layer using a full-board electroplating process. The second copper layer covers both the surface of the molding compound and the surface of the first copper layer. Then, a pattern etching process is used to etch the second copper layer, retaining the second copper layer on the surface of the first copper layer and the surrounding surface of the molding compound, thus forming a fan-out pad. In this embodiment, the fan-out pad covers the surface of the first copper layer and part of the surface of the molding compound. In other embodiments, the fan-out pad may only cover the surface of the first copper layer. In this embodiment, the fan-out pad covers the first copper layer and part of the surrounding surface of the molding compound, which provides better sealing of the chip.

[0055] In this embodiment, the thickness of the second copper layer can be 35 micrometers. In other embodiments, the thickness of the second copper layer can be set according to actual needs.

[0056] The beneficial effects of this embodiment are as follows: by attaching the side of the chip away from the chip pad to the surface of the carrier board, the chip is encapsulated once using molding compound to expose the chip pad, and a first copper layer is formed on the surface of the chip pad. The chip is then encapsulated a second time using molding compound to expose the first copper layer, and fan-out pads are formed on the surface of the first copper layer to complete the chip encapsulation. The chip pads on the chip surface are transferred to the surface of the encapsulation component through the fan-out pads, thereby leading out the chip pads. This avoids damage to the chip pads caused by slotting the chip pad surface through windowing / slotting processes, and is beneficial for the fabrication of small chips and small pads.

[0057] This application also provides another chip packaging method; please refer to [link / reference]. Figure 2 , Figure 2 This is a flowchart illustrating another embodiment of the chip packaging method of this application. Figure 2 As shown, the chip packaging method includes:

[0058] S21: Provides carrier board and chip.

[0059] In this embodiment, the chip is a diode, and chip pads are provided on one side of the chip surface. The carrier board is a PCB board, and the copper thickness difference inside the carrier board is small.

[0060] Specifically, please refer to Figure 3a , Figure 3a This is a schematic diagram of the structure of one embodiment of the carrier plate of this application. Figure 3a As shown, the carrier board includes an intermediate dielectric layer 31, and a first resin layer 32, an inner copper layer 33, and a second resin layer 34 are respectively formed on opposite sides of the intermediate dielectric layer 31.

[0061] S22: A copper foil layer is laminated onto the opposite two surfaces of the carrier board.

[0062] In this embodiment, the thickness of the copper foil layer is 1 ounce. In other embodiments, the thickness of the copper foil layer can be set according to actual needs.

[0063] Specifically, please refer to Figure 3b , Figure 3b for Figure 2 A structural schematic diagram of embodiment S22. (See diagram below.) Figure 3b As shown, the copper foil layer 35 covers a portion of the surface of the second resin layer 34. In this embodiment, the area of ​​the copper foil layer 35 is the same as the bottom area of ​​one side of the chip, that is, the size of the copper foil layer 35 is set according to the size of the chip. In other embodiments, the area of ​​the copper foil layer 35 may also be larger than the bottom area of ​​the chip.

[0064] S23: Use silver paste to solder chips onto the surface of the copper foil layer.

[0065] Specifically, the side of the chip furthest from the chip pads is soldered to the copper foil layer surface of the carrier board.

[0066] Please refer to further information. Figure 3c , Figure 3c for Figure 2 A structural schematic diagram of embodiment S23. (See diagram below.) Figure 3c As shown, a layer of silver paste 36 covers the surface of the copper foil layer 35. One side of the chip 37 is soldered to the surface of the copper foil layer 35 through the silver paste 36. Chip pads 371 are provided on the side of the chip 37 away from the carrier board. In this embodiment, the chip 37 includes two chip pads 371, which are located on the same side of the chip 37 and away from the carrier board.

[0067] S24: The chip is encapsulated using molding compound, exposing the chip pads.

[0068] Specifically, molding compound is used to fill the surface of the chip to form a first molding layer that is the same height as the chip pads on the chip surface, and the chip pads are exposed.

[0069] This invention also includes using a desmearing process to remove the molding compound on and around the chip pad surface, in order to avoid residual molding compound on the chip pad surface, which could affect the electroplated copper layer on the chip pad surface.

[0070] Please refer to further information. Figure 3d , Figure 3d for Figure 2 A structural schematic diagram of one embodiment of S24. (See diagram below.) Figure 3d As shown, the first molding compound 381 covers the entire surface of the chip 37 except for the chip pads 371 on the surface of the chip 37, and the first molding compound 381 is at the same height as the chip pads 371, that is, the thickness of the first molding compound 381 is the same as the height of the chip pads 371 protruding from the surface of the chip 37.

[0071] S25: Create the first copper layer on the surface of the chip pad.

[0072] This process includes: electroplating a first copper layer on the surface of the first molding compound and the chip pads using a full-board electroplating process; then etching the first copper layer covering the molding compound surface using a pattern etching process, while retaining the first copper layer on the chip pad surface. The thickness of the first copper layer is controlled to be approximately 20 micrometers. In other embodiments, the thickness of the first copper layer can be designed according to the electrical performance requirements of different products.

[0073] Specifically, please refer to Figure 3e , Figure 3e for Figure 2 A structural schematic diagram of one embodiment of S25. (See diagram below.) Figure 3eAs shown, a first copper layer 391 is formed on the surface of the chip pad 371. In this embodiment, the first copper layer 391 covers a portion of the surface of the chip pad 371. In another embodiment, the first copper layer 391 covers the entire surface of the chip pad 371, which is not limited here.

[0074] S26: The chip is repackaged using molding compound, exposing the first copper layer.

[0075] Specifically, a second molding compound is used to fill the surface and surrounding area of ​​the chip to form a second molding layer with the same height as the first copper layer, exposing the first copper layer on the surface of the chip pads.

[0076] Please refer to further information. Figure 3f , Figure 3f for Figure 2 A structural schematic diagram of an embodiment of S26. (See diagram below.) Figure 3f As shown, the second molding layer 382 covers the surface of the first molding layer 381 and part of the chip pad 371, exposing only the first copper layer 391, and the thickness of the second molding layer 382 is the same as the thickness of the first copper layer 391.

[0077] S27: Create fan-out pads on the surface of the first copper layer.

[0078] Specifically, this involves: using a full-board electroplating process to electroplat a second copper layer on the surface of the molding compound and the first copper layer, and then using a pattern etching process to etch the second copper layer, retaining the second copper layer on the surface of the first copper layer and the surrounding surface of the molding compound to form fan-out pads.

[0079] In this embodiment, the fan-out pad is a portion of the second copper layer, and the fan-out pad covers the surface of the first copper layer and a portion of the second molding compound.

[0080] Specifically, please refer to Figure 3g , Figure 3g for Figure 2 A structural schematic diagram of one embodiment of S27. (See diagram below.) Figure 3g As shown, the fan-out pad 392 covers the entire surface of the first copper layer 391 and a portion of the surface of the second molding compound 382 surrounding the first copper layer 391.

[0081] S28: The carrier board is separated from the middle using a splitting process to form two packaged chips.

[0082] The carrier board is separated using a splitting process to form two identical packaged chips.

[0083] This also includes: applying ink to the surface of the separated carrier plate away from the chip.

[0084] Specifically, please refer to Figure 3h , Figure 3hfor Figure 2 A structural schematic diagram of embodiment S28. (See diagram below.) Figure 3h As shown, the intermediate dielectric layer 31 of the carrier board is cut and separated, and ink is applied to the separated intermediate dielectric layer 31 to obtain two packaged chips containing the chip.

[0085] The beneficial effects of this embodiment are: by processing chips on two opposite sides of the carrier board respectively, two separate packaged chips are obtained, which improves the efficiency of chip packaging and also makes mass production of chip packaging possible.

[0086] This application also provides a packaged chip; please refer to further details. Figure 4 , Figure 4 This is a schematic diagram of the structure of a packaged chip according to an embodiment of this application. Figure 4 As shown, the packaged chip includes: a carrier board 41, a chip 42 soldered to one side surface of the carrier board 41, and a chip pad 401 disposed on the side surface of the chip 42 away from the carrier board 41; a first molding compound 43 covering the surface of the chip 42 and exposing the chip pad 401; a second molding compound 44 covering the surface of the first molding compound 43; and a fan-out pad 45 including a first copper layer 451 and a second copper layer 452, the first copper layer 451 covering the chip pad 401 on the surface of the chip 42, and the second copper layer 452 covering the surface of the first copper layer 451.

[0087] In this embodiment, the second copper layer 452 and the first copper layer 451 have the same area. In this embodiment, the area of ​​the first copper layer 451 is the same as the area of ​​the chip pad 401, or it may be smaller than the area of ​​the chip pad 401.

[0088] In this embodiment, the second molding layer 44 also covers a portion of the surface of the chip pad 401.

[0089] In this embodiment, a copper foil layer 46 and a silver paste layer 47 are also provided between the carrier board 41 and the chip 42 for soldering the chip 42 to the carrier board 41.

[0090] In this embodiment, the carrier board 41 is a PCB board, and the chip 42 is a diode.

[0091] The beneficial effects of this embodiment are: by encapsulating the chip surface with the first molding layer and the second molding layer and exposing the chip pads on the chip surface, it is convenient to make fan-out pads and connect them to the chip pads, thereby leading out the chip pads, avoiding damage to the chip pads, and protecting the chip pads to the greatest extent.

[0092] This application also provides another packaged chip; please refer to [link / reference needed]. Figure 5 , Figure 5 This is a schematic diagram of another embodiment of the packaged chip in this application. Figure 5As shown, the packaged chip includes: a carrier board 51, a chip 52 soldered to one side surface of the carrier board 51, and a chip pad 501 disposed on the side surface of the chip 52 away from the carrier board 51; a first molding compound 53 covering the surface of the chip 52 and exposing the chip pad 501; a second molding compound 55 covering the surface of the first molding compound 53; and a fan-out pad 55 including a first copper layer 551 and a second copper layer 552, the first copper layer 551 covering the chip pad 501 on the surface of the chip 52, and the second copper layer 552 covering the surface of the first copper layer 551.

[0093] In this embodiment, the first copper layer 551 covers a portion of the surface of the chip pad 501, and the second molding layer covers another portion of the surface of the chip pad 501.

[0094] In this embodiment, the second copper layer 552 also covers a portion of the surface of the second molding compound 55 to better seal the chip 52 and bring out the chip pads 501 on the surface of the chip 52. The area of ​​the second copper layer 552 can be larger than or equal to the chip pads 501.

[0095] The beneficial effects of this embodiment are: by encapsulating the chip surface with the first molding layer and the second molding layer and exposing the chip pads on the chip surface, it is convenient to make fan-out pads. Thus, the chip and chip pads are encapsulated, and damage to the chip pads is avoided. This maximizes the protection of the chip pads and is beneficial for the encapsulation of small chips.

[0096] The above description is merely an embodiment of this application and does not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A chip packaging method, characterized in that, The encapsulation method includes: A carrier board and a chip are provided; wherein, one side surface of the chip is provided with chip pads protruding from the chip surface; The surface of the chip furthest from the chip pads is attached to at least one surface of the carrier board; The chip surface, excluding the chip pads, is filled with molding compound to form a first molding layer of the same height as the chip pads, directly exposing the chip pads. A first copper layer is formed on the surface of the exposed chip pads; The molding compound is used to fill the surface of the chip, except for the first copper layer, to form a second molding layer with the same height as the first copper layer, and the first copper layer is directly exposed. Fan-out pads are fabricated on the exposed surface of the first copper layer to complete the encapsulation of the chip.

2. The chip packaging method according to claim 1, characterized in that, The step of creating a first copper layer on the exposed surface of the chip pads includes: The first copper layer is electroplated onto the surfaces of the molding compound and the chip pads using a full-board electroplating process. The first copper layer is etched using a pattern etching process, retaining the first copper layer on the surface of the chip pads.

3. The chip packaging method according to claim 2, characterized in that, The step of creating fan-out pads on the exposed surface of the first copper layer includes: A second copper layer is electroplated onto the molding compound and the first copper layer using a full-board electroplating process; The second copper layer is etched using a pattern etching process, retaining the surface of the first copper layer and the surrounding second copper layer to form the fan-out pad.

4. The chip packaging method according to claim 3, characterized in that, The thickness of the first copper layer is 20 micrometers, and the thickness of the second copper layer is 35 micrometers.

5. The chip packaging method according to claim 1, characterized in that, Prior to the step of attaching the side surface of the chip away from the chip pads to at least one side surface of the carrier board, the method includes: A copper foil layer is laminated onto the surface of the carrier plate; wherein the copper foil layer has a thickness of 1 ounce; The step of attaching the side surface of the chip away from the chip pads to at least one side surface of the carrier board includes: The chip is soldered onto the copper foil layer on the surface of the carrier board using silver paste.

6. The chip packaging method according to claim 1, characterized in that, The step of attaching the side surface of the chip away from the chip pads to at least one side surface of the carrier board includes: The chips are attached to opposite sides of the carrier plate. After creating fan-out pads on the exposed surface of the first copper layer to complete the chip packaging, the process includes: The carrier board is separated from the middle using a splitting process to form two packaged chips.

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