Semiconductor structure and method of forming the same

Abstract

Semiconductor structures and methods of forming semiconductor structures are provided. A method includes receiving a semiconductor substrate having a first region and a second region; forming a dielectric layer over the semiconductor substrate; removing portions of the dielectric layer to form a dielectric structure in the first region, wherein the dielectric structure includes a base structure and a plurality of first isolation structures located over the base structure; forming a semiconductor layer covering the first region and the second region; removing portions of the semiconductor layer to expose top surfaces of the plurality of first isolation structures; and forming a plurality of second isolation structures in the second region.

Description

Technical Field

[0001] The embodiments of the present invention relate to semiconductor structures and methods for forming the same. Background Technology

[0002] Electronic devices involving semiconductor devices are essential for many modern applications. Technological advancements in materials and design have resulted in generations of semiconductor devices, each with smaller and more complex circuitry than the previous generation. The demand for higher-performance circuitry has driven the development of silicon-on-insulator (SOI) technology. In SOI, metal-oxide-semiconductor field-effect transistors (MOSFETs) are formed on an active layer placed above an insulating material layer. Devices formed on SOI offer many advantages over their bulk counterparts, including reduced junction capacitance and full dielectric isolation. However, challenges remain in improving device performance and reducing manufacturing costs. Summary of the Invention

[0003] Some embodiments of the present invention provide a method for forming a semiconductor structure, comprising: receiving a semiconductor substrate having a first region and a second region; forming a dielectric layer over the semiconductor substrate; removing a portion of the dielectric layer to form a dielectric structure in the first region, wherein the dielectric structure includes a substrate structure and a plurality of first isolation structures located over the substrate structure; forming a semiconductor layer covering the first region and the second region; removing a portion of the semiconductor layer to expose the top surfaces of the plurality of first isolation structures; and forming a plurality of second isolation structures in the second region.

[0004] Other embodiments of the present invention provide a method for forming a semiconductor structure, comprising: receiving a semiconductor substrate having a plurality of first regions and a plurality of second regions; forming a dielectric layer over the semiconductor substrate, wherein the dielectric layer has a first thickness; removing a portion of the dielectric layer to form a dielectric structure in the first regions, wherein the dielectric structure includes a substrate structure and a plurality of first isolation structures located over the substrate structure, the substrate structure having a second thickness, the plurality of first isolation structures having a first height, and the first thickness being substantially equal to the sum of the second thickness and the first height; forming a semiconductor layer over the semiconductor substrate; removing a portion of the semiconductor layer to expose the top surfaces of the plurality of first isolation structures; and forming a first transistor in at least one of the plurality of first regions and forming a second transistor in at least one of the plurality of second regions, wherein the first transistor and the second transistor are separated by at least one of the plurality of first isolation structures.

[0005] Further embodiments of the present invention provide a semiconductor structure comprising: a semiconductor substrate having a first region and a second region; a first semiconductor layer located above the semiconductor substrate and in the first region; a dielectric structure located above the semiconductor substrate and in the second region, the dielectric structure having a first upper boundary below the upper surface of the first semiconductor layer, wherein the dielectric structure has a first portion extending along a first direction and a second portion extending along a second direction, and the first portion and the second portion are interconnected; a second semiconductor layer located above the first portion of the dielectric structure; a first transistor located above the first semiconductor layer and in the first region; and a second transistor located above the second semiconductor layer and in the second region. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, aspects of embodiments of the invention will be best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the various structures are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various structures may be arbitrarily increased or decreased.

[0007] Figure 1 This is a flowchart illustrating a method 100 for forming a semiconductor structure according to one or more embodiments of the present invention.

[0008] Figures 2A to 2N This is a cross-sectional view illustrating semiconductor structures created at different manufacturing stages according to one or more embodiments of the present invention.

[0009] Figures 3A to 3C This is a cross-sectional view illustrating semiconductor structures created at different manufacturing stages according to one or more embodiments of the present invention.

[0010] Figures 4A to 4F This is a cross-sectional view showing a semiconductor structure 300 at different manufacturing stages created according to one or more embodiments of the present invention.

[0011] Figures 5A to 5C This is a cross-sectional view illustrating semiconductor structures created at different manufacturing stages according to one or more embodiments of the present invention.

[0012] Figure 6 This is a flowchart illustrating a method for forming a semiconductor structure according to one or more embodiments of the present invention.

[0013] Figures 7A to 7F This is a schematic cross-sectional view illustrating a semiconductor structure at different manufacturing stages created according to one or more embodiments of the present invention. Detailed Implementation

[0014] The following disclosure provides numerous embodiments or instances of different components for implementing the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include instances where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various embodiments. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0016] As used herein, although terms such as “first,” “second,” and “third” describe individual elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Unless the context clearly indicates otherwise, terms such as “first,” “second,” and “third” as used herein do not imply order or sequence.

[0017] While the numerical ranges and parameters illustrating the broad scope of the invention are approximate, the values ​​described in specific examples are reported as precisely as possible. However, any numerical value inherently contains some error, which is necessarily due to the standard deviation found in the corresponding test measurements. Furthermore, as used herein, the terms “substantially,” “approximately,” or “about” generally refer to values ​​or ranges that can be considered by one of ordinary skill in the art. Alternatively, when considered by one of ordinary skill in the art, the terms “substantially,” “approximately,” or “about” mean within an acceptable standard error of the average. One of ordinary skill in the art will understand that acceptable standard errors can vary depending on the technology. Except in operational / working examples, or unless expressly stated otherwise, all numerical ranges, quantities, values, and percentages disclosed herein, such as material quantities, durations, temperatures, operating conditions, ratios of quantities, etc., should be understood to be modified in all cases by the terms “substantially,” “approximately,” or “about.” Therefore, unless indicated to the contrary, the numerical parameters set forth in the invention and the appended claims are approximate values ​​that can vary as needed. At a minimum, each numerical parameter should be interpreted according to the number of significant figures reported and by applying ordinary rounding techniques. In this document, a range can be expressed from one endpoint to another or between two endpoints. Unless otherwise stated, all ranges disclosed herein include the endpoints.

[0018] Techniques have been developed for fabricating MOS devices on hybrid substrates (or composite substrates). Such substrates can have multiple device regions independently optimized for different devices. The hybrid substrate may include a first device region having a bulk substrate and a second device region having an SOI substrate. Optionally, the hybrid substrate may include a thick active layer located in the first device region and a thin active layer located in the second device region, situated above an insulating layer.

[0019] The isolation structures (or isolation regions) for different devices formed in different regions are designed to have different heights. Many problems encountered in MOS manufacturing involve forming isolation structures of different heights in different regions. For example, methods involving the formation of isolation structures suffer from yield losses. Therefore, the alternative method of forming isolation structures on a hybrid substrate is advantageous.

[0020] Some embodiments of the present invention provide semiconductor structures and methods for forming the same. In some embodiments, the method includes forming isolation structures of different heights in different regions in separate operations. In some embodiments, the method includes defining different portions of a dielectric structure in separate steps. Therefore, greater packaging density and lower manufacturing costs can be achieved. Furthermore, better dielectric isolation and lower leakage can be achieved.

[0021] Figure 1This is a flowchart illustrating a method 100 for forming a semiconductor structure according to one or more embodiments of the present invention. The method 100 for forming a semiconductor structure includes operation 102, in which a semiconductor substrate is received. In some embodiments, the semiconductor substrate has a first region and a second region. The method 100 further includes operation 104, in which a dielectric layer is formed over the semiconductor substrate. The method 100 further includes operation 106, in which a portion of the dielectric layer is removed to form a dielectric structure in the first region. In some embodiments, the dielectric structure includes a substrate structure and a plurality of first isolation structures located over the substrate structure. The method 100 further includes operation 108, in which a semiconductor layer covering the first and second regions is formed. The method 100 further includes operation 110, in which a portion of the semiconductor layer is removed to expose the top surfaces of the plurality of first isolation structures. The method 100 further includes operation 112, in which a plurality of second isolation structures are formed in the second region.

[0022] The method is described for the purpose of illustrating the concept of the invention, and this description is not intended to limit the invention beyond what is expressly stated in the claims. It can be applied above and... Figure 1 Additional operations are provided before, during, and after the method shown, and some of the described operations can be replaced, eliminated, or moved for additional embodiments of the method.

[0023] Figures 2A to 2N This is a cross-sectional view showing a semiconductor structure 200 at different manufacturing stages created according to one or more embodiments of the present invention.

[0024] refer to Figure 2A , to receive or form a semiconductor substrate 202. Figure 1 Operation 102 of method 100 illustrates the corresponding steps. The semiconductor substrate 202 can be a semiconductor wafer such as a silicon wafer. The semiconductor substrate 202 can include elemental semiconductor materials, compound semiconductor materials, or alloy semiconductor materials. Examples of elemental semiconductor materials can be, for example, but not limited to, single-crystal silicon, polycrystalline silicon, amorphous silicon, and / or germanium (Ge). Examples of compound semiconductor materials can be, for example, but not limited to, silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb). Examples of alloy semiconductor materials can be, for example, but not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP. In an optional embodiment, the semiconductor substrate 202 can be a glass substrate. In other embodiments, the semiconductor substrate 202 can be a multilayer substrate, a gradient substrate, or a mixed-orientation substrate.

[0025] The semiconductor substrate 202 may include various device regions. In some embodiments, the semiconductor substrate 202 includes one or more first regions 202a and one or more second regions 202b. The first regions 202a and the second regions 202b may be used to accommodate different devices. For example, the first region 202a is a radio frequency (RF) region in which a first transistor 250 will be formed (see...). Figure 2L The second region 202b is a logic region in which the second transistor 260 will be formed (see...). Figure 2L In some embodiments, at least one first region 202a is disposed between two adjacent second regions 202b. In some embodiments, at least one second region 202b is disposed between two adjacent first regions 202a. The arrangement of the first regions 202a and the second regions 202b can be designed according to different product requirements.

[0026] Still referencing Figure 2A A dielectric layer 204 is formed on top of the semiconductor substrate 202. Figure 1 Operation 104 of method 100 illustrates the corresponding steps. The dielectric layer 204 may comprise any suitable insulating material. In some embodiments, the dielectric layer 204 may comprise a semiconductor oxide layer. The dielectric layer 204 may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. In some embodiments, the thickness T1 of the dielectric layer 204 is substantially in the range from about 200 nanometers (nm) to about 400 nanometers.

[0027] Figures 2B to 2C The formation of one or more dielectric structures 216 is shown. (Reference) Figure 2B and Figure 2C Remove part of the dielectric layer 204 ( Figure 2A Dielectric structure 216 is formed in the first region 202a. Figure 1 Operation 106 of method 100 shows the corresponding steps.

[0028] refer to Figure 2B Etching dielectric layer 204 ( Figure 2A One or more isolation structures 210 are formed in the first region 202a. In some embodiments, a hard mask layer 206 is formed over the dielectric layer 204, and then the hard mask layer 206 is patterned with patterned photoresist (not shown) to form openings that expose portions of the dielectric layer 204. The exposed portions of the dielectric layer 204 are etched through the openings of the patterned hard mask layer 206 to form one or more recesses 208. The remaining portion of the dielectric layer 204 may include a base 212 and isolation structures 210. Etching can be performed by a dry etching process using an etching gas. Etching can also be performed by a wet etching process using an etching solution. The etching process can be tailored to meet the requirements of the resulting transistor or device.

[0029] The depth of the recess 208 is approximately equal to the height H1 of the isolation structure 210. The isolation structure 210 can be configured as the first transistor 250 to be formed (see...). Figure 2L Shallow trench isolation (STI). Select the height H1 and width W of the isolation structure 210. I This allows the isolation structure 210 to satisfy the first transistor 250 ( Figure 2L The requirements are as follows. In some embodiments, the height H1 and width W of the isolation structure 210 are selected. I Thus, the semiconductor layer 220 ( Figure 2D The isolation structure 210 may be covered. In some embodiments, the height H1 of the isolation structure 210 is substantially in the range of about 50 nanometers (nm) to about 150 nanometers. In some embodiments, the width W of the isolation structure 210 is... I Basically, it ranges from about 5 nanometers (nm) to about 100 nanometers. The base 212 may have a thickness T2. The base 212 can be configured as the first transistor 250 to be formed. Figure 2L The buried oxide region of the base 212 is selected such that the base 212 can satisfy the first transistor 250. Figure 2L The requirements of the isolation structure 210 are as follows. In some embodiments, the thickness T2 of the base 212 is greater than or substantially equal to the height H1 of the isolation structure 210. In some embodiments, the thickness T2 of the base 212 is substantially in the range of about 150 nanometers to about 350 nanometers. In some embodiments, the sum of the thickness T2 and the height H1 is substantially equal to the thickness T1.

[0030] refer to Figure 2C Then, the patterned hard mask layer 206 is removed. The dielectric layer 204 in the second region 202b can also be removed. Figure 2A ) base 212 ( Figure 2B The semiconductor substrate 202 in the second region 202b is exposed by etching. In some embodiments, the base 212 of the dielectric layer 204 in the second region 202b is removed by etching. Etching can be performed by a dry etching process using an etching gas. Etching can also be performed by a wet etching process using an etching solution. A photolithography process can define a mask element to define the etched area. As a result of etching, the upper surface of the semiconductor substrate 202 in the second region 202b is exposed. The dielectric layer 204 ( Figure 2A The remaining portion forms one or more dielectric structures 216. The dielectric structure 216 includes a substrate structure 214 and one or more isolation structures 210 located above the substrate structure 214. In some embodiments, at least two isolation structures 210 are disposed above a single substrate structure 214. In some embodiments, the width W of the substrate structure 214 is... bWidth W greater than the isolation structure 210 I .

[0031] The spacing S1 is between two adjacent isolation structures 210. The spacing S1 is configured to define a space for forming or accommodating the first transistor 250. Figure 2L The space between the isolation structures 210 is selected to allow for the formation of the first transistor 250. Figure 2L The requirements are as follows. In some embodiments, the spacing distance S1 is substantially in the range of about 50 nanometers (nm) to about 150 nanometers. In some embodiments, the spacing distance S2 between the sidewalls of the isolation structure 210 and the sidewalls of the substrate structure 214 is substantially in the range of about 50 nanometers to about 150 nanometers. The spacing distance S3 is between two adjacent dielectric structures 216. The spacing distance S3 is configured to define the formation or accommodation of the second transistor 260. Figure 2L The space between the dielectric structures 216 is selected such that the space can meet the requirements of the second transistor 260. In some embodiments, the spacing S3 is substantially in the range of about 50 nanometers to about 150 nanometers. In some embodiments, the width W of the substrate structure 214 is... b Basically equal to twice the interval distance S1, twice the interval distance S2, and the width W I The sum of twice the total. The spacing distances S1, S2, and S3 can be designed according to the different requirements of different semiconductor devices.

[0032] refer to Figure 2D A semiconductor layer 220 is formed. Figure 1 Operation 108 of method 100 illustrates the corresponding steps. In some embodiments, a semiconductor layer 220 is formed to cover a first region 202a and a second region 202b. In some embodiments, the semiconductor layer 220 is formed on an exposed surface of the semiconductor substrate 202 by an epitaxial growth process. In some embodiments, the epitaxial growth process includes providing silicon deposition using a silane-based precursor gas. Epitaxial growth can occur on the exposed surface of the semiconductor substrate 202. In some embodiments, the semiconductor layer 220 is grown to a thickness T3 greater than the thickness T2 of the substrate structure 214. In some embodiments, the thickness T3 is greater than the sum of the thickness T2 of the substrate structure 214 and the height H1 of the isolation structure 210.

[0033] A portion of semiconductor layer 220 having a thickness greater than the sum of thickness T2 and height H1 can be considered as an overfilled portion 222 of semiconductor layer 220. Epitaxial growth of semiconductor layer 220 can proceed laterally from the overfilled portion 222 of semiconductor layer 220 and extend above the exposed surface of dielectric structure 216. In other words, the formation of semiconductor layer 220 includes laterally growing semiconductor layer 220 on the upper surface of dielectric structure 216. In some embodiments, semiconductor layer 220 comprises the same material as semiconductor substrate 202 and has the same crystal orientation. In some embodiments, semiconductor layer 220 may comprise silicon, germanium, carbon, gallium arsenide, or other semiconductor materials, or combinations thereof. In alternative embodiments, semiconductor layer 220 is formed using any suitable technique, such as LPCVD, PECVD, or ALD.

[0034] refer to Figure 2E A portion of the semiconductor layer 220 is removed to expose the top surface of the isolation structure 210. Figure 1 Operation 110 of method 100 illustrates the corresponding steps. In some embodiments, a portion of the semiconductor layer 220 is removed by a planarization operation, such as a chemical mechanical polishing (CMP) operation. The planarization operation is performed to remove excess portions of the semiconductor layer 220 above the top surface of the isolation structure 210, resulting in… Figure 2E The structure is shown. In some embodiments, the upper surface of the semiconductor layer 220 is substantially flush with the top surface of the isolation structure 210. In some embodiments, the semiconductor layer 220 is reduced to a thickness T4 after a planarization operation. In some embodiments, the sum of the thickness T2 and the height H1 is substantially equal to the thickness T4.

[0035] refer to Figure 2F One or more isolation structures 224 are formed in the second region 202b. Figure 1 Operation 112 of method 100 illustrates the corresponding steps. In some embodiments, a hard mask layer (not shown) is formed over semiconductor layer 220, and then the hard mask layer is patterned with patterned photoresist (not shown) to form openings exposing portions of semiconductor layer 220. The exposed portions of semiconductor layer 220 are etched through the openings of the patterned hard mask layer to form one or more trenches exposing the underlying semiconductor substrate 202. The patterned hard mask layer is then removed. The trenches are then filled with an insulating material. A planarization operation is then performed to remove excess insulating material over semiconductor layer 220, thereby producing Figure 2F The isolation structure 224 is shown. Isolation structure 224 may include any suitable insulating material. In some embodiments, isolation structure 224 includes the same material as isolation structure 210. In some embodiments, isolation structure 224 may include a semiconductor oxide layer.

[0036] The isolation structure 224 can be configured as, for example, a second transistor 260 (see...). Figure 2L The shallow trench isolation (STI) isolation area. Isolation structure 224 has a height H2 and a width W. II Select the height H2 and width W of the isolation structure 224. II This allows the isolation structure 224 to satisfy the second transistor 260 ( Figure 2L The height H2 of the isolation structure 224 is substantially greater than the height H1 of the isolation structure 210. In some embodiments, the height H2 is substantially equal to the sum of the thickness T2 and the height H1. In some embodiments, the height H2 of the isolation structure 224 is substantially in the range of about 200 nanometers to about 400 nanometers.

[0037] The proposed method for forming semiconductor structures offers advantages in some embodiments. The proposed method involves forming isolation structures of different regions in separate operations (e.g., operations 106 and 112). Furthermore, the proposed method provides a structure with substantially no interface between the isolation structure 210 and the substrate structure 214. Therefore, lower manufacturing costs, better dielectric isolation, and lower leakage can be achieved.

[0038] refer to Figure 2G Gate stacks 230 and 240 are formed in a first region 202a and a second region 202b, respectively. Gate stacks 230 and 240 can be removed in subsequent steps and replaced by their respective replacement gates. Therefore, in some embodiments, gate stacks 230 and 240 are sacrificial gates. Gate stack 230 includes a gate dielectric 232 and a gate electrode 234. Gate stack 240 includes a gate dielectric 242 and a gate electrode 244. Gate dielectrics 232 and 242 can be formed of silicon oxide, silicon nitride, silicon carbide, etc. Gate electrodes 234 and 244 can include conductive layers. In some embodiments, gate electrodes 234 and 244 can include polysilicon. Gate electrodes 234 and 244 can also be formed of other conductive materials such as metals, metal alloys, metal silicides, metal nitrides, and / or other similar materials. In some embodiments, gate stacks 230 and 240 also include hard masks 236 and 246, respectively. Hard masks 236 and 246 can be formed of, for example, silicon nitride; however, other materials such as silicon carbide, silicon oxynitride, etc., can also be used. In an alternative embodiment, hard masks 236 and 246 are not formed.

[0039] refer to Figure 2HGate spacers 238 and 248 are formed on the sidewalls of gate stacks 230 and 240, respectively. According to some embodiments, each gate spacer 238 and 248 includes a silicon oxide layer and a silicon nitride layer on the silicon oxide layer. The formation of gate spacers 238 and 248 may include depositing a blanket dielectric layer, followed by anisotropic etching to remove horizontal portions of the blanket dielectric layer. Available deposition methods include plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), subatmospheric chemical vapor deposition (SACVD), and other deposition methods.

[0040] refer to Figure 2I Source and drain regions (hereinafter collectively referred to as source / drain regions) 252 and 262 are formed in a first region 202a and a second region 202b. The source / drain regions 252 and 262 can be formed in a single formation process, and therefore have the same depth and are formed of the same material. The source / drain regions 252 and 262 can be formed simultaneously in a single implantation process. In some embodiments, the source / drain regions 252 and 262 are n-type and heavily doped, and are therefore referred to as N+ regions. In some embodiments, a patterned hard mask layer (not shown) is formed over the semiconductor layer 220 of the semiconductor substrate 202 to define the locations of the source / drain regions 252 and 262. The source / drain regions 252 and 262 may have edges aligned with the edges of the gate spacers 238 and 248, respectively. Other methods for forming source / drain regions 252 and 262 are also possible, including, for example, forming epitaxial components.

[0041] In some embodiments, silicide regions (not shown) are formed in a first region 202a and a second region 202b, respectively. The process for forming the silicide regions may include forming a resist protective oxide (RPO) over portions of the semiconductor substrate 202 not protected by gate spacers 238 and 248. The RPO may serve as a silicide barrier layer during the formation of the silicide regions. The silicide regions can be formed using silicide processes such as self-aligned silicide (salicide), in which a metal material is formed over a semiconductor layer 220 of the semiconductor substrate 202, the temperature is increased to anneal the semiconductor substrate 202 and induce a reaction between the silicon and metal in the underlying semiconductor layer 220 to form a silicide, and unreacted metal is etched away. The silicide regions may be formed in a self-aligned manner on various components such as source / drain regions 252 and 262 to reduce contact resistance.

[0042] refer to Figure 2JAn interlayer dielectric (ILD) layer 270 is formed over a semiconductor substrate 202. The ILD layer 270 is formed in a blanket manner to a height above the top surfaces of the gate stacks 230 and 240. In some embodiments, a planarization operation is performed to remove excess portions of the ILD layer 270 until the top surfaces of the gate stacks 230 and 240 are exposed. If hard masks 236 and 246 are present, planarization can be stopped on the hard masks 236 and 246. Optionally, hard masks 236 and 246 are removed during planarization, exposing gate electrodes 234 and 244. The ILD layer 270 may be formed from an oxide using, for example, flowable chemical vapor deposition (FCVD). The ILD layer 270 may also be a spin-coated glass formed using spin coating. For example, the ILD layer 270 can be made of phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS) oxide, TiN, SiOC or other low-k dielectric materials.

[0043] Figure 2K and Figure 2L The formation of alternative gate stacks 254 and 264 according to some embodiments is shown. (Reference) Figure 2K Remove gate stacks 230 and 240 ( Figure 2J In some embodiments, gate stacks 230 and 240 are removed to form gate trenches 272 and 274, respectively, in the ILD layer 270. In some embodiments, a dry etching operation is performed to remove gate stacks 230 and 240. In some embodiments, the dry etching operation uses fluorine-containing plasma, chlorine-containing plasma, and / or bromine-containing plasma to remove gate stacks 230 and 240.

[0044] It should be understood that the semiconductor substrate 202 may include various device regions, and each device region may include various n-type or p-type FET devices and one or more passive devices such as resistors. It should also be understood that different devices may require different types of components. In some embodiments, when using I / O FET devices, gate dielectrics 232 and 242 ( Figure 2J These can be used as interface layers (IL). Therefore, gate dielectrics 232 and 242 can be left in place. In an alternative embodiment, when using a core FET device, gate dielectrics 232 and 242 are removed, thereby exposing semiconductor layer 220 to gate trenches 272 and 274, respectively.

[0045] refer to Figure 2L Gate stacks 230 and 240 ( Figure 2JThe gates 256 and 268 are replaced by gate stacks 254 and 264, respectively. Gate stack 254 includes a gate dielectric 256 and a gate electrode 258. Gate stack 264 includes a gate dielectric 266 and a gate electrode 268. Gate dielectrics 256 and 266 may include high-k dielectric materials such as hafnium oxide, lanthanum oxide, aluminum oxide, etc. Furthermore, gate dielectrics 256 and 266 can be formed in a single forming process, thus having the same thickness and being formed of the same dielectric material.

[0046] Gate electrodes 258 and 268 may include a conductive layer. In some embodiments, gate electrodes 258 and 268 may include at least a barrier metal layer, a work function metal layer, and a gap-filling metal layer. The barrier metal layer may include, for example, but not limited to, TiN. The work function metal layer may include a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials, but is not limited to such materials. In some embodiments, the gap-filling metal layer includes a conductive material such as Al, Cu, AlCu, or W, but is not limited to these. Methods for forming gate electrodes 258 and 268 include physical vapor deposition (PVD), chemical vapor deposition (CVD), etc. Furthermore, gate electrodes 258 and 268 may be formed in a single forming process and formed from the same materials. A planarization operation (e.g., CMP) is then performed to remove excess portions of the gate dielectrics 256 and 266 and the gate electrodes 258 and 268, leaving... Figure 2L The structure shown.

[0047] Based on reference Figures 2G to 2L The described operation thereby forms one or more first transistors 250 and one or more second transistors 260. The first transistor 250 includes a gate electrode 258, a gate dielectric 256, and a source / drain region 252. The second transistor 260 includes a gate electrode 268, a gate dielectric 266, and a source / drain region 262. According to some embodiments, the first transistor 250 is an RF device, and the second transistor 260 is a logic device. In some embodiments, the first transistor 250 is a partially depleted transistor. In some embodiments, the first transistor 250 and the second transistor 260 are separated from each other by isolation structures 210 and 224. In some embodiments, the first transistor 250 and the second transistor 260 are separated from each other by isolation structures 210, 224 and a semiconductor layer 220 between the isolation structures 210 and 224.

[0048] Figure 2MA dielectric layer 280 is shown formed over replacement gate stacks 254 and 264. The dielectric layer 280 can be formed from the same material selected from the candidate materials considered for forming the ILD layer 270. The ILD layer 270 and the dielectric layer 280 can be formed from the same or different materials.

[0049] refer to Figure 2M Contact plugs 282, 284, 286, and 288 are formed in dielectric layer 280 and ILD layer 270. The formation process may include forming contact plug openings in ILD layer 270 and dielectric layer 280 to expose source / drain regions 252 and 262 and gate electrodes 258 and 268, and filling the contact plug openings to form contact plugs 282, 284, 286, and 288. In some embodiments, at least one of the contact plugs 282 located on gate electrode 258 is referred to as a gate via of a first transistor 250. Contact plug 284 located on source / drain region 252 may be referred to as a source / drain via of the first transistor 250. In some embodiments, at least one of the contact plugs 286 located on gate electrode 268 is referred to as a gate via of a second transistor 260. Contact plug 288 located on source / drain region 262 may be referred to as a source / drain via of the second transistor 260.

[0050] refer to Figure 2N An interconnect structure 290 is disposed above the dielectric layer 280. The interconnect structure 290 may include one or more inter-metal dielectric (IMD) layers 291. The IMD layer 291 may include, for example, one or more layers of oxide, low-k dielectric, or ultra-low-k dielectric. The IMD layer 291 may surround one or more metal lines (or metal vias) 292, 294, 296, and 298, including, for example, copper, tungsten, and / or aluminum. A contact plug 282 may be configured to electrically couple the gate electrode 258 of the first transistor 250 to the metal line 292 of the interconnect structure 290. In some embodiments, a contact plug 284 may be configured to electrically couple the source / drain region 252 of the first transistor 250 to the metal line 294 of the interconnect structure 290. A contact plug 286 may be configured to electrically couple the gate electrode 268 of the second transistor 260 to the metal line 296 of the interconnect structure 290. In some embodiments, the contact plug 288 is configured to electrically couple the source / drain region 262 of the second transistor 260 to the metal line 298 of the interconnect structure 290.

[0051] The structure of the present invention is not limited to the above embodiments and may have other different embodiments. To simplify the description and facilitate comparison between the various embodiments of the present invention, the same (or similar) components in the following embodiments are referred to by the same (or similar) reference numerals. To facilitate comparison of the differences between embodiments, the following description will detail the differences between different embodiments, while the same features, values, and limitations will not be repeated.

[0052] Figures 3A to 3C This is a cross-sectional view showing a semiconductor structure 200 at different manufacturing stages created according to one or more embodiments of the present invention. Figures 3A to 3C An alternative method for obtaining dielectric structure 216 is shown.

[0053] refer to Figure 3A A semiconductor substrate 202 is received or formed. In addition, a dielectric layer 204 is formed on the semiconductor substrate 202.

[0054] refer to Figure 3B Remove dielectric layer 204 from the second region 202b. Figure 3A In some embodiments, the dielectric layer 204 in the second region 202b is removed by etching. Etching can be performed using a dry etching process with an etching gas. Etching can also be performed using a wet etching process with an etching solution. As a result of etching, the upper surface of the semiconductor substrate 202 in the second region 202b is exposed. The remaining portion of the dielectric layer 204 forms one or more dielectric structures 218. The dielectric structure 218 may have a thickness T1 and a width W1. The width W1 is configured to define a space for forming or accommodating a first transistor 250. Figure 2L The space is chosen such that the space is sufficient to form the first transistor 250. In some embodiments, the width W1 is substantially in the range of about 100 nanometers to about 500 nanometers. The spacing S4 is between two adjacent dielectric structures 218. The spacing S4 is configured to define a space for forming or accommodating the second transistor 260. Figure 2L The space between the dielectric structures 218 is selected such that the space can meet the requirements for forming the second transistor 260. In some embodiments, the spacing S4 between two adjacent dielectric structures 218 is substantially in the range of about 50 nanometers to about 150 nanometers.

[0055] refer to Figure 3C Etched dielectric structure 218 ( Figure 3BOne or more isolation structures 210 are formed in the first region 202a. In some embodiments, a hard mask layer (not shown) is formed over the dielectric structure 218, and then the hard mask layer is patterned with patterned photoresist (not shown) to form openings that expose portions of the dielectric structure 218. The exposed portions of the dielectric structure 218 are etched through the openings of the patterned hard mask layer. The patterned hard mask layer is then removed. The remaining portion of the dielectric structure 218 is formed as a dielectric structure 216 that may include a substrate structure 214 and an isolation structure 210. In some embodiments, two adjacent dielectric structures 218 ( Figure 3B The spacing S4 between the two dielectric structures 216 is basically equal to the spacing S3 between the two adjacent dielectric structures 216.

[0056] Figures 4A to 4F This is a cross-sectional view showing a semiconductor structure 300 at different manufacturing stages created according to one or more embodiments of the present invention.

[0057] refer to Figure 4A , to receive or form a semiconductor substrate 202. Figure 1 Operation 102 of method 100 illustrates the corresponding steps. The semiconductor substrate 202 may include various device regions. In some embodiments, the semiconductor substrate 202 includes one or more first regions 202a and one or more second regions 202b. The first regions 202a and the second regions 202b may include different devices. For example, the first region 202a is a radio frequency (RF) region, in which a first transistor 250 will be formed (see...). Figure 4F The second region 202b is a logic region in which the second transistor 260 will be formed (see...). Figure 4F In some embodiments, one or more first transistors 250 are disposed in a first region 202a and one or more second transistors 260 are disposed in a second region 202b. In some embodiments, the first region 202a is laterally surrounded by the second region 202b.

[0058] Still referencing Figure 4A A dielectric layer 204 is formed on top of the semiconductor substrate 202. Figure 1 Operation 104 of method 100 illustrates the corresponding steps. The dielectric layer 204 may comprise any suitable insulating material.

[0059] Figures 4B to 4C The formation of one or more dielectric structures 217 is shown. (Reference) Figure 4B and Figure 4C A portion of the dielectric layer 204 is removed to form a dielectric structure 217 in the first region 202a. Figure 1 Operation 106 of method 100 shows the corresponding steps.

[0060] refer to Figure 4B Etching dielectric layer 204 ( Figure 4A One or more isolation structures 210 are formed in the first region 202a. In some embodiments, a hard mask layer (not shown) is formed over the dielectric layer 204, and then the hard mask layer is patterned with patterned photoresist (not shown) to form openings that expose portions of the dielectric layer 204. The exposed portions of the dielectric layer 204 are etched through the openings of the patterned hard mask layer. The patterned hard mask layer is then removed. The remaining portion of the dielectric layer 204 may include a base 212 and isolation structures 210. The height H1 of the isolation structures 210 and / or the thickness T2 of the base 212 are selected such that they meet the requirements of the first transistor 250 to be formed.

[0061] refer to Figure 4C Remove dielectric layer 204 from the second region 202b. Figure 4A ) base 212 ( Figure 4B This exposes the semiconductor substrate 202 in the second region 202b. In some embodiments, the base 212 of the dielectric layer 204 in the second region 202b is removed by etching. As a result of etching, the upper surface of the semiconductor substrate 202 in the second region 202b is exposed. Dielectric layer 204 ( Figure 4A The remaining portion forms one or more dielectric structures 217. The dielectric structure 217 includes a substrate structure 214 and one or more isolation structures 210 located above the substrate structure 214. In some embodiments, the spacing S1 between two adjacent isolation structures 210 is substantially in the range of about 50 nanometers to about 150 nanometers. In some embodiments, the spacing S2 between the sidewalls of the isolation structure 210 and the sidewalls of the substrate structure 214 is substantially in the range of about 50 nanometers to about 150 nanometers. A spacing S5 is between two adjacent isolation structures 210 (two adjacent first transistors 250, see...). Figure 4F The spacing S5 between two adjacent isolation structures 210 of two adjacent first transistors 250 can be selected so that the two adjacent first transistors 250 do not interfere with each other. In some embodiments, the spacing S5 is substantially in the range of about 50 nanometers to about 150 nanometers. The spacings S1, S2, and S5 can be designed according to the different requirements of different semiconductor devices.

[0062] Reference Figure 4D A semiconductor layer 220 is formed. Figure 1Operation 108 of method 100 illustrates the corresponding steps. In some embodiments, a semiconductor layer 220 is formed to cover the first region 202a and the second region 202b. In some embodiments, the semiconductor layer 220 is formed on the exposed upper surface of the semiconductor substrate 202 by an epitaxial growth process. Epitaxial growth can occur on the exposed upper surface of the semiconductor substrate 202. In some embodiments, the semiconductor layer 220 is grown to a thickness T3 greater than the thickness T2 of the substrate structure 214. In some embodiments, the thickness T3 is greater than the sum of the thickness T2 of the substrate structure 214 and the height H1 of the isolation structure 210.

[0063] The portion of semiconductor layer 220 having a thickness greater than the sum of thickness T2 and height H1 can be considered as an overfilled portion 222 of semiconductor layer 220. Epitaxial growth of semiconductor layer 220 can proceed laterally from the overfilled portion 222 of semiconductor layer 220 and extend above the exposed surface of dielectric structure 217. In other words, the formation of semiconductor layer 220 includes laterally growing semiconductor layer 220 on the upper surface of dielectric structure 217.

[0064] refer to Figure 4E A portion of the semiconductor layer 220 is removed to expose the top surface of the isolation structure 210. Figure 1 Operation 110 of method 100 illustrates the corresponding steps. In some embodiments, a portion of the semiconductor layer 220 is removed by a planarization operation, such as a chemical mechanical polishing (CMP) operation. The planarization operation is performed to remove excess portions of the semiconductor layer 220 above the top surface of the isolation structure 210, resulting in… Figure 4E The structure is shown. In some embodiments, after a planarization operation, the semiconductor layer 220 is reduced to a thickness T4. In some embodiments, the sum of thickness T2 and height H1 is substantially equal to thickness T4.

[0065] refer to Figure 4F One or more isolation structures 224 are formed in the second region 202b. Figure 1 Operation 112 of method 100 illustrates the corresponding steps. In some embodiments, a hard mask layer (not shown) is formed over semiconductor layer 220, and then the hard mask layer is patterned with patterned photoresist (not shown) to form openings exposing portions of semiconductor layer 220. The exposed portions of semiconductor layer 220 are etched through the openings of the patterned hard mask layer to form one or more trenches exposing the underlying semiconductor substrate 202. The patterned hard mask layer is then removed. The trenches are then filled with an insulating material. A planarization operation is then performed to remove excess insulating material over semiconductor layer 220, thereby producing Figure 4FThe isolation structure 224 is shown. Isolation structure 224 may comprise any suitable insulating material. In some embodiments, isolation structure 224 comprises the same material as isolation structure 210. The height H2 of isolation structure 224 is substantially greater than the height H1 of isolation structure 210. In some embodiments, height H2 is substantially equal to the sum of thickness T2 and height H1. In some embodiments, the height H2 of isolation structure 224 is substantially in the range of about 200 nanometers to about 400 nanometers.

[0066] The proposed method for forming semiconductor structures offers advantages. The proposed method involves forming isolation structures in different regions in separate operations, such as operations 106 and 112. Furthermore, the proposed method provides a structure with virtually no interface between the isolation structure 210 and the substrate structure 214. Therefore, lower manufacturing costs, better dielectric isolation, and lower leakage can be achieved.

[0067] Still referencing Figure 4F It can be repeated and referenced. Figures 2G to 2L The similar operations described herein are used to form one or more first transistors 250 and one or more second transistors 260. The first transistor 250 includes a gate electrode 258, a gate dielectric 256, and a source / drain region 252. The second transistor 260 includes a gate electrode 268, a gate dielectric 266, and a source / drain region 262. In some embodiments, the first transistor 250 is an RF device, and the second transistor 260 is a logic device. In some embodiments, the first transistor 250 is a partially depleted transistor. In some embodiments, the first transistor 250 and the second transistor 260 are isolated from each other by isolation structures 210 and 224. In some embodiments, the first transistor 250 and the second transistor 260 are isolated from each other by isolation structures 210, 224 and a semiconductor layer 220 between the isolation structures 210 and 224.

[0068] Optionally or additionally, the above references may be repeated. Figures 2M to 2N Similar operations are described to form an ILD layer 270 and a dielectric layer 280 over the first and second transistors 250 and 260. Furthermore, contact plugs 282, 284, 286, and 288 are formed in the dielectric layer 280 and the ILD layer 270. An interconnect structure 290 may be disposed over the dielectric layer 280. The interconnect structure 290 may include one or more inter-metal dielectric (IMD) layers 291. The IMD layer 291 may surround one or more metal lines (or metal vias) 292, 294, 296, and 298.

[0069] Figures 5A to 5C This is a cross-sectional view showing a semiconductor structure 300 at different manufacturing stages created according to one or more embodiments of the present invention. Figures 5A to 5C An alternative method for obtaining dielectric structure 217 is shown.

[0070] refer to Figure 5A A semiconductor substrate 202 is received or formed. In addition, a dielectric layer 204 is formed on the semiconductor substrate 202.

[0071] refer to Figure 5B Remove dielectric layer 204 from the second region 202b. Figure 5A In some embodiments, the dielectric layer 204 in the second region 202b is removed by etching. Etching can be performed by a dry etching process using an etching gas. Etching can also be performed by a wet etching process using an etching solution. As a result of etching, the upper surface of the semiconductor substrate 202 in the second region 202b is exposed. The remaining portion of the dielectric layer 204 forms one or more dielectric structures 219. The dielectric structure 219 may have a thickness T1 and a width W2. The width W2 is configured to define a space for forming or accommodating a first transistor 250. Figure 4F The space is chosen such that the space is sufficient to form the first transistor 250. In some embodiments, the width W2 is substantially in the range of about 100 nanometers to about 500 nanometers.

[0072] refer to Figure 5C Etched dielectric structure 219 ( Figure 5B One or more isolation structures 210 are formed in the first region 202a. In some embodiments, a hard mask layer (not shown) is formed over the dielectric structure 219, and then the hard mask layer is patterned with patterned photoresist (not shown) to form openings that expose portions of the dielectric structure 219. The exposed portions of the dielectric structure 219 are etched through the openings of the patterned hard mask layer. The patterned hard mask layer is then removed. The remaining portion of the dielectric structure 219 is formed as a dielectric structure 217 that may include the substrate structure 214 and the isolation structure 210.

[0073] Figure 6This is a flowchart illustrating a method 600 for forming a semiconductor structure according to one or more embodiments of the present invention. The method 600 for forming a semiconductor structure includes operation 602, in which a semiconductor substrate is received. In some embodiments, the semiconductor substrate has a plurality of first regions and a plurality of second regions. The method 600 further includes operation 604, in which a dielectric layer is formed over the semiconductor substrate. In some embodiments, the dielectric layer has a first thickness. The method 600 further includes operation 606, in which a portion of the dielectric layer is removed to form a dielectric structure in the first regions. In some embodiments, the dielectric structure includes a substrate structure and a plurality of first isolation structures located over the substrate structure. In some embodiments, the substrate structure has a second thickness, the plurality of first isolation structures have a first height, and the first thickness is substantially equal to the sum of the second thickness and the first height. The method 600 further includes operation 608, in which a semiconductor layer is formed over the semiconductor substrate. The method 600 further includes operation 610, in which a portion of the semiconductor layer is removed to expose the top surfaces of the plurality of first isolation structures. Method 600 further includes operation 612, in which a first transistor is formed in at least one of a plurality of first regions and a second transistor is formed in at least one of a plurality of second regions. In some embodiments, the first transistor is isolated from the second transistor by at least one of a plurality of first isolation structures.

[0074] The method is described for the purpose of illustrating the concept of the invention, and this description is not intended to limit the invention beyond what is expressly stated in the claims. It can be understood above and... Figure 6 Additional operations are provided before, during, and after the method shown, and some of the described operations can be replaced, eliminated, or moved for additional embodiments of the method.

[0075] Figures 7A to 7F This is a schematic cross-sectional view illustrating a semiconductor structure 700 at different manufacturing stages created according to one or more embodiments of the present invention.

[0076] refer to Figure 7A , to receive or form a semiconductor substrate 202. Figure 6 Operation 602 of method 600 illustrates the corresponding steps. The semiconductor substrate 202 may include various device regions. In some embodiments, the semiconductor substrate 202 includes one or more first regions 202a and one or more second regions 202b. The first regions 202a and the second regions 202b may include different devices. For example, the first region 202a is a radio frequency (RF) region, in which a first transistor 250 will be formed (see...). Figure 7F The second region 202b is a logic region in which the second transistor 260 will be formed (see...). Figure 7FIn some embodiments, at least one first region 202a is disposed between two adjacent second regions 202b. In some embodiments, at least one second region 202b is disposed between two adjacent first regions 202a.

[0077] Still referencing Figure 7A A dielectric layer 204 is formed on top of the semiconductor substrate 202. Figure 6 Operation 604 of method 600 illustrates the corresponding steps. The thickness T1 of the dielectric layer 204 is substantially less than or equal to the thickness of the semiconductor substrate 202. In some embodiments, the thickness T1 of the dielectric layer 204 is substantially in the range of about 200 nanometers to about 400 nanometers.

[0078] Figures 7B to 7C The formation of one or more dielectric structures 716 is shown. (Reference) Figure 7B and Figure 7C A portion of the dielectric layer 204 is removed to form a dielectric structure 716 in the first region 202a. Figure 6 Operation 606 of method 600 shows the corresponding steps.

[0079] refer to Figure 7B Remove dielectric layer 204 from the second region 202b. Figure 7A This exposes the semiconductor substrate 202 in the second region 202b. In some embodiments, the dielectric layer 204 in the second region 202b is removed by etching. As a result of etching, the upper surface of the semiconductor substrate 202 in the second region 202b is exposed. The remaining portion of the dielectric layer 204 forms one or more dielectric structures 718. The dielectric structure 718 may have a thickness T1 and a width W3. The width W3 is configured to define a space for forming or accommodating the first transistor 250. Figure 7F The space is chosen such that the width W3 can meet the requirements for forming the first transistor 250. In some embodiments, the width W3 is substantially in the range of about 100 nanometers to about 800 nanometers. The spacing S6 is between two adjacent dielectric structures 718. The spacing S6 is configured to define a space for forming or accommodating the second transistor 260. Figure 7F The space between two adjacent dielectric structures 718 is selected such that the space can meet the requirements for forming the second transistor 260. In some embodiments, the spacing S6 between two adjacent dielectric structures 718 is substantially in the range of about 50 nanometers to about 150 nanometers.

[0080] refer to Figure 7C Etched dielectric structure 718 ( Figure 7BOne or more isolation structures 710 are formed in a first region 202a. In some embodiments, a hard mask layer (not shown) is formed over a dielectric structure 718, and then the hard mask layer is patterned with patterned photoresist (not shown) to form openings that expose portions of the dielectric structure 718. The exposed portions of the dielectric structure 718 are etched through the openings of the patterned hard mask layer. The patterned hard mask layer is then removed. The remaining portion of the dielectric structure 718 forms a dielectric structure 716. The dielectric structure 716 includes a substrate structure 714 and one or more isolation structures 710. The substrate structure 714 has a thickness T2, and the isolation structure 710 has a height H1 and a width W4. In some embodiments, the thickness T1 is substantially equal to the sum of the thickness T2 and the height H1. The height H1 and width W4 of the isolation structure 710 are selected such that the semiconductor layer 720 ( Figure 7D The substrate structure 714 may cover the isolation structure 710. In some embodiments, the thickness T2 of the substrate structure 714 is substantially in the range of about 150 nanometers to about 350 nanometers. In some embodiments, the height H1 of the isolation structure 710 is substantially in the range of about 50 nanometers to about 150 nanometers. In some embodiments, the width W4 of the isolation structure 710 is substantially in the range of about 50 nanometers to about 150 nanometers.

[0081] Alternatively, the dielectric structure 716 can be formed by etching the dielectric layer 204 to form an isolation structure 710 in the first region 202a. After forming the isolation structure 710, a portion of the dielectric layer 204 in the second region 202b is removed to expose the semiconductor substrate 202 in the second region 202b.

[0082] Reference Figure 7D A semiconductor layer 720 is formed. Figure 6 Operation 608 of method 600 illustrates the corresponding steps. In some embodiments, a semiconductor layer 720 is formed over a semiconductor substrate 202. The semiconductor layer 720 may be formed to cover a first region 202a and a second region 202b. In some embodiments, the semiconductor layer 720 is formed on an exposed surface of the semiconductor substrate 202 by an epitaxial growth process. Epitaxial growth may occur on the exposed surface of the semiconductor substrate 202. In some embodiments, the semiconductor layer 720 is grown to a thickness T3 greater than the thickness T2 of the substrate structure 714. In some embodiments, the semiconductor layer 720 is grown to a thickness T3 greater than the sum of the thickness T2 of the substrate structure 714 and the height H1 of the isolation structure 710.

[0083] A portion of the semiconductor layer 720 having a thickness greater than the sum of its thickness T2 and height Hl can be considered as an overfilled portion 722 of the semiconductor layer 720. Epitaxial growth of the semiconductor layer 720 can proceed laterally from the overfilled portion 722 of the semiconductor layer 720 and extend above the exposed surface of the dielectric structure 716. In other words, the formation of the semiconductor layer 720 includes forming the semiconductor layer 720 over the dielectric structure 716 via an epitaxial growth process and filling the space between two adjacent isolation structures 710 with the semiconductor layer 720. In some embodiments, the semiconductor layer 720 comprises the same material as the semiconductor substrate 202 and has the same crystal orientation. In alternative embodiments, the semiconductor layer 720 is formed using any suitable technique such as LPCVD, PECVD, or ALD.

[0084] refer to Figure 7E A portion of the semiconductor layer 720 is removed to expose the top surface of the isolation structure 710. Figure 6 Operation 610 of method 600 illustrates the corresponding steps. In some embodiments, a planarization operation, such as chemical mechanical polishing (CMP), is performed to remove a portion of the semiconductor layer 720. The planarization operation removes excess portions of the semiconductor layer 720 located above the plane of the isolation structure 710, thereby creating a first semiconductor layer 726 in a first region 202a and a second semiconductor layer 728 in a second region 202b. In some embodiments, the upper surfaces of the first semiconductor layer 726 and the second semiconductor layer 728 are substantially flush with the top surface of the isolation structure 710. The second semiconductor layer 728 has a thickness T4. In some embodiments, the sum of thickness T2 and height H1 is substantially equal to thickness T4.

[0085] refer to Figure 7F It can be repeated and referenced. Figures 2F to 2L The operations described are similar to those for forming one or more first transistors 250 in the first region 202a and one or more second transistors 260 in the second region 202b. Figure 6 Operation 612 of method 600 illustrates the corresponding steps. The first transistor 250 includes a gate electrode 258, a gate dielectric 256, and a source / drain region 252. The second transistor 260 includes a gate electrode 268, a gate dielectric 266, and a source / drain region 262. According to some embodiments, the first transistor 250 is an RF device, while the second transistor 260 is a logic device. In some embodiments, the first transistor 250 is a partially depleted transistor. In some embodiments, the first transistor 250 and the second transistor 260 are isolated from each other by an isolation structure 710.

[0086] Optionally or additionally, may be repeated with reference. Figures 2M to 2NThe operations described are similar to those described above, forming an ILD layer 270 and a dielectric layer 280 over the first and second transistors 250 and 260. Furthermore, contact plugs 282, 284, 286, and 288 are formed in the dielectric layer 280 and the ILD layer 270. An interconnect structure 290 may be disposed over the dielectric layer 280. The interconnect structure 290 may include one or more inter-metal dielectric (IMD) layers 291. The IMD layers 291 may surround one or more metal lines (or metal vias) 292, 294, 296, and 298.

[0087] Still referencing Figure 7F The dielectric structure 716 may have a concave profile. The dielectric structure 716 has a first upper boundary U1 below the upper surface of the semiconductor layer 220. The dielectric structure 716 has a second upper boundary U2 substantially flush with the upper surface of the semiconductor layer 220. The dielectric structure 716 may have a first portion 716-1 extending along a first direction D1 and one or more second portions 716-2 extending along a second direction D2. The first portion 716-1 and the second portion 716-2 are interconnected. The first portion 716-1 and the second portion 716-2 together form a concave profile. In some embodiments, the first direction D1 is substantially transverse, and the second direction D2 is substantially vertical.

[0088] In some embodiments, the first transistor 250 and the second transistor 260 are separated by a dielectric structure 716. In some embodiments, the first transistor 250 is separated from the second transistor 260 by a second portion 716-2 of the dielectric structure 716. In some embodiments, at least a sub-portion 716-21 of the second portion 716-2 is configured as an isolation structure for the first transistor 250. In some embodiments, at least a sub-portion 716-22 of the second portion 716-2 is configured as an isolation structure for the second transistor 260. In some embodiments, the first transistor 250 and the second transistor 260 are separated by sub-portions 716-21 and 716-22.

[0089] The proposed method for forming semiconductor structures offers advantages. The proposed method involves forming isolation structures (e.g., sub-parts 716-21 and 716-22) for different devices in a single operation (e.g., operation 606). The isolation structures for different devices are interconnected. The proposed method includes defining different portions of the dielectric structure in separate steps. Therefore, greater packaging density and lower manufacturing costs can be achieved. Furthermore, the proposed method provides a structure with substantially no interface between the isolation structure 710 and the substrate structure 714. Therefore, better dielectric isolation and lower leakage can be achieved.

[0090] According to some embodiments of the present invention, a method for forming a semiconductor structure is provided. The method includes receiving a semiconductor substrate having a first region and a second region; forming a dielectric layer over the semiconductor substrate; removing a portion of the dielectric layer to form a dielectric structure in the first region, wherein the dielectric structure includes a substrate structure and a plurality of first isolation structures located over the substrate structure; forming a semiconductor layer covering the first and second regions; removing a portion of the semiconductor layer to expose the top surfaces of the plurality of first isolation structures; and forming a plurality of second isolation structures in the second region. In some embodiments, the plurality of first isolation structures have a first height, and the plurality of second isolation structures have a second height different from the first height. In some embodiments, the second height is greater than the first height. In some embodiments, the second height is substantially equal to the sum of the thickness of the substrate structure and the first height. In some embodiments, removing a portion of the dielectric layer to form the dielectric structure in the first region includes: etching the dielectric layer to form the plurality of first isolation structures in the first region; and removing the dielectric layer in the second region to expose the semiconductor substrate in the second region. In some embodiments, the etching of the dielectric layer to form the plurality of first isolation structures in the first region is performed before removing the dielectric layer in the second region to expose the semiconductor substrate in the second region. In some embodiments, after removing the dielectric layer in the second region to expose the semiconductor substrate in the second region, etching of the dielectric layer is performed to form a plurality of first isolation structures in the first region. In some embodiments, forming a semiconductor layer covering the first and second regions includes an epitaxial growth process. In some embodiments, the semiconductor layer is grown to a thickness greater than the thickness of the substrate structure. In some embodiments, the semiconductor layer is grown to a thickness greater than the sum of the thickness of the substrate structure and the first heights of the plurality of first isolation structures. In some embodiments, forming the semiconductor layer includes laterally growing the semiconductor layer on the upper surface of the dielectric structure.

[0091] According to some embodiments of the present invention, a method for forming a semiconductor structure is provided. The method includes receiving a semiconductor substrate having a plurality of first regions and a plurality of second regions; forming a dielectric layer over the semiconductor substrate, wherein the dielectric layer has a first thickness; removing a portion of the dielectric layer to form a dielectric structure in the first regions, wherein the dielectric structure includes a substrate structure and a plurality of first isolation structures located over the substrate structure, the substrate structure having a second thickness, the plurality of first isolation structures having a first height, and the first thickness being substantially equal to the sum of the second thickness and the first height; forming a semiconductor layer over the semiconductor substrate; removing a portion of the semiconductor layer to expose the top surfaces of the plurality of first isolation structures; and forming a first transistor in at least one of the plurality of first regions and forming a second transistor in at least one of the plurality of second regions, wherein the first transistor and the second transistor are separated by at least one of the plurality of first isolation structures. In some embodiments, at least one of the plurality of first regions is located between two adjacent second regions in the plurality of second regions. In some embodiments, at least two of the plurality of first regions are adjacent to each other. In some embodiments, the method of forming the semiconductor structure further includes forming a plurality of second isolation structures in the plurality of second regions. In some embodiments, forming a semiconductor layer over a semiconductor substrate further includes: forming a semiconductor layer over a dielectric layer, and filling the space between two adjacent first isolation structures of a plurality of first isolation structures with the semiconductor layer by an epitaxial growth process.

[0092] According to some embodiments of the present invention, a semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor layer located above the semiconductor substrate and in the first region; a dielectric structure located above the semiconductor substrate and in the second region, the dielectric structure having a first upper boundary below the upper surface of the first semiconductor layer, wherein the dielectric structure has a first portion extending along a first direction and a second portion extending along a second direction, and the first portion and the second portion are interconnected; a second semiconductor layer located above the first portion of the dielectric structure; a first transistor located above the first semiconductor layer and in the first region; and a second transistor located above the second semiconductor layer and in the second region. In some embodiments, the first transistor and the second transistor are separated by the dielectric structure. In some embodiments, the first direction is a substantially transverse direction, and the second direction is a substantially vertical direction. In some embodiments, the dielectric structure has a second upper boundary substantially flush with the upper surface of the first semiconductor layer.

[0093] The foregoing outlines the structures of several embodiments to enable those skilled in the art to better understand various aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made therein without departing from the spirit and scope of the invention.

Claims

1. A method for forming a semiconductor structure, comprising: Receive a semiconductor substrate having a first region and a second region; A dielectric layer is formed over the semiconductor substrate; A portion of the dielectric layer is removed to form a dielectric structure in the first region, wherein the dielectric structure includes a substrate structure and a plurality of first isolation structures located above the substrate structure; A semiconductor layer covering the first region and the second region is formed; Removing a portion of the semiconductor layer to expose the top surface of the plurality of first isolation structures; and Multiple second isolation structures are formed in the second region. Wherein, removing a portion of the dielectric layer to form the dielectric structure in the first region includes: Etching the dielectric layer to form the plurality of first isolation structures in the first region; and Remove the dielectric layer in the second region to expose the semiconductor substrate in the second region.

2. The method according to claim 1, wherein, The plurality of first isolation structures have a first height, and the plurality of second isolation structures have a second height different from the first height.

3. The method according to claim 2, wherein, The second height is greater than the first height.

4. The method according to claim 2, wherein, The second height is substantially equal to the sum of the thickness of the base structure and the first height.

5. The method according to claim 1, wherein, The first region is a radio frequency region, and the second region is a logic region.

6. The method according to claim 1, wherein, Before removing the dielectric layer in the second region to expose the semiconductor substrate in the second region, the etching of the dielectric layer is performed to form the plurality of first isolation structures in the first region.

7. The method according to claim 5, wherein, After removing the dielectric layer in the second region to expose the semiconductor substrate in the second region, the etching of the dielectric layer is performed to form the plurality of first isolation structures in the first region.

8. The method according to claim 1, wherein, Forming the semiconductor layer covering the first region and the second region includes an epitaxial growth process.

9. The method according to claim 8, wherein, The semiconductor layer is grown to a thickness greater than that of the substrate structure.

10. The method according to claim 8, wherein, The semiconductor layer is grown to a thickness greater than the sum of the thickness of the substrate structure and the first height of the plurality of first isolation structures.

11. The method according to claim 8, wherein, The formation of the semiconductor layer includes laterally growing the semiconductor layer on the upper surface of the dielectric structure.

12. A method for forming a semiconductor structure, comprising: Receive a semiconductor substrate having a plurality of first regions and a plurality of second regions; A dielectric layer is formed over the semiconductor substrate, wherein the dielectric layer has a first thickness; A portion of the dielectric layer is removed to form a dielectric structure in the first region, wherein the dielectric structure includes a substrate structure and a plurality of first isolation structures located above the substrate structure, the substrate structure having a second thickness, the plurality of first isolation structures having a first height, and the first thickness being substantially equal to the sum of the second thickness and the first height; A semiconductor layer is formed over the semiconductor substrate; Removing a portion of the semiconductor layer to expose the top surface of the plurality of first isolation structures; and A first transistor is formed in at least one of the plurality of first regions and a second transistor is formed in at least one of the plurality of second regions, wherein the first transistor and the second transistor are separated by at least one of the plurality of first isolation structures. Wherein, removing a portion of the dielectric layer to form the dielectric structure in the first region includes: Etching the dielectric layer to form the plurality of first isolation structures in the first region; and Remove the dielectric layer in the second region to expose the semiconductor substrate in the second region.

13. The method according to claim 12, wherein, At least one of the plurality of first regions is located between two adjacent second regions of the plurality of second regions.

14. The method according to claim 12, wherein, At least two of the plurality of first regions are adjacent to each other.

15. The method of claim 12, further comprising: Multiple second isolation structures are formed in the multiple second regions.

16. The method according to claim 12, wherein, Forming a semiconductor layer over the semiconductor substrate further includes: The semiconductor layer is formed above the dielectric layer, and the space between two adjacent first isolation structures in the plurality of first isolation structures is filled by the semiconductor layer through an epitaxial growth process.

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