Semiconductor structure and method of manufacturing the same
By adjusting the etching sequence of the dielectric layer in semiconductor structure fabrication and reducing the trench depth-to-width ratio, the problems of insufficient filling of contact structure materials and porosity defects were solved, thereby improving the semiconductor process yield and electrical performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-06-23
- Publication Date
- 2026-08-04
AI Technical Summary
In the manufacturing process of dynamic random access memory, an increased trench aspect ratio in the contact structure leads to insufficient filling of the contact structure material and porosity defects, causing electrical abnormalities and affecting the yield of semiconductor manufacturing processes.
By utilizing the difference in etching ratio between the initial filling dielectric layer and the bit line dielectric layer during the semiconductor structure fabrication process, a portion of the initial filling dielectric layer is first removed to form a filling dielectric layer, and then the filling dielectric layer and a portion of the bit line dielectric layer are removed, thereby reducing the trench depth-to-width ratio and avoiding insufficiently filled voids in the memory node contact structure.
It improves the electrical properties of the semiconductor structure, increases process yield, and avoids electrical anomalies caused by porosity.
Smart Images
Figure CN115274551B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for preparing the same. Background Technology
[0002] As semiconductor manufacturing processes shrink, critical dimensions become smaller in the manufacturing process of Dynamic Random Access Memory (DRAM). In the manufacturing process of contact structures, the aspect ratio of trenches is becoming increasingly higher, leading to more severe defects such as insufficient filling of contact structure materials and the presence of voids. This results in serious electrical anomalies, such as high resistance, which in turn affects the yield loss of semiconductor manufacturing processes.
[0003] Therefore, how to improve the defects of insufficient filling of contact structure materials and the presence of pores in semiconductor manufacturing processes is an urgent problem to be solved. Summary of the Invention
[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the shortcomings of existing technologies.
[0005] On one hand, this disclosure provides a method for fabricating a semiconductor structure, including:
[0006] Provide substrate;
[0007] Multiple spaced bit line structures are formed on the substrate; the bit line structure includes a stacked structure; the stacked structure includes a bit line conductive layer and a bit line dielectric layer stacked sequentially from bottom to top;
[0008] An initial fill dielectric layer is formed, wherein the initial fill dielectric layer at least fills the gap between adjacent bit line structures;
[0009] A portion of the initial fill dielectric layer located between adjacent bit line structures is removed to form a fill dielectric layer; wherein, in a direction perpendicular to the substrate, the height of the fill dielectric layer is less than the height of the bit line structure;
[0010] Remove the filling medium layer and part of the bit line medium layer to form a memory node contact hole between adjacent bit line structures;
[0011] A storage node contact structure is formed within the storage node contact hole, and the storage node contact structure is filled without any pores within the storage node contact hole.
[0012] In one embodiment, removing a portion of the initial filling medium layer includes:
[0013] A patterned photoresist layer is formed on the upper surface of the bit line structure and the initial filling dielectric layer;
[0014] Based on the patterned photoresist layer, a portion of the initial filling dielectric layer located between adjacent bit line structures is etched away;
[0015] Remove the patterned photoresist layer.
[0016] In one embodiment, a bottom dielectric layer is further formed on the upper surface of the substrate between adjacent bit line structures;
[0017] The removal of the filler dielectric layer and part of the bit line dielectric layer includes:
[0018] Remove the bit line dielectric layer that is above the upper surface of the filling dielectric layer;
[0019] Remove the filling medium layer;
[0020] After removing the filling dielectric layer, the method for fabricating the semiconductor structure further includes:
[0021] Remove the bottom dielectric layer to expose the substrate.
[0022] In one embodiment, the bit line structure further includes sidewalls;
[0023] The sidewall is located on the side wall of the stacked structure;
[0024] While removing part of the bit line dielectric layer, a portion of the sidewalls is also removed.
[0025] In one embodiment, after forming the memory node contact structure within the memory node contact hole, the method for fabricating the semiconductor structure further includes:
[0026] Remove the exposed sidewalls.
[0027] In one embodiment, forming a storage node contact structure within the storage node contact hole includes:
[0028] A conductive material layer is formed; the conductive material layer fills the memory node contact holes and covers the bit line structure;
[0029] The conductive material layer is etched back to remove the conductive material layer outside the storage node contact hole and the portion of the conductive material layer inside the storage node contact hole; the conductive material layer remaining inside the storage node contact hole constitutes the storage node contact structure.
[0030] In one embodiment, the substrate includes an array region and a peripheral region located around the array region;
[0031] The peripheral area is further covered by a covering medium layer, which covers the peripheral area.
[0032] The method for fabricating the semiconductor structure, while removing a portion of the bit line dielectric layer, further includes:
[0033] Remove a portion of the covering medium layer so that the upper surface of the remaining covering medium layer is flush with the upper surface of the filling medium layer.
[0034] In one embodiment, the conductive material layer further covers the upper surface of the covering dielectric layer retained in the peripheral region;
[0035] The process of forming a storage node contact structure within the storage node contact hole includes:
[0036] The conductive material layer is etched back to remove the conductive material layer located on the upper surface of the retained overlay dielectric layer.
[0037] In one embodiment, a transistor is also formed on the upper surface of the peripheral region, and the covering dielectric layer covers the transistor.
[0038] In one embodiment, during the process of removing a portion of the initial filler dielectric layer located between adjacent bit line structures, the thickness of the initial filler dielectric layer removed is 1 / 2 to 2 / 3 of the height of the bit line dielectric layer.
[0039] In one embodiment, before forming a plurality of spaced bit line structures on the substrate, the method for fabricating the semiconductor structure further includes:
[0040] An embedded word line is formed within the substrate, the embedded word line extending along a first direction; the bit line structure extends along a second direction; the second direction intersects the first direction.
[0041] In one embodiment, a shallow trench isolation structure is formed in the substrate, and the shallow trench isolation structure isolates a plurality of spaced active regions in the substrate;
[0042] After forming the buried word line within the substrate and before forming a plurality of spaced bit line structures on the substrate, the method for fabricating the semiconductor structure further includes:
[0043] A bit line contact structure is formed within the substrate, and the bit line contact structure is in contact with the active region; the bit line conductive layer of the bit line structure is in contact with the bit line contact structure.
[0044] On the other hand, according to some embodiments, this disclosure also provides a semiconductor structure, including:
[0045] A substrate having a plurality of spaced bit line structures; the bit line structures include a stacked structure; the stacked structure includes a bit line conductive layer and a bit line dielectric layer stacked sequentially from bottom to top;
[0046] Storage node contact holes are located between adjacent bit line structures;
[0047] A storage node contact structure, wherein the storage node contact structure is located within the storage node contact hole;
[0048] The method for forming the contact hole of the storage node includes:
[0049] An initial fill dielectric layer is formed, wherein the initial fill dielectric layer at least fills the gap between adjacent bit line structures;
[0050] A portion of the initial fill dielectric layer located between adjacent bit line structures is removed to form a fill dielectric layer, wherein the height of the fill dielectric layer is less than the height of the bit line structure in a direction perpendicular to the substrate;
[0051] Remove the filling medium layer and part of the bit line medium layer to form a memory node contact hole between adjacent bit line structures.
[0052] In one embodiment, the bit line structure further includes a sidewall located on the sidewall of the stacked structure;
[0053] The substrate also includes embedded word lines extending along a first direction; the bit line structure extends along a second direction; the second direction intersects the first direction;
[0054] A shallow trench isolation structure is formed within the substrate, the shallow trench isolation structure isolating multiple spaced active regions within the substrate; the semiconductor structure further includes:
[0055] The bit line contact structure is in contact with the active region; the bit line conductive layer of the bit line structure is in contact with the bit line contact structure.
[0056] In one embodiment, the substrate includes an array region and a peripheral region located around the array region;
[0057] A transistor is also formed on the upper surface of the peripheral region, and a covering dielectric layer is formed in the peripheral region, which covers the transistor.
[0058] The semiconductor structure and its fabrication method disclosed herein have at least the following beneficial effects:
[0059] The semiconductor structure fabrication method disclosed herein utilizes the difference in etching ratio between the initial filling dielectric layer and the bit line dielectric layer when fabricating trenches between adjacent bit line structures to accommodate memory node contact structures. First, a portion of the initial filling dielectric layer is removed to form a filling dielectric layer, and then the filling dielectric layer and a portion of the bit line dielectric layer are removed. This reduces the aspect ratio of the fabricated trench, avoids porosity in the memory node contact structure due to insufficient filling, thereby improving the electrical properties of the resulting semiconductor structure and increasing the process yield.
[0060] In the semiconductor structure provided in this disclosure, the memory node contact hole is formed by first removing part of the initial fill dielectric layer to form a fill dielectric layer, and then removing the fill dielectric layer and part of the bit line dielectric layer. Therefore, the depth-to-width ratio of the trench used to accommodate the memory node contact structure between adjacent bit line structures is reduced, and there will be no gaps in the memory node contact structure located in the memory node contact hole, which can avoid electrical abnormality problems. Attached Figure Description
[0061] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0062] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
[0063] Figure 2 Figure (a) shows the structure obtained in step S3 of the semiconductor structure fabrication method provided in an embodiment of this disclosure. Figure 3 A schematic diagram of the cross-sectional structure along the aa' direction. Figure 2 Figure (b) shows the structure obtained in step S3 of the semiconductor structure fabrication method provided in an embodiment of this disclosure. Figure 3 A schematic diagram of the cross-sectional structure in the bb' direction. Figure 2 Figure (c) is a schematic cross-sectional view of the structure obtained in step S3 of the semiconductor structure fabrication method provided in an embodiment of this disclosure in the peripheral region;
[0064] Figure 3 This is a top view of the array region in the structure obtained in step S2 of the semiconductor structure fabrication method provided in an embodiment of the present disclosure.
[0065] Figure 4 A flowchart of step S4 in a method for fabricating a semiconductor structure according to an embodiment of this disclosure;
[0066] Figure 5 Figure (a) shows the structure obtained in step S401 of the semiconductor structure fabrication method provided in an embodiment of this disclosure, along... Figure 3 A schematic diagram of the cross-sectional structure along the aa' direction. Figure 5 Figure (b) shows the structure obtained in step S401 of the semiconductor structure fabrication method provided in an embodiment of this disclosure, along... Figure 3 A schematic diagram of the cross-sectional structure in the bb' direction. Figure 5 Figure (c) is a schematic cross-sectional view of the structure obtained in step S401 of the semiconductor structure fabrication method provided in an embodiment of this disclosure in the peripheral region;
[0067] Figure 6 Figure (a) shows the structure obtained in step S403 of the semiconductor structure fabrication method provided in an embodiment of this disclosure, along... Figure 3 A schematic diagram of the cross-sectional structure along the aa' direction. Figure 6 Figure (b) shows the structure obtained in step S403 of the semiconductor structure fabrication method provided in an embodiment of this disclosure, along... Figure 3 A schematic diagram of the cross-sectional structure in the bb' direction. Figure 6 Figure (c) is a schematic cross-sectional view of the structure obtained in step S403 of the semiconductor structure fabrication method provided in an embodiment of this disclosure in the peripheral region;
[0068] Figure 7 This is a flowchart of step S5 in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
[0069] Figure 8 Figure (a) shows the structure obtained in step S502 of the semiconductor structure fabrication method provided in an embodiment of this disclosure, along... Figure 3 A schematic diagram of the cross-sectional structure along the aa' direction. Figure 8 Figure (b) shows the structure obtained in step S502 of the semiconductor structure fabrication method provided in an embodiment of this disclosure, along... Figure 3 A schematic diagram of the cross-sectional structure in the bb' direction. Figure 8 Figure (c) is a schematic cross-sectional view of the structure obtained in step S502 of the semiconductor structure fabrication method provided in an embodiment of this disclosure in the peripheral region;
[0070] Figure 9 This is a flowchart of step S6 in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
[0071] Figure 10Figure (a) shows the structure obtained in step S601 of the semiconductor structure fabrication method provided in an embodiment of this disclosure, along... Figure 3 A schematic diagram of the cross-sectional structure along the aa' direction. Figure 10 Figure (b) shows the structure obtained in step S601 of the semiconductor structure fabrication method provided in an embodiment of this disclosure, along... Figure 3 A schematic diagram of the cross-sectional structure in the bb' direction. Figure 10 Figure (c) is a schematic cross-sectional view of the structure obtained in step S601 of the semiconductor structure fabrication method provided in an embodiment of this disclosure in the peripheral region;
[0072] Figure 11 Figure (a) shows the structure obtained in step S602 of the semiconductor structure fabrication method provided in an embodiment of this disclosure, along... Figure 3 A schematic diagram of the cross-sectional structure along the aa' direction. Figure 11 Figure (b) shows the structure obtained in step S602 of the semiconductor structure fabrication method provided in an embodiment of this disclosure, along... Figure 3 A schematic diagram of the cross-sectional structure in the bb' direction. Figure 11 Figure (c) is a schematic cross-sectional view of the structure obtained in step S602 of the semiconductor structure fabrication method provided in an embodiment of this disclosure in the peripheral region;
[0073] Figure 12 Figure (a) shows the structure obtained after removing exposed sidewalls in a semiconductor structure fabrication method according to an embodiment of this disclosure, along... Figure 3 A schematic diagram of the cross-sectional structure along the aa' direction. Figure 12 Figure (b) shows the structure obtained after removing exposed sidewalls in a semiconductor structure fabrication method according to an embodiment of this disclosure, along... Figure 3 A schematic diagram of the cross-sectional structure in the bb' direction. Figure 12 Figure (c) is a schematic cross-sectional view of the structure obtained after removing the exposed sidewalls in the peripheral region in a semiconductor structure fabrication method provided in an embodiment of this disclosure. Figure 12 Figure (a) in the figure also shows a semiconductor structure provided in an embodiment of this disclosure along the […]. Figure 3 A schematic diagram of the cross-sectional structure along the aa' direction. Figure 12 Figure (b) in the figure also shows a semiconductor structure provided in an embodiment of this disclosure along the […]. Figure 3 A schematic diagram of the cross-sectional structure in the bb' direction. Figure 12 Figure (c) is also a schematic diagram of the cross-sectional structure of the semiconductor structure in the peripheral region provided in an embodiment of this disclosure.
[0074] Explanation of reference numerals in the attached figures:
[0075] 1. Substrate; 101. Cover dielectric layer; 102. Transistor; 103. Buried word line; 104. Shallow trench isolation structure; 105. Active region; 106. Bit line contact structure; 2. Bit line structure; 201. Bit line conductive layer; 202. Bit line dielectric layer; 203. Sidewall; 3. Initial fill dielectric layer; 4. Fill dielectric layer; 401. Patterned photoresist layer; 5. Storage node contact hole; 6. Storage node contact structure; 601. Conductive material layer; 7. Bottom dielectric layer. Detailed Implementation
[0076] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0077] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.
[0078] It should be understood that when an element or layer is referred to as "on" other elements or layers, it may be directly on other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion; for example, a first direction may be referred to as a second direction, and similarly, a second direction may be referred to as a first direction; the first direction and the second direction are different directions.
[0079] Spatial relation terms such as “on top of” or “on the upper surface of” are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that spatial relation terms include not only the orientation shown in the figure, but also different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “on top of” or “on the upper surface of” will be oriented “below” other elements or features. Therefore, the exemplary terms “on top of” or “on the upper surface of” can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0080] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0081] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the present disclosure.
[0082] This disclosure provides a method for fabricating a semiconductor structure according to some embodiments.
[0083] Please see Figure 1 In one embodiment, the method for fabricating the semiconductor structure may include the following steps:
[0084] S1: Provide substrate.
[0085] S2: A plurality of spaced bit line structures are formed on a substrate; the bit line structures may include a stacked structure; and the stacked structure may include a bit line conductive layer and a bit line dielectric layer stacked sequentially from bottom to top.
[0086] S3: Form an initial filler dielectric layer; the initial filler dielectric layer should at least fill the gap between adjacent bit line structures.
[0087] S4: Remove a portion of the initial fill dielectric layer located between adjacent bit line structures to form a fill dielectric layer; wherein, in the direction perpendicular to the substrate, the height of the fill dielectric layer should be less than the height of the bit line structure.
[0088] S5: Remove the filler dielectric layer and part of the bit line dielectric layer to form a memory node contact hole between adjacent bit line structures.
[0089] S6: A storage node contact structure is formed inside the storage node contact hole, and the storage node contact structure is filled without any pores inside the storage node contact hole.
[0090] The semiconductor structure fabrication method provided in the above embodiments utilizes the difference in etching ratio between the initial filling dielectric layer and the bit line dielectric layer when fabricating trenches between adjacent bit line structures to accommodate memory node contact structures. First, a portion of the initial filling dielectric layer is removed to form a filling dielectric layer, defining the size of the subsequently obtained trench. Then, the filling dielectric layer and a portion of the bit line dielectric layer are removed. This reduces the aspect ratio of the fabricated trench, avoids voids in the memory node contact structure due to insufficient filling, thereby improving the electrical properties of the obtained semiconductor structure and increasing the process yield.
[0091] Please see Figure 2 In step S1, substrate 1 is provided.
[0092] The method for fabricating the semiconductor structure disclosed herein does not specifically limit the material of the substrate 1. As an example, the substrate 1 may be any one or more of the following: silicon substrate, sapphire substrate, glass substrate, silicon carbide substrate, gallium nitride substrate, or gallium arsenide substrate; that is, the material of the substrate 1 may be any one or more of the following: silicon (Si), sapphire, glass, silicon carbide (SiC), gallium nitride (GaN), or gallium arsenide (GaAs).
[0093] In some possible embodiments of this disclosure, substrate 1 may include an array region and a peripheral region located outside the array region.
[0094] Please see Figure 2 Figure (a) in the middle and Figure 2 In Figure (b), in the semiconductor structure fabrication method provided in this disclosure, a shallow trench isolation structure 104 can be formed in the substrate 1, and the shallow trench isolation structure 104 isolates a plurality of spaced active regions 105 in the substrate 1.
[0095] Please continue reading. Figure 2 In step S2, a plurality of spaced bit line structures 2 are formed on the substrate 1.
[0096] Specifically, the bit line structure 2 may include a stacked structure. The stacked structure may include a bit line conductive layer 201 and a bit line dielectric layer 202 stacked sequentially from bottom to top.
[0097] In one embodiment, before forming a plurality of spaced bit line structures 2 on the substrate 1, the method for fabricating the semiconductor structure may further include the step of forming buried word lines 103.
[0098] Specifically, an embedded word line 103 extending in a first direction can be formed within the substrate 1. Based on this, the bit line structure 2 should extend in a second direction, and the second direction should intersect with the first direction.
[0099] The method for fabricating the semiconductor structure disclosed herein does not specifically limit the materials of the bit line conductive layer 201 and the bit line dielectric layer 202. As an example, the material of the bit line conductive layer 201 may include, but is not limited to, titanium (Ti) or tungsten (W). As an example, the bit line dielectric layer 202 may include, but is not limited to, a silicon nitride (SiN) layer.
[0100] In some embodiments where embedded word lines 103 are formed in the substrate 1, the semiconductor structure fabrication method may further form bit line contact structures 106 in the substrate 1 before forming bit line structures 2.
[0101] Specifically, the bit line contact structure 106 should be in contact with the active region 105. Furthermore, the bit line conductive layer 201 of the bit line structure 2 should be in contact with the bit line contact structure 106.
[0102] The method for fabricating the semiconductor structure disclosed herein does not specifically limit the material of the bit line contact structure 106. As an example, the bit line contact structure 106 may be any one or more of a polycrystalline silicon layer, a titanium nitride (TiN) layer, and / or a tungsten layer.
[0103] Please continue reading. Figure 2 In step S3, an initial filling medium layer 3 is formed.
[0104] Specifically, the initial filling dielectric layer 3 should at least fill the gap between adjacent bit line structures 2.
[0105] Please combine Figure 3 Continue reading Figure 2 , Figure 3 The aa' and bb' directions in embodiments of this disclosure are shown; Figure 2 Figure (a) shows the structure obtained in step S3 of this disclosure along... Figure 3 A schematic diagram of the cross-sectional structure along the aa' direction. Figure 2 Figure (b) illustrates the structure obtained in step S3 of this disclosure along... Figure 3A schematic diagram of the cross-sectional structure in the bb' direction.
[0106] It should be noted that, Figure 3 The diagram shown is a top view of the array region in the structure obtained in step S2.
[0107] In step S4, a portion of the initial fill dielectric layer 3 located between adjacent bit line structures 2 is removed, and the remaining initial fill dielectric layer 3 is used as the fill dielectric layer 4. In the direction perpendicular to the substrate 1, the height of the fill dielectric layer 4 should be less than the height of the bit line structure 2.
[0108] In the semiconductor structure fabrication method provided in this disclosure, a portion of the initial filling dielectric layer 3 can be removed in step S4 to form a filling dielectric layer 4, and the size of the bit line dielectric layer 202 to be removed in step S5 is defined.
[0109] In the semiconductor structure fabrication method provided in this disclosure, the thickness of the initial filling dielectric layer 3 removed during the removal of a portion of the initial filling dielectric layer 3 located between adjacent bit line structures 2 is not specifically limited. As an example, the thickness of the initial filling dielectric layer 3 removed during the removal of a portion of the initial filling dielectric layer 3 located between adjacent bit line structures 2 can be 1 / 2 to 2 / 3 of the height of the bit line dielectric layer 202; for example, the thickness of the removed initial filling dielectric layer 3 can be 1 / 2, 7 / 12, or 2 / 3 of the height of the bit line dielectric layer 202, etc.
[0110] The semiconductor structure fabrication method disclosed herein does not specifically limit the materials of the initial filling dielectric layer 3 and the filling dielectric layer 4. As an example, the initial filling dielectric layer 3 and the filling dielectric layer 4 may include, but are not limited to, spin-on dielectric (SOD) layers. The initial filling dielectric layer 3 and the filling dielectric layer 4 formed by spin coating can have good adhesion and gap filling ability.
[0111] Please combine Figure 4 See Figures 5 to 6 In one embodiment, the following steps can be used to remove a portion of the initial fill dielectric layer 3 located between adjacent bit line structures 2, including:
[0112] S401: A patterned photoresist layer 401 is formed on the upper surface of the bit line structure 2 and the initial filling dielectric layer 3.
[0113] like Figure 5 As shown, Figure 5 Figure (a) shows the structure obtained in step S401 of this disclosure along... Figure 3 A schematic diagram of the cross-sectional structure along the aa' direction. Figure 5Figure (b) illustrates the structure obtained in step S401 of this disclosure along... Figure 3 A schematic diagram of the cross-sectional structure along the bb' direction. It should be noted that the patterned photoresist layer 401 has openings (not shown), which expose the array region. Figure 5 Figure (a) in the middle and Figure 5 (b) in the diagram corresponds to the opening within the patterned photoresist layer 401, where there is no patterned photoresist layer 401.
[0114] S402: Based on the patterned photoresist layer 401, etch away part of the initial filling dielectric layer 3 located between adjacent bit line structures 2.
[0115] S403: Remove patterned photoresist layer 401.
[0116] like Figure 6 As shown, Figure 6 Figure (a) shows the structure obtained in step S403 of this disclosure along... Figure 3 A schematic diagram of the cross-sectional structure along the aa' direction. Figure 6 Figure (b) illustrates the structure obtained in step S403 of this disclosure along... Figure 3 A schematic diagram of the cross-sectional structure in the bb' direction.
[0117] This disclosure does not specifically limit the method of forming the patterned photoresist layer 401 in step S401. As an example, the patterned photoresist layer 401 can be formed by methods such as coating-curing, inkjet printing, or deposition to form a photoresist layer covering the upper surface of the obtained structure; and the aforementioned photoresist layer is patterned by patterning processes such as masking, exposure, development, and etching to obtain the patterned photoresist layer 401.
[0118] The semiconductor structure fabrication method disclosed herein does not specifically limit the material of the patterned photoresist layer 401 in step S401. As an example, the material of the patterned photoresist layer 401 may include a reverse photoresist material.
[0119] This disclosure does not specifically limit the method of removing part of the initial filler dielectric layer 3 in step S402. As an example, an oxide cleaning (CLN) process can be used, but is not limited to, to remove part of the initial filler dielectric layer 3.
[0120] This disclosure does not specifically limit the method of removing the patterned photoresist layer 401 in step S403. As an example, the patterned photoresist layer 401 can be removed using, but is not limited to, an ashing (ASH) process.
[0121] Please see Figures 7 to 8In step S5, the filling medium layer 4 and part of the bit line medium layer 202 are removed to form a storage node contact hole 5 between adjacent bit line structures 2.
[0122] like Figure 7 As shown, in one embodiment, the following steps can be used to remove the fill dielectric layer 4 and part of the bit line dielectric layer 202, including:
[0123] S501: Remove bit line dielectric layer 202 that is above the upper surface of filling dielectric layer 4.
[0124] S502: Remove the filler medium layer 4.
[0125] like Figure 8 As shown, Figure 8 Figure (a) shows the structure obtained in step S502 of this disclosure along... Figure 3 A schematic diagram of the cross-sectional structure along the aa' direction. Figure 8 Figure (b) illustrates the structure obtained in step S502 of this disclosure along... Figure 3 A schematic diagram of the cross-sectional structure in the bb' direction.
[0126] In some possible embodiments of this disclosure, such as Figure 6 As shown in Figure (a), a bottom dielectric layer 7 can also be formed on the upper surface of the substrate 1 between adjacent bit line structures 2. Based on this, as... Figure 8 As shown in Figure (a), the semiconductor structure fabrication method can also remove the bottom dielectric layer 7 after removing the filling dielectric layer 4 to expose the substrate 1.
[0127] In some possible embodiments of this disclosure, such as Figure 6 As shown in Figure (a), the bitline structure 2 may also include sidewalls 203. Based on this, as... Figure 8 As shown in Figure (a), the semiconductor structure fabrication method can remove part of the bit line dielectric layer 202 and part of the sidewall 203 at the same time.
[0128] As previously described, in some possible embodiments of this disclosure, substrate 1 may include an array region and a peripheral region located around the array region. Figure 6 As shown in Figure (c), a covering medium layer 101 is also formed in the outer region to cover the outer region.
[0129] Based on this, such as Figure 8 As shown in Figure (c), the semiconductor structure fabrication method can remove part of the bit line dielectric layer 202 and part of the cover dielectric layer 101 at the same time, so that the upper surface of the remaining cover dielectric layer 101 is flush with the upper surface of the fill dielectric layer 4.
[0130] In the above embodiments, when removing the bit line dielectric layer 202 that is higher than the upper surface of the filling dielectric layer 4, a portion of the cover dielectric layer 101 can be removed simultaneously until the upper surface of the remaining cover dielectric layer 101 is flush with the upper surface of the filling dielectric layer 4, at which point the removal stops.
[0131] In one embodiment, a transistor 102 is also formed on the upper surface of the peripheral region.
[0132] Specifically, the covering dielectric layer 101 can cover the transistor 102.
[0133] The method for fabricating the semiconductor structure provided in this disclosure does not specifically limit the form of transistor 102. As an example, transistor 102 may include, but is not limited to, a metal-oxide-semiconductor field-effect transistor (MOSFET or MOS transistor).
[0134] The method for fabricating the semiconductor structure disclosed herein does not specifically limit the material of the covering dielectric layer 101. As an example, the material of the covering dielectric layer 101 may include, but is not limited to, a silicon nitride layer.
[0135] In one embodiment, the material of the overlay dielectric layer 101 may be the same as the material of the bit line dielectric layer 202.
[0136] In some possible embodiments, an oxide pad layer and a nitride layer may be formed in the peripheral region. The oxide pad layer and the nitride layer may be formed sequentially on the substrate 1, and the shallow trench isolation structure 104 may be formed on the surface of the nitride layer away from the oxide pad layer.
[0137] Please see Figures 9 to 11 In step S6, a storage node contact structure 6 is formed in the storage node contact hole 5, and the storage node contact structure 6 is filled in the storage node contact hole 5 without any pores.
[0138] like Figure 9 As shown, in one embodiment, the storage node contact structure 6 can be formed within the storage node contact hole 5 using the following steps:
[0139] S601: Forming a conductive material layer 601.
[0140] Specifically, the conductive material layer 601 should fill the storage node contact hole 5 and cover the bit line structure 2.
[0141] like Figure 10 As shown, Figure 10 Figure (a) shows the structure obtained in step S601 of this disclosure along... Figure 3A schematic diagram of the cross-sectional structure along the aa' direction. Figure 10 Figure (b) illustrates the structure obtained in step S601 of this disclosure along... Figure 3 A schematic diagram of the cross-sectional structure in the bb' direction.
[0142] S602: The conductive material layer 601 is etched back to remove the conductive material layer 601 located outside the storage node contact hole 5 and the portion of the conductive material layer 601 located inside the storage node contact hole 5; the conductive material layer 601 retained inside the storage node contact hole 5 is the storage node contact structure 6.
[0143] like Figure 11 As shown, Figure 11 Figure (a) shows the structure obtained in step S602 of this disclosure along... Figure 3 A schematic diagram of the cross-sectional structure along the aa' direction. Figure 11 Figure (b) illustrates the structure obtained in step S602 of this disclosure along... Figure 3 A schematic diagram of the cross-sectional structure in the bb' direction.
[0144] This disclosure does not specifically limit the method of forming the conductive material layer 601 in step S601. As examples, the conductive material layer 601 may be formed by processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), high-density plasma deposition (PCVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD).
[0145] The semiconductor structure fabrication method disclosed herein does not specifically limit the material of the conductive material layer 601. As an example, the material of the conductive material layer 601 may be any one or more of titanium nitride, titanium, tungsten silicide (Si2W), or tungsten, etc.
[0146] In embodiments where the substrate 1 may include a peripheral region, the conductive material layer 601 formed in step S601 may also cover the upper surface of the covering dielectric layer 101 retained in the peripheral region.
[0147] Based on this, during the process of forming the storage node contact structure 6 in the storage node contact hole 5, the step of etching back the conductive material layer 601 to remove the conductive material layer 601 located on the upper surface of the retained covering dielectric layer 101 may also be included.
[0148] Please see Figure 12 Figure (a) in the middle and Figure 12 In Figure (b), in an embodiment where the bit line structure 2 includes sidewalls 203, after forming the memory node contact structure 6 within the memory node contact hole 5, the method for fabricating the semiconductor structure may further include the step of removing the exposed sidewalls 203.
[0149] It should be understood that, although Figure 1 , Figure 4 , Figure 7 and Figure 9 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 , Figure 4 , Figure 7 and Figure 9 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.
[0150] This disclosure also provides a semiconductor structure according to some embodiments. The semiconductor structure can be prepared using the fabrication methods described in the foregoing embodiments.
[0151] Please continue reading. Figure 12 Figure (a) in the middle and Figure 12 In Figure (b) of the diagram, in one embodiment, the semiconductor structure may include a substrate 1, a memory node contact hole 5, and a memory node contact structure 6.
[0152] The substrate 1 has multiple spaced bit line structures 2; each bit line structure 2 includes a stacked structure; the stacked structure includes a bit line conductive layer 201 and a bit line dielectric layer 202 stacked sequentially from bottom to top. Storage node contact holes 5 are located between adjacent bit line structures 2. Storage node contact structures 6 are located within the storage node contact holes 5.
[0153] The storage node contact hole 5 in the above embodiments can be prepared by the following steps, for example:
[0154] An initial fill dielectric layer 3 is formed, which at least fills the gap between adjacent bit line structures 2. After forming the initial fill dielectric layer 3, a portion of the initial fill dielectric layer 3 located between adjacent bit line structures 2 is removed to form a fill dielectric layer 4, wherein the height of the fill dielectric layer 4 is less than the height of the bit line structure 2 in the direction perpendicular to the substrate 1. After forming the fill dielectric layer 4, the fill dielectric layer 4 and a portion of the bit line dielectric layer 202 are removed to form a memory node contact hole 5 between adjacent bit line structures 2.
[0155] In the semiconductor structure provided in the above embodiments, the memory node contact hole 5 is formed by first removing part of the initial filling dielectric layer 3 to form the filling dielectric layer 4, and then removing the filling dielectric layer 4 and part of the bit line dielectric layer 202. Therefore, the trench depth-to-width ratio between adjacent bit line structures 2 used to accommodate the memory node contact structure 6 is reduced, and the memory node contact structure 6 located in the memory node contact hole 5 will not have gaps, which can avoid electrical abnormality problems.
[0156] As an example, in the semiconductor structure provided in this disclosure, substrate 1 may be any one or more of the following: silicon substrate, sapphire substrate, glass substrate, silicon carbide substrate, gallium nitride substrate, or gallium arsenide substrate.
[0157] As an example, in the semiconductor structure provided in this disclosure, the material of the bit line conductive layer 201 may include, but is not limited to, titanium (Ti) or tungsten (W). The bit line dielectric layer 202 may include, but is not limited to, a silicon nitride (SiN) layer.
[0158] As an example, the material of the storage node contact structure 6 in the semiconductor structure provided in this disclosure may be any one or more of titanium nitride, titanium, tungsten silicide (Si2W) or tungsten.
[0159] Please continue reading. Figure 12 Figure (a) in the middle and Figure 12 In Figure (b) of the diagram, in one embodiment, the bit line structure 2 may further include a sidewall 203 located on the sidewall of the stacked structure.
[0160] Please continue reading. Figure 12 Figure (a) in the middle and Figure 12 In Figure (b) of the diagram, in one embodiment, the substrate 1 may also have an embedded word line 103 extending along a first direction. Based on this, the bit line structure 2 should extend along a second direction, which intersects the first direction.
[0161] Please continue reading. Figure 12 Figure (a) in the middle and Figure 12In Figure (b) of the figure, in one embodiment, a shallow trench isolation structure 104 is formed in the substrate 1, which can isolate multiple spaced active regions 105 in the substrate 1.
[0162] Please continue reading. Figure 12 Figure (a) in the middle and Figure 12 In Figure (b) of the diagram, in one embodiment, the semiconductor structure may further include a bit line contact structure 106. The bit line contact structure 106 shall be in contact with the active region 105; thereby, the bit line conductive layer 201 of the bit line structure 2 is in contact with the bit line contact structure 106.
[0163] As an example, in the semiconductor structure provided in this disclosure, the bit line contact structure 106 may include, but is not limited to, any one or more of a polysilicon layer, a titanium nitride layer, and / or a tungsten layer.
[0164] Please continue reading. Figure 12 In Figure (c), substrate 1 includes an array region and a peripheral region located around the array region. Furthermore, transistors 102 can be formed on the upper surface of the peripheral region.
[0165] As an example, in the semiconductor structure provided in this disclosure, transistor 102 may include, but is not limited to, a MOS transistor.
[0166] In one embodiment, a covering dielectric layer 101 may also be formed in the peripheral region, which covers the transistor 102.
[0167] As an example, the material covering the dielectric layer 101 in the semiconductor structure provided in this disclosure may include, but is not limited to, a silicon nitride layer.
[0168] It should be noted that the methods for preparing the semiconductor structure in the embodiments of this disclosure can all be used to prepare the corresponding semiconductor structure. Therefore, the technical features between the method embodiments and the structure embodiments can be substituted and supplemented for each other without conflict, so that those skilled in the art can learn the technical content of this disclosure.
[0169] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0170] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.
Claims
1. A method of fabricating a semiconductor structure, characterized by, include: Provide substrate; Multiple spaced bit line structures are formed on the substrate; the bit line structure includes a stacked structure; the stacked structure includes a bit line conductive layer and a bit line dielectric layer stacked sequentially from bottom to top; An initial fill dielectric layer is formed, wherein the initial fill dielectric layer at least fills the gap between adjacent bit line structures; A portion of the initial fill dielectric layer located between adjacent bit line structures is removed to form a fill dielectric layer; wherein, in a direction perpendicular to the substrate, the height of the fill dielectric layer is less than the height of the bit line structure; Remove the filling medium layer and part of the bit line medium layer to form a memory node contact hole between adjacent bit line structures; A storage node contact structure is formed within the storage node contact hole, and the storage node contact structure is filled without any pores within the storage node contact hole.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that, Removing part of the initial filling medium layer includes: A patterned photoresist layer is formed on the upper surface of the bit line structure and the initial filling dielectric layer; Based on the patterned photoresist layer, a portion of the initial filling dielectric layer located between adjacent bit line structures is etched away; Remove the patterned photoresist layer.
3. The method for preparing a semiconductor structure according to claim 1, characterized in that, A bottom dielectric layer is also formed on the upper surface of the substrate between adjacent bit line structures; The removal of the filler dielectric layer and part of the bit line dielectric layer includes: Remove the bit line dielectric layer that is above the upper surface of the filling dielectric layer; Remove the filling medium layer; After removing the filling dielectric layer, the method for fabricating the semiconductor structure further includes: Remove the bottom dielectric layer to expose the substrate.
4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The bitline structure also includes sidewalls; The sidewall is located on the side wall of the stacked structure; In addition to removing part of the bit line dielectric layer, part of the sidewalls are also removed.
5. The method for preparing a semiconductor structure according to claim 4, characterized in that, After forming the memory node contact structure within the memory node contact hole, the method for fabricating the semiconductor structure further includes: Remove the exposed sidewalls.
6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The process of forming a storage node contact structure within the storage node contact hole includes: A conductive material layer is formed; the conductive material layer fills the storage node contact holes and covers the bit line structure; The conductive material layer is etched back to remove the conductive material layer outside the storage node contact hole and the portion of the conductive material layer inside the storage node contact hole; the conductive material layer remaining inside the storage node contact hole constitutes the storage node contact structure.
7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The substrate includes an array region and a peripheral region located around the array region; The peripheral area is further covered by a covering medium layer, which covers the peripheral area. The method for fabricating the semiconductor structure, while removing part of the bit line dielectric layer, further includes: Remove a portion of the covering medium layer so that the upper surface of the remaining covering medium layer is flush with the upper surface of the filling medium layer.
8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The conductive material layer also covers the upper surface of the covering dielectric layer retained in the peripheral region; The process of forming a storage node contact structure within the storage node contact hole includes: The conductive material layer is etched back to remove the conductive material layer located on the upper surface of the retained overlay dielectric layer.
9. The method for preparing a semiconductor structure according to claim 7, characterized in that, A transistor is also formed on the upper surface of the peripheral region, and the covering dielectric layer covers the transistor.
10. The method for preparing a semiconductor structure according to claim 1, characterized in that, During the process of removing a portion of the initial filler dielectric layer located between adjacent bit line structures, the thickness of the initial filler dielectric layer removed is 1 / 2 to 2 / 3 of the height of the bit line dielectric layer.
11. The method for preparing a semiconductor structure according to claim 1, characterized in that, Before forming a plurality of spaced bit line structures on the substrate, the method for fabricating the semiconductor structure further includes: An embedded word line is formed within the substrate, the embedded word line extending along a first direction; the bit line structure extends along a second direction; the second direction intersects the first direction.
12. The method for preparing a semiconductor structure according to claim 11, characterized in that, A shallow trench isolation structure is formed in the substrate, and the shallow trench isolation structure isolates multiple spaced active regions in the substrate. After forming the buried word line within the substrate and before forming a plurality of spaced bit line structures on the substrate, the method for fabricating the semiconductor structure further includes: A bit line contact structure is formed within the substrate, and the bit line contact structure is in contact with the active region; The bitline conductive layer of the bitline structure is in contact with the bitline contact structure.
13. A semiconductor structure, prepared by the method according to any one of claims 1-12, characterized in that, The semiconductor structure includes: A substrate having a plurality of spaced bit line structures; the bit line structures include a stacked structure; the stacked structure includes a bit line conductive layer and a bit line dielectric layer stacked sequentially from bottom to top; Storage node contact holes are located between adjacent bit line structures; A storage node contact structure, wherein the storage node contact structure is located within the storage node contact hole; The method for forming the contact hole of the storage node includes: An initial fill dielectric layer is formed, wherein the initial fill dielectric layer at least fills the gap between adjacent bit line structures; A portion of the initial fill dielectric layer located between adjacent bit line structures is removed to form a fill dielectric layer, wherein the height of the fill dielectric layer is less than the height of the bit line structure in a direction perpendicular to the substrate; Remove the filling medium layer and part of the bit line medium layer to form a memory node contact hole between adjacent bit line structures.
14. The semiconductor structure according to claim 13, characterized in that, The bit line structure also includes a side wall, which is located on the side wall of the stacked structure; The substrate also has embedded word lines that extend along a first direction; The bit line structure extends along the second direction; The second direction intersects with the first direction; A shallow trench isolation structure is formed in the substrate, and the shallow trench isolation structure isolates multiple spaced active regions in the substrate. The semiconductor structure also includes: Bit line contact structure, wherein the bit line contact structure is in contact with the active region; The bitline conductive layer of the bitline structure is in contact with the bitline contact structure.
15. The semiconductor structure according to claim 13, characterized in that, The substrate includes an array region and a peripheral region located around the array region; A transistor is also formed on the upper surface of the peripheral region, and a covering dielectric layer is formed in the peripheral region, which covers the transistor.