Semiconductor device and method of manufacturing the same

Abstract

According to embodiments of this application, a method for manufacturing a semiconductor device is provided, comprising: forming a first semiconductor fin, a second semiconductor fin, and a hybrid fin between the first and second semiconductor fins; recess-etching the first semiconductor fin and the hybrid fin while the second semiconductor fin is covered by a first mask; forming a first epitaxial source / drain component connected to the first semiconductor fin, and doping the first epitaxial source / drain component with an n-type dopant; recess-etching the second semiconductor fin, wherein the hybrid fin and the first semiconductor fin are covered by a second mask; and forming a second epitaxial source / drain component connected to the second semiconductor fin, and doping the second epitaxial source / drain component with a p-type dopant. According to other embodiments of this application, a semiconductor device is also provided.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods for manufacturing semiconductor devices. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have resulted in several generations of ICs, each with smaller and more complex circuitry than the previous one. In the course of IC development, functional density (i.e., the number of interconnect devices per chip area) has typically increased, while geometry (i.e., the smallest component (or wire) that can be produced using manufacturing processes) has decreased. This scaling down process generally provides benefits through increased production efficiency and reduced associated costs. However, this scaling down also increases the complexity of handling and manufacturing ICs.

[0003] Therefore, improvements are needed in the handling and manufacturing of ICs. Summary of the Invention

[0004] According to an embodiment of this application, a semiconductor device is provided, comprising: an isolation layer having a top surface; a first epitaxial source / drain component extending from the isolation layer beyond the top surface, wherein the first epitaxial source / drain component is used for an n-type device; a second epitaxial source / drain component extending from the isolation layer beyond the top surface, wherein the second epitaxial source / drain component is used for a p-type device; a hybrid fin disposed between the first epitaxial source / drain component and the second epitaxial source / drain component, wherein the hybrid fin has a first end embedded in the isolation layer and a second end extending beyond the top surface of the isolation layer; and a source / drain contact component connected to the first and second epitaxial source / drain components at a bottom surface, wherein the bottom surface of the source / drain contact component is above the second end of the hybrid fin.

[0005] According to another embodiment of this application, a semiconductor device is provided, comprising: a first semiconductor fin; a second semiconductor fin; a first epitaxial source / drain component connected to the first semiconductor fin, wherein the first epitaxial source / drain component is doped with an n-type dopant; a second epitaxial source / drain component connected to the second semiconductor fin, wherein the second epitaxial source / drain component is doped with a p-type dopant; a hybrid fin disposed between the first and second semiconductor fins and between the first and second epitaxial source / drain components; and a gate structure disposed above the first semiconductor fin, the second semiconductor fin, and the hybrid fin, wherein the hybrid fin has a first top surface below the gate structure, a second top surface between the first and second epitaxial source / drain components, and the second top surface is lower than the first top surface.

[0006] According to another embodiment of this application, a method for manufacturing a semiconductor device is provided, comprising: forming a first semiconductor fin, a second semiconductor fin, and a hybrid fin between the first and second semiconductor fins; recess-etching the first semiconductor fin and the hybrid fin while the second semiconductor fin is covered by a first mask; forming a first epitaxial source / drain component connected to the first semiconductor fin, and doping the first epitaxial source / drain component with an n-type dopant; recess-etching the second semiconductor fin, wherein the hybrid fin and the first semiconductor fin are covered by a second mask; and forming a second epitaxial source / drain component connected to the second semiconductor fin, and doping the second epitaxial source / drain component with a p-type dopant. Attached Figure Description

[0007] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figure 1 This is a flowchart of a method for manufacturing a semiconductor device according to embodiments of the present disclosure.

[0009] Figures 2 to 28 as well as Figures 28A-28E The various stages of manufacturing a semiconductor device according to embodiments of the present disclosure are illustrated schematically.

[0010] Figure 29 , Figure 29A , Figure 29B , Figure 29C Various views of a semiconductor device according to embodiments of the present disclosure are shown.

[0011] Figures 30 to 33 as well as Figures 33A-33B Various stages of a semiconductor device according to embodiments of the present disclosure are shown.

[0012] Figures 34 to 40 as well as Figures 40A-40B Various stages of a semiconductor device according to an embodiment of the present disclosure are shown. Detailed Implementation

[0013] The following disclosure provides numerous embodiments or instances of different components for implementing the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” “top,” and “upper” can be used here to readily describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0015] The foregoing provides a general overview of some aspects of the embodiments described in this disclosure. While some embodiments described herein are set in the context of nanostructured FETs (e.g., nanowire transistors, nanosheet transistors, all-around gate transistors, etc.), implementations of some aspects of this disclosure can be used in other processes and / or other devices, such as planar FETs, Fin-FETs, and other suitable devices. Other modifications that may be made within the scope of this disclosure will be readily understood by those skilled in the art. Furthermore, while method embodiments may be described in a particular order, various other method embodiments may be performed in any logical order and may include fewer or more steps than those described herein. In this disclosure, source / drain refers to the source and / or drain. Source and drain are used interchangeably.

[0016] This disclosure relates to semiconductor devices with source / drain contacts, exhibiting improved RC delay and reduced resistance. In particular, the semiconductor device according to this disclosure includes a highly variable hybrid fin between the boundaries of a p-type device region and an n-type device region.

[0017] Figure 1 This is a flowchart of a method 100 for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figures 2-28 The various stages of manufacturing a semiconductor device 200 according to embodiments of the present disclosure are illustrated schematically. In particular, it can be based on... Figure 1 Method 100 is used to manufacture semiconductor devices 200. Figures 2-28 This is a schematic perspective view of semiconductor device 200.

[0018] In operation 102 of method 100, a semiconductor fin 204 is formed on the substrate 202, such as Figure 2 As shown. Figure 2 This is a schematic perspective view of the semiconductor device 200 according to the present disclosure. The substrate 202 may be a bulk silicon substrate. Alternatively, the substrate 202 may include elemental semiconductors such as silicon (Si) or germanium (Ge) in a crystal structure; compound semiconductors such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); or combinations thereof. The substrate 202 may also be a silicon-on-insulator (SOI) substrate. SOI substrates are fabricated using SIMOX (simulated oxygen isolation), wafer bonding, and / or other suitable methods.

[0019] Substrate 202 may include various doping configurations depending on the circuit design. For example, substrate 202 may include one or more p-doped regions and one or more n-doped regions. The p-doped regions may be doped with p-type dopants, such as boron or BF2. The n-doped regions may be doped with n-type dopants, such as phosphorus or arsenic. The doped regions may be formed directly on substrate 202, in a P-well structure, in an N-well structure, in a double-well structure, and / or using bump structures. Substrate 202 may also include various active regions, such as regions configured for N-type metal-oxide-semiconductor transistor devices and regions configured for P-type metal-oxide-semiconductor transistor devices. Semiconductor fins 204n and 204p (collectively referred to as 204) may be formed by suitable patterning and etching processes. N-type devices are subsequently formed by semiconductor fin 204n, and P-type devices are subsequently formed by semiconductor fin 204p. Semiconductor fin 204n is formed over n-type device region 200n and semiconductor fin 204p is formed over p-type device region 200p.

[0020] In some embodiments, a pad layer 206 and a mask layer 208 are deposited on a substrate 202, then patterned, and used as a mask to form a semiconductor fin 204. The pad layer 206 and mask layer 208 may be formed over the substrate 202 by blanket deposition. A patterned photosensitive layer (not shown) may then be formed over the mask layer 208. The pad layer 206 and mask layer 208 may be patterned using one or more photolithography processes with the patterned photosensitive layer. In some embodiments, dual-patterning or multi-patterning processes may be used to pattern the pad layer 206 and mask layer 208. The patterned pad layer 206 and mask layer 208 are then used as a mask to etch the substrate 202 to form the semiconductor fin 204. In some embodiments, the pad layer 206 may be a thin film comprising, for example, silicon oxide formed using a thermal oxidation process. The pad layer 206 may act as an adhesion layer between the substrate 202 and the mask layer 208. In some embodiments, the mask layer 208 includes silicon nitride, for example, silicon nitride formed using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0021] like Figure 2 As shown, semiconductor fins 204p and 204n extend from substrate 202 along the x-direction. Trench 210 (210s, 210n, 210l) are formed between adjacent semiconductor fins 204p and 204n. The trench 210 is formed along the x-direction. Figure 2 As shown, depending on the circuit design, trench 210 can have different widths along the y-direction. In some embodiments, hybrid fins or dielectric fins will be formed in some trenches 210. In some embodiments, hybrid fins can be used to provide electrical isolation between active regions of different devices. In other embodiments, hybrid fins are used to provide support for subsequently formed gate structures, particularly when providing support for sacrificial gate structures between wide trenches 210l. Trench 210l represents a wider trench in which hybrid fins are subsequently formed, while trenches 210s, 210n represent narrower trenches in which hybrid fins are not formed.

[0022] At operation 104 of method 100, an isolation layer 212 is deposited over semiconductor fin 204, such as Figure 3As shown. In some embodiments, mask layer 208 and pad layer 206 may be retained on semiconductor fin 204 during deposition of isolation layer 212. In some embodiments, isolation layer 212 may be deposited conformally to a target thickness such that narrow trenches 210n are filled by isolation layer 212, while trenches 210r are retained in wider trenches 210l. The dimensions of trenches 210r may be determined to suit the hybrid fins to be formed therein. Isolation layer 212 may be formed by high-density plasma chemical vapor deposition (HDP-CVD), CVD (CVD), atomic layer deposition (ALD), or other suitable deposition processes. In some embodiments, isolation layer 212 may comprise silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, or combinations thereof.

[0023] At operation 106 of method 100, a dielectric fin layer 214 is deposited over substrate 202, such as Figure 4 As shown, a dielectric fin layer 214 fills the trench 210r, such that dielectric fins or hybrid fins are formed in the trench 210r. In some embodiments, the dielectric fin layer 214 is formed by a suitable deposition process to fill the trench 210r.

[0024] The dielectric fin layer 214 may comprise a single layer of dielectric material or two or more layers of dielectric material continuously deposited therein. In some embodiments, the dielectric fin layer 214 may comprise a dielectric material having etch selectivity relative to the isolation layer 212. In some embodiments, the dielectric fin layer 214 may be silicon nitride (SiN), oxide nitride, silicon carbide (SiC), silicon oxynitride (SiON), oxide, SiO2, Si3N4, SiOCN, etc. The dielectric fin layer 214 may be formed by methods used to form such a layer, such as CVD, plasma-enhanced CVD, sputtering, or other suitable methods.

[0025] In some embodiments, the dielectric fin layer 214 may include a high-k dielectric material, such as a metal oxide, such as HfO2, ZrO2, or HfAlO. x HfSiO x The dielectric fin layer 214 can be formed by CVD, plasma-enhanced CVD, sputtering, and other suitable methods. In some embodiments, the dielectric fin layer 214 can be made of a high-k material other than a metallic dielectric material.

[0026] In some embodiments, the dielectric fin layer 214 includes an outer dielectric layer and an inner dielectric layer. The outer dielectric layer may be deposited first to cover the sidewalls of the trench 210r, and then the inner dielectric layer may be deposited over the outer dielectric layer. In some embodiments, the dielectric layer may be a silicon nitride (SiN), oxide oxynitride, silicon carbide (SiC), silicon oxynitride (SiON), oxide, SiO2, Si3N4, SiOCN, or a metal oxide layer. The inner dielectric layer may be a low-k dielectric layer, such as a silicon oxide layer.

[0027] In some embodiments, the dielectric fin layer 214 may include air gaps 216 formed therein. In some embodiments, air gaps 216 may be formed because the trench 210r has a high aspect ratio. During deposition, the openings of the trench 210r are squeezed closed before the trench 210r is completely filled, forming air gaps 216. Air gaps 216 may be desirable because they reduce the dielectric value of the dielectric fin layer 214, thus reducing RC delay. Figure 4 In the diagram, an air gap 216 with an elliptical cross-section is shown formed within each trench 210r. However, depending on the size of the trench 210r and the process used to deposit the dielectric fin layer 214, air gaps of various sizes and shapes may exist at different locations. In some embodiments, the air gap 216 may extend along the x-direction within the dielectric fin layer 214.

[0028] At operation 108 of method 100, a hybrid fin 218p, 218pn, and 218n (collectively referred to as 218) is formed adjacent to the semiconductor fin 204, such as Figure 5 and Figure 6 As shown. After filling trench 210r, a planarization process can be performed to expose semiconductor fins 204 and isolation layer 212, as... Figure 5 As shown. Then, an etch-back process is performed to expose portions of the hybrid fin 218 and the semiconductor fin 204, as shown. Figure 6 As shown. The etch-back process can be performed using a suitable anisotropic etching process to etch back the isolation layer 212 and expose portions of the semiconductor fins 204 and the hybrid fins 218.

[0029] After operation 108, semiconductor fin 204 and hybrid fin 218 extend from isolation layer 212. In some embodiments, after etch-back, semiconductor fin 204 and hybrid fin 218 have substantially the same height above the top surface 212t of isolation layer 212. In some embodiments, semiconductor fin 204 and hybrid fin 218 have a protruding fin height H1 above isolation layer 212. For example, the protruding fin height H1 may be defined by the distance between the top surface 214t of hybrid fin 218 and the top surface 212t of isolation layer 212. The protruding fin height H1 can vary depending on the circuit design. In some embodiments, the protruding fin height H1 is in the range of about 20 nm to about 100 nm. A portion of hybrid fin 218 is embedded in isolation layer 212. In some embodiments, the embedded fin height H0 of hybrid fin 218 is embedded in isolation layer 212. For example, the embedded fin height H0 may be defined by the distance between the bottom surface 214b of hybrid fin 218 and the top surface 212t of isolation layer 212. The hybrid fin 218 may have a width W1 along the y-direction. The width W1 of the hybrid fin 218 may vary depending on the circuit design. In some embodiments, the width W1 is in the range of about 10 nm to about 20 nm.

[0030] The hybrid fin 218 is essentially a strip extending along the x-direction. The hybrid fin 218 includes one or more dielectric fin layers 214. One or more air gaps 216 may be formed in the hybrid fin 218. In some embodiments, the air gaps 216 are located within the internal volume of the hybrid fin 218 and are along the x-direction.

[0031] Hybrid fin 218p is located in p-type device region 200p. Hybrid fin 218p can be located between or adjacent to two semiconductor fins 204p. Hybrid fin 218n is located in n-type device region 200n. Hybrid fin 218n can be located between or adjacent to two semiconductor fins 204n. Hybrid fin 218pn is located at the boundary between n-type device region 200n and p-type device region 200p. Hybrid fin 218pn is located between one semiconductor fin 204n and one semiconductor fin 204p.

[0032] At operation 110 of method 100, a sacrificial gate structure 226 is formed over the semiconductor fin 204, the hybrid fin 218, and the isolation layer 212, as shown below. Figure 7 and Figure 8 As shown in the diagram, a sacrificial gate dielectric layer 220 is conformally deposited over semiconductor fin 204, hybrid fin 218, and isolation layer 212. The sacrificial gate dielectric layer 220 may include silicon oxide, silicon nitride, combinations thereof, etc. The sacrificial gate dielectric layer 220 may be deposited or thermally grown according to acceptable techniques, such as thermal CVD, CVD, ALD, and other suitable methods.

[0033] A sacrificial gate electrode layer 222 is deposited on a sacrificial gate dielectric layer 220. The sacrificial gate electrode layer 222 comprises silicon, such as polycrystalline silicon, amorphous silicon, polycrystalline silicon germanium (poly-SiGe), etc. The sacrificial gate electrode layer 222 can be deposited using CVD, PVD, ALD, or other suitable processes, including LPCVD and PECVD. In some embodiments, a planarization process may be performed after the deposition of the sacrificial gate electrode layer 222.

[0034] Mask layer 224 continues to be deposited over sacrificial gate electrode layer 222. In some embodiments, a pad layer (not shown) may be deposited between mask layer 224 and sacrificial gate electrode layer 222. The pad layer may include silicon nitride. Mask layer 224 may include silicon oxide. Patterning operations are performed on mask layer 224, pad layer (if present), sacrificial gate electrode layer 222, and sacrificial gate dielectric layer 220 using one or more etching processes, such as one or more plasma etching processes or one or more wet etching processes, to form sacrificial gate structure 226. In some embodiments, mask layer 224 may be patterned first using a patterning process. The patterned mask layer 224 is then used as an etching mask to pattern sacrificial gate electrode layer 222. In some embodiments, sacrificial gate electrode layer 222 may be etched using anisotropic etching, such as reactive ion etching (RIE). Anisotropic etching has an etch rate along the Z direction that is greater than the etch rates along the X and Y directions. During the etching of the sacrificial gate electrode layer 222, the sacrificial gate dielectric layer 220 on the semiconductor fin 204 can act as an etch stop layer to prevent the etchant from removing the semiconductor fin 204.

[0035] In some embodiments, after patterning the sacrificial gate electrode layer 222, any exposed residual sacrificial gate dielectric layer 220 is removed by a suitable etching process. In some embodiments, the residual sacrificial gate dielectric layer 220 can be etched by adjusting one or more parameters, such as the etchant, etching temperature, etch solution concentration, etching pressure, source power, radio frequency (RF) bias voltage, and etchant flow rate of the etching process used to etch the sacrificial gate electrode layer 222. Figure 8 As shown, the sacrificial gate structure 226 covers a portion of the semiconductor fin 204 and the hybrid fin 218. The portion of the semiconductor fin 204 covered by the sacrificial gate structure 226 ultimately forms the channel region in the transistor.

[0036] In operation 112 of method 100, a sidewall spacer 228 is formed on the sidewall of the sacrificial gate structure 226, such as Figure 8 , Figure 8A and Figure 8B As shown. Figure 8A It is along Figure 8 A schematic cross-sectional view of semiconductor device 200 on line AA. Figure 8B It is along Figure 8 A schematic cross-sectional view of semiconductor device 200 on the BB line.

[0037] Sidewall spacers 228 are formed on the sidewalls of each sacrificial gate structure 226. After the sacrificial gate structure 226 is formed, the sidewall spacers 228 are formed by blanket deposition of one or more layers of insulating material. After the deposition of the insulating material, anisotropic etching is performed to remove portions of the insulating material from the horizontal surface. In some embodiments, the insulating material may also be removed from the sidewalls of the semiconductor fin 204. In some embodiments, portions of the sidewall spacers 228 may remain on the sidewalls of the semiconductor fin 204 (not shown). In some embodiments, the insulating material of the sidewall spacers 228 is a silicon nitride-based material, such as SiN, SiON, SiOCN, or SiCN, or combinations thereof. The sidewall spacers 228 may have a thickness in the range of about 4 nm to about 7 nm.

[0038] Figure 8A A cross-sectional view within the sacrificial gate structure 226 is schematically shown. Figure 8B A cross-sectional view within the 218pn hybrid fin is schematically shown. Figure 8B The image shows two additional sacrificial gate structures 226 to illustrate the arrangement of the sacrificial gate structures 226. (See image for details.) Figure 8B As shown, the air gap 216 within the hybrid fin 218 can extend through the hybrid fin 218 along the x-direction.

[0039] At operation 114 of method 100, a sacrificial spacer layer 230 is provided above the semiconductor device 200, such as... Figure 9 As shown. The sacrificial spacer layer 230 may be a dielectric layer used to protect areas not processed during subsequent source / drain formation. The sacrificial spacer layer 230 may be selected from any material with higher etch selectivity than the materials of semiconductor fin 204 and hybrid fin 218. In some embodiments, the sacrificial spacer layer 230 comprises silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof. In some embodiments, the sacrificial spacer layer 230 is formed by CVD, ALD, and / or other suitable techniques.

[0040] At operation 116 of method 100, the sacrificial spacer layer 230 is patterned to expose the hybrid fins 218pn separating the n-type device region 200n and the p-type device region 200p, and to expose one type of device region, such as the n-type device region 200n or the p-type device region 200p. Figure 10 and Figure 11As shown. A photoresist layer 232 can be formed over the sacrificial spacer layer 230. The photoresist layer 232 is then patterned and used as a mask to remove the sacrificial spacer layer 230 over the hybrid fin 218pn and a type of device region connected to the hybrid fin 218pn.

[0041] According to embodiments of this disclosure, a hybrid fin located between a device region to be processed and a device region to be covered is exposed and etched back during a semiconductor fin etch-back process. In some embodiments, the device region to be processed and the device region to be covered can be different types of device regions. In other embodiments, the device region to be processed and the device region to be covered can be the same type of device region. Figure 10A As shown, the photoresist layer 232 is patterned to expose the sacrificial spacer layer 230 above the hybrid fin 218pn and the n-type device region 200n. In some embodiments, the photoresist layer 232 may be patterned to expose partially untreated device regions. Figure 10 and Figure 10A In the middle, a small portion of the unprocessed device region (p-type device region 200p) is exposed by the patterned photoresist layer 232. Figure 10A It is along Figure 10 A schematic cross-sectional view of the semiconductor device 200 with the AA line in the middle. In some embodiments, the exposed portion of the untreated device region may have a width W2 along the y-direction or in a direction perpendicular to the length of the hybrid fin 218. In some embodiments, the width W2 may be in the range of about 0 nm and 20 nm. In some embodiments, the width W1 may be in the range of about 6 nm and 20 nm.

[0042] After the photoresist layer 232 is patterned, the sacrificial spacer layer 230 is patterned to expose the n-type device region 200n, the hybrid fin 218pn, and part of the p-type device region 200p, such as Figure 11 and Figure 11A As shown. Figure 11A It is along Figure 11 A schematic cross-sectional view of semiconductor device 200 on line AA.

[0043] At operation 118 of method 100, one or more etching processes are performed to etch back portions of the semiconductor fins 204 and hybrid fins 218 exposed by the sacrificial spacer layer 230, such as Figure 12 , Figure 12A and Figure 12B As shown. Figure 12A It is along Figure 12 A schematic cross-sectional view of semiconductor device 200 on line AA. Figure 12B It is along Figure 12 A schematic cross-sectional view of semiconductor device 200 on the BB line.

[0044] In some embodiments, the semiconductor fin 204n is recessed and etched to a desired level for subsequent formation of source / drain components therefrom. In some embodiments, the semiconductor fin 204n may be recessed to a level below the top surface 212t of the isolation layer 212, such as... Figure 12A As shown.

[0045] The exposed hybrid fins 218n and 218pn are also recessed and etched below the top surface 204t of the originally formed semiconductor fin 204. In some embodiments, the exposed hybrid fins 218n and 218pn may be etched back. As a result of the recessed etching, the hybrid fins 218n and 218pn have cut top surfaces 218nt and 218pnt, respectively, and vertical cut surfaces 218v. The vertical cut surface 218v is substantially flush with the sidewall spacer 228. The cut top surfaces 218nt and 218pnt may be located above the top surface 212t of the isolation layer 212 at a protruding fin height H2. The protruding fin height H2 may be selected to expose the hybrid fins 218n and 218pn above the landing plane of the source / drain contact components. In some embodiments, the air gap 216 formed in the hybrid fins 218n and 218pn may become open and exposed at the cut top surfaces 218nt and 218pnt and / or the vertical cut surface 218v.

[0046] Recessing can be performed using any suitable process, such as dry etching, wet etching, or combinations thereof. In some embodiments, etchants such as tetramethylammonium hydroxide (TMAH), CF4, CHF3, O2, H3, CH4, Ar, CH3F, HBr, He, or combinations thereof can be used to recess the material. For example, combinations such as CH4 plus Ar, CH3F plus O2 plus CH4, or HBr plus He can be used to recess the material. The etchant is selected so that different materials have different etching rates. For example, the semiconductor material of semiconductor fin 204n can have a first etching rate of the etchant, and the hybrid fins 218pn, 218pn can have a second etching rate of the etchant. The composition of the etchant can be selected to achieve the target height of semiconductor fin 204n and hybrid fins 218n, 218pn.

[0047] In some embodiments, after operation 112, the sidewall spacer 228 may remain on the semiconductor fin 204. In some embodiments, after recessed etching of the semiconductor fin 204, a portion of the sidewall spacer 228 may remain on the isolation layer 212. The height of the sidewall spacer 228 can be used to control the shape of the source / drain components to be formed.

[0048] At operation 120, the epitaxial source / drain component 234n is formed from the semiconductor fin 204n, as shown below. Figure 13 and Figure 13A As shown. Figure 13A It is along Figure 13 A schematic cross-sectional view of semiconductor device 200 on line AA.

[0049] In some embodiments, a pre-cleaning process may be performed to remove any unwanted silicon oxide formed due to oxidation of exposed surfaces. In some embodiments, the pre-cleaning process may be performed using inductively coupled plasma with a cleaning agent. In some embodiments, the cleaning agent includes Ar, NF3, and NH3. The pre-cleaning process may be performed for a time period between 80 seconds and about 400 seconds within a temperature range between about 25°C and about 74°C. Alternatively, the pre-cleaning process may be performed using an HF-based gas or a SiCoNi-based gas.

[0050] The epitaxial source / drain component 234n can be formed by any suitable method, such as by CVD, CVD epitaxy, molecular beam epitaxy (MBE), or any suitable deposition technique. The epitaxial source / drain component 234n may comprise one or more layers of Si, SiP, SiC, and SiCP. The epitaxial source / drain component 234n also includes an n-type dopant, such as phosphorus (P), arsenic (As), etc. In some embodiments, the epitaxial source / drain component 234n may be a Si layer including a phosphorus dopant. In some embodiments, the epitaxial source / drain component 234n comprises approximately 1E20 atoms / cm². 3 Approximately 5E21 atoms / cm 3 The dopant concentration between.

[0051] The shape and size of the epitaxial source / drain component 234n can be controlled by adjusting processing parameters and / or the height of the sidewall spacers (if present). In some embodiments, the cross-section of the epitaxial source / drain component 234n may have a wider middle portion and narrower upper and lower portions, such as an ellipse or hexagon. In some embodiments, the widest middle portion along the y-direction may have a center height H3 from the top surface 212t of the isolation layer 212. In some embodiments, the center height H3 may be greater than the protruding fin height H2 of the mixing fin 218.

[0052] At operation 122, the sacrificial spacer layer 230 is removed, as... Figure 14 As shown, the semiconductor fin 204p in the p-type device region 200p is exposed for processing. The sacrificial spacer layer 230 can be removed by any suitable etching method.

[0053] At operation 124, a sacrificial spacer layer 236 is deposited by blanket deposition, such as... Figure 15As shown. The sacrificial spacer layer 236 can be a dielectric layer used to protect regions not processed during subsequent processing operations. For example, the sacrificial spacer layer 236 would protect the epitaxial source / drain structure 234n. Similar to the sacrificial spacer layer 230, the sacrificial spacer layer 236 can be selected from silicon nitride, silicon oxide, silicon oxynitride, or combinations thereof. In some embodiments, the sacrificial spacer layer 236 is formed by CVD, ALD, and / or other suitable techniques.

[0054] At operation 126 of method 100, the sacrificial spacer layer 236 is patterned to expose the p-type device region 200p, as shown. Figure 16 and Figure 17 As shown, a photoresist layer 238 is formed over the sacrificial spacer layer 236. The photoresist layer 238 is then patterned and used as a mask to remove a portion of the sacrificial spacer layer 236 over the p-type device region 200p to expose the semiconductor fins 204p and the hybrid fins 218p. After the photoresist layer 238 is patterned, the pattern is transferred to the sacrificial spacer layer 236 using a suitable etching method.

[0055] In some embodiments, the hybrid fins 218pn between the p-type device region 200p and the n-type device region 200n are still covered by the sacrificial spacer layer 236, as... Figure 17 As shown. The hybrid fin 218pn ensures that the epitaxial source / drain component 234n is protected by the sacrificial spacer layer 236, especially when a portion of the epitaxial source / drain component 234n extends over the hybrid fin 218pn.

[0056] At operation 128 of method 100, one or more etching processes are performed to etch back portions of the semiconductor fins 204 and hybrid fins 218 exposed by the sacrificial spacer layer 236, such as Figure 18 As shown.

[0057] In some embodiments, semiconductor fin 204p is recessed and etched to a desired level for subsequent formation of source / drain components therefrom. In some embodiments, semiconductor fin 204p may be recessed to a level below the top surface 212t of isolation layer 212. Exposed hybrid fin 218p is also recessed and etched below the top surface 204t of the originally formed semiconductor fin 204. The recessing can be performed by any suitable process such as dry etching, wet etching, or a combination thereof. In some embodiments, exposed hybrid fin 218p may be etched to a protruding fin height H4 above the top surface 212t of isolation layer 212. For example, the protruding fin height H4 may be defined by the distance between the cut top surface 218pt of hybrid fin 218p and the top surface 212t of isolation layer 212. In some embodiments, the recessed etching may be similar to the etching method used at operation 118.

[0058] At operation 130 of method 100, the epitaxial source / drain component 234p is formed from the semiconductor fin 204p, as... Figure 19 As shown. In some embodiments, a pre-cleaning process may be performed to remove any unwanted silicon oxide formed due to oxidation of the exposed surface. The epitaxial source / drain component 234p can be formed by any suitable method, such as by CVD, CVD epitaxy, molecular beam epitaxy (MBE), or any suitable deposition technique. The epitaxial source / drain component 234p may comprise one or more layers of Si, SiGe, Ge having a p-type dopant (such as boron (B)) for use in p-type devices such as pFETs. In some embodiments, the epitaxial source / drain component 234p may be a SiGeB material, wherein boron is the dopant. In some embodiments, the epitaxial source / drain component 234p has a density of approximately 5E18 atoms / cm². 3 Approximately 1E21 atoms / cm 3 The SiGeB layer with varying boron concentrations.

[0059] The shape and size of the epitaxial source / drain component 234p can be controlled by adjusting processing parameters and / or the height of the sidewall spacers (if present). In some embodiments, the cross-section of the epitaxial source / drain component 234p may have a wider middle portion and narrower upper and lower portions, such as a hexagon or ellipse. In some embodiments, the widest middle portion along the y-direction may have a center height H5 from the top surface 212t of the isolation layer 212. In some embodiments, the widest middle portion appears near the center of the semiconductor fin 204. The center height H5 is approximately 50% of the protruding fin height H1. In some embodiments, the center height H5 may be greater than the protruding fin height H4 of the hybrid fin 218p and the protruding fin height H2 of the hybrid fin 218pn.

[0060] At operation 132 of method 100, the sacrificial spacer layer 236 is removed, as follows: Figure 20 As shown. The hybrid fins 218p, 218pn, and 218n, as well as the epitaxial source / drain components 234n and 234p, are exposed for subsequent processing. The sacrificial spacer layer 236 can be removed by any suitable etching method.

[0061] At operation 134 of method 100, a contact etch stop layer (CESL) 240 is deposited over semiconductor device 200, as follows: Figure 21 , Figure 21A , Figure 21B and Figure 21C As shown. Figure 21A It is along Figure 21 A schematic cross-sectional view of semiconductor device 200 on line AA. Figure 21B It is along Figure 21A schematic cross-sectional view of semiconductor device 200 on the BB line. Figure 21C It is along Figure 21 A schematic cross-sectional view of the semiconductor device 200 with a CC line. The CESL240 is conformally formed above the exposed surface of the semiconductor device 200. (See diagram) Figure 21 As shown, CESL240 covers the exposed surfaces of epitaxial source / drain components 234n, 234p, hybrid fins 218n, 218p, 218pn, isolation layer 212, and sidewall spacers 228. CESL240 may comprise SiN, SiON, SiCN, or any other suitable material, and may be formed by CVD, PVD, or ALD.

[0062] In some embodiments, the CESL240 may have a thickness T1 on the exposed surfaces of the epitaxial source / drain components 234n, 234p. In some embodiments, the thickness T1 of the CESL240 on the epitaxial source / drain components 234n, 234p may be maintained at a sufficient value to protect the epitaxial source / drain components 234n, 234p during the contact hole etching process. In some embodiments, the thickness T1 may be in the range of about 1 nm to about 10 nm.

[0063] like Figure 21A and Figure 21B As shown, an air gap 242 can be formed between the epitaxial source / drain components 234n, 234p and the mixing fins 218n, 218p, 218pn disposed adjacent to the epitaxial source / drain components 234n, 234p. The air gap 242 is formed during the deposition of the CESL 240 layer when the inlet to the space between the epitaxial source / drain components 234n, 234p and the mixing fins 218n, 218p, 218pn is squeezed shut. Depending on the size and shape of the epitaxial source / drain components 234n, 234p and the adjacent mixing fins 218n, 218p, and 218pn, the CESL 240 around the air gap 242 can be thinner than the thickness T1. Alternatively, the CESL 240 can fill the space between the epitaxial source / drain components 234n, 234p and the adjacent mixing fins 218, without forming any air gap between them. In some embodiments, the air gap 242 may be formed during the formation of the epitaxial source / drain components 234n, 234p, so no CESL material is disposed within the air gap 242.

[0064] like Figure 21A and Figure 21BAs shown, CESL240 can be deposited on the cut top surfaces 218nt, 218pnt, 218pt and the vertical cut surface 218v of the hybrid fins 218n, 218pn, and 218p. CESL240 can seal any air gaps 216 exposed in the cut top surfaces 218nt, 218pnt, 218pt and the vertical cut surface 218v. Because the cut top surfaces 218nt, 218pnt, 218pt of the hybrid fins 218 are at a level below the widest portions of the epitaxial source / drain components 234n, 234p, the CESL240 deposited on the widest portions of the epitaxial source / drain components 234n, 234p is also located above the cut top surface 218h of the hybrid fins 218. Therefore, the recessed hybrid fins 218 can have an additional layer for protection by the CESL240. In other words, the CESL240 disposed above the cut top surfaces 218nt, 218pnt, and 218pt can have a thickness greater than the thickness T1. For example, the CESL240 can have a thickness T2 above the cut top surfaces 218nt, 218pnt, and 218pt. In some embodiments, the ratio between thickness T2 and thickness T1 can be in the range of 1.5 to 6.0. A ratio less than 2.0 allows the CESL240 to seal the air gap 216 in the hybrid fin 218 below during etching when forming contact holes. A ratio greater than 4.0 may increase RC delay without providing additional benefit for sealing protection.

[0065] In some embodiments, depending on the size and geometry of the space between the epitaxial source / drain components 234n, 234p and the hybrid fin 218pn, and the deposition parameters of the CESL240, an air gap 244 may be formed over the CESL240 region. Alternatively, the air gap 244 may exist within the CESL240 above the hybrid fin 218.

[0066] At operation 136 of method 100, an interlayer dielectric (ILD) layer 246 is formed above CESL 240, such as... Figure 22 As shown. Materials used for the ILD layer 246 include compounds comprising Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials such as polymers can be used for the ILD layer 246. In some embodiments, the ILD layer 246 can be formed by flowable CVD (FCV). The ILD layer 246 protects the epitaxial source / drain components 234n, 234p during the removal of the sacrificial gate structure 226. After depositing the ILD layer 246, a planarization process can be performed to expose the sacrificial gate structure 226 for subsequent replacement gate processes.

[0067] At operation 138 of method 100, the sacrificial gate structure 226 is removed, and a gate cavity 226v is formed between the sidewall spacers 228, as shown. Figure 23 As shown. The sacrificial gate dielectric layer 220 and the sacrificial gate electrode layer 222 are removed by one or more suitable processes such as dry etching, wet etching, or a combination thereof to expose the semiconductor fin 204. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution is used. Figure 23A It is along Figure 23 A schematic cross-sectional view of the semiconductor device 200 along the AA line. (See attached diagram.) Figure 21A As shown, the hybrid fins 218p, 218pn, and 218n in the gate cavity 226v essentially maintain the protruding fin height H1.

[0068] At operation 140 of method 100, a replacement gate structure 252 is formed, such as Figure 24 , Figure 24A , Figure 24B , Figure 24C As shown. Figure 24A It is along Figure 24 A schematic cross-sectional view of semiconductor device 200 on line AA. Figure 24B It is along Figure 24 A schematic cross-sectional view of semiconductor device 200 on the BB line. Figure 24C It is along Figure 24 A schematic cross-sectional view of the semiconductor device 200 with a middle CC line. The alternative gate structure 252 may include a gate dielectric layer 248 and a gate electrode layer 250.

[0069] The gate dielectric layer 248 can be conformally deposited on the exposed surface in the gate cavity 226V. For N-type and P-type devices, the gate dielectric layer 248 can have different compositions and sizes, and can be formed using patterned mask layers and different deposition formulations. The gate dielectric layer 248 may include one or more dielectric materials, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 248 can be formed by CVD, ALD, or any suitable method.

[0070] A gate electrode layer 250 is then formed on the gate dielectric layer 248 to fill the gate cavity 226v. The gate electrode layer 250 may comprise one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. In some embodiments, the gate electrode layer 250 may be formed by CVD, ALD, electroplating, or other suitable methods. After forming the gate electrode layer 250, a planarization process, such as a CMP process, is performed to remove excess deposition of the gate electrode material and expose the top surface of the ILD layer 246.

[0071] At operation 142 of method 100, a dielectric structure 254 is formed in the replacement gate structure 252, such as Figure 25 and Figure 25A As shown. Figure 25A It is along Figure 25 A schematic cross-sectional view of the semiconductor device 200 with AA line shown. Dielectric structure 254 includes a dielectric material and serves to divide the gate electrode layer 250 into electrically isolated portions. In some embodiments, dielectric structure 254 is connected to one of the hybrid fins 218, and the gate electrode layer 250 is divided into electrically isolated portions by dielectric structure 254 and the hybrid fins 218 connected to dielectric structure 254, such as... Figure 25A As shown. Alternatively, dielectric structure 254 can extend from the top surface 212t of isolation layer 212 to the top of replacement gate structure 252.

[0072] One or more etching processes are performed to remove portions of the gate dielectric layer 248 and the gate electrode layer 250 to divide the replacement gate structure 252 into two or more portions along the y-direction. The etching process may be a plasma etching process employing one or more etchants such as chlorine-containing gases, bromine-containing gases, and / or fluorine-containing gases. The etching process allows selective etching of the gate dielectric layer 248 and the gate electrode layer 250 from the ILD layer 246 and CESL 240. The gate dielectric layer 248 and the gate electrode layer 250 are etched back to a level below the top surface 218t of the hybrid fin 218, parallel to the semiconductor fin 204.

[0073] The dielectric structure 254 is formed by filling trenches in the gate structure 252 through one or more deposition processes and then by a planarization process to expose the gate electrode layer 250. The dielectric structure 254 may include one or more layers of dielectric material. In some embodiments, the dielectric structure 254 may include silicon nitride, silicon oxynitride, silicon carbide, etc., formed by PVD, CVD, ALD, or other suitable deposition methods.

[0074] At operation 144 of method 100, contact holes 255, 256 for epitaxial source / drain contact components 260 and / or epitaxial source / drain contact components 262 are formed by one or more patterning and suitable etching processes, such as Figure 26 As shown. At operation 144, contact holes 255 and 256 are formed by one or more patterning and etching processes to remove portions of the ILD layer 246 and expose the CESL 240 covering the epitaxial source / drain components 234n and 234p to be connected. Contact holes 255 and 256 may be intended to form contact components connecting a single source / drain component or joint contact components connecting two or more epitaxial source / drain components.

[0075] exist Figure 26 In this embodiment, contact hole 256 is designed to form a joint contact for connecting epitaxial source / drain components 234n and 234p disposed on opposite sides of the hybrid fin 218pn. In some embodiments, after operation 144, a portion of CESL 240 above the epitaxial source / drain components 234n, 234p and the hybrid fin 218pn is exposed to contact hole 256.

[0076] At operation 146 of method 100, CESL240 is removed and the epitaxial source / drain components 234n and 234p are etched back to create a contact landing plane, as shown. Figure 27 As shown.

[0077] In some embodiments, the CESL240 may be removed first using a suitable etching process. In some embodiments, the CESL240 may be etched using anisotropic etching. As discussed above, because the hybrid fin 218pn has been etched back to the level below the widest portion of the epitaxial source / drain components 234n, 234p, the CESL240 above the cut top surface 218pnt of the hybrid fin 218pn has a greater thickness than the CESL240 on other portions of the epitaxial source / drain components 234n, 234p. The thicker CESL240 above the hybrid fin 218pn ensures that the hybrid fin 218pn remains covered by the CESL240 after the epitaxial source / drain components 234n, 234p are exposed to the contact hole 256.

[0078] After removing CESL240 from the epitaxial source / drain components 234n, 234p, portions of the epitaxial source / drain components 234n, 234p are then removed to create contact surfaces in the epitaxial source / drain components 234n, 234p. In some embodiments, the epitaxial source / drain components 234n, 234p can be etched along the z-direction using an anisotropic etching method. The contact surface in each of the epitaxial source / drain components 234n, 234p may include horizontal portions 234nl, 234pl that are substantially parallel to the xy-plane, and various non-horizontal surfaces depending on the location and shape of the contact hole 256 and the shape of the epitaxial source / drain components 234n, 234p. The horizontal portions 234nl, 234pl may be referred to as landing planes. The horizontal portions 234nl, 234pl of the epitaxial source / drain components 234n, 234p may be at substantially the same level in the z-direction. The horizontal portions 234nl and 234pl can be selected to increase the contact area. In some embodiments, the horizontal portions 234nl and 234pl, i.e., the landing plane, can be a landing height H6 from the top surface 212t of the isolation layer 212. In some embodiments, the landing height H6 of the landing plane is higher than the protruding fin height H4 of the recessed hybrid fins 218pn, 218p, and 218n. In some embodiments, the landing height H6 of the landing plane can be higher than the center height H5 of the widest portion of the epitaxial source / drain components 234n and 234p.

[0079] At operation 148 of method 100, source / drain contact components 260 and 262 are formed in contact holes 255 and 256, such as Figure 28 , Figure 28A , Figure 28B and Figure 28C As shown. Figure 28A It is along Figure 28 A schematic cross-sectional view of the semiconductor device 200 along the AA line. Figure 28B It is along Figure 28 A schematic cross-sectional view of the semiconductor device 200 with the BB line in the diagram. Figure 28C It is along Figure 28 A schematic cross-sectional view of the semiconductor device 200 with the CC line in the diagram.

[0080] In some embodiments, a silicide layer 258 is selectively formed over the exposed surfaces of the epitaxial source / drain components 234n, 234p exposed by the source / drain contact holes. In some embodiments, the silicide layer 258 is formed on the contact surface. In some embodiments, the silicide layer 258 comprises one or more of WSi, CoSi, NiSi, TiSi, MoSi, and TaSi.

[0081] The source / drain contact components 260 and 262 are then formed by filling the contact holes 255 and 256 with conductive material. In some embodiments, the conductive material layer for the source / drain contact components can be formed by CVD, PVD, electroplating, ALD, or other suitable techniques. In some embodiments, the conductive material for the source / drain contact components 260 and 262 includes TiN, TaN, Ta, Ti, Hf, Zr, Ni, W, Co, Cu, Ag, Al, Zn, Ca, Au, Mg, Mo, Cr, etc. Subsequently, a CMP process is performed to remove a portion of the conductive material layer above the top surface of the ILD layer 246.

[0082] like Figure 28A As shown, the source / drain contact component 260 connected to the epitaxial source / drain components 234p and 234n may have a bottom surface 260b, which includes at least three portions 260bn, 260bp, and 260bh. Portion 260bn contacts the epitaxial source / drain component 234n, portion 260bp contacts the epitaxial source / drain component 234p, and portion 260bh is located above the hybrid fin 218pn. Portion 260bh may contact a portion of the CESL 240 located between portion 260bp and the hybrid fin 218pn. In some embodiments, portion 260bh is at a level below portions 260bn and 260bp.

[0083] like Figure 28B As shown, the hybrid fin 218pn located between the p-type epitaxial source / drain component 234p and the n-type epitaxial source / drain component 234n has two heights. In some embodiments, the hybrid fin 218pn below the gate has a first protruding fin height H1 from the top surface 212t of the isolation layer 212. The hybrid fin 218pn outside the gate structure has a second protruding height H4 from the top surface of the isolation layer 212t. The hybrid fin 218pn is higher below the gate structure and lower between the external gate structures, or the first protruding height is higher than the second protruding height. In some embodiments, the cut top surface 218pnt is below the midpoint of the semiconductor fin 204, or below the widest portion of the epitaxial source / drain component 234. In some embodiments, the second height is less than 50% of the first height. Because the cut-out top surface 218pnt of the hybrid fin 218pn is lower than the middle portion of the semiconductor fin 204, the contact holes for source / drain contact components (such as source / drain contact component 260) do not expose the hybrid fin 218pn. As a result, when the contact holes are filled with conductive material, the conductive material will not fill any air gaps in the hybrid fin 218pn.

[0084] The portion of the hybrid fin 218 below the gate structure and the portion of the hybrid fin 218 outside the gate structure are connected by a vertically diced surface 218v. The vertically diced surface 218v of the hybrid fin 218 contacts the CESL 240. The hybrid fin 218pn outside the gate structure is defined by a diced top surface 218pnt. In some embodiments, the diced top surface 218pnt contacts the CESL 240. In some embodiments, the thickness of the portion of the CESL 240 on the hybrid fin 218pn is greater than the thickness of the CESL 240 on the epitaxial source / drain components 234n, 234p. In some embodiments, as Figure 28B As shown, the CESL240 above the hybrid fin 218pn includes an air gap.

[0085] Figure 29 , Figure 29A , Figure 29B , Figure 29C A semiconductor device 200a according to this disclosure is schematically shown. The semiconductor device 200a is substantially similar to... Figure 28 Semiconductor device 200, except that there is no air gap in CESL240. Similar to semiconductor device 200, semiconductor device 200a can be manufactured using method 100.

[0086] Figures 30-33 Various stages of a semiconductor device 200b according to an embodiment of the present disclosure are illustrated. The semiconductor device 200b can be manufactured using the method 100 discussed above. The semiconductor device 200b is similar to the semiconductor device 200, wherein the epitaxial source / drain components of the semiconductor device 200b have different shapes than the epitaxial source / drain components of the semiconductor device 200. Figure 30 This is a schematic perspective view of semiconductor device 200b after operation 132. (See diagram.) Figure 30 As shown, the epitaxial source / drain components 234p and 234n do not extend above the hybrid fin 218. Figure 31 This is a schematic perspective view of the semiconductor device 200b after operation 134, in which CESL240 is deposited. Because the epitaxial source / drain components 234p, 234n are further away from the cut top surface 218pnt of the mixed fin 218pn, CESL240 is formed on only a single thickness T1 thereon.

[0087] Figure 32This is a schematic perspective view of the semiconductor device 200b after operation 144, wherein the ILD layer 246 is removed to form contact holes 255, 256. The ILD layer 246 is removed down to a level 246h at a height H7 above the cut top surface 218pnt of the hybrid fin 218pn. Height H7 is a thickness sufficient to protect the CESL 240 during operation 148. In some embodiments, height H7 is in the range of about 10 nm and 30 nm.

[0088] Figure 33 This is a schematic perspective view of the semiconductor device 200b after operation 148, in which source / drain contact components 260 and 262 are formed. Figure 33A It is along Figure 33 A cross-sectional view of semiconductor device 200b with line AA. Figure 33B It is along Figure 33 A cross-sectional view of the semiconductor device 200b of line BB.

[0089] like Figure 33 As shown, a portion 260bh of the bottom surface 260b of the source / drain contact component 260 is located above the hybrid fin 218pn. The portion 260bh is in contact with the ILD layer 246 located between the portion 260bp and the hybrid fin 218pn.

[0090] like Figure 33A As shown, the hybrid fin 218pn located between the p-type epitaxial source / drain component 234p and the n-type epitaxial source / drain component 234n has two heights. In some embodiments, the hybrid fin 218pn is higher below the gate structure and lower between the external gate structures. The vertical cleaved surface 218v of the hybrid fin 218 contacts the CESL 240. In some embodiments, the cleaved top surface 218pnt contacts the CESL 240. In some embodiments, the CESL 240 portion on the hybrid fin 218pn has substantially the same thickness as the CESL 240 on the epitaxial source / drain components 234n and 234p.

[0091] Figures 34-40 Various stages of a semiconductor device 200c according to an embodiment of the present disclosure are illustrated. The semiconductor device 200c can be manufactured using a manufacturing method that does not etch back the mixed fins 218pn located between the n-type device region 200n and the p-type device region 200p during the formation of epitaxial source / drain components 234n, 234p.

[0092] Figure 34 This is a schematic perspective view of the semiconductor device 200c during operation 116, wherein the photoresist layer 232 is patterned to remove portions of the exposed n-type device region 200n, which is used for further processing. Figure 34 As shown, the photoresist layer 232 is patterned to expose the sacrificial spacer layer 230 above the n-type device region 200n, while the hybrid fin 218pn is not exposed.

[0093] Figure 35 This is a schematic perspective view of the semiconductor device 200c after operation 132. The hybrid fin 218pn retains the original protruding fin height H1. Figure 36 This is a schematic perspective view of the semiconductor device 200c after operation 134, where the CESL240 is positioned above the exposed surface. The hybrid fin 218pn is covered by the CESL240.

[0094] Figure 37 This is a schematic perspective view of the semiconductor device 200c after operation 144, where the ILD layer 246 is removed to form contact holes 255, 256. The ILD layer 246 is etched back to level 246h. The hybrid fin 218pn, along with CESL 240, partially extends beyond level 246h.

[0095] Figure 38 This is a schematic perspective view of the semiconductor device 200c after operation 146, in which an etching process is performed to remove the exposed CESL240 to expose the epitaxial source / drain components 234n, 234p. During the removal of CESL240, the hybrid fin 218pn may also be partially etched to cut the top surface 218pnt' to expose the air gap 216.

[0096] According to embodiments of this disclosure, a deposition process can be performed after operation 146 and before operation 148, followed by an etch-back process to fill the air gaps 216 in the hybrid fin 218pn with dielectric filling material 264, such as... Figure 39 As shown. In some embodiments, the dielectric filling material 264 may be silicon nitride (SiN), oxide nitride, silicon carbide (SiC), silicon oxynitride (SiON), oxide, SiO2, Si3N4, SiOCN, etc. In some embodiments, the dielectric filling material 264 may include high-k dielectric materials, such as metal oxides, such as HfO2, ZrO2, HfAlO x HfSiO x The dielectric filling material 264 can be formed by methods used to form such a layer, such as CVD, plasma-enhanced CVD, sputtering or other suitable methods to fill or at least partially fill the air gap 216.

[0097] Following the deposition process, an etching process is performed to remove any excess dielectric filler material 264 outside the air gap 216. Any suitable etching method can be used to remove the excess dielectric filler material 264.

[0098] In some embodiments, an over-etching process may be performed on the epitaxial source / drain components 234n, 234p to create contact surfaces in the epitaxial source / drain components 234n, 234 for operation of the process at 148.

[0099] Figure 40 This is a schematic perspective view of the semiconductor device 200c after operation 148, in which source / drain contact components 260 and 262 are formed. Figure 40A It is along Figure 40 A cross-sectional view of the semiconductor device 200c with line AA. Figure 40B It is along Figure 40 A cross-sectional view of the semiconductor device 200c of line BB.

[0100] like Figure 40 As shown, the top portion of the hybrid fin 218pn extends from a portion 260bh of the bottom surface 260b into the source / drain contact portion 260. The exposed air gaps in the hybrid fin 218pn are filled with a dielectric filler material 264. The top portion of the hybrid fin 218pn is in direct contact with the source / drain contact portion 260. Because the air gaps on the surface of the hybrid fin 218pn are filled with the dielectric filler material 264, the dielectric filler material 264 prevents conductive material from entering the interior of the hybrid fin 218pn, particularly the interior portion below the gate structure.

[0101] By recessing a portion of the hybrid fin located between two different epitaxial source / drain components, embodiments of this disclosure prevent conductive material from entering the internal air gap of the hybrid fin, thereby preventing short circuits between the source / drain contacts and the gate electrode. This recessing of the hybrid fin can be achieved by expanding the mask during semiconductor fin etch-back, thus without increasing manufacturing costs.

[0102] It should be understood that not all advantages need to be discussed herein, all embodiments or examples do not require specific advantages, and other embodiments or examples may provide different advantages.

[0103] Some embodiments of this disclosure provide a semiconductor device including an isolation layer having a top surface; a first epitaxial source / drain component extending beyond the top surface from the isolation layer, wherein the first epitaxial source / drain component is used for an n-type device; a second epitaxial source / drain component extending beyond the top surface from the isolation layer, wherein the second epitaxial source / drain component is used for a p-type device; a hybrid fin disposed between the first epitaxial source / drain component and the second epitaxial source / drain component, wherein the hybrid fin has a first end embedded in the isolation layer and a second end extending beyond the top surface of the isolation layer; and a source / drain contact component electrically contacting the first and second epitaxial source / drain components on a bottom surface, wherein the bottom surface of the source / drain contact component is above the second end of the hybrid fin.

[0104] Some embodiments of this disclosure provide a semiconductor device including a first semiconductor fin; a second semiconductor fin; a first epitaxial source / drain component electrically contacting the first semiconductor fin, wherein the first epitaxial source / drain component is doped with an n-type dopant; a second epitaxial source / drain component electrically contacting the second semiconductor fin, wherein the second epitaxial source / drain component is doped with a p-type dopant; a hybrid fin disposed between the first and second semiconductor fins and between the first and second epitaxial source / drain components; and a gate structure disposed above the first semiconductor fin, the second semiconductor fin, and the hybrid fin, wherein the hybrid fin has a first top surface below the gate structure, a second top surface between the first and second epitaxial source / drain components, and the second top surface is lower than the first top surface.

[0105] Some embodiments of the present invention provide a method for manufacturing a semiconductor device, including forming a first semiconductor fin, a second semiconductor fin, and a hybrid fin between the first and second semiconductor fins; recess-etching the first semiconductor fin and the hybrid fin while covering the second semiconductor fin with a first mask; forming a first epitaxial source / drain component connected to the first semiconductor fin, and doping the first epitaxial source / drain component with an n-type dopant; recess-etching the second semiconductor fin while covering the hybrid fin and the first semiconductor fin with a second mask; and forming a second epitaxial source / drain component connected to the second semiconductor fin, and doping the second epitaxial source / drain component with a p-type dopant.

[0106] According to embodiments of this application, a semiconductor device is provided, comprising: an isolation layer having a top surface; a first epitaxial source / drain component extending beyond the top surface from the isolation layer, wherein the first epitaxial source / drain component is used for an n-type device; a second epitaxial source / drain component extending beyond the top surface from the isolation layer, wherein the second epitaxial source / drain component is used for a p-type device; a hybrid fin disposed between the first epitaxial source / drain component and the second epitaxial source / drain component, wherein the hybrid fin has a first end embedded in the isolation layer and a second end extending beyond the top surface of the isolation layer; and a source / drain contact component connected to the first and second epitaxial source / drain components at a bottom surface, wherein the bottom surface of the source / drain contact component is above the second end of the hybrid fin. In some embodiments, the semiconductor device further comprises: a contact etch stop layer (CESL) disposed between the bottom surface of the source / drain contact component and the second end of the hybrid fin. In some embodiments, the contact etch stop layer contacts the second end of the hybrid fin. In some embodiments, the contact etch stop layer contacts the bottom surface of the source / drain contact component. In some embodiments, the semiconductor device further includes an interlayer dielectric layer between the bottom surface of the source / drain contact and the contact etch stop layer. In some embodiments, the first epitaxial source / drain component has a first height extending from the top surface of the isolation layer, the second end of the hybrid fin has a second height from the top surface of the isolation layer, and the second height is less than 50% of the first height. In some embodiments, the semiconductor device further includes a gate structure disposed adjacent to the first and second epitaxial source / drain components, wherein the hybrid fin extends below the gate structure, and the top surface of the portion of the hybrid fin below the gate structure is higher than the top surface of the second end of the hybrid fin.

[0107] According to another embodiment of this application, a semiconductor device is provided, comprising: a first semiconductor fin; a second semiconductor fin; a first epitaxial source / drain component connected to the first semiconductor fin, wherein the first epitaxial source / drain component is doped with an n-type dopant; a second epitaxial source / drain component connected to the second semiconductor fin, wherein the second epitaxial source / drain component is doped with a p-type dopant; a hybrid fin disposed between the first and second semiconductor fins and between the first and second epitaxial source / drain components; and a gate structure disposed above the first semiconductor fin, the second semiconductor fin, and the hybrid fin, wherein the hybrid fin has a first top surface below the gate structure, a second top surface between the first and second epitaxial source / drain components, and the second top surface is lower than the first top surface. In some embodiments, the first top surface is located at a first height from the top surface of an isolation layer, the second top surface is located at a second height from the top surface of the isolation layer, and the second height is less than 50% of the first height. In some embodiments, the semiconductor device further comprises a contact etch stop layer disposed on the first and second epitaxial source / drain components and on the hybrid fin between the first and second epitaxial source / drain components. In some embodiments, the semiconductor device further includes source / drain contact components disposed on the first and second epitaxial source / drain components, wherein a portion of the contact etch stop layer is disposed between the source / drain contact component and the hybrid fin. In some embodiments, the semiconductor device further includes an interlayer dielectric layer, wherein a portion of the interlayer dielectric layer is disposed above the contact etch stop layer and the source / drain contact. In some embodiments, the hybrid fin includes: a dielectric fin layer having one or more air gaps; and a dielectric filling layer disposed in the one or more air gaps.

[0108] According to another embodiment of this application, a method for manufacturing a semiconductor device is provided, comprising: forming a first semiconductor fin, a second semiconductor fin, and a hybrid fin between the first and second semiconductor fins; recess-etching the first semiconductor fin and the hybrid fin while the second semiconductor fin is covered by a first mask; forming a first epitaxial source / drain component connected to the first semiconductor fin, and doping the first epitaxial source / drain component with an n-type dopant; recess-etching the second semiconductor fin, wherein the hybrid fin and the first semiconductor fin are covered by a second mask; and forming a second epitaxial source / drain component connected to the second semiconductor fin, and doping the second epitaxial source / drain component with a p-type dopant. In some embodiments, the method for manufacturing a semiconductor device further comprises: depositing a contact etch stop layer over the first and second epitaxial source / drain components and the hybrid fin; and depositing an interlayer dielectric layer over the contact etch stop layer. In some embodiments, the method for manufacturing a semiconductor device further comprises: forming contact holes in the interlayer dielectric layer over the first and second epitaxial source / drain components.

[0109] In some embodiments, the method for manufacturing a semiconductor device further includes etching a contact etch stop layer from first and second epitaxial source / drain components. In some embodiments, forming the first semiconductor fin, the second semiconductor fin, and the hybrid fin includes forming the first semiconductor fin, the second semiconductor fin, and the hybrid fin to a first protrusion height from the top surface of the isolation layer. In some embodiments, the method for manufacturing a semiconductor device further includes forming a gate structure over the first semiconductor fin, the second semiconductor fin, and the hybrid fin. In some embodiments, recessed etching of the first semiconductor fin and the hybrid fin includes recessing the hybrid fin to a second protrusion height from the top surface of the isolation layer, wherein the second protrusion height is less than 50% of the first protrusion height.

[0110] According to this disclosure, the hybrid fin, located between two distinct epitaxial source / drain components, is recessed to prevent conductive material from entering the internal air gap of the hybrid fin, thereby preventing a short circuit between the source / drain contact and the gate electrode. This hybrid fin recess can be achieved by expanding the mask during semiconductor fin etch-back, thus without increasing manufacturing costs.

[0111] The foregoing outlines components of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: An isolation layer with a top surface; A first epitaxial source / drain component extends from the isolation layer beyond the top surface, wherein the first epitaxial source / drain component is used for an n-type device; A second epitaxial source / drain component extends from the isolation layer beyond the top surface, wherein the second epitaxial source / drain component is used for a p-type device; A hybrid fin is disposed between the first epitaxial source / drain component and the second epitaxial source / drain component, wherein the hybrid fin has a first end embedded in the isolation layer and a second end extending beyond the top surface of the isolation layer; Source / drain contact components are connected to the first and second epitaxial source / drain components at their bottom surfaces, wherein the bottom surfaces of the source / drain contact components are above the second end of the hybrid fin; as well as A contact etch stop layer is disposed on the first epitaxial source / drain component, the second epitaxial source / drain component, and the second end of the hybrid fin, wherein the contact etch stop layer on the first epitaxial source / drain component, the second epitaxial source / drain component, and the second end of the hybrid fin closes to form an air gap.

2. The semiconductor device of claim 1, wherein, A portion of the first epitaxial source / drain component and a portion of the second epitaxial source / drain component are located above the second end of the hybrid fin.

3. The semiconductor device according to claim 1, wherein, The contact etch stop layer contacts the second end of the hybrid fin.

4. The semiconductor device according to claim 3, wherein, The contact etch stop layer is in contact with the bottom surface of the source / drain contact component.

5. The semiconductor device of claim 3, further comprising an interlayer dielectric layer between the bottom surface of the source / drain contact component and the contact etch stop layer.

6. The semiconductor device of claim 1, wherein the first epitaxial source / drain component has a first height extending from the top surface of the isolation layer, the second end of the hybrid fin has a second height from the top surface of the isolation layer, and the second height is less than 50% of the first height.

7. The semiconductor device of claim 1, further comprising a gate structure disposed adjacent to the first and second epitaxial source / drain components, wherein the hybrid fin extends below the gate structure, and the top surface of the portion of the hybrid fin below the gate structure is higher than the top surface of the second end of the hybrid fin.

8. A semiconductor device, comprising: First semiconductor fin; Second semiconductor fin; A first epitaxial source / drain component connected to the first semiconductor fin, wherein the first epitaxial source / drain component is doped with an n-type dopant; A second epitaxial source / drain component connected to the second semiconductor fin, wherein the second epitaxial source / drain component is doped with a p-type dopant; A hybrid fin is disposed between the first and second semiconductor fins and between the first and second epitaxial source / drain components; A gate structure is disposed above the first semiconductor fin, the second semiconductor fin, and the hybrid fin, wherein the hybrid fin has a first top surface below the gate structure, a second top surface between the first and second epitaxial source / drain components, and the second top surface is lower than the first top surface; as well as A contact etch stop layer is disposed on the first epitaxial source / drain component and the second epitaxial source / drain component, as well as on the second top surface of the hybrid fin, wherein the contact etch stop layer on the first epitaxial source / drain component and the second epitaxial source / drain component, as well as on the second top surface of the hybrid fin, closes to form an air gap.

9. The semiconductor device of claim 8, wherein the first top surface is located at a first height from the top surface of the isolation layer, the second top surface is located at a second height from the top surface of the isolation layer, and the second height is less than 50% of the first height.

10. The semiconductor device according to claim 8, wherein, A portion of the first epitaxial source / drain component and a portion of the second epitaxial source / drain component are located above the second top surface of the hybrid fin.

11. The semiconductor device of claim 8, further comprising source / drain contact components disposed on the first and second epitaxial source / drain components, wherein, A portion of the contact etch stop layer is disposed between the source / drain contact component and the hybrid fin.

12. The semiconductor device of claim 11, further comprising an interlayer dielectric layer, wherein, A portion of the interlayer dielectric layer is disposed between the contact etch stop layer and the bottom surface of the source / drain contact component.

13. The semiconductor device according to claim 8, wherein, The hybrid fins include: Dielectric fins having one or more air gaps; and A dielectric filling layer is disposed in the one or more air gaps.

14. A method for manufacturing a semiconductor device, comprising: Forming a first semiconductor fin, a second semiconductor fin, and a hybrid fin between the first and second semiconductor fins; During the period when the second semiconductor fin is covered by the first mask, the first semiconductor fin and the hybrid fin are recessed and etched. A first epitaxial source / drain component is formed and connected to the first semiconductor fin, and the first epitaxial source / drain component is doped with an n-type dopant; The second semiconductor fin is recessed and etched, wherein the hybrid fin and the first semiconductor fin are covered by a second mask; A second epitaxial source / drain component is formed and connected to the second semiconductor fin, and the second epitaxial source / drain component is doped with a p-type dopant; as well as A contact etch stop layer is deposited on the first epitaxial source / drain component, the second epitaxial source / drain component, and the hybrid fin, wherein the contact etch stop layer on the first epitaxial source / drain component, the second epitaxial source / drain component, and the top surface of the hybrid fin closes to form an air gap.

15. The method of claim 14, further comprising: An interlayer dielectric layer is deposited above the contact etch stop layer.

16. The method of claim 15, further comprising: Contact holes are formed in the interlayer dielectric layer above the first and second epitaxial source / drain components.

17. The method of claim 16, further comprising: The contact etch stop layer is etched from the first and second epitaxial source / drain components.

18. The method of claim 14, wherein forming the first semiconductor fin, the second semiconductor fin, and the hybrid fin comprises: The first semiconductor fin, the second semiconductor fin, and the hybrid fin are formed at a first protrusion height from the top surface of the isolation layer.

19. The method of claim 18, further comprising: A gate structure is formed above the first semiconductor fin, the second semiconductor fin, and the hybrid fin.

20. The method of claim 18, wherein recess etching of the first semiconductor fin and the hybrid fin comprises: The hybrid fin is recessed to a second protrusion height from the top surface of the isolation layer, wherein the second protrusion height is less than 50% of the first protrusion height.

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