Semiconductor test structures and their manufacturing methods, test methods, semiconductor devices

Abstract

This application provides a semiconductor test structure, its manufacturing method, a testing method, and a semiconductor device. The semiconductor test structure includes a test unit, comprising: at least one transistor disposed on the front side of a substrate; wherein a doped layer is formed in the substrate, and the doped layer is exposed on the back side of the substrate; a first test section electrically connected to the gate of the transistor; a second test section electrically connected to the source of the transistor; and a third test section electrically connected to the drain of the transistor through the doped layer; wherein the thickness of the doped layer along the direction from the back side to the front side is less than or equal to 5 μm.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to semiconductor test structures, their manufacturing methods, testing methods, and semiconductor devices. Background Technology

[0002] Transistors are widely used as switching devices or driving devices in electronic devices. For example, transistors can be used in Dynamic Random Access Memory (DRAM) to control the capacitance in each memory cell, and transistor arrays consisting of multiple transistors can be used in semiconductor memory devices. Summary of the Invention

[0003] In view of the above, embodiments of this application provide a semiconductor test structure and its manufacturing method, test method, and semiconductor device to solve at least one technical problem existing in the prior art.

[0004] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0005] In a first aspect, embodiments of this application provide a semiconductor test structure, the semiconductor test structure including a test unit, the test unit comprising:

[0006] At least one transistor disposed on the front side of a substrate; wherein a doped layer is formed in the substrate, and the doped layer is exposed on the back side of the substrate;

[0007] A first test section electrically connected to the gate of the transistor;

[0008] A second test section electrically connected to the source of the transistor;

[0009] A third test section electrically connected to the drain of the transistor via the doped layer;

[0010] The thickness of the doped layer along the direction from the back side to the front side is less than or equal to 5 μm.

[0011] In some embodiments, the semiconductor test structure includes multiple test units, and the thickness of the doped layer in different test units is different along the direction from the back side to the front side.

[0012] In some embodiments, the doping concentration of the doped layer is greater than the doping concentration of the drain electrode.

[0013] In some embodiments, the transistor has a channel that extends perpendicularly to the substrate;

[0014] A gate is provided on at least one sidewall of the channel.

[0015] In some embodiments, the transistor has a channel that extends perpendicularly to the substrate;

[0016] The source and drain of the transistor are respectively provided at both ends of the extension direction of the channel.

[0017] Secondly, embodiments of this application provide a method for manufacturing a semiconductor test structure, the method comprising:

[0018] A substrate is provided, wherein a doped layer is formed therein, and at least one transistor is formed on the front side of the substrate; the drain of the transistor is electrically connected to the doped layer.

[0019] A first test section is formed that is electrically connected to the gate of the transistor;

[0020] A second test section is formed that is electrically connected to the source of the transistor;

[0021] The back side of the substrate is thinned so that the thickness of the doped layer in the direction from the back side to the front side is less than or equal to 5 μm;

[0022] A third test section is formed that is electrically connected to the doped layer.

[0023] In some embodiments, the thinning process on the back side of the substrate to form the doped layer includes:

[0024] The back side of the substrate is thinned to form doped layers of different thicknesses; wherein the thickness is the thickness along the direction from the back side to the front side.

[0025] In some embodiments, providing the substrate includes:

[0026] Provide substrate;

[0027] The substrate is doped to form a doped layer;

[0028] At least one transistor is formed on the front side of the substrate.

[0029] In some embodiments, providing the substrate includes:

[0030] Provide substrate;

[0031] At least one transistor is formed on the front side of the substrate;

[0032] The substrate is doped to form a doped layer.

[0033] In some embodiments, the substrate is an unthinned substrate.

[0034] In some embodiments, the doping depth of the doped layer is greater than or equal to 5 μm before the thinning process is performed on the back side of the substrate.

[0035] Thirdly, embodiments of this application provide a testing method for testing the semiconductor test structure described in the above technical solution; the testing method includes:

[0036] For each test unit: electrical signals are applied to the gate, source, and drain of the transistor through the first test section, the second test section, and the third test section, respectively;

[0037] If the transistor is turned on, it is determined that the test unit has no defects;

[0038] If the transistor is not conducting, the test unit is determined to be defective.

[0039] Fourthly, embodiments of this application provide a semiconductor device, the semiconductor device including at least one transistor, the transistor comprising:

[0040] Ditch;

[0041] The source electrode is located at the first end in the extension direction of the channel;

[0042] The drain is located at the second end of the channel in the extension direction; wherein the first end and the second end are the two opposite ends of the channel in the extension direction.

[0043] The transistor has a gate on at least one sidewall of its channel;

[0044] The drain of the transistor is connected to a doped layer; wherein the doping type of the doped layer is the same as the doping type of the drain, and the doping concentration of the doped layer is higher than that of the drain.

[0045] In some embodiments, the thickness of the doped layer along the extension direction is less than or equal to 5 μm.

[0046] In some embodiments, the semiconductor device further includes:

[0047] Word lines, which are electrically connected to the gate of the transistor;

[0048] Bit lines, which are electrically connected to the drain of the transistor through the doped layer;

[0049] A storage capacitor, wherein the upper plate of the storage capacitor is electrically connected to the source of the transistor, and the lower plate of the storage capacitor is connected to a common terminal.

[0050] Fifthly, embodiments of this application provide a method for manufacturing a semiconductor device, the semiconductor device including at least one transistor; the manufacturing method includes:

[0051] At least one transistor pillar is formed on the surface of a substrate; wherein the extending direction of the transistor pillar is perpendicular to the surface of the substrate;

[0052] A gate is formed on at least one sidewall of the transistor pillar of the transistor;

[0053] A source is formed at the first end of the extending direction of the transistor pillar of the transistor;

[0054] A drain is formed at the second end of the transistor pillar in the extending direction of the transistor; wherein the first end and the second end are opposite ends of the transistor pillar in the extending direction; the transistor pillar between the source and the drain forms the channel of the transistor;

[0055] The substrate is doped to form a doped layer; wherein the doped layer is electrically connected to the drain of the transistor; the doping type of the doped layer is the same as the doping type of the drain, and the doping concentration of the doped layer is higher than that of the drain.

[0056] This application provides a semiconductor test structure, its manufacturing method, a testing method, and a semiconductor device. The semiconductor test structure includes a test unit, comprising: at least one transistor disposed on the front side of a substrate; wherein a doped layer is formed within the substrate, and the doped layer is exposed on the back side of the substrate; a first test section electrically connected to the gate of the transistor; a second test section electrically connected to the source of the transistor; and a third test section electrically connected to the drain of the transistor through the doped layer; wherein the thickness of the doped layer along the direction from the back side to the front side is less than or equal to 5 μm. The semiconductor test structure provided in this application includes a test unit, and by performing a back-side thinning process on the substrate to obtain a doped layer of a certain thickness, the transistor can be electrically tested through the first, second, and third test sections, thereby achieving electrical monitoring of the back-side thinning process. Attached Figure Description

[0057] Figure 1 A schematic flowchart illustrating the manufacturing method of the semiconductor test structure provided in this application embodiment;

[0058] Figures 2A to 2K This is a schematic diagram illustrating the process of manufacturing a semiconductor test structure provided in an embodiment of this application;

[0059] Figure 3A three-dimensional schematic diagram of the test unit in the semiconductor test structure provided in the embodiments of this application;

[0060] Figure 4A A top view of the formation of lead-out pads provided in an embodiment of this application;

[0061] Figure 4B A cross-sectional view of an optional structure of the first pad provided in an embodiment of this application;

[0062] The figure includes: 101, substrate; 101a, front side of substrate; 101b, back side of substrate; 102, active region; 103, first trench; 104, first isolation layer; 105, doped layer; 106, second trench; 107, gate oxide layer; 108, gate; 109, second isolation layer; 110, third trench; 111, third isolation layer; 112, channel; 113, source; 114, drain; 115, first test section; 116, second test section; 117, third test section; 118, first bonding pad; 119, second bonding pad; 120, third bonding pad; 121, conductive via. Detailed Implementation

[0063] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0064] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0065] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0066] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0067] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0068] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0069] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0070] Mainstream memory transistor arrays include planar transistor arrays and buried channel array transistors (BCATs). However, regardless of whether it's a planar transistor array or a buried channel transistor array, the source and drain are located on opposite sides of the gate. In this structure, the source and drain occupy different locations, resulting in a relatively large area for both planar and buried channel transistor arrays.

[0071] To further reduce the size of the transistor array, the transistor array of the memory can include a Vertical Gate Transistor (VGT). In this structure, each transistor in the transistor array has a channel, wherein the channels of the transistor array are arrayed along a first direction and a second direction, and the extension direction of the channels is perpendicular to the plane formed by the first direction and the second direction. At least one side of each channel of the transistor array can form a gate oxide layer and a gate, and the two ends of the extension direction of each channel of the transistor array have a source and a drain, respectively. The substrate needs to be thinned on the back side to expose each channel of the transistor array, and the exposed channels are doped to form the drain of each transistor, which is subsequently used to connect bit lines (BL).

[0072] Here, the vertical gate transistor array allows the source and drain to be formed at opposite ends of the channel, avoiding the problem of a large transistor array area caused by forming them on both sides of the gate. This provides a smaller transistor array structure and improves the device's storage density. However, through further research and analysis of the above-mentioned vertical gate transistor array, the inventors discovered that back-side thinning of the substrate is a key process step in manufacturing the vertical gate transistor array. If the channel length of the vertical gate transistor array is small, for example, less than 1 μm, then the substrate needs to be thinned to less than 1 μm, or even to the nanometer level, which increases the risk of damaging the device structure.

[0073] Furthermore, the substrate is thinned on the back side to expose the channels of the transistor array. The exposed channels are then doped to form the drains of the transistors, which are subsequently used to connect bit lines. If, after the bit lines are led out, the device structure is found to be damaged, or even if the transistors fail to conduct, it is impossible to determine whether the defect lies in the front-side process of the substrate (e.g., the process of forming the transistors) or the back-side process of the substrate (e.g., the process of thinning the back side of the substrate).

[0074] In view of this, embodiments of this application provide a semiconductor test structure and its manufacturing method, test method, and semiconductor device.

[0075] refer to Figure 1 , Figure 1 This is a schematic flowchart illustrating a method for manufacturing a semiconductor test structure provided in an embodiment of this application. Figure 1 As shown in the figure, this application provides a method for manufacturing a semiconductor test structure, the method comprising:

[0076] Step S101: Provide a substrate, wherein a doped layer is formed in the substrate, and at least one transistor is formed on the front side of the substrate; the drain of the transistor is electrically connected to the doped layer.

[0077] Step S102: Form a first test section that is electrically connected to the gate of the transistor;

[0078] Step S103: Form a second test section electrically connected to the source of the transistor;

[0079] Step S104: Thin the back side of the substrate so that the thickness of the doped layer in the direction from the back side to the front side is less than or equal to 5 μm;

[0080] Step S105: Form a third test section that is electrically connected to the doped layer.

[0081] In this embodiment, the substrate can be a single-crystal silicon material used for fabricating semiconductor devices. The substrate has two opposing surfaces, one of which is the front side of the substrate, and the other is the back side of the substrate. Typically, the front side of the substrate can be used to form a transistor pillar, the transistor pillar extending perpendicularly to the substrate. The transistor pillar has two ends along the extending direction, namely a first end and a second end. After doping the first end of the transistor pillar, a source electrode can be formed. After thinning the back side of the substrate, the second end of the transistor pillar is exposed. After doping the second end of the transistor pillar, a drain electrode can be formed. Signals can be led out from the drain electrode from the back side of the substrate.

[0082] In this embodiment of the application, the back side of the substrate is thinned to form doped layers of different thicknesses; wherein, the thickness is the thickness along the direction from the back side to the front side.

[0083] Here, the semiconductor test structure manufacturing method provided in this application embodiment can perform back-side thinning of the substrate to form doped layers of different thicknesses, and form a first test section, a second test section and a third test section respectively to perform electrical tests on the transistor, thereby realizing electrical monitoring of the back-side thinning process.

[0084] Next reference Figures 2A to 2K The manufacturing process of the semiconductor test structure provided in the embodiments of this application will be further described in detail.

[0085] It should be noted that the thickness direction of the substrate is defined as the Z-direction. Intersecting X and Y directions are defined on the top or bottom surface of the substrate perpendicular to the Z-direction. Based on the X and Y directions, the top or bottom surface of the substrate perpendicular to the Z-direction can be determined. For example, the X and Y directions may have a certain angle. Alternatively, the X and Y directions may be perpendicular to each other. Thus, the X, Y, and Z directions are all mutually perpendicular. Here, the X-direction is the row direction, and the Y-direction is the column direction.

[0086] In some embodiments, providing the substrate includes:

[0087] Provide substrate;

[0088] At least one transistor is formed on the front side of the substrate;

[0089] The substrate is doped to form a doped layer.

[0090] refer to Figure 2A and Figure 2B , Figure 2A and Figure 2B These are partial top views and partial cross-sectional views, respectively, of the process of forming the active region and the first groove provided in the embodiments of this application. Figure 2A and Figure 2B As shown, substrate 101 has two opposing surfaces, including a front surface 101a and a back surface 101b. The front surface of substrate 101 is etched along its thickness direction (i.e., the Z direction) to form a plurality of active regions 102 parallel to the Y direction, and a first groove 103 located between adjacent active regions 102. The first groove exposes the Y-direction-parallel sidewalls of the active regions, which are subsequently used to form the channels of transistors.

[0091] In this embodiment, a dry etching process, such as plasma etching or reactive ion etching, can be used to etch the substrate. It is worth noting that in this embodiment, the etching of the substrate is a partial etching along the thickness direction of the substrate; that is, the etching process does not penetrate the substrate.

[0092] In this embodiment, by etching the entire surface of the substrate to simultaneously form the active region and a first groove with substantially the same depth, the manufacturing process can be simplified and efficiency improved. In actual processes, due to process errors, the depth of the first groove formed by etching is the same or meets the error range requirements.

[0093] refer to Figure 2C and Figure 2D , Figure 2C and 2D These are partial top views and partial cross-sectional views, respectively, of the process for forming the first isolation layer provided in the embodiments of this application. Figure 2C and 2D As shown, insulating material is deposited in the first groove to form a first isolation layer 104 located between adjacent active regions. The first isolation layer 104 covers the sidewalls of each active region parallel to the Y direction.

[0094] In the embodiments of this application, the deposition process may include, but is not limited to, the following: chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0095] In this embodiment, the insulating material forming the first isolation layer may include, but is not limited to, silicon nitride, silicon oxynitride, or silicon dioxide. In a specific example, silicon dioxide may be deposited first in the first groove, followed by silicon nitride, to form the first isolation layer located between adjacent active regions.

[0096] It should be noted that during the actual deposition of insulating material, the insulating material will cover the top surface of the active region. Typically, after deposition, in some embodiments, a chemical mechanical polishing (CMP) process can be used to grind away excess insulating material to expose the top surface of the active region.

[0097] In this embodiment of the application, the substrate is an unthinned substrate, and at least one transistor is formed on the front side of the unthinned substrate; the unthinned substrate is doped to form a doped layer.

[0098] refer to Figure 2E and Figure 2F , Figure 2E and Figure 2F These are all partial cross-sectional views of the process of forming a doped layer on a substrate, as provided in the embodiments of this application. Figure 2E As shown, substrate 101 is doped to form a doped layer 105, at which point the doped layer 105 is not exposed on the back side 101b of the substrate. Figure 2F As shown, the substrate is then thinned on the back side until the doped layer 105 is exposed.

[0099] Here, a multi-step ion implantation method can be used. Particles to be doped are introduced into the substrate using an ion beam. Through a series of physicochemical interactions, the doped particles gradually lose energy and remain within the substrate, forming a doped layer with a doping depth greater than or equal to 5 μm. At this point, the back side of the substrate is not exposed. By adjusting ion implantation parameters, such as the ion implantation dose and energy, the depth and concentration distribution of the doped layer within the substrate can be controlled, ensuring that the back side of the substrate is not exposed and that some active regions are simultaneously doped during the substrate doping process. Further, the substrate undergoes backside thinning, removing a portion of the substrate while retaining a doped layer of a certain thickness. In other words, the substrate undergoes backside thinning, removing a portion of the substrate and retaining a doped layer of a certain thickness.

[0100] It should be noted that the process of thinning the substrate on the back side to expose the doped layer and the process of thinning the substrate on the back side to bring out the drain are different processes. After performing the process of thinning the substrate on the back side to expose the doped layer, the substrate still retains a thickness of at least 5 μm, while after performing the process of thinning the substrate on the back side to bring out the drain, the substrate may be thinned to less than 1 μm, or even to the nanometer level.

[0101] Alternatively, the substrate can be directly doped to form a doped layer, in which case the doped layer is exposed on the back side of the substrate. This eliminates the need for the step of thinning the back side of the substrate to expose the doped layer. It should be noted that those skilled in the art can consider the substrate thickness and the thickness of the doped layer along the back side of the substrate towards the front side to determine how to form the doped layer within the substrate and expose the doped layer on the back side.

[0102] In the above process steps, after forming an active region on the front side of the unthinned substrate, the back side of the substrate is doped to form a doped layer. Alternatively, the back side of the unthinned substrate can be doped first, and then the active region can be formed on the front side of the unthinned substrate. For example, in this embodiment, a heavily doped N-type epitaxial substrate (N-type EPI wafer) can be used directly, which is equivalent to already forming a doped layer on the substrate. In this embodiment, there are no special restrictions on the process order of forming the active region and forming the doped layer.

[0103] In other embodiments, providing the substrate includes:

[0104] Provide substrate;

[0105] The substrate is doped to form a doped layer;

[0106] At least one transistor is formed on the front side of the substrate.

[0107] In this embodiment of the application, the substrate is an unthinned substrate, and the unthinned substrate is doped to form a doped layer; at least one transistor is formed on the front side of the unthinned substrate.

[0108] Here, ion implantation can be used to dope an unthinned substrate to form a doped layer. In this embodiment, there are no special restrictions on the direction of ion beam implantation; for example, the ion beam can be implanted from the front side of the unthinned substrate, or it can be implanted from the back side. It should be noted that those skilled in the art can consider the impact of substrate thickness and ion implantation direction on the process difficulty to determine the ion implantation direction when forming a doped layer within the substrate.

[0109] refer to Figure 2G , Figure 2G This is a partial top view of the process of forming the second groove provided in an embodiment of this application. Figure 2G As shown, the front side of the substrate 101 is etched along the thickness direction of the substrate (i.e., the Z direction) to form a plurality of second grooves 106 parallel to the X direction. The second grooves 106 expose the sidewalls of the active region 102 parallel to the X direction. The second grooves divide each of the plurality of active regions parallel to the Y direction into several parts, and the sidewalls of the active regions parallel to the X direction are the sidewalls for the subsequent formation of the gate.

[0110] refer to Figure 2H , Figure 2H This is a partial top view of the process for forming the gate oxide layer and the gate, provided for an embodiment of this application. Figure 2HAs shown, an insulating material is deposited in the second groove to form a gate oxide layer 107 that covers the sidewalls of the active region 102 parallel to the X direction. A conductive material is deposited in the second groove to form a gate 108 that covers the sidewalls of the gate oxide layer 107. An insulating material is further deposited in the second groove to form a second isolation layer 109.

[0111] In this embodiment, the gate oxide layer 107 is an insulating material, such as silicon dioxide. Here, the gate oxide layer is located between the channel and the gate for electrical isolation, preventing direct contact between the gate and the channel from causing charge leakage.

[0112] In this embodiment, the gate 108 is a conductive material, which may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or other conductive materials. In a preferred embodiment, the conductive material is tungsten. Here, gates in the same row of channels are connected to form word lines parallel to the X direction. The word lines are used to provide word line voltage and control the transistor to turn on or off via the word line voltage.

[0113] In this embodiment, the insulating material forming the second isolation layer 109 may include, but is not limited to, silicon nitride, silicon oxynitride, or silicon dioxide.

[0114] In this embodiment, the gate oxide layer, the gate, and the second isolation layer can be sequentially formed in the second groove using CVD, PVD, or ALD processes.

[0115] refer to Figure 2I , Figure 2I This is a partial top view of the process of forming the third groove provided in an embodiment of this application. Figure 2I As shown, the front side of the substrate is etched along the thickness direction of the substrate to form multiple third grooves 110 parallel to the X direction. Among them, the third grooves 110 expose the sidewalls of the active region parallel to the X direction, that is, the third grooves 110 expose the sidewalls of the channel.

[0116] refer to Figure 2J , Figure 2J This is a partial top view of the process for forming the third isolation layer provided in an embodiment of this application. Figure 2J As shown, insulating material is deposited in the third groove to form a third insulating layer 111.

[0117] In this embodiment of the application, the channel can be a columnar channel. Figure 2J The illustrated channel 112 appears as a rectangle in the top view. Of course, the channel can also appear as a circle, ellipse, or other shapes in the top view. This application does not impose any special restrictions on the shape of the channel in the top view.

[0118] In this embodiment of the application, the materials of the first isolation layer 104, the second isolation layer 109, and the third isolation layer 111 can be the same or different.

[0119] Here, multiple first grooves 103 parallel to the Y direction are formed to form multiple active regions parallel to the Y direction on the front side of the substrate. A first isolation layer 104 isolates the multiple active regions parallel to the Y direction from each other. Further, multiple second grooves 106 and third grooves 110 parallel to the X direction are formed, dividing each active region in the multiple active regions parallel to the Y direction into several channels 112. Second isolation layers 109 and third isolation layers 111 isolate channels located in the same column from each other (e.g., ...). Figure 2J (As shown). In this embodiment, the channels are arranged in an array along the X and Y directions. The channels are used to transfer or stop the transfer of charge under the action of an external electric field, so that the transistor is turned on or off, and the extension direction of each channel is perpendicular to the surface of the substrate. Here, the extension direction of the channel is the direction of the current when the transistor is turned on.

[0120] Furthermore, the shape of the channel's orthographic projection onto the substrate can be circular, elliptical, rectangular, rhomboid, or polygonal, etc., and the embodiments of this application do not have any special limitations in this regard. It should be noted that... Figures 2A to 2K The example is given with the shape of the channel's orthographic projection onto the substrate being rectangular.

[0121] refer to Figure 2K , Figure 2K A cross-sectional view of a transistor provided in an embodiment of this application. Figure 2K Indicate Figure 2J A schematic diagram of the cross-sectional structure of a transistor, shown within the dashed circle. (See diagram below.) Figure 2K As shown, ion implantation is performed on the channel 112 to form the source 113 of the transistor at the end of the channel 112 away from the substrate, and the drain 114 is formed at the end of the channel 112 near the doped layer 105.

[0122] Here, during ion implantation, the particles to be doped are incident on the end of each channel away from the substrate using an ion beam. Through a series of physicochemical interactions, the doped particles gradually lose energy and remain there, forming the source of each transistor at the end of each channel away from the substrate and the drain at the end of the transistor channel near the doped layer.

[0123] In this embodiment, the channel is trapezoidal in shape in the cross section perpendicular to the substrate (including the YZ plane and the XZ plane). Of course, the channel can also be in other shapes in the cross section perpendicular to the substrate, and this embodiment does not have any special limitations on this.

[0124] In this embodiment, the gate covers one sidewall of each channel of each transistor, and the gates of channels in the same row are connected to each other to form word lines parallel to the X direction. Of course, a gate surrounding the channel can also be formed, that is, a gate all around transistor is formed. This embodiment does not have any special limitations on this.

[0125] In the embodiments of this application, the transistor in the semiconductor test structure may include a vertical gate transistor. Specifically, the transistor may include, but is not limited to, a single-gate transistor, a dual-gate transistor, a triple-gate transistor, and a multi-gate transistor.

[0126] This application also provides a semiconductor test structure, which includes multiple test units. The thickness of the doped layer in each test unit is different. The doped layers of different thicknesses can be obtained by back-side thinning of the substrate. In this way, the transistor can be electrically tested through the first test unit, the second test unit and the third test unit, thereby realizing the electrical monitoring of the back-side thinning process.

[0127] refer to Figure 3 , Figure 3 This is a three-dimensional schematic diagram of the test unit in the semiconductor test structure provided in an embodiment of this application. Figure 3 As shown, the test unit includes: at least one transistor disposed on the front side of a substrate; wherein a doped layer 105 is formed in the substrate, and the doped layer 105 is exposed on the back side of the substrate; a first test section 115 electrically connected to the gate 108 of the transistor; a second test section 116 electrically connected to the source 113 of the transistor; and a third test section 117 electrically connected to the drain 114 of the transistor through the doped layer 105.

[0128] Still Figure 3 As shown, the transistor has a channel 112, the extension direction of the channel 112 is perpendicular to the substrate, the source 113 and the drain 114 of the transistor are respectively provided at both ends of the extension direction of the channel 112, and the gate 108 is provided on at least one sidewall of the channel 112.

[0129] In some embodiments, the doping concentration of the doped layer is greater than the doping concentration of the drain electrode.

[0130] Here, the substrate is doped to form a doped layer, and the portion of the doped layer connected to the channel forms the drain. The source of the transistor can be directly led out and electrically connected to the second test section, while the drain of the transistor is led out through the doped layer and electrically connected to the third test section. In a specific example, the substrate can undergo multiple ion implantations, the drain can be a lightly doped drain (LDD), and the doped layer can be a deep N-well (DNW).

[0131] In this embodiment, the thickness of the doped layer along the direction from the back side to the front side is less than or equal to 5 μm.

[0132] In the embodiments of this application, the semiconductor test structure includes multiple test units, and the thickness of the doped layer in different test units is different in the direction from the back side of the substrate to the front side of the substrate.

[0133] Here, the semiconductor test structure includes multiple test units, each with a different thickness of doped layer. Doped layers of different thicknesses can be obtained by back-side thinning of the substrate. In this way, the transistors can be electrically tested through the first test unit, the second test unit, and the third test unit, thereby realizing the electrical monitoring of the back-side thinning process.

[0134] It should be noted that during the formation of the semiconductor test structure, the gate, source, and doped layer electrically connected to the drain of the transistor can themselves be used to extract electrical signals. In other words, the source, gate, and doped layer electrically connected to the drain of the transistor can function as a test section. Of course, different test sections can also be set up separately to extract the electrical signals from the gate, source, and doped layer electrically connected to the drain of the transistor.

[0135] In some embodiments, the test unit further includes: a first pad, wherein the first test portion is electrically connected to the gate via the first pad; and / or, a second pad, wherein the second test portion is electrically connected to the source via the second pad; and / or, a third pad, wherein the third test portion is electrically connected to the doped layer via the third pad.

[0136] refer to Figure 4A , Figure 4A This is a top view showing the formation of the first, second, and third solder pads, provided for an embodiment of this application. Figure 4A As shown, the first pad 118 is electrically connected to the word line, the second pad 119 is electrically connected to the source of each transistor, and the third pad 120 is electrically connected to the doped layer below the transistor.

[0137] refer to Figure 4B , Figure 4BA cross-sectional view of an optional structure of the first solder pad provided in an embodiment of this application. (See attached image.) Figure 4B As shown, the first pad 118 is used to electrically connect the gate 108 of the transistor to the first test section 115. The first pad 118 and the gate 108 are connected through a conductive via 121, and the first pad 118 and the first test section 115 are connected through a conductive via 121. Figure 4B This diagram only illustrates a cross-sectional view of an optional structure where the first test section is electrically connected to the transistor gate via the first pad. Of course, other structures can also be used to connect the first test section and the transistor gate, as long as the electrical connection function is achieved. The electrical connections between the second test section and the transistor source via the second pad, and between the third test section and the doped layer beneath the transistor drain via the third pad, can be referenced. Figure 4B The process will not be elaborated upon here.

[0138] This application embodiment also provides a semiconductor testing method for testing the semiconductor test structure described in the above technical solution, the testing method comprising:

[0139] For each test unit: electrical signals are applied to the gate, source, and drain of the transistor through the first test section, the second test section, and the third test section, respectively;

[0140] If the transistor is turned on, it is determined that the test unit has no defects;

[0141] If the transistor is not conducting, the test unit is determined to be defective.

[0142] Here, a doped layer electrically connected to the drain of the transistor is formed in the substrate. The thickness of this doped layer is relatively large, for example, greater than or equal to 5 μm. Electrical signals are applied to the gate, source, and drain of the transistor through the first, second, and third test sections, respectively. If the transistor conducts, it is determined that the test unit has no defects; that is, all previous process steps have been executed normally, and subsequent process steps can continue. In other words, by performing an electrical test on the transistor, if the transistor conducts, it can be determined that the front-side process of the substrate is defect-free, meaning the transistor formation process is defect-free. If the transistor does not conduct, it is determined that the test unit has a defect; that is, at least one of the previous process steps must have been executed abnormally, and subsequent process steps cannot continue. In other words, by performing an electrical test on the transistor, if the transistor does not conduct, it can be determined that the front-side process of the substrate has defects, meaning the transistor formation process has defects.

[0143] In some embodiments, if a transistor still fails to conduct even when a thick doped layer is retained on the back side of the substrate, it indicates that the process steps for forming the transistor on the front side of the substrate are malfunctioning. The cause of the malfunction can be further investigated by examining the transistor formation process steps.

[0144] In some embodiments, if the transistor is turned on, it is determined that the test unit has no defects; the test method further includes:

[0145] The back side of the substrate is thinned to obtain a test unit with a doped layer of a predetermined thickness;

[0146] Electrical signals are applied to the gate, source, and drain of the transistor through the first test section, the second test section, and the third test section, respectively.

[0147] If the transistor is turned on, it is determined that the thinning process is free of defects;

[0148] If the transistor is not conducting, it is determined that the thinning process has a defect.

[0149] Here, with all transistor formation steps on the front side of the substrate proceeding normally, the doped layer is thinned to obtain test cells with doped layers of varying thicknesses. For example, by thinning to different thicknesses, five test cells with doped layer thicknesses of 1 μm, 2 μm, 3 μm, 4 μm, and 5 μm can be obtained. Electrical signals are applied to the gate, source, and drain of the transistors in the test cells through the first, second, and third test sections, respectively. By observing whether the transistors in the test cells with doped layers of different thicknesses are conducting, electrical monitoring of the back-side thinning process can be achieved without increasing costs.

[0150] If all transistors in the five test units are conductive, then the process steps for thinning the doped layer in these five test units are considered to be without defects. If the transistors in the test units with doped layer thicknesses of 3μm, 4μm, and 5μm are conductive, while the transistors in the test units with doped layer thicknesses of 1μm and 2μm are not conductive, then the process steps for thinning the doped layer in the test units with doped layer thicknesses of 3μm, 4μm, and 5μm are considered to be without defects, while the process steps for thinning the doped layer in the test units with doped layer thicknesses of 1μm and 2μm are considered to be defective. In other words, after thinning the back side of the substrate, the minimum thickness of the doped layer that can be retained is 3μm.

[0151] In this embodiment of the application, by forming doped layers of different thicknesses, it is possible to determine whether there are defects in the process steps of forming transistors on the front side of the substrate, and also to determine whether there are defects in the process steps of thinning the back side of the substrate. Furthermore, it is possible to determine the maximum thickness of the doped layer that can be removed by the thinning process (or the minimum thickness of the doped layer that can be retained).

[0152] In this embodiment, doped layers of different thicknesses are obtained by back-side thinning of the substrate. This allows for electrical testing of the transistors using the first, second, and third testing sections, thereby enabling electrical monitoring of the back-side thinning process. Furthermore, the back-side thinning process parameters can be adjusted using the results of this electrical monitoring.

[0153] In some embodiments, the doping depth of the doped layer is greater than or equal to 5 μm before the thinning process is performed on the back side of the substrate.

[0154] Here, applications that typically thin to a thickness of only a few micrometers are more mature. Therefore, a doped layer with a doping depth greater than or equal to 5 μm can be formed in the substrate by ion implantation before the backside thinning process is performed on the substrate.

[0155] In some embodiments, after the back side of the substrate is thinned, the thickness of the doped layer in the direction from the back side to the front side is less than or equal to 5 μm.

[0156] Here, multiple test units with doped layers of different thicknesses can be fabricated, and electrical tests can be performed on each test unit. Based on the results of the electrical tests, it can be determined whether there are defects in the back-side thinning process.

[0157] The testing method provided in this application embodiment obtains doped layers of different thicknesses through back-side thinning, and performs electrical tests on semiconductor structures with doped layers of different thicknesses, thereby realizing electrical monitoring of the back-side thinning process.

[0158] The testing methods provided in this application are applicable to various types of semiconductor devices, such as DRAM, NAND flash memory, static random access memory (SRAM), and phase change memory (PCM).

[0159] The testing method provided in this application embodiment can be used to monitor the electrical properties of the back-side thinning process of vertical gate transistors. The testing method provided in this application embodiment can be applied to the electrical monitoring of the back-side thinning process of single-gate transistors, dual-gate transistors, tri-gate transistors, and even multi-gate transistors.

[0160] Still referencing Figure 4A The testing method provided in this application embodiment can select a transistor as a test unit from multiple transistors arranged in an array, and extract the signals of the gate, source, and drain of the transistor through the first, second, and third bonding pads, respectively. Then, the transistor is electrically tested through the first, second, and third test sections, respectively. Alternatively, all multiple transistors arranged in the array can be used as test units, and the signals of the gate, source, and drain of each transistor can be extracted through the first, second, and third bonding pads, respectively. Then, each transistor is electrically tested through the first, second, and third test sections, respectively. This application embodiment does not have a special limitation on the number of transistors used for electrical testing.

[0161] This application embodiment also provides a semiconductor device, the semiconductor device including at least one transistor, the transistor comprising:

[0162] Ditch;

[0163] The source electrode is located at the first end in the extension direction of the channel;

[0164] The drain is located at the second end of the channel in the extension direction; wherein the first end and the second end are the two opposite ends of the channel in the extension direction.

[0165] The transistor has a gate on at least one sidewall of its channel;

[0166] The drain of the transistor is connected to a doped layer; wherein the doping type of the doped layer is the same as the doping type of the drain, and the doping concentration of the doped layer is higher than that of the drain.

[0167] In this embodiment, the drain of the transistor is connected to a doped layer. The doped layer increases the size of the transistor along the channel extension direction, avoiding damage to the transistor during the back-side thinning process to expose the doped layer. In other words, adding a doped layer improves the safety of the back-side thinning process.

[0168] In this embodiment of the application, the semiconductor device may include a transistor array, wherein the transistors of the transistor array are arranged in an array along a first direction and a second direction, and the extension direction of the channel of the transistor is perpendicular to the plane formed by the first direction and the second direction.

[0169] Furthermore, in this embodiment, the source and drain are respectively disposed at both ends of the extension direction of each channel. The doped layer connected to the drain only increases the size of the semiconductor device along the extension direction of the channel, avoiding the problem of a large transistor array area caused by the source and drain being formed on both sides of the gate. Here, the doping concentration of the doped layer is higher than that of the drain. By setting drains and doped layers with different doping concentrations, the channel electric field can be modulated, thereby improving the reliability of the semiconductor device.

[0170] In some embodiments, the thickness of the doped layer along the extension direction is less than or equal to 5 μm.

[0171] In some embodiments, the thickness of the doped layer along the extension direction of the channel is greater than the thickness of the transistor.

[0172] Here, as the size of each transistor in the transistor array continues to shrink, the size of the transistor may reach the nanometer level. By adding a doping layer, it is ensured that the back-side thinning process will not damage the semiconductor device.

[0173] In some embodiments, the semiconductor device further includes:

[0174] Word lines, which are electrically connected to the gate of the transistor;

[0175] Bit lines, which are electrically connected to the drain of the transistor through the doped layer;

[0176] A storage capacitor, wherein the upper plate of the storage capacitor is electrically connected to the source of the transistor, and the lower plate of the storage capacitor is connected to a common terminal.

[0177] This application also provides a method for manufacturing a semiconductor device, the semiconductor device including at least one transistor; the manufacturing method includes:

[0178] At least one transistor pillar is formed on the surface of a substrate; wherein the extending direction of the transistor pillar is perpendicular to the surface of the substrate;

[0179] A gate is formed on at least one sidewall of the transistor pillar of the transistor;

[0180] A source is formed at the first end of the extending direction of the transistor pillar of the transistor;

[0181] A drain is formed at the second end of the transistor pillar in the extending direction of the transistor; wherein the first end and the second end are opposite ends of the transistor pillar in the extending direction; the transistor pillar between the source and the drain forms the channel of the transistor;

[0182] The substrate is doped to form a doped layer; wherein the doped layer is electrically connected to the drain of the transistor; the doping type of the doped layer is the same as the doping type of the drain, and the doping concentration of the doped layer is higher than that of the drain.

[0183] In some embodiments, the thickness of the doped layer along the extension direction of the channel is greater than the thickness of the transistor.

[0184] In some embodiments, the manufacturing method further includes:

[0185] Bit lines are formed and connected to the doped layer;

[0186] A storage capacitor is formed, the upper plate of which is electrically connected to the source of the transistor, and the lower plate of which is connected to a common terminal.

[0187] This application provides a semiconductor test structure, its manufacturing method, a testing method, and a semiconductor device. The semiconductor test structure includes a test unit, comprising: at least one transistor disposed on the front side of a substrate; wherein a doped layer is formed within the substrate, and the doped layer is exposed on the back side of the substrate; a first test section electrically connected to the gate of the transistor; a second test section electrically connected to the source of the transistor; and a third test section electrically connected to the drain of the transistor through the doped layer; wherein the thickness of the doped layer along the direction from the back side to the front side is less than or equal to 5 μm. The semiconductor test structure provided in this application includes a test unit, and by performing a back-side thinning process on the substrate to obtain a doped layer of a certain thickness, the transistor can be electrically tested through the first, second, and third test sections, thereby achieving electrical monitoring of the back-side thinning process.

[0188] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0189] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. All equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A semiconductor test structure, characterized by, The semiconductor test structure includes a test unit, which includes: At least one transistor disposed on the front side of a substrate, the transistor including a channel, a source, a drain and a gate, the channel extending perpendicular to the substrate, the source and the drain being respectively disposed at both ends of the channel extending in the direction of the channel; wherein a doped layer is formed in the substrate, and the doped layer is exposed on the back side of the substrate; A first test section electrically connected to the gate of the transistor; A second test section electrically connected to the source of the transistor; A third test section electrically connected to the drain of the transistor via the doped layer; The thickness of the doped layer along the direction from the back side to the front side is less than or equal to 5 μm.

2. The semiconductor test structure of claim 1, wherein, The semiconductor test structure includes multiple test units, and the thickness of the doped layer in different test units is different along the direction from the back side to the front side.

3. The semiconductor test structure of claim 1, wherein, The doping concentration of the doped layer is greater than the doping concentration of the drain electrode.

4. The semiconductor test structure of claim 1, wherein, The transistor has a channel, and the channel extends perpendicularly to the substrate; A gate is provided on at least one sidewall of the channel.

5. A method of manufacturing a semiconductor test structure, characterized by, The manufacturing method includes: A substrate is provided, wherein a doped layer is formed therein, and at least one transistor is formed on the front side of the substrate. The transistor includes a channel, a source, a drain, and a gate. The channel extends perpendicularly to the substrate, and the source and the drain are respectively provided at both ends of the channel extending in the direction of the channel. The drain of the transistor is electrically connected to the doped layer. A first test section is formed that is electrically connected to the gate of the transistor; A second test section is formed that is electrically connected to the source of the transistor; The back side of the substrate is thinned so that the thickness of the doped layer in the direction from the back side to the front side is less than or equal to 5 μm; A third test section is formed that is electrically connected to the doped layer.

6. The method of fabricating a semiconductor test structure according to claim 5, wherein, The process of thinning the back side of the substrate to form the doped layer includes: The back side of the substrate is thinned to form doped layers of different thicknesses; wherein the thickness is the thickness along the direction from the back side to the front side.

7. The method of fabricating a semiconductor test structure of claim 5, wherein, The provision of the substrate includes: Provide substrate; The substrate is doped to form a doped layer; At least one transistor is formed on the front side of the substrate.

8. The method of fabricating a semiconductor test structure of claim 5, wherein, The provision of the substrate includes: Provide substrate; At least one transistor is formed on the front side of the substrate; The substrate is doped to form a doped layer.

9. The method for manufacturing a semiconductor test structure according to claim 7 or 8, characterized in that, The substrate is an unthinned substrate.

10. The method for manufacturing a semiconductor test structure according to claim 5, characterized in that, Before the back side of the substrate is thinned, the doping depth of the doped layer is greater than or equal to 5 μm.

11. A testing method, characterized in that, For testing the semiconductor test structure according to any one of claims 1 to 4; the test method includes: For each test unit: electrical signals are applied to the gate, source, and drain of the transistor through the first test section, the second test section, and the third test section, respectively; If the transistor is turned on, it is determined that the test unit has no defects; If the transistor is not conducting, the test unit is determined to be defective.

12. A semiconductor device, characterized in that, The semiconductor device includes: at least one transistor, a word line, a bit line, and a storage capacitor, wherein the transistor includes: Ditch; The source is located at the first end in the extension direction of the channel. The upper plate of the storage capacitor is electrically connected to the source of the transistor, and the lower plate of the storage capacitor is connected to the common terminal. The drain is located at the second end of the channel in the extension direction; wherein the first end and the second end are the two opposite ends of the channel in the extension direction. The transistor has a gate on at least one sidewall of its channel, and the word line is electrically connected to the gate of the transistor. The drain of the transistor is connected to a doped layer, and the bit line is electrically connected to the drain of the transistor through the doped layer; wherein the doping type of the doped layer is the same as the doping type of the drain, and the doping concentration of the doped layer is higher than that of the drain.

13. The semiconductor device according to claim 12, characterized in that, The thickness of the doped layer along the extension direction is less than or equal to 5 μm.

14. A method for manufacturing a semiconductor device, characterized in that, The semiconductor device includes: at least one transistor; the manufacturing method includes: At least one transistor pillar is formed on the surface of a substrate; wherein the extending direction of the transistor pillar is perpendicular to the surface of the substrate; A gate is formed on at least one sidewall of the transistor pillar of the transistor; a word line is formed that is electrically connected to the gate of the transistor; A source is formed at the first end of the extending direction of the transistor pillar of the transistor; a storage capacitor is formed and electrically connected to the source of the transistor, the upper plate of the storage capacitor is electrically connected to the source of the transistor, and the lower plate of the storage capacitor is connected to a common terminal. A drain is formed at the second end of the transistor pillar in the extending direction of the transistor; wherein the first end and the second end are opposite ends of the transistor pillar in the extending direction; the transistor pillar between the source and the drain forms the channel of the transistor; The substrate is doped to form a doped layer; a bit line is formed that is electrically connected to the drain of the transistor through the doped layer; wherein the doped layer is electrically connected to the drain of the transistor; the doping type of the doped layer is the same as the doping type of the drain, and the doping concentration of the doped layer is higher than that of the drain.

Images