Package and method of packaging thereof

Abstract

This application discloses a package and its packaging method. The package includes: a substrate, one side of which is covered with a patterned first conductive layer, wherein at least one pair of first transistors and a second transistor are disposed on the first conductive layer; a first insulating layer covering the first transistors, the second transistors, and the first conductive layer, the side of the first insulating layer away from the first conductive layer being covered with a patterned second conductive layer; a second insulating layer covering the second conductive layer, the side of the second insulating layer away from the second conductive layer being covered with a patterned third conductive layer, wherein a control chip is connected to the third conductive layer. The power module package of this application has multiple current output paths. By placing the larger transistors among a large number of components between multiple layers, the package size is reduced. At the same time, the metal layer connected to the transistors helps the transistors absorb heat, improving the heat dissipation problem of the multi-output power module.

Description

Technical Field

[0001] This application relates to the technical field of device packaging, and in particular to a package and a packaging method thereof. Background Technology

[0002] In recent years, with the application of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and IGBT (Insulated Gate Bipolar Transistor) power modules in almost all power industrial products, corresponding power devices have also been steadily developing towards high performance, high speed, small size and multi-chip interconnection packaging.

[0003] The trend towards miniaturization necessitates the development of power semiconductor packaging technology towards the superior PLFO (Pane Level Fan Out) process. Furthermore, in products with multiple output voltages, the package contains more components, making it crucial to address the challenge of miniaturizing the packaging of these numerous components. Summary of the Invention

[0004] The main technical problem addressed by this application is to provide a package and its packaging method to achieve three-dimensional packaging of the package, thereby miniaturizing multi-device packaging as much as possible and achieving better heat dissipation.

[0005] To solve the above-mentioned technical problems, the first technical solution adopted in this application is to provide a package, comprising: a substrate, one side of which is covered with a patterned first conductive layer, wherein at least one pair of first transistors and a second transistor are disposed on the first conductive layer; a first insulating layer covering the first transistors, the second transistors, and the first conductive layer, wherein a patterned second conductive layer is covered on the side of the first insulating layer away from the first conductive layer; a second insulating layer covering the second conductive layer, wherein a patterned third conductive layer is covered on the side of the second insulating layer away from the second conductive layer, wherein a control chip is connected to the third conductive layer; wherein the third conductive layer is electrically connected to the second conductive layer at a corresponding position, and the second conductive layer is electrically connected to the first transistor or the second transistor at a corresponding position, so as to electrically connect the control chip to the first transistor and the second transistor.

[0006] The first insulating layer has multiple first metal vias, and the second conductive layer is electrically connected to the first transistor or the second transistor at the corresponding position through the first metal vias; the second insulating layer has multiple second metal vias, and the third conductive layer is electrically connected to the second conductive layer at the corresponding position through the second metal vias, so as to electrically connect the control chip to the first transistor and the second transistor.

[0007] It also includes: a patterned fourth conductive layer, which covers the other side of the substrate that is covered by the first conductive layer and is electrically connected to the first conductive layer; wherein solder balls are disposed on the fourth conductive layer.

[0008] The substrate has a third metal via, and the first conductive layer is electrically connected to the fourth conductive layer at the corresponding position through the third metal via.

[0009] The package has a fourth metal via, and the third conductive layer is electrically connected to the fourth conductive layer at the corresponding position through the fourth metal via.

[0010] The third conductive layer has several pads.

[0011] The third conductive layer has several inductors electrically connected to it via pads. The inductors are arranged corresponding to the first transistor and the second transistor, and the inductors are electrically connected to the first transistor and the second transistor at the corresponding positions.

[0012] Among them, a number of first resistors and capacitors and a number of second resistors and capacitors are electrically connected to the third conductive layer via pads; the first end of the first resistor and capacitor is electrically connected to the first end of the first transistor, the second end of the first resistor and capacitor is grounded, the second end of the first transistor is electrically connected to the control chip, the third end of the first transistor is electrically connected to the first end of the inductor, and the second end of the inductor is electrically connected to the first end of the second resistor and capacitor.

[0013] This also includes: a molding compound, which covers the components on the third conductive layer and fills the gaps between the components and the third conductive layer.

[0014] To solve the above-mentioned technical problems, the second technical solution adopted in this application is to provide a packaging method for a package, comprising: obtaining a substrate with a first conductive layer on one side, and performing patterning processing on the first conductive layer; disposing at least one pair of first transistors and a second transistor on the patterned first conductive layer; fabricating a first insulating layer on the first conductive layer with the first transistors and the second transistors, wherein the first insulating layer covers the first transistors, the second transistors and the first conductive layer; pressing a second conductive layer onto the side of the first insulating layer away from the first conductive layer, and performing patterning processing on the second conductive layer; fabricating a second insulating layer on the patterned second conductive layer; pressing a third conductive layer onto the side of the second insulating layer away from the second conductive layer, and performing patterning processing on the third conductive layer; wherein a control chip is disposed on the third conductive layer; wherein the third conductive layer is electrically connected to the second conductive layer at a corresponding position, and the second conductive layer is electrically connected to the first transistor or the second transistor at a corresponding position, so as to electrically connect the control chip to the first transistor and the second transistor.

[0015] The beneficial effects of this application are as follows: Unlike the prior art, this application provides a package and its packaging method, which encapsulates multiple transistors and has more than one current path. By embedding multiple transistors with larger dimensions among the components between the multiple layers of the package, the size of the multi-output current power module is miniaturized. Furthermore, the metal conductive layer absorbs heat for the transistors connected to it and conducts heat for the transistors, thereby not only miniaturizing the multi-output circuit power module but also improving its heat dissipation. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0017] Figure 1 This is a schematic diagram of the structure of an embodiment of the package of this application;

[0018] Figure 2 yes Figure 1 Top view of the middle package structure;

[0019] Figure 3 yes Figure 1 A schematic diagram of the circuit structure of one embodiment of the package;

[0020] Figure 4 This is a flowchart illustrating one embodiment of the encapsulation method for the encapsulation body of this application.

[0021] Reference numerals: 100, Package; 111, First conductive layer; 112, Second conductive layer; 113, Third conductive layer; 114, Fourth conductive layer; 120, Substrate; 131, First insulating layer; 132, Second insulating layer; 141, First metal via; 142, Second metal via; 143, Third metal via; 144, Fourth metal via; 151 / M1, First transistor; 152 / M2, Second transistor; 161 / S, Control chip; 171 / L, Inductor; 181 / C1, First resistor-capacitor; 1831, Resistor; 1832, Capacitor; 182 / C2, Second resistor-capacitor; 191, Solder ball; 192, Molded package. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the application. The singular forms “a,” “said,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless otherwise clearly indicated above. “Multiple” generally includes at least two, but does not exclude the inclusion of at least one.

[0024] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0025] It should be understood that the terms "comprising," "including," or any other variations used herein are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0026] Each output circuit of a power module contains multiple transistors, inductors, and other components. When a power module needs to implement multiple output circuits, it is necessary to package an even larger number of transistors, inductors, and other components within the product. This increase in components leads to a larger package size and raises heat dissipation issues. Therefore, how to achieve miniaturization and efficient heat dissipation while providing multiple output voltages has become a pressing problem to solve.

[0027] To address the aforementioned problems, this invention proposes a package and its packaging method, which embeds a large-sized transistor within the package substrate and utilizes a large-area metal layer for heat dissipation, effectively improving the aforementioned issues.

[0028] The following describes in detail, with reference to the accompanying drawings and embodiments, a package and a packaging method provided in this application.

[0029] Please see Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of an embodiment of the package of this application. Figure 2 yes Figure 1 Top view of the structure of the middle package.

[0030] In this embodiment, the package 100 includes a substrate 120, a first conductive layer 111, a first insulating layer 131, a second conductive layer 112, a second insulating layer 132, and a third conductive layer 113.

[0031] The substrate 120 has a patterned first conductive layer 111 covering one side, on which two pairs of first transistors 151 and two pairs of second transistors 152 are disposed. Specifically, the first conductive layer 111 can be made of copper, aluminum, gold, silver, or alloys thereof, or a metal-filled organic compound. In this embodiment, the first conductive layer 111 is copper foil, and the substrate 120 is a copper-clad laminate. In this embodiment, the first conductive layer 111 is covered on one side of the substrate 120 by chemical copper plating followed by electroplating. In other embodiments, other copper plating methods such as chemical copper plating or electroless copper plating can also be used. After the first conductive layer 111 is covered on one side of the substrate 120, it needs to be patterned. This can be done by chemical etching or other methods such as ion etching. Patterning the first conductive layer 111 provides different patterned current paths for the first transistors 151 and the second transistors 152 on the first conductive layer 111 to realize the logic circuit required by the power module.

[0032] like Figure 2As shown, in this embodiment, the package 100 contains two pairs of first transistors 151 and second transistors 152. In other embodiments, three or more pairs of first transistors 152 and second transistors 152 can be adapted to achieve more current paths, which is not limited here.

[0033] With the above structure, the power module package 100 of this embodiment has two output circuits. Multiple first transistors 151 and second transistors 152 are connected to the first conductive layer 111. The large-area copper first conductive layer 111 not only enables the patterned logic circuit connection between the multiple first transistors 151 and second transistors 152, but also has excellent thermal conductivity, instantly absorbing the heat generated by the first transistors 151 and second transistors, effectively enhancing the heat dissipation capability of the multi-output circuit multi-component power module package 100.

[0034] In this embodiment, a first insulating layer 131 covers the first transistor 151, the second transistor 152, and the first conductive layer 111. A patterned second conductive layer 112 is covered on the side of the first insulating layer 131 away from the first conductive layer 111. Specifically, the first insulating layer 131 fills the space between the first conductive layer 111 and the second conductive layer 112, serving to support the second conductive layer 112 and protect the first transistor 151 and the second transistor 152 on the first conductive layer 111. The formation process involves laying insulating material on the first conductive layer 111 and allowing it to cure to form the first insulating layer 131. The material of the first insulating layer 131 can specifically include one or more of epoxy resin, polyimide, bismaleimide triazine (BT), and ceramic-based materials. The specific material is not limited here. In this embodiment, the process of covering the surface of the first insulating layer 131 with the second conductive layer 112 and its patterning is the same as the process of forming and patterning the first conductive layer 111, and will not be described again here.

[0035] The second insulating layer 132 covers the second conductive layer 112. A patterned third conductive layer 113 is covered on the side of the second insulating layer 132 away from the second conductive layer 112, and a control chip 161 is connected to the third conductive layer 113. The third conductive layer 113 is electrically connected to the corresponding position of the second conductive layer 112, and the second conductive layer 112 is electrically connected to the corresponding position of the first transistor 151 or the second transistor 152, thereby electrically connecting the control chip 161 to the first transistor 151 and the second transistor 152. Specifically, the process of covering the second insulating layer 132 onto the second conductive layer 112 and the process of covering the third conductive layer 113 onto the second insulating layer 132 are the same as the formation process of the first insulating layer 131 and the second conductive layer 112, and will not be described in detail here. The pins of the control chip 161 are also electrically connected to the third conductive layer 113 via electrical connection lines (not shown). This invention sets up multiple conductive and insulating layers to embed the larger transistors among the numerous components of the multi-current output circuit power module between the multiple layers, while other components can be placed on other layers. The components do not need to be placed on the same board, thus realizing three-dimensional packaging of the components and making the multi-current output circuit package 100 as small as possible.

[0036] With the above structure, the package 100 of this embodiment is provided with two pairs of first transistors 151 and two pairs of second transistors 152 and other components, and has two current output circuits. By placing the transistors, which are among the largest components, in a multi-layer substrate, the package volume of the power module package 100 with multiple current output circuits is effectively reduced. At the same time, the transistors are arranged to directly contact a large-area conductive layer, which is used to absorb the heat generated by the transistors during operation, thus achieving a more efficient heat dissipation effect.

[0037] Please continue reading. Figure 1 The other technical features of the package 100 in this embodiment are described below.

[0038] The system also includes a patterned fourth conductive layer 114, which covers the other side of the substrate 120 that covers the first conductive layer 111 and is electrically connected to the first conductive layer 111. Solder balls 191 are disposed on the fourth conductive layer 114. Specifically, in this embodiment, the substrate 120 is a double-sided copper-clad board, which can be obtained by directly depositing copper on both sides of the substrate 120, or by depositing copper on one side of both substrates 120 and then laminating them. The solder balls 191 on the fourth conductive layer 114 facilitate the soldering of the power module package 100 onto other boards or devices requiring circuit support.

[0039] The third conductive layer 113 has several pads (not shown). Two inductors 171 are electrically connected to the third conductive layer 113 via these pads. The inductors 171 are correspondingly positioned with the first transistor 151 and the second transistor 152, and are electrically connected to their respective positions. Specifically, in this embodiment, the pads are electroplated nickel-palladium-gold pads. Nickel, palladium, and gold layers are deposited on the pads using chemical deposition to form the electroplated nickel-palladium-gold pads. Plating the pads with nickel, palladium, and gold creates a large metal surface, enhancing heat dissipation and thus improving the heat dissipation effect of the inductors 171. In other embodiments, other pads can be used. In this embodiment, there are two current output circuits, consisting of two first transistors 151 and two second transistors 152. Each first transistor 151 and each second transistor 152 is connected to an inductor 171, which stores the energy to be transferred to the load. In this embodiment, inductor 171 is correspondingly positioned with first transistor 151 and second transistor 152, and inductor 171 is located in the same vertical direction with first transistor 151 and second transistor 152. This structural design reduces the current path between inductor 171 and first transistor 151 and second transistor 152. Reducing the current path reduces power loss and heat generation, thus improving heat dissipation and cooling effect. In other embodiments, the current output circuit of the power module package is not limited to two circuits; it can also have three, four, or more circuits. Correspondingly, the number of pairs of first transistor 151 and second transistor 152 can also be adaptively set to three, four, or more pairs, and the number of inductors 171 can also be adaptively set to three, four, or more. It is only necessary to ensure that the position of inductor 171 corresponds to that of first transistor 151 and second transistor 152; this application will not elaborate further here.

[0040] In this embodiment, the third conductive layer 113 is also electrically connected to two first capacitor components 181 and two second capacitor components 182 via pads. The first end of the first capacitor component 181 is electrically connected to the first end of the first transistor 151, and the second end of the first capacitor component 181 is grounded. The second end of the second transistor 152 is electrically connected to the control chip 161, the third end of the first transistor 151 is electrically connected to the first end of the inductor 171, and the second end of the inductor 171 is electrically connected to the first end of the second capacitor component 182. Specifically, both the first capacitor component 181 and the second capacitor component 182 include a resistor 1831 and a capacitor 1832. The resistor 1831 serves as a circuit protection element, and the capacitor 1832 is used to stabilize the voltage. In the output circuit of the power module, the first capacitor component 181 is used to stabilize the input voltage, and the second capacitor component 182 is responsible for stabilizing the output voltage. For details regarding the current flow and working process of the first capacitor component 181, the second capacitor component 182, and other components, please refer to the subsequent instructions. Figure 3 describe.

[0041] The first insulating layer 131 has multiple first metal vias 141, and the second conductive layer 112 is electrically connected to the first transistor 151 or the second transistor 152 at corresponding positions through the first metal vias 141. The second insulating layer 132 has multiple second metal vias 142, and the third conductive layer 113 is electrically connected to the second conductive layer 112 at corresponding positions through the second metal vias 142, so as to electrically connect the control chip 161 to the first transistor 151 and the second transistor 152. The substrate 120 has a third metal via 143, and the first conductive layer 111 is electrically connected to the fourth conductive layer 114 at corresponding positions through the third metal via 143. The package 100 has a fourth metal via 144, and the third conductive layer 113 is electrically connected to the fourth conductive layer 114 at corresponding positions through the fourth metal via 144. Specifically, the first metal via 141, the second metal via 142, the third metal via 143, and the fourth metal via 144 are formed by first creating through holes or connection holes on the substrate 120 or insulating layer using laser drilling or chemical etching, and then chemically electroplating copper to form the first metal via 141, the second metal via 142, the third metal via 143, and the fourth metal via 144. The metal vias enable electrical connections between the various conductive layers, thereby achieving electrical connections between transistors and various components, and realizing the logic circuits required by the power module.

[0042] It should be noted that in this embodiment, the electrical connections between the first conductive layer 111, the second conductive layer 112, the third conductive layer 113, and the fourth conductive layer 114, as well as the electrical connections between each conductive layer and the transistor, are achieved through metal vias. In other preferred embodiments, pads can be provided on each conductive layer, and connecting wires can be used to connect the pads to achieve electrical connections between the conductive layers and between the conductive layers and the first transistor 151 and the second transistor 152. The connecting wires can be made of materials with excellent conductivity, such as gold, silver, and copper. Using connecting wires to achieve electrical connections has the advantage of further reducing the package size, and the connection process does not require drilling, thus avoiding dust generation and preventing harm to equipment and personnel. When using connecting wires for electrical connections, it is important to fill and protect the connector with filler adhesive at the connection end to strengthen the connection. All different electrical connection methods for each conductive layer should be included within the scope of protection of this application, and will not be elaborated upon further here.

[0043] This includes a molding compound 192, which encapsulates the components on the third conductive layer 113 and fills the gaps between the components and the third conductive layer 113. Specifically, the molding compound 192 protects the components on the third conductive layer 113. Its formation process involves applying molding compound to the third conductive layer 113, encapsulating the components on the third conductive layer 113, and filling the gaps between the components and the third conductive layer 113. After the molding compound cures, the molding compound 192 is formed. The molding compound 192 can specifically include one or more of the following: epoxy resin, polyimide, bismaleimide triazine (BT), and ceramic matrix. The specific material is not limited here.

[0044] Please see Figure 3 , Figure 3 yes Figure 1 A schematic diagram of the circuit structure of package 100 in one embodiment.

[0045] In this embodiment, the electronic components include two first transistors M1, two second transistors M2, two inductors L, two first resistor-capacitor components C1, two second resistor-capacitor components C2, and a control chip S. Specifically, in this embodiment, the power module package has two output circuits, each of which includes one first transistor M1, one second transistor M2, one inductor L, one first resistor-capacitor component C1, and one second resistor-capacitor component C2. The control chip S controls the operation of both output circuits simultaneously. The operating principles and current flow of the two output circuits are exactly the same; therefore, one of the two output circuits will be described in detail below.

[0046] The first terminal of the first resistor-capacitor C1 is electrically connected to the first terminal of the first transistor M1, the second terminal of the first resistor-capacitor C1 is grounded, the second terminal of the first transistor M1 is electrically connected to the control chip S, the third terminal of the first transistor M1 is electrically connected to the first terminal of the inductor L, and the second terminal of the inductor L is electrically connected to the first terminal of the second resistor-capacitor C2.

[0047] Its working principle is as follows: Input voltage (VIN) → first resistor-capacitor C1 (input capacitor) → second resistor-capacitor C2 → inductor L → second resistor-capacitor C2 (output capacitor) → output voltage (VOUT), which supplies power to the load. The function of inductor L is to store the energy to be transferred to the load. The control chip S controls the conduction and cutoff of the transistor, providing a current path for inductor L. The first resistor-capacitor C1 is used to stabilize the input voltage, and the second resistor-capacitor C2 is responsible for stabilizing the output voltage.

[0048] In a specific application scenario, the first terminal of the first capacitor C1 is connected to the input voltage, which can store and release the voltage. The third terminal of the first transistor M1 is also connected to the first terminal of the second transistor M2. The second terminal of the second transistor M2 is connected to the control chip S, and the third terminal of the second transistor M2 is grounded. When the connection between the first transistor M1 and the first capacitor C1 is turned off, the voltage is stored in the first capacitor C1. When the connection between the first transistor M1 and the first capacitor C1 is turned on, the first capacitor C1 releases the voltage value to the first transistor M1, which is then transmitted to the power controller and the chip control circuit. When the first transistor M1 is connected to the inductor L, the voltage is transmitted to the inductor L, then to the second capacitor C2 for storage, and finally output from the second capacitor C2 to VOUT.

[0049] The circuit described above is used to implement the function of the control chip S controlling the output circuit. It can be applied to various circuits that require power support, such as test chip control circuits, light-emitting chip control circuits, or other chip control circuits, etc., and this application does not limit it.

[0050] It should be noted that in this embodiment, there are two output circuits, including two pairs of first transistors M1 and second transistors M2, two inductors L, two first resistor-capacitor components C1, and two second resistor-capacitor components C2. In other embodiments, the number of output circuits may be three, four, or more, and the types and numbers of components may also be adjusted accordingly. This application does not impose any limitations on this.

[0051] With the above structure, the package of this embodiment is provided with two pairs of first transistors, two pairs of second transistors, and other components, and has two current output circuits. By placing the larger transistors among the numerous components within a multi-layer substrate, the package size of the multi-current output circuit power module is effectively reduced. The transistors are positioned to directly contact a large conductive layer, which absorbs the heat generated during transistor operation, achieving a more efficient heat dissipation effect. Simultaneously, the inductor on the third conductive layer is positioned in the same vertical direction as the first and second transistors, reducing the current path between the inductor and the first and second transistors. Reducing the current path reduces power loss and heat generation, further improving the heat dissipation and cooling effect.

[0052] Correspondingly, this application proposes a packaging method for a package.

[0053] Please refer to the details. Figure 4 , Figure 4 This is a flowchart illustrating one embodiment of the encapsulation method for the encapsulated body of this application.

[0054] Step S11: Obtain a substrate with a first conductive layer, and perform patterning processing on the first conductive layer. Deposit at least one pair of first transistors and a second transistor on the patterned first conductive layer.

[0055] Specifically, the material of the first conductive layer can be selected from copper, aluminum, gold, silver, and their alloys or metal-filled organic materials. In this embodiment, the first conductive layer is copper foil, and the substrate is a copper-clad laminate. In this embodiment, the first conductive layer is covered on one side of the substrate by chemical copper plating followed by electroplating. In other embodiments, other copper-clad layer methods such as chemical copper plating or electroless copper plating can also be used. After the first conductive layer is covered on one side of the substrate, the first conductive layer needs to be patterned. This can be done by chemical etching or other methods such as ion etching. Patterning the first conductive layer can provide different patterned current paths for the first transistor and the second transistor on the first conductive layer to realize the logic circuit required by the power module.

[0056] Step S12: A first insulating layer is fabricated on the first conductive layer on which the first transistor and the second transistor are disposed, and the first insulating layer covers the first transistor, the second transistor and the first conductive layer. A second conductive layer is pressed onto the side of the first insulating layer away from the first conductive layer, and the second conductive layer is patterned.

[0057] Specifically, the first insulating layer fills the space between the first conductive layer and the second conductive layer, serving to support the second conductive layer and protect the first and second transistors on the first conductive layer. Its formation process involves laying insulating material on the first conductive layer and allowing it to cure to form the first insulating layer. The material of the first insulating layer can specifically include one or more of epoxy resins, polyimides, bismaleimide triazine (BT), and ceramic substrates. The specific material is not limited here. In this embodiment, the process of covering the surface of the first insulating layer with the second conductive layer and its patterning is the same as the process of forming and patterning the first conductive layer, and will not be described again here.

[0058] Step S13: A second insulating layer is fabricated on the patterned second conductive layer, a third conductive layer is laminated on the side of the second insulating layer away from the second conductive layer, and the third conductive layer is patterned, wherein a control chip is disposed on the third conductive layer.

[0059] The third conductive layer is electrically connected to the corresponding second conductive layer, and the second conductive layer is electrically connected to the corresponding first or second transistor, thereby electrically connecting the control chip to the first and second transistors. Specifically, the process of covering the second insulating layer onto the second conductive layer and the process of covering the third conductive layer onto the second insulating layer are the same as the formation process of the first insulating layer and the second conductive layer, and will not be described in detail here. This invention, by setting multiple conductive and insulating layers, enables the embedding of larger transistors among the numerous components of the multi-current output circuit power module between multiple layers, while other components can be placed on other layers. Components do not need to be placed on the same board, achieving three-dimensional packaging of components and minimizing the size of the multi-current output circuit package.

[0060] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or principle transformations made based on the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A package, characterized in that, The package includes: A substrate, one side of which is covered with a patterned first conductive layer, wherein a plurality of pairs of first transistors and second transistors are disposed on the first conductive layer; A first insulating layer covers the first transistor, the second transistor, and the first conductive layer, and a patterned second conductive layer is covered on the side of the first insulating layer away from the first conductive layer; A second insulating layer covers the second conductive layer, and a patterned third conductive layer is covered on the side of the second insulating layer away from the second conductive layer, wherein a control chip is connected to the third conductive layer; The third conductive layer is electrically connected to the second conductive layer at the corresponding position, and the second conductive layer is electrically connected to the first transistor and the second transistor at the corresponding position, so as to electrically connect the control chip to the first transistor and the second transistor. The third conductive layer is provided with a plurality of pads, and a plurality of inductors are electrically connected to the third conductive layer through the pads. The inductors are correspondingly provided with the first transistor and the second transistor, and the inductors are electrically connected to the first transistor and the second transistor at the corresponding positions. A plurality of first resistors and capacitors and a plurality of second resistors and capacitors are also electrically connected to the third conductive layer through the pads. The first terminal of the first resistor-capacitor is electrically connected to the first terminal of the first transistor, the second terminal of the first resistor-capacitor is grounded, the second terminal of the first transistor is electrically connected to the control chip, the third terminal of the first transistor is electrically connected to the first terminal of the inductor, the second terminal of the inductor is electrically connected to the first terminal of the second resistor-capacitor, the first terminal of the inductor is also connected to the first terminal of the second transistor, the second terminal of the second transistor is electrically connected to the control chip, the second terminal of the second resistor-capacitor is connected to the third terminal of the second transistor, and the third terminal of the second transistor is grounded.

2. The package according to claim 1, characterized in that, The first insulating layer is provided with a plurality of first metal vias, and the second conductive layer is electrically connected to the first transistor and the second transistor at corresponding positions through the first metal vias; The second insulating layer is provided with a plurality of second metal vias, and the third conductive layer is electrically connected to the second conductive layer at the corresponding position through the second metal vias, so as to electrically connect the control chip to the first transistor and the second transistor.

3. The package according to claim 1, characterized in that, Also includes: A patterned fourth conductive layer covers the other side of the substrate that is covered by the first conductive layer and is electrically connected to the first conductive layer; wherein solder balls are disposed on the fourth conductive layer.

4. The package according to claim 3, characterized in that, A third metal via is provided on the substrate, and the first conductive layer is electrically connected to the fourth conductive layer at the corresponding position through the third metal via.

5. The package according to claim 3, characterized in that, The package body is provided with a fourth metal via, and the third conductive layer is electrically connected to the fourth conductive layer at the corresponding position through the fourth metal via.

6. The package according to claim 1, characterized in that, Also includes: A molding compound that covers the components on the third conductive layer and fills the gap between the components and the third conductive layer.

7. A method for packaging a package, characterized in that, The encapsulation method of the package includes: A substrate with a first conductive layer is obtained, and a patterning process is performed on the first conductive layer. Multiple pairs of first transistors and second transistors are disposed on the patterned first conductive layer. A first insulating layer is formed on a first conductive layer on which the first transistor and the second transistor are disposed, and the first insulating layer covers the first transistor, the second transistor and the first conductive layer. A second conductive layer is pressed onto the side of the first insulating layer away from the first conductive layer, and the second conductive layer is patterned. A second insulating layer is fabricated on the patterned second conductive layer, and a third conductive layer is laminated onto the side of the second insulating layer away from the second conductive layer. The third conductive layer is then patterned, and a control chip is disposed on the third conductive layer. The third conductive layer is electrically connected to the second conductive layer at a corresponding position, and the second conductive layer is electrically connected to the first transistor and the second transistor at a corresponding position, so as to electrically connect the control chip to the first transistor and the second transistor. The third conductive layer has a plurality of pads, and a plurality of inductors are connected to the third conductive layer through the pads. The inductors are correspondingly arranged to the first transistor and the second transistor, and are electrically connected to the first transistor and the second transistor at their respective positions. The third conductive layer also has a plurality of first capacitors and a plurality of second capacitors electrically connected to it through the pads. The first end of the first capacitor is electrically connected to the first end of the first transistor, and the second end of the first capacitor is grounded. The second end of the first transistor is electrically connected to the control chip. The third end of the first transistor is electrically connected to the first end of the inductor. The second end of the inductor is electrically connected to the first end of the second capacitor. The first end of the inductor is also connected to the first end of the second transistor. The second end of the second transistor is electrically connected to the control chip. The second end of the second capacitor is connected to the third end of the second transistor, and the third end of the second transistor is grounded.

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