Semiconductor structure

Abstract

Embodiments of the invention provide a semiconductor structure including two circuit regions and two inner seal rings, each inner seal ring surrounding one of the circuit regions. Each inner seal ring has a generally rectangular periphery with four inner corner stress-sink (CSR) structures. The semiconductor structure further includes an outer seal ring surrounding the two inner seal rings. The outer seal ring has a generally rectangular periphery but lacks CSR structures at the four inner corners of the outer seal ring. The outer seal ring includes a plurality of first fin structures between each of the two inner seal rings and a respective short side of the outer seal ring. Each first fin structure is parallel to the respective short side of the outer seal ring. The length of the first fin structures gradually decreases along a direction from the inner seal ring to the respective short side of the outer seal ring.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the field of semiconductors, and more specifically, to semiconductor structures. Background Technology

[0002] In semiconductor technology, semiconductor wafers are processed through various manufacturing steps to form integrated circuits (ICs). Typically, multiple circuits or IC dies are formed on the same semiconductor wafer. The wafer is then diced to separate the circuits formed thereon. To protect the circuits from moisture damage, ion contamination, and the effects of the dicing process, a sealing ring is formed around each IC die. This sealing ring is formed during the fabrication of many layers containing the circuitry, including front-end processing (FEOL) and back-end processing (BEOL) processes. FEOL includes the formation of transistors, capacitors, diodes, and / or resistors on a semiconductor substrate. BEOL includes metal interconnects and vias formed to provide wiring for the various components of the FEOL.

[0003] While existing sealing ring structures and manufacturing methods are generally sufficient to meet their intended purpose, improvements are still needed. For example, there is a desire to form dual sealing rings based on chip architecture. Summary of the Invention

[0004] One aspect of the present invention provides a semiconductor structure comprising: two circuit regions; two inner sealing rings, each of the two inner sealing rings surrounding a corresponding one of the two circuit regions, wherein each inner sealing ring has a generally rectangular periphery and four corner stress relief (CSR) structures are located at the four corners of the corresponding inner sealing ring; and an outer sealing ring surrounding the two inner sealing rings, wherein the outer sealing ring has a generally rectangular periphery but lacks the CSR structures at the four corners of the outer sealing ring, wherein the outer sealing ring includes a plurality of first fin structures located between each of the two inner sealing rings and a corresponding short side of the outer sealing ring, wherein each of the plurality of first fin structures is parallel to the corresponding short side of the outer sealing ring, and wherein the length of the plurality of first fin structures gradually decreases along a direction from the inner sealing ring to the corresponding short side of the outer sealing ring.

[0005] Another aspect of the present invention provides a semiconductor structure comprising: two circuit regions; two first sealing rings, each of the two first sealing rings having a generally rectangular periphery and surrounding a corresponding one of the two circuit regions; and a second sealing ring surrounding the two first sealing rings, the second sealing ring having a generally rectangular periphery and having four generally right-angled interior angles, wherein the second sealing ring includes a plurality of first fin structures located between each of the two first sealing rings and a corresponding short side of the second sealing ring, and a plurality of second fin structures located between each of the two first sealing rings and a long side of the second sealing ring, wherein each of the plurality of first fin structures and each of the plurality of second fin structures is parallel to the short side of the second sealing ring, wherein, among the plurality of first fin structures, the first fin structure closest to the corresponding short side of the second sealing ring is the shortest or one of the shortest first fin structures, and among the plurality of second fin structures, the second fin structure closest to the corresponding short side of the second sealing ring is the shortest or one of the shortest second fin structures.

[0006] Another aspect of the present invention provides a semiconductor structure comprising: two circuit regions; two first sealing rings, each of the two first sealing rings surrounding a corresponding one of the two circuit regions; and a second sealing ring surrounding the two first sealing rings, the second sealing ring having a generally rectangular periphery having two short sides and two long sides, wherein the second sealing ring includes a plurality of first fin structure pairs located between each of the two first sealing rings and a corresponding short side of the second sealing ring, and a plurality of second fin structure pairs located between each of the two first sealing rings and a corresponding long side of the second sealing ring, wherein each first fin structure and each second fin structure are parallel to the short side of the second sealing ring, wherein the first fin structures in each first fin structure pair have approximately equal lengths, and each first fin structure pair is shorter in length than an adjacent first fin structure pair farther from the corresponding short side of the second sealing ring, and wherein the second fin structures in each second fin structure pair have approximately equal lengths, and each second fin structure pair is shorter in length than an adjacent second fin structure pair farther from the corresponding short side of the second sealing ring. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1A This is a top view of a semiconductor structure having multiple circuit regions and multiple sealing rings according to various aspects of the present disclosure.

[0009] Figure 1B This is a top view of a semiconductor structure according to various aspects of the present disclosure, wherein the inner sealing ring is selectively opened and interconnects are selectively formed between the circuit regions.

[0010] Figure 2A According to embodiments of this disclosure Figure 1A A close-up top view of the semiconductor structure shown in region C.

[0011] Figure 2B According to embodiments of this disclosure Figure 1A A close-up top view of the semiconductor structure shown in region D.

[0012] Figure 3A According to another embodiment of this disclosure Figure 1A A close-up top view of a portion of the semiconductor structure shown in region C.

[0013] Figure 3B According to another embodiment of this disclosure Figure 1A A close-up top view of a portion of the semiconductor structure shown in region D.

[0014] Figure 4 According to embodiments of this disclosure Figure 1A A close-up top view of a portion of the semiconductor structure shown in region C.

[0015] Figure 5 It is based on the various aspects of this disclosure. Figure 1A The line "cut-A" in Figure 1A A cross-sectional view of a portion of the semiconductor structure is shown in the figure.

[0016] Figure 6 It is based on the various aspects of this disclosure. Figure 1A The line "cut-B" in Figure 1A A cross-sectional view of a portion of the semiconductor structure is shown in the figure.

[0017] Figure 7 An embodiment according to this disclosure is shown. Figures 1A-1B Cross-sectional views of each layer of the semiconductor structure are shown.

[0018] Figure 8a , Figure 8b , Figure 8c and Figure 8d Processes for forming fin structures in semiconductor structures according to various aspects of this disclosure are shown. Detailed Implementation

[0019] This invention provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, for ease of description, spatially relative terms such as “below,” “below,” “lower,” “under,” and “higher” may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. In addition to the orientation depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used in this disclosure may be interpreted accordingly. Furthermore, when numbers or ranges of numbers are described using terms such as “approximately,” “about,” etc., the term includes numbers within certain variations (e.g., + / - 10% or other variations) based on the knowledge of those skilled in the art specific to the art disclosed herein, unless otherwise stated. For example, the term “about 5 nm” may cover a size range from 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, etc.

[0021] This application generally relates to semiconductor structures and manufacturing processes, and more specifically to providing a sealing ring structure including a dual sealing ring (or double sealing ring). A double sealing ring includes an outer sealing ring surrounding two or more inner sealing rings. Each inner sealing ring surrounds a circuit region (or IC region or chip region). Certain regions of the inner sealing rings can be selectively opened or closed during manufacturing, depending on the chip architecture. For example, two circuit regions can be formed with interconnects (wafer-level interconnects) between them to form a connected die, or they can be formed as separate, individual dies. In the former case, the inner sealing rings surrounding each circuit region are partially open to allow the interconnects to pass through. In the latter case, the inner sealing rings surrounding each circuit region are completely closed. In either case, the outer sealing ring is completely closed. In the former case, the wafer is cut (or diced) outside the outer sealing ring, thus the outer sealing ring provides fully enclosed protection for the connected dies. In the latter case, the wafer is cut between the inner sealing rings, and the outer sealing ring is also cut, thus the inner sealing rings provide fully enclosed protection for a single die.

[0022] In embodiments of this disclosure, both the outer and inner sealing rings have a generally rectangular perimeter (i.e., their external contours are rectangular or approximately rectangular). Each inner sealing ring also includes four corner stress relief (CSR) structures at the four interior corners of its rectangular perimeter. The CSR structures are triangular to improve the structural and mechanical stability of the inner sealing ring. The outer sealing ring does not have CSR structures at its four interior corners. Therefore, both the outer and inner boundaries of the outer sealing ring are generally rectangular, which allows the inner sealing ring to be placed very close to the outer sealing ring. In other words, the inner and outer sealing rings can be placed adjacent to each other without any empty or redundant area between them. This advantageously reduces the packaging area of ​​the outer sealing ring and the total chip area after chip sorting.

[0023] The outer sealing ring according to this disclosure includes a fin structure extending longitudinally parallel to the short side of the outer sealing ring. The fin structure is disposed along both the short and long sides of the inner sealing ring. The fin structure disposed along the short side of the inner sealing ring forms approximately a right angle with the fin structure disposed along the long side of the same inner sealing ring, and the outer corner of the inner sealing ring fits tightly against this right angle. In an embodiment, the fin structure is formed from a spacer pattern derived from a mandrel pattern in a mandrel-spacer dual patterning process. The mandrel pattern is formed together with other mandrel patterns in the circuit area and the sealing ring area to improve pattern consistency. Subsequently, the fin structure is formed by etching a semiconductor substrate using the spacer pattern or a derivative thereof. Therefore, the fin structure comprises a semiconductor material. Furthermore, the fin structure forms a portion of a wall structure extending from the substrate to a passivation layer. The wall structure may include a gate structure, contacts, a dielectric layer, and a metal layer constructed above the fin structure, and is part of the outer sealing ring. By forming these fin structures, the circuit area can be better protected. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures for performing the embodiments described herein and / or achieving the same benefits.

[0024] Figure 1A This is a top view of a semiconductor structure (or semiconductor device) 100 according to the present disclosure. The semiconductor structure 100 (e.g., a fabricated wafer or a portion thereof) includes an outer sealing ring 350 surrounding (or enclosing) a plurality of inner sealing rings 300. Each inner sealing ring 300 surrounds a circuit region (or IC die) 150. Figure 1AThe embodiment depicted shows two inner sealing rings 300 surrounding two circuit regions 150. In other embodiments (not shown), an outer sealing ring 350 may surround more than two inner sealing rings 300, each inner sealing ring 300 surrounding a circuit region 150. In some embodiments, each circuit region 150 may perform the same function. For example, each circuit region 150 may be a memory chip or a processor chip. In some embodiments, the circuit regions 150 may perform different functions. For example, one circuit region 150 may be a transmitter chip (e.g., a wireless transmitter), while another circuit region 150 may be a receiver chip (e.g., a wireless receiver). Figure 1A In the illustrated embodiment, each circuit region 150 is manufactured as a separate die or chip. For example, as... Figure 1A As shown, the semiconductor structure 100 is cut (or diced) along the scribing line 180. As a result, the outer sealing ring 350 is also cut. The inner sealing ring 300 remains intact during the cutting process and provides sealing and protection for each individual circuit region 150 (also referred to as an individual die 150 in this embodiment).

[0025] Figure 1B yes Figure 1A A variation of the illustrated embodiment, wherein the inner sealing ring 300 has an opening 500 formed at a selected location, and an interconnect 510 (which is a conductor) is formed to connect multiple circuit regions 150 through the opening 500. The interconnect 510 is a wafer-level (or die-level) interconnect, which advantageously provides reduced resistance and better noise immunity compared to some off-chip interconnects. The interconnected circuit regions 150 (also referred to in this embodiment as connected dies 150) form a larger system (or system-on-wafer). In such an embodiment, the semiconductor structure 100 is cut (or diced) along a scribe line 180 outside the outer sealing ring 350, such as... Figure 1B As shown. Therefore, the outer sealing ring 350 provides a sealing and protection function for the connected core 150.

[0026] In the embodiments, for forming Figure 1A The semiconductor structure 100 shown includes a mask group (referred to as mask group A) and a mask for forming... Figure 1BThe mask group (referred to as mask group B) of the semiconductor structure 100 shown shares some common masks. Masks, also called photomasks or photolithography templates, are used to perform photolithography on a semiconductor wafer to form the various components of the semiconductor structure 100. For example, mask group A and mask group B may share common masks for some of the diffusion layers, fin layers, gate layers, contact layers, via layers, and metal layers. A fin layer refers to the semiconductor layer containing semiconductor fins that are formed over a semiconductor substrate (e.g., a silicon substrate) for FinFETs. Mask group A and mask group B differ in that the layers on which interconnects 510 are formed, such as some metal layers, particularly higher-level metal layers, such as a fifth metal (M5) layer, a sixth metal (M6) layer, and / or other metal layers. By sharing masks between mask group A and mask group B, manufacturers can selectively produce individual dies 150, connected dies 150, or both, while reducing overall costs. For example, if mask group A and mask group B each have N masks, the manufacturer may only need to produce M common masks, N1 masks specifically for mask group A, and N2 masks specifically for mask group B, where M + N1 + N2 is less than 2N. The fewer masks produced, the lower the manufacturer's cost. Single dies 150 and connected dies 150 can meet different market demands.

[0027] Figure 1A and Figure 1B The outer sealing ring 350 in the illustrated embodiment is the same. Except... Figure 1B Beyond those openings of 500, Figure 1A and Figure 1B The inner sealing ring 300 in the illustrated embodiment is the same. Therefore, for simplicity, the following description of the inner sealing ring 300 and the outer sealing ring 350 applies to both embodiments, unless it pertains to the opening 500.

[0028] refer to Figure 1AThe outer sealing ring 350 has a rectangular or substantially rectangular periphery. In other words, the outer contour (or outer boundary) of the outer sealing ring 350 is rectangular or substantially rectangular. Furthermore, each inner sealing ring 300 has a rectangular or substantially rectangular periphery. In other words, the outer contour (or outer boundary) of each inner sealing ring 300 is rectangular or substantially rectangular. The inner sealing ring 300 also includes four corner sealing ring (CSR) structures 360 at the four interior corners of the rectangular or substantially rectangular periphery. In embodiments, the CSR structures 360 are triangular or substantially triangular. For example, the periphery of each CSR structure 360 ​​is a right-angled triangle or a right-angled isosceles triangle. The legs of the triangle are parallel to the periphery edges of the inner sealing ring 300. The CSR structures 360 provide various mechanical and structural advantages to the inner sealing ring 300, such as preventing layer peeling at chip corners during dicing processes. For the CSR structures 360, the internal contour (or internal boundary) of the inner sealing ring 300 is octagonal or substantially octagonal. The outer sealing ring 350 does not have this CSR structure at its inner corners. Therefore, the inner corners of the outer sealing ring 350 are 90 degrees or approximately 90 degrees. This allows the outer corners (right angles) of the inner sealing ring 300 to fit tightly into the inner corners (also right angles) of the outer sealing ring 350, resulting in no gaps between the outer sealing ring 350 and the inner sealing ring 300. This reduces the total area occupied by the semiconductor structure 100, thereby saving manufacturing costs. The region 420 between the inner sealing rings 300 may include dummy patterns (not shown) for achieving a uniform pattern density.

[0029] An embodiment according to this disclosure is shown in Figure 1A A close-up top view of the semiconductor structure 100 shown in region C. Figure 2B An embodiment according to this disclosure is shown in Figure 1A A close-up top view of the semiconductor structure 100 shown in region D. (Reference) Figures 2A-2B The outer sealing ring 350 includes fin structures 402, 412, 414, 440, 442, 444, and 446. Fin structure 440 is positioned longitudinally parallel to the long side 350-L of the outer sealing ring 350. Fin structure 442 is positioned longitudinally parallel to the short side 350-S of the outer sealing ring 350. Fin structure 444 diagonally connects fin structure 440 and fin structure 442. Figure 2B As shown, the fin structure 442 constitutes a portion of the short side 350-S of the outer sealing ring 350. Furthermore, even in Figures 2A-2B Not shown in the diagram, fin structures 440, 442, and 444 also form a continuous ring surrounding the inner sealing ring 300 (e.g., Figure 1A(As shown). Fin structures 446 are positioned longitudinally parallel to fin structures 444 and are located at the outer corner of the outer sealing ring 350. In other words, fin structures 446 and the inner sealing ring 300 are located on opposite sides of fin structure 444. Fin structures 446 are discrete segments, not annular. Furthermore, the length of fin structures 446 gradually decreases as they move away from fin structure 444. The fin structures 446 together form an approximately triangular shape.

[0030] Fin structures 402 are positioned longitudinally parallel to the short side 350-S of the outer sealing ring 350. Therefore, they are also parallel to the short side of the inner sealing ring 300. Fin structures 402 are narrower in width than fin structures 442. In one embodiment, each fin structure 442 is up to three times wider than each fin structure 402. Fin structures 402 are discrete segments, not annular. Fin structures 402 are placed close to fin structures 444. In one embodiment, fin structures 402 are placed as close as possible to fin structures 444, where design rules permit. For example, in some embodiments, the distance d1 between fin structures 402 and fin structures 444 in the "X" direction can be 1 μm or less, such as in the range of 0.5 μm to 1 μm. Furthermore, the length of fin structures 402 gradually decreases in the "+Y" direction (i.e., from the short side of the inner sealing ring to the short side of the outer sealing ring). Therefore, the fin structure 402 closest to the inner sealing ring 300 is the longest, and the fin structure 402 furthest from the inner sealing ring 300 is the shortest. The fin structures 402 are also called staggered fin structures 402 because their lengths are staggered (one is shorter than the other along the "+Y" direction). The fin structures 402 together form a trapezoidal shape.

[0031] Fin structures 414 and 412 are also positioned longitudinally parallel to the short side 350-S of the outer sealing ring 350. They are positioned between the long side 350-L of the inner sealing ring 300 and the outer sealing ring 350. Fin structures 414 have approximately equal lengths to each other. The length of fin structures 412 gradually decreases along the "+Y" direction. Therefore, the fin structure 412 closest to the short side 350-S of the outer sealing ring 350 is the shortest, and the fin structure 412 farthest from the short side 350-S of the outer sealing ring 350 is the longest. The fin structures 412 together form a trapezoidal shape. Fin structures 412 are also referred to as staggered fin structures 412. In one embodiment, the ends of fin structures 412 and fin structures 402 near fin structure 444 are substantially aligned in a straight line. Furthermore, the ends of fin structures 412 farthest from fin structure 444 are substantially aligned in a straight line along the Y direction. Therefore, the fin structures 402, 412 and 414 almost completely fill the space between the inner sealing ring 300 and the fin structures 440, 444 and 442, which achieves good pattern density and improves manufacturing processes such as photolithography and chemical mechanical polishing (CMP).

[0032] Figures 3A-3BAnother embodiment of the semiconductor structure 100 is shown. For simplicity, Figures 3A-3B Not all components of the semiconductor structure 100 are shown. In this embodiment, fin structure 402 includes fin structure pairs 402p. The two fin structures in each fin structure pair 402p have approximately equal lengths (i.e., they are considered to have the same length within manufacturing tolerances). The length of each fin structure pair 402p is shorter than the length of the adjacent pair 402p closer to the inner sealing ring 300. Similarly, fin structure 412 includes fin structure pairs 412p. The two fin structures in each fin structure pair 412p have approximately equal lengths (i.e., they are considered to have the same length within manufacturing tolerances). The length of each fin structure pair 412p is shorter than the length of the adjacent pair 412p farther from the short side 350-S of the outer sealing ring 350. Fin structure 414 also includes fin structure pairs 414p. However, all fin structure pairs 414p have approximately equal lengths. In one embodiment, fin structures 402, 412, and 414 are formed by a double-patterning process located on a mandrel pattern (e.g., Figures 8a-8b The spacer pattern on the sidewall of the mandrel pattern 112 (e.g.) Figures 8b-8c The spacer pattern 114 is formed. Each pair of 402p, 412p, or 414p corresponds to a pair of spacer patterns on the same mandrel pattern. Therefore, each pair of 402p, 412p, or 414p has approximately the same length. Furthermore, the mandrel pattern used to form the fin structure 402 is formed with staggered lengths, for example... Figure 2A The staggered lengths of the fin structures 402. Therefore, each fin structure pair 402p is formed with staggered lengths. Similarly, the mandrel pattern used to form the fin structures 412 is formed with staggered lengths, for example... Figure 2A The staggered length of the midfin structure 412. Therefore, each fin structure pair 412p is formed with a staggered length.

[0033] Figure 4 It shows Figure 1A The inner sealing ring 300 is located in region C. As shown in the figure, the inner sealing ring 300 includes fin structures 340, 342, 344, 346, and CSR 360. Fin structure 340 is positioned longitudinally parallel to the "Y" direction (i.e., parallel to...). Figure 2A The long side 350-L of the outer sealing ring 350 in the middle. The fin structure 342 is positioned longitudinally parallel to the "X" direction (i.e., parallel to the direction of the "X" direction). Figure 2A The short side 350-S of the outer sealing ring 350. Fin structures 344 diagonally connect fin structures 340 and 342. Furthermore, even though not shown, fin structures 340, 342, and 344 form a circuit region 150 (see...). Figure 1AA continuous ring. Fin structure 346 is positioned longitudinally parallel to fin structure 344 and located at the outer corner of inner sealing ring 300. In other words, fin structure 346 and CSR 360 are located on opposite sides of fin structure 344. CSR 360 may include discrete segments, and the overall shape of CSR 360 is trapezoidal, wherein the shorter base of the trapezoid is close to fin structure 344, the longer base of the trapezoid is away from fin structure 344, and the two sides of the trapezoid are parallel to fin structure 342 and fin structure 340, respectively. Fin structure 346 is discrete segments, not annular. Furthermore, the length of fin structures 346 gradually decreases as they move away from fin structure 344. The fin structures 346 together form a substantially triangular shape, which closely matches the right angle formed by fin structures 402, 414, and 412 (see Figure 2A ).

[0034] Figure 5 The semiconductor structure 100 according to an embodiment is illustrated along... Figure 1A The line “Cut-A” shows the cross-section. In fact, it illustrates the cross-section of the outer sealing ring 350 according to an embodiment. Figure 6 The edge of semiconductor structure 100 is shown Figure 1A The line “Cut-B” in the diagram represents a cross-section. In fact, it shows a cross-section of the inner sealing ring 300 according to an embodiment. Some structures of the outer sealing ring 350 and the inner sealing ring 300 are the same or substantially the same. For example, each of the outer sealing ring 350 and the inner sealing ring 300 includes sub-sealing rings 212a, 212b, 212c, and 212d.

[0035] refer to Figure 5 and Figure 6 The semiconductor structure 100 includes a substrate 202. In this embodiment, the substrate 202 is a silicon substrate. In various embodiments, the substrate 202 may alternatively include other semiconductor materials, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof. The substrate 202 may include doped active regions, such as P-wells and / or N-wells 204 (see...). Figure 7 The substrate 202 may further include other components, such as a buried layer and / or an epitaxial layer. Additionally, the substrate 202 may be a semiconductor-on-insulator, such as silicon-on-insulator (SOI). In other embodiments, the substrate 202 may include a doped epitaxial layer, a graded semiconductor layer, and / or may also include a semiconductor layer overlaid on another different type of semiconductor layer, such as a silicon layer on a silicon-germanium layer. The substrate 202 includes an active region (e.g., N0) configured as an NMOS device (e.g., nFET) or a PMOS device (e.g., pFET). + or P +Doped region). Substrate 202 may include an underlayer, devices, junctions, and other components (not shown). Outer sealing ring 350, inner sealing ring 300, and circuit region 150 are embedded in or on substrate 202. Substrate 202 also includes an assembly isolation region 170 between inner sealing ring 300 and circuit region 150 (see Figure 6 And a scribe line area (for scribe line 180) surrounding the outer sealing ring 350 and optionally overlapping the outer sealing ring 350.

[0036] The outer sealing ring 350 includes sub-sealing rings 212a, 212b, 212c, 212d, and 212f. Sub-sealing ring 212a is wider than the other sub-sealing rings and can therefore be referred to as the main sub-sealing ring. The multiple nested sub-sealing rings ensure that at least the inner sub-sealing rings are not broken during cutting (e.g., die sawing). For example, sub-sealing rings 212c and 212d can protect sub-sealing rings 212a, 212b, and 212f from damage that may occur during cutting.

[0037] Each of the sub-sealing rings 212a, 212b, 212c, 212d, and 212f includes one or more conductive elements 218 disposed on or within fin structures 440 and 414 formed on or within substrate 202. Although not shown, one or more conductive elements 218 are also disposed on fin structures 402, 412, 442, 444, and 446 formed on or within substrate 202. The fin structures are isolated from each other by an isolation structure 230 such as shallow trench isolation (STI). The conductive elements 218 may include a plurality of vertically stacked conductors and may include doped semiconductors, metals, conductive nitrides, conductive oxides, or other types of conductive materials. Above the conductive elements 218, each of the sub-sealing rings 212a, 212b, 212c, 212d, and 212f also includes a plurality of metal layers 251 stacked on top of each other and vertically connected through metal vias 252. The metal layer 251 and the metal via 252 may comprise copper, a copper alloy, or other conductive materials, and may be formed using a damascene or dual damascene process. Each of the metal layer 251 and the metal via 252 may comprise a conductive barrier layer (such as TiN or TaN) surrounding a metal core (e.g., copper). In one embodiment, each of the metal layers 251 is formed as an annular or quasi-annular structure (such as a substantially square annular structure) surrounding the inner sealing ring 300 and the circuit region 150. In other words, each of the metal layers 251 is formed as a closed structure and extends along the edge of the area occupied by the inner sealing ring 300 and the circuit region 150. In this embodiment, an annular or quasi-annular structure refers to a closed structure that may be rectangular, square, substantially rectangular, substantially square, or other polygonal. In one embodiment, the outer vias 252 (the vias 252 closest to and farthest from the inner sealing ring 300 and the circuit region 150, respectively) are formed as annular. Therefore, they are also referred to as via bars. The internal through-holes 252 are formed as discrete through-holes, which form lines parallel to the external through-holes 252. In this embodiment, each sub-sealing ring 212a and 212c also includes an aluminum pad 264.

[0038] Conductive components 218, metal layer 251, and metal vias 252 are embedded in dielectric layer 210. Dielectric layer 210 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, very low-k (ELK) dielectric material, or other suitable dielectric material (e.g., including silicon, oxygen, nitrogen, carbon, or other suitable insulating components), or combinations thereof. Semiconductor structure 100 also includes a passivation layer 260 above dielectric layer 210 and another passivation layer 262 above passivation layer 260. Each aluminum pad 264 includes a top disposed above passivation layer 260 and a bottom penetrating passivation layer 260 and electrically connected to sub-sealing rings 212a and 212c. In an embodiment, each aluminum pad 264 is formed as an annulus surrounding inner sealing ring 300 and circuit region 150. Therefore, aluminum pad 264 may also be referred to as aluminum ring 264. Aluminum pad 264 can be formed simultaneously with bonding pads (not shown) exposed on the top surface of circuit region 150. Passivation layer 262 is disposed above passivation layer 260 and aluminum pad 264. Passivation layers 260 and 262 can be formed of oxides, nitrides, and combinations thereof, and can be formed of the same or different materials. Each sub-sealing ring 212a-212f takes the form of a vertical wall extending from substrate 202 (specifically, from fin structures 402, 412, 414, 440, 442, 444, and 446) to upper metal layer 251 and aluminum pad 264.

[0039] Trench 261 is disposed in passivation layer 262 above sub-sealing ring 212b. Another trench 263 is disposed in passivation layer 262 above sub-sealing ring 212d. In one embodiment, each of trenches 261 and 263 is formed in an annular shape surrounding inner sealing ring 300 and circuit region 150. An advantageous feature of the dual trenches 261, 263 is that if a crack occurs in the scribe line during dicing, the crack will be prevented by trench 263. Even if a crack propagates through trench 263, the stress on the crack, if any, is significantly reduced by trench 261. Semiconductor structure 100 may include Figure 5 Other components and layers not shown.

[0040] Figure 6 The semiconductor structure 100 according to various aspects of this disclosure is shown along... Figure 1A A cross-sectional view of the section marked "Cut-B". (Reference) Figure 6 Similar to the outer sealing ring 350, the inner sealing ring 300 also includes multiple sub-sealing rings, such as sub-sealing rings 212a, 212b, 212c, and 212d. The components of the inner sealing ring 300 are the same as those of the outer sealing ring 350, except that, for example, the dimensions of the sub-sealing rings may be different.

[0041] The semiconductor structure 100 also includes an assembly isolation region 170 between the inner sealing ring 300 and the circuit region 150. The assembly isolation region 170 includes an isolation structure (e.g., shallow trench isolation) 230. The isolation structure 230 may include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon, or other suitable isolation components) or combinations thereof. The isolation structure 230 may include different structures, such as shallow trench isolation (STI) structures and / or deep trench isolation (DTI) structures. In some embodiments, the semiconductor structure 100 may include various pseudo-wires and pseudo-vias in the assembly isolation region 170.

[0042] Figure 7 A cross-sectional view of a semiconductor structure 100 is shown, illustrating various layers therein, including a well (or diffusion layer) 204, an isolation structure 230, fin layers 215 (including fin structures 402, 412, 414, 440, 444, 442, 446, 340, 342, 344, and 346), a gate layer 240, a gate via layer 242, a contact layer (not shown, but at the same level as the gate layer 240), a contact via (or via 0) layer (not shown, but at the same level as the gate via layer 242), first to sixth metal (M1, M2, M3, M4, M5, and M6) layers 251, and first to fifth via (via 1, via 2, via 3, via 4, and via 5) layers 252. The semiconductor structure 100 may include... Figure 7 Other layers or components not shown, such as doped source / drain semiconductor layers. Conductive component 218 may include doped source / drain semiconductor layers, gate layer 240, gate via layer 242, contact layer, contact via, or combinations thereof.

[0043] In an embodiment, well 204 is formed in or on substrate 202 in circuit region 150. Well 204 includes a p-type doped region configured for an n-type transistor and an n-type doped region configured for a p-type transistor. Fin layer 215 includes fin-shaped semiconductor material (or fin or fin structure) protruding from substrate 202. In an embodiment, fin layer 215 may include silicon, germanium, silicon-germanium, or other suitable semiconductor material.

[0044] Gate layer 240 includes a gate structure having a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include silicon dioxide, silicon oxynitride, and / or high-k dielectric materials, such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, and HfAlO. xZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, or combinations thereof. High-k dielectric materials generally refer to dielectric materials with a high dielectric constant (such as greater than that of silicon oxide (k≈3.9)). The gate electrode layer may include titanium, aluminum, tantalum carbide, tantalum carbonitride, silicon tantalum nitride, titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, tungsten, cobalt, copper, and / or other suitable materials.

[0045] Each of the gate via layer 242, contact layer (not shown), contact via layer (not shown), via layer 252, and metal layer 251 may comprise titanium, tantalum, tungsten, cobalt, molybdenum, ruthenium, or conductive nitrides such as titanium nitride, aluminum titanium nitride, tungsten nitride, tantalum nitride, or combinations thereof, and may be formed by CVD, PVD, ALD, and / or other suitable processes.

[0046] Figures 8a-8d The process for forming fin structures 402, 412, 414 and other fin structures using a mandrel-spacer dual patterning method is shown. (Reference) Figure 8a Hard mask layers 106, 108, and 110 are formed over substrate 202, and a mandrel pattern 112 is formed over hard mask layer 110. Hard mask layers 106, 108, and 110 may comprise any suitable material, including titanium nitride, silicon oxide, and silicon carbide. Mandrel pattern 112 may comprise an anti-reflective polymeric material. Mandrel pattern 112 may be formed using photolithography and etching processes and may be shaped as fin structures 402, 412, 414, and other fin structures, such as reference fins. Figures 2A-2B Those described. In an embodiment (not shown), the mandrel pattern 112 is used as an etching mask to etch hard mask layers 106, 108, and 110 to form a hard mask pattern, and then the hard mask pattern is used as an etching mask to etch substrate 202, thereby forming fin structures 402, 412, and 414 in substrate 202. In this embodiment, spacer pattern 114 is formed on the sidewall of mandrel pattern 112, as... Figure 8b As shown. Subsequently, the mandrel pattern 112 is removed, leaving the spacer pattern 114 on the hard mask layer 110, as shown. Figure 8c As shown. The spacer pattern 114 can then be adjusted. In an embodiment, the spacer pattern 114 has a shape similar to the reference pattern. Figures 3A-3BThe fin structures 402, 412, and 414 are described in corresponding shapes. Subsequently, the shape of the spacer pattern 114 is transferred to the substrate 202 using an etching process, thereby forming the fin structures 402, 412, and 414 in or on the substrate 202, as shown. Figure 8d As shown.

[0047] While not intended to be limiting, embodiments of this disclosure offer one or more of the following advantages. For example, embodiments of this disclosure provide a semiconductor structure with a dual-sealing ring structure. The dual-sealing ring structure includes an outer sealing ring surrounding two or more inner sealing rings. Each inner sealing ring encloses a circuit region. The semiconductor structure can be used to form connected dies or individual dies. The outer sealing ring provides sealing and protection for the connected dies. The inner sealing rings provide sealing and protection for the individual dies. The inner sealing rings fit tightly against the outer sealing rings, with no extra space between them, thereby reducing the package area of ​​the semiconductor structure. Furthermore, in some embodiments, multiple (e.g., four) sub-sealing rings are formed in the outer and inner sealing rings to further improve the operational reliability of the sealing rings. Embodiments of this disclosure can be readily integrated into existing semiconductor manufacturing processes.

[0048] In one embodiment, this disclosure relates to a semiconductor structure comprising two circuit regions and two inner sealing rings. Each of the two inner sealing rings surrounds a corresponding one of the two circuit regions. Each inner sealing ring has a generally rectangular periphery and four corner stress relief (CSR) structures at the four corners of the corresponding inner sealing ring. The semiconductor structure also includes an outer sealing ring surrounding the two inner sealing rings, wherein the outer sealing ring has a generally rectangular periphery and no CSR structures at the four corners of the outer sealing ring. The outer sealing ring includes a plurality of first fin structures located between each of the two inner sealing rings and a corresponding short side of the outer sealing ring. Each of the plurality of first fin structures is parallel to the corresponding short side of the outer sealing ring. The length of the plurality of first fin structures gradually decreases along the direction from the inner sealing ring to the corresponding short side of the outer sealing ring.

[0049] In one embodiment of the semiconductor structure, the plurality of first fin structures include a plurality of pairs of first fin structures, wherein the first fin structures in each pair of first fin structures have substantially equal lengths, and the length of each pair of first fin structures is shorter than that of the adjacent pair of first fin structures closer to the inner sealing ring.

[0050] In one embodiment, the outer sealing ring further includes a plurality of second fin structures located between the long sides of the two inner sealing rings and the outer sealing ring, wherein each of the plurality of second fin structures is parallel to the short side of the outer sealing ring, and the one closest to the short side of the outer sealing ring is the shortest among the plurality of second fin structures. In a further embodiment, the plurality of second fin structures includes a plurality of pairs of second fin structures, wherein the second fin structures in each pair of second fin structures have substantially equal lengths, and the length of each pair of second fin structures is shorter than the length of the adjacent pair of second fin structures farther from the short side of the outer sealing ring.

[0051] In another embodiment, the outer sealing ring further includes a plurality of third fin structures forming the long side of the outer sealing ring, a plurality of fourth fin structures forming the short side of the outer sealing ring, and a plurality of fifth fin structures diagonally connecting the plurality of third fin structures and the plurality of fourth fin structures. In a further embodiment, the outer sealing ring further includes a plurality of sixth fin structures parallel to the plurality of fifth fin structures, wherein the plurality of sixth fin structures and the inner sealing ring are disposed on opposite sides of the plurality of fifth fin structures. In yet another embodiment, the distance from the plurality of first fin structures to the plurality of fifth fin structures along a direction parallel to the short side of the outer sealing ring is less than 1 μm.

[0052] In an embodiment of the semiconductor structure, each inner sealing ring includes a plurality of seventh fin structures forming the long side of the corresponding inner sealing ring, a plurality of eighth fin structures forming the short side of the corresponding inner seal, and a plurality of ninth fin structures, with the plurality of seventh fin structures and the plurality of eighth fin structures diagonally connected. In a further embodiment, each inner sealing ring also includes a plurality of tenth fin structures parallel to the plurality of ninth fin structures, wherein the plurality of tenth fin structures are disposed between the plurality of ninth fin structures and the outer sealing ring. In another embodiment, one of the plurality of tenth fin structures and the CSR structure is disposed on opposite sides of the plurality of ninth fin structures.

[0053] In another embodiment, this disclosure relates to a semiconductor structure. The semiconductor structure includes two circuit regions; two first sealing rings, each of the two first sealing rings having a generally rectangular periphery and surrounding a corresponding one of the two circuit regions; and a second sealing ring surrounding the two first sealing rings, the second sealing ring having a generally rectangular periphery and four generally right-angled interior angles. The second sealing ring includes a plurality of first fin structures located between each of the two first sealing rings and a corresponding short side of the second sealing ring, and a plurality of second fin structures located between each of the two first sealing rings and a long side of the second sealing ring. Each of the plurality of first fin structures and each of the plurality of second fin structures is parallel to the short side of the second sealing ring. Among the plurality of first fin structures, the one closest to the corresponding short side of the second sealing ring is either the shortest or one of the shortest, and among the plurality of second fin structures, the one closest to the corresponding short side of the second sealing ring is either the shortest or one of the shortest.

[0054] In an embodiment of the semiconductor structure, a plurality of first fin structures and a plurality of second fin structures are formed by spacer patterns on the sidewalls of a mandrel pattern in a dual patterning process.

[0055] In another embodiment, the plurality of first fin structures include a plurality of pairs of first fin structures, wherein the first fin structures in each pair have approximately equal lengths, and the length of each pair of first fin structures is shorter than the length of the adjacent pair of first fin structures farther from the corresponding short side of the second sealing ring. In a further embodiment, the plurality of second fin structures include a plurality of pairs of second fin structures, wherein the second fin structures in each pair have approximately equal lengths, and the length of each pair of second fin structures is shorter than the length of the adjacent pair of second fin structures farther from the corresponding short side of the second sealing ring.

[0056] In one embodiment, the plurality of first fin structures and the plurality of second fin structures comprise semiconductor material. In another embodiment, each of the plurality of first fin structures and the plurality of second fin structures is located at the bottom of a vertical structure extending from the semiconductor substrate to a top metal layer covered by a passivation layer.

[0057] In another embodiment, this disclosure relates to a semiconductor structure comprising two circuit regions and two first sealing rings, each of the two first sealing rings surrounding a corresponding one of the two circuit regions. The semiconductor structure also includes a second sealing ring surrounding the two first sealing rings. The second sealing ring has a generally rectangular periphery with two short sides and two long sides. The second sealing ring includes a plurality of first fin structure pairs located between each of the two first sealing rings and a corresponding short side of the second sealing ring, and a plurality of second fin structure pairs located between each of the two first sealing rings and a corresponding long side of the second sealing ring. Each first fin structure and each second fin structure is parallel to the short side of the second sealing ring. The first fin structures in each first fin structure pair have approximately equal lengths, and the length of each first fin structure pair is shorter than that of an adjacent first fin structure pair farther from the corresponding short side of the second sealing ring. The second fin structures in each second fin structure pair have approximately equal lengths, and the length of each second fin structure pair is shorter than that of an adjacent second fin structure pair farther from the corresponding short side of the second sealing ring.

[0058] In one embodiment, the second sealing ring further includes a third fin structure located between each of the two first sealing rings and a corresponding long side of the second sealing ring, wherein the third fin structure is longitudinally parallel to the second fin structure, and the third fin structure has approximately equal lengths and is distributed approximately evenly along the corresponding long side of the second sealing ring.

[0059] In another embodiment, the first and second fin structures are formed by etching a semiconductor substrate using spacer patterns formed on the sidewalls of a mandrel pattern in a dual patterning process. In yet another embodiment, a plurality of first fin structure pairs are distributed substantially uniformly in a space of about 5 μm to 8 μm wide.

[0060] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can be modified, substituted, and altered in various ways without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, comprising: Two circuit regions; Two inner sealing rings, each of which surrounds a corresponding one of the two circuit regions, wherein each inner sealing ring has a rectangular periphery, and four corner stress relief (CSR) structures are located at the four corners of the corresponding inner sealing ring; and An outer sealing ring surrounds the two inner sealing rings, wherein the outer sealing ring has a rectangular perimeter, but lacks the inner corner stress relief structure at the four inner corners of the outer sealing ring. The outer sealing ring includes a plurality of first pseudo-fin structures located between each of the two inner sealing rings and the corresponding short side of the outer sealing ring. Each of the plurality of first pseudo-fin structures is parallel to the corresponding short side of the outer sealing ring, and The lengths of the plurality of first pseudofin structures gradually decrease along the direction from the inner sealing ring to the corresponding short side of the outer sealing ring.

2. The semiconductor structure according to claim 1, wherein, The plurality of first pseudofin structures include a plurality of pairs of first pseudofin structures, wherein the first pseudofin structures in each pair of first pseudofin structures have substantially equal lengths, and each pair of first pseudofin structures is shorter in length than the adjacent pair of first pseudofin structures closer to the inner sealing ring.

3. The semiconductor structure according to claim 1, wherein, The outer sealing ring also includes: Multiple second pseudo-fin structures are located between the long sides of the two inner sealing rings and the outer sealing ring. Each of the plurality of second pseudo-fin structures is parallel to the short side of the outer sealing ring, and Among the plurality of second pseudo-fin structures, the second pseudo-fin structure closest to the short side of the outer sealing ring is the shortest.

4. The semiconductor structure according to claim 3, wherein, The plurality of second pseudofin structures include a plurality of pairs of second pseudofin structures, wherein the second pseudofin structures in each pair of second pseudofin structures have substantially equal lengths, and each pair of second pseudofin structures is shorter in length than the adjacent pair of second pseudofin structures that is farther from the short side of the outer sealing ring.

5. The semiconductor structure according to claim 3, wherein, The outer sealing ring also includes: Multiple third pseudofin structures form the long side of the outer sealing ring; Multiple fourth pseudo-fin structures form the short side of the outer sealing ring; and Multiple fifth pseudofin structures are diagonally connected to the multiple third pseudofin structures and the multiple fourth pseudofin structures.

6. The semiconductor structure according to claim 5, wherein, The outer sealing ring also includes: Multiple sixth pseudofin structures are parallel to the multiple fifth pseudofin structures, wherein the multiple sixth pseudofin structures and the inner sealing ring are disposed on opposite sides of the multiple fifth pseudofin structures.

7. The semiconductor structure according to claim 5, wherein, Along the direction parallel to the short side of the outer sealing ring, the distance from the plurality of first pseudo-fin structures to the plurality of fifth pseudo-fin structures is less than 1 μm.

8. The semiconductor structure according to claim 6, wherein, Each inner sealing ring includes: Multiple seventh pseudofin structures form the long side of the corresponding inner sealing ring; Multiple eighth pseudofin structures form the short sides of the corresponding inner sealing rings; and Multiple ninth pseudofin structures are diagonally connected to the multiple seventh pseudofin structures and the multiple eighth pseudofin structures.

9. The semiconductor structure according to claim 8, wherein, Each inner sealing ring also includes: Multiple tenth pseudofin structures are parallel to the multiple ninth pseudofin structures, wherein the multiple tenth pseudofin structures are disposed between the multiple ninth pseudofin structures and the outer sealing ring.

10. The semiconductor structure according to claim 9, wherein, One of the plurality of tenth pseudofin structures and the inner angle stress relief structure is disposed on opposite sides of the plurality of ninth pseudofin structures.

11. A semiconductor structure, comprising: Two circuit regions; Two first sealing rings, each of which has a rectangular periphery and surrounds a corresponding one of the two circuit regions; as well as A second sealing ring surrounds the two first sealing rings. The second sealing ring has a rectangular outer perimeter and four right-angled inner angles. The second sealing ring includes a plurality of first pseudo-fin structures located between each of the two first sealing rings and a corresponding short side of the second sealing ring, and a plurality of second pseudo-fin structures located between each of the two first sealing rings and a long side of the second sealing ring. Each of the plurality of first pseudo-fin structures and each of the plurality of second pseudo-fin structures is parallel to the short side of the second sealing ring. Among the plurality of first pseudo-fin structures, the first pseudo-fin structure closest to the corresponding short side of the second sealing ring is the shortest or one of the shortest first pseudo-fin structures, and among the plurality of second pseudo-fin structures, the second pseudo-fin structure closest to the corresponding short side of the second sealing ring is the shortest or one of the shortest second pseudo-fin structures.

12. The semiconductor structure according to claim 11, wherein, The plurality of first pseudofin structures and the plurality of second pseudofin structures are formed by spacer patterns on the sidewalls of the mandrel pattern in a dual patterning process.

13. The semiconductor structure according to claim 11, wherein, The plurality of first pseudofin structures include a plurality of pairs of first pseudofin structures, wherein the first pseudofin structures in each pair of first pseudofin structures have substantially equal lengths, and each pair of first pseudofin structures is shorter in length than the adjacent pair of first pseudofin structures that is farther from the corresponding short side of the second sealing ring.

14. The semiconductor structure according to claim 13, wherein, The plurality of second pseudofin structures include a plurality of pairs of second pseudofin structures, wherein the second pseudofin structures in each pair of second pseudofin structures have substantially equal lengths, and each pair of second pseudofin structures is shorter in length than the adjacent pair of second pseudofin structures that is farther from the corresponding short side of the second sealing ring.

15. The semiconductor structure according to claim 11, wherein, The plurality of first pseudofin structures and the plurality of second pseudofin structures comprise semiconductor materials.

16. The semiconductor structure according to claim 11, wherein, Each of the plurality of first pseudofin structures and the plurality of second pseudofin structures is located at the bottom of a vertical structure extending from the semiconductor substrate to a top metal layer covered by a passivation layer.

17. A semiconductor structure comprising: Two circuit regions; Two first sealing rings, each of the two first sealing rings surrounding a corresponding one of the two circuit regions; as well as A second sealing ring surrounds the two first sealing rings. The second sealing ring has a rectangular periphery with two short sides and two long sides. The second sealing ring includes a plurality of first pseudo-fin structure pairs located between each of the two first sealing rings and a corresponding short side of the second sealing ring, and a plurality of second pseudo-fin structure pairs located between each of the two first sealing rings and a corresponding long side of the second sealing ring. Each of the first pseudo-fin structures and each of the second pseudo-fin structures is parallel to the short side of the second sealing ring. In each pair of first pseudo-fin structures, the first pseudo-fin structures have substantially equal lengths, and each pair of first pseudo-fin structures is shorter in length than its adjacent pair of first pseudo-fin structures that is farther from the corresponding short side of the second sealing ring. In each pair of second pseudofin structures, the second pseudofin structures have substantially equal lengths, and each pair of second pseudofin structures is shorter in length than the adjacent pair of second pseudofin structures that is farther from the corresponding short side of the second sealing ring.

18. The semiconductor structure according to claim 17, wherein, The second sealing ring also includes: A third pseudo-fin structure is located between each of the two first sealing rings and the corresponding long side of the second sealing ring, wherein the third pseudo-fin structure is longitudinally parallel to the second pseudo-fin structure, the third pseudo-fin structures have substantially equal lengths and are evenly distributed along the long side of the second sealing ring.

19. The semiconductor structure according to claim 17, wherein, The first pseudofin structure and the second pseudofin structure are formed by etching a semiconductor substrate using spacer patterns formed on the sidewalls of a mandrel pattern in a dual patterning process.

20. The semiconductor structure according to claim 17, wherein, The plurality of first pseudofin structures are evenly distributed in a space of 5 μm to 8 μm width.

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