Semiconductor device and method of forming the same

Abstract

A semiconductor device includes a first transistor having a first gate stack and first source / drain regions on opposite sides of the first gate stack, a second transistor having a second gate stack and second source / drain regions on opposite sides of the second gate stack, and a gate isolation structure separating the first gate stack from the second gate stack. The gate isolation structure includes a dielectric liner having a varying thickness along sidewalls of the first gate stack and the second gate stack and a dielectric fill material over the dielectric liner, wherein the dielectric fill material includes a seam. Embodiments of the present application also relate to methods of forming a semiconductor device.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer of material on a semiconductor substrate, and using photolithography to pattern the individual material layers to form circuit components and elements thereon.

[0003] The semiconductor industry is constantly increasing the integration density of individual electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the size of the smallest components, which allows more components to be integrated into a given area. Summary of the Invention

[0004] Some embodiments of this application provide a semiconductor device including: a first transistor having a first gate stack and a first source / drain region located on opposite sides of the first gate stack; a second transistor having a second gate stack and a second source / drain region located on opposite sides of the second gate stack; a gate isolation structure separating the first gate stack from the second gate stack, wherein the gate isolation structure includes: a dielectric pad having a varying thickness along the sidewalls of the first gate stack and the second gate stack; and a dielectric filler material located above the dielectric pad, wherein the dielectric filler material includes seams.

[0005] Other embodiments of this application provide a semiconductor device including: a first gate stack located in an interlayer dielectric; a second gate stack located in the interlayer dielectric; and a gate isolation structure located between the first gate stack and the second gate stack, wherein the gate isolation structure contacts the sidewalls of the first gate stack and the sidewalls of the second gate stack, wherein the gate isolation structure includes: a dielectric pad, wherein a first lateral dimension of the dielectric pad is smaller than a second lateral dimension of the dielectric pad, wherein the first lateral dimension of the dielectric pad is measured at a horizontal plane of the top surface of the interlayer dielectric, wherein the second lateral dimension of the dielectric pad is measured at a horizontal plane of the bottom surface of the interlayer dielectric; and a dielectric filler material located above the dielectric pad, wherein the dielectric filler material includes a seam.

[0006] Further embodiments of this application provide a method for forming a semiconductor device, comprising: patterning an extension through an opening of a dummy gate stack; depositing a dielectric pad on the sidewalls and bottom surface of the opening, wherein depositing the dielectric pad includes a non-conformal deposition process; depositing a dielectric filler material in the opening above the dielectric pad, wherein depositing the dielectric filler material includes a deposition process of a different type than depositing the dielectric pad, and wherein depositing the dielectric filler material includes forming a seam in the dielectric filler material; removing the dummy gate stack; and forming a first gate stack and a second gate stack on opposite sides of the dielectric pad. Attached Figure Description

[0007] Aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 An example of a FinFET is shown in a three-dimensional view according to some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 17C , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 19C , Figure 19D , Figure 19E , Figure 19F , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A and Figure 22B This is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments.

[0010] Figure 23A and Figure 23B This is a cross-sectional view of a FinFET according to some embodiments.

[0011] Figure 24A and Figure 24B This is a cross-sectional view of a FinFET according to some embodiments.

[0012] Figure 25A and Figure 25B This is a cross-sectional view of a FinFET according to some embodiments.

[0013] Figure 26 A perspective view of an NSFET according to some embodiments is shown.

[0014] Figure 27A and Figure 27B This is a cross-sectional view of an NSFET according to some embodiments. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0017] In various embodiments, a gate dicing process is performed to separate adjacent dummy gates and define a pattern for the replacement gate stack. As part of the gate dicing process, the dummy gates are etched to define openings, and a gate isolation structure is formed within the openings. The gate isolation structure may include dielectric pads (sometimes called spacers) deposited using a non-conformal deposition process to have a tapered profile, and the gate isolation structure may also include a dielectric filler material deposited over the dielectric pads. By maintaining the tapered profile within the dielectric pads, the width at the top of the opening can be kept relatively large, and the deposition window for the dielectric filler material is improved. Therefore, the dielectric filler material can be formed with fewer manufacturing tolerances, such as reduced seams / voids. The reduction in the size / number of seams / voids can further reduce electrical defects (e.g., short circuits) that may result from conductive material being unintentionally trapped in exposed seams during subsequent processing steps (e.g., during the formation of gate or source / drain contacts).

[0018] Figure 1 An example of a FinFET is shown in a three-dimensional view according to some embodiments. The FinFET includes a fin 52 on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are disposed in the substrate 50, and the fin 52 protrudes over and from adjacent isolation regions 56. Although the isolation regions 56 are described / shown as being separated from the substrate 50, as used herein, the term "substrate" may be used to refer only to a semiconductor substrate or a semiconductor substrate including the isolation regions. Furthermore, although the fin 52 is shown as a single, continuous material like the substrate 50, the fin 52 and / or the substrate 50 may comprise a single material or multiple materials. In this context, fin 52 refers to the portion extending between adjacent isolation regions 56.

[0019] The gate dielectric layer 92 is located along the sidewall of the fin 52 and above the top surface of the fin 52, and the gate electrode 94 is located above the gate dielectric layer 92. Source / drain regions 82 are disposed on the opposite sides of the fin 52 relative to the gate dielectric layer 92 and the gate electrode 94. Figure 1 Reference cross sections used in later figures are also shown. Cross section AA is along the longitudinal axis of the gate electrode 94 and in a direction, for example, perpendicular to the current flow direction between the source / drain regions 82 of the FinFET. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of fin 52, and in a direction, for example, the current flow direction between the source / drain regions 82 of the FinFET. Cross section CC is parallel to cross section AA and extends through the source / drain regions of the FinFET. For clarity, subsequent figures refer to these reference cross sections.

[0020] Some embodiments discussed herein are presented in the context of FinFETs formed using a post-gate process. In other embodiments, a pre-gate process may be used. Furthermore, some embodiments consider aspects for use in planar devices, such as planar FETs, nanostructured (e.g., nanosheets, nanowires, all-around gate, etc.) field-effect transistors (NSFETs), etc.

[0021] Figures 2 to 22B This is a cross-sectional view of an intermediate stage in the fabrication of a FinFET in device 100 according to some embodiments. Figures 2 to 7 It shows Figure 1 The reference cross section AA shown here, in addition to having multiple fin / FinFETs and / or having a gate isolation structure. Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 19C , Figure 20A , Figure 21A and Figure 22A along Figure 1 The reference section AA shown is illustrated, and Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 17C , Figure 18B , Figure 19B , Figure 19D , Figure 19E , Figure 20B , Figure 21B and Figure 22B along Figure 1 The BB shown in the diagram has a similar cross-section, in addition to multiple fins / FinFETs and / or has a gate isolation structure. Figure 10C and Figure 10D along Figure 1 The reference cross section CC shown in the figure illustrates the presence of multiple fins / FinFETs. Figure 13C and Figure 19F A top view of a gate structure according to some embodiments is shown.

[0022] exist Figure 2A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., having p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate that is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 50 can include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0023] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type FinFET. The p-type region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type FinFET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by separator 51), and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P.

[0024] exist Figure 3 In this embodiment, fins 52 are formed in substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 can be formed in substrate 50 by etching trenches in substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic.

[0025] The fin can be patterned using any suitable method. For example, the fin 52 can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a smaller spacing than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin. In some embodiments, a mask (or other layer) may be retained on the fin 52.

[0026] exist Figure 4An insulating material 54 is formed over the substrate 50 and between adjacent fins 52. The insulating material 54 can be an oxide, such as silicon oxide, nitrides, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to transform it into another material, such as an oxide), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In the embodiment, the insulating material 54 is formed such that excess insulating material 54 covers the fins 52. Although the insulating material 54 is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a pad (not shown) may first be formed along the surfaces of the substrate 50 and the fins 52. Subsequently, a filler material, such as those discussed above, may be formed over the pad.

[0027] exist Figure 5 In this process, a removal process is applied to the insulating material 54 to remove excess insulating material 54 above the fin 52. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etching back processes, or combinations thereof may be used. The planarization process exposes the fin 52 so that, after the planarization process is completed, the top surface of the fin 52 is flush with the insulating material 54. In embodiments where the mask remains on the fin 52, the planarization process may expose or remove the mask so that, after the planarization process is completed, the top surface of the mask or the fin 52 is flush with the insulating material 54, respectively.

[0028] exist Figure 6 In this process, the insulating material 54 is recessed to form shallow trench isolation (STI) regions 56. The insulating material 54 is recessed such that the upper portions of the fins 52 in the n-type region 50N and p-type region 50P protrude from between adjacent STI regions 56. Furthermore, the top surface of the STI region 56 can have a flat surface, a convex surface, a concave surface (such as a recess), or a combination thereof, as shown. The top surface of the STI region 56 can be formed as flat, convex, and / or concave by appropriate etching. The STI region 56 can be recessed using acceptable etching processes, such as etching processes that are selective to the material of the insulating material 54 (e.g., etching the material of the insulating material 54 at a faster rate than the material of the fins 52). For example, oxide removal can be used (using, for example, dilute hydrofluoric acid (dHF)).

[0029] about Figures 2 to 6The described process is merely one example of how fin 52 can be formed. In some embodiments, the fin can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over the top surface of substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoethelic structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed, allowing the homoethelic structure to protrude from the dielectric layer to form the fin. Furthermore, in some embodiments, heteroethelic structures can be used for fin 52. For example, a heteroethelic structure can be... Figure 5 The fin 52 is recessed, and a different material can be epitaxially grown over the recessed fin 52. In such an embodiment, the fin 52 comprises a recessed material and an epitaxially grown material disposed over the recessed material. In a further embodiment, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer. A heteroepitaxial structure can then be epitaxially grown in the trenches using a material different from that of the substrate 50, and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments of epitaxially growing homoepitaxial or heteroepitaxial structures, the epitaxially grown material can be in-situ doped during growth, which avoids prior and subsequent implantation, but in-situ and implantation doping can be used together.

[0030] Furthermore, it may be advantageous to epitaxially grow a material different from that in the p-type region 50P (e.g., the PMOS region) in the n-type region 50N (e.g., the NMOS region). In various embodiments, the upper portion of the fin 52 may be made of silicon-germanium (Si). x Ge 1-x The semiconductor can be formed from materials such as silicon carbide, pure or nearly pure germanium, III-V compound semiconductors, and II-VI compound semiconductors, where x can be in the range of 0 to 1. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, and gallium phosphide.

[0031] Further in Figure 6 In this process, suitable wells (not shown) may be formed in the fin 52 and / or the substrate 50. In some embodiments, a P-well may be formed in the n-type region 50N and an N-well may be formed in the p-type region 50P. In some embodiments, a P-well or an N-well may be formed in the n-type region 50N and the p-type region 50P.

[0032] In embodiments with different well types, different implantation steps for the n-type region 50N and the p-type region 50P can be implemented using photoresist and / or other masks (not shown). For example, photoresist can be formed over the fin 52 and STI region 56 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P of the substrate 50. The photoresist can be formed using a spin-coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurity implantation into the n-type region 50N. The n-type impurity can be of a concentration equal to or less than 10 in the implantation region. 18 cm -3 Phosphorus, arsenic, antimony, etc., such as in about 10 16 cm -3 Peace Treaty 10 18 cm -3 Between. After implantation, the photoresist is removed, such as through an acceptable ashing process.

[0033] After implanting the p-type region 50P, photoresist is formed over the fins 52 and STI regions 56 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N of the substrate 50. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurity implantation into the p-type region 50P. The p-type impurity can be of a concentration equal to or less than 10 in the implanted region. 18 cm -3 Boron, boron fluoride, indium, etc., such as in about 10 16 cm -3 Peace Treaty 10 18 cm -3 Between. After implantation, the photoresist can be removed, such as through an acceptable ashing process.

[0034] After implantation of the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and to activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be doped in situ during growth, which can avoid implantation, but in-situ and implantation doping can be used together.

[0035] exist Figure 7In this process, a dummy dielectric layer 60 is formed on fin 52. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, combinations thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed above the dummy dielectric layer 60, and a mask layer 64 is formed above the dummy gate layer 62. The dummy gate layer 62 can be deposited and then planarized (e.g., by CMP) above the dummy dielectric layer 60. The mask layer 64 can be deposited above the dummy gate layer 62. The dummy gate layer 62 can be a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 62 can be made of other materials with high etch selectivity relative to the etching of the isolation region (e.g., STI region 56 and / or dummy dielectric layer 60). Mask layer 64 may include one or more layers such as silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across the n-type region 50N and the p-type region 50P. It should be noted that, for illustrative purposes only, dummy dielectric layer 60 is shown as covering only fin 52. In some embodiments, dummy dielectric layer 60 may be deposited such that dummy dielectric layer 60 covers STI region 56, extends over STI region, and extends between dummy gate layer 62 and STI region 56.

[0036] Figures 8A to 22B The various additional steps in the fabrication of the embodiment device are shown. Figures 8A to 22B Components in either the n-type region 50N or the p-type region 50P are shown. For example, Figures 8A to 22B The structure shown can be applied to both n-type region 50N and p-type region 50P. Differences (if any) between the structures of n-type region 50N and p-type region 50P are described in the accompanying text for each figure.

[0037] exist Figure 8A and Figure 8B In the middle, mask layer 64 (see Figure 7 The mask 74 can be patterned using acceptable photolithography and etching techniques. The pattern of the mask 74 can then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 using acceptable etching techniques to form the dummy gate 72. The dummy gate 72 covers the corresponding channel region 58 of the fin 52. The pattern of the mask 74 can be used to physically separate each of the dummy gates 72 from its adjacent dummy gate. The dummy gate 72 can also have a longitudinal orientation substantially perpendicular to the longitudinal direction of the corresponding epitaxial fin 52.

[0038] Further in Figure 8A and Figure 8B In this process, a gate sealing spacer 80 may be formed on the exposed surfaces of the dummy gate 72, mask 74, and / or fin 52. Thermal oxidation or deposition, followed by anisotropic etching, can form the gate sealing spacer 80. The gate sealing spacer 80 may be formed from silicon oxide, silicon nitride, silicon oxynitride, etc.

[0039] After forming the gate sealing spacer 80, implantation for the lightly doped source / drain (LDD) region (not explicitly shown) can be performed. In embodiments with different device types, similar to the above... Figure 6 The implantation discussed earlier can involve forming a mask, such as photoresist, over the n-type region 50N while exposing the p-type region 50P, and implanting an impurity of an appropriate type (e.g., p-type) into the exposed fins 52 in the p-type region 50P. The mask can then be removed. The n-type impurity can be any n-type impurity discussed earlier, and the p-type impurity can be any p-type impurity discussed earlier. The lightly doped source / drain regions can have approximately 10... 15 cm -3 To about 10 19 cm -3 The concentration of impurities. Annealing can be used to repair implantation damage and to reactivate the implanted impurities.

[0040] exist Figure 9A and Figure 9B In this process, a gate spacer 86 is formed on the gate sealing spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacer 86 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof.

[0041] It should be noted that the above disclosure provides a general description of the process for forming the spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, and different step sequences can be employed (e.g., the gate sealing spacer 80 can be left unetched before forming the gate spacer 86, creating an "L-shaped" gate sealing spacer; spacers can be formed and removed, etc.). Furthermore, n-type and p-type devices can be formed using different structures and steps. For example, the LDD region for an n-type device can be formed before forming the gate sealing spacer 80, while the LDD region for a p-type device can be formed after forming the gate sealing spacer 80.

[0042] exist Figure 10A and Figure 10B In the fin 52, epitaxial source / drain regions 82 are formed. The epitaxial source / drain regions 82 are formed in the fin 52 such that each dummy gate 72 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend into and may penetrate the fin 52. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance such that the epitaxial source / drain regions 82 do not short-circuit the subsequently formed gate of the resulting FinFET. The material of the epitaxial source / drain regions 82 can be selected to apply stress in the corresponding channel regions 58, thereby improving performance.

[0043] The epitaxial source / drain region 82 in the n-type region 50N can be formed by masking the p-type region 50P and etching the source / drain region of the fin 52 in the n-type region 50N to form a groove in the fin 52. The epitaxial source / drain region 82 in the n-type region 50N is then epitaxially grown in the groove. The epitaxial source / drain region 82 can include any acceptable material, such as that suitable for an n-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in the n-type region 50N can include a material for applying tensile strain in the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 82 in the n-type region 50N can have a surface protruding from the corresponding surface of the fin 52 and can have a small facet.

[0044] The epitaxial source / drain region 82 in the p-type region 50P can be formed by masking the n-type region 50N and etching the source / drain region of the fin 52 in the p-type region 50P to form a groove in the fin 52. The epitaxial source / drain region 82 in the p-type region 50P is then epitaxially grown in the groove. The epitaxial source / drain region 82 can include any acceptable material, such as that suitable for a p-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in the p-type region 50P can include a material for applying compressive strain in the channel region 58, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 82 in the p-type region 50P can have a surface protruding from the corresponding surface of the fin 52 and can have a small facet.

[0045] The epitaxial source / drain regions 82 and / or fins 52 can be implanted with dopants to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions and subsequent annealing. The source / drain regions can have a dopant content of approximately 10. 19 cm -3 Peace Treaty 10 21 cm -3The impurity concentrations between these values. The n-type and / or p-type impurities used for the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 82 can be doped in situ during growth.

[0046] Due to the epitaxial process used to form the epitaxial source / drain regions 82 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions has small planes that extend laterally outward beyond the sidewalls of the fin 52. In some embodiments, these small planes cause adjacent source / drain regions 82 of the same FinFET to merge, such as... Figure 10C As shown. In other embodiments, after the epitaxial process is completed, adjacent source / drain regions 82 remain separated, as shown. Figure 10D As shown. In Figure 10C and Figure 10D In the illustrated embodiment, the gate spacer 86 is formed as a portion of the sidewall of the fin 52 extending over the STI region 56, thereby blocking epitaxial growth. In some other embodiments, the spacer etching used to form the gate spacer 86 may be adjusted to remove spacer material to allow the epitaxial growth region to extend to the surface of the STI region 56.

[0047] exist Figure 11A and Figure 11B In Figure 10A and Figure 10B A first interlayer dielectric (ILD) 88 is deposited over the structure shown. The first ILD 88 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first ILD 88 and the epitaxial source / drain region 82, mask 74, and gate spacer 86. CESL 87 may include a dielectric material having a lower etch rate than the material of the first ILD 88 above, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0048] exist Figure 12A and Figure 12BIn this process, a planarization process such as CMP can be performed to make the top surface of the first ILD 88 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process may also remove the mask 74 on the dummy gate 72, as well as portions of the gate sealing spacers 80 and 86 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, gate sealing spacers 80, gate spacers 86, CESL 87, and the first ILD 88 are flush. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD 88. In some embodiments, the mask 74 may be retained, in which case the planarization process makes the top surface of the first ILD 88 flush with the top surface of the mask 74.

[0049] exist Figures 13A to 17C In the process, a gate dicing process is performed to form a gate isolation structure 130 extending through certain dummy gates 72 (see...). Figures 17A to 17C This process separates and patterns the dummy gates 72. In various embodiments, the gate dicing process can be used to define the pattern of the subsequently formed replacement gate structure.

[0050] First refer to Figures 13A to 13C A hard mask 120 can be deposited and patterned over the first ILD 88, dummy gate 72, gate sealing spacer 80, CESL 87, and gate spacer 86. The hard mask 120 can be patterned to provide an opening 122 that exposes a portion of the dummy gate 72. Figure 13C A top view of the hard mask 120 and opening 122 is shown. The positions of the dummy gate 72 and fin 52 are shown in dashed lines for reference. Figure 13C The locations of sections AA and BB are further shown below. For clarity, subsequent figures refer to these sections. Specifically, Figure 13A , Figure 14A , Figure 15A , Figure 16A and Figure 17A A view is shown along section AA (e.g., in a direction parallel to the longitudinal direction of fin 52) and through one of the openings 122, and Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B and Figure 17C A view is shown along section BB (e.g., in a direction perpendicular to the longitudinal direction of fin 52) and through one of the openings 122.

[0051] The material of the hard mask 120 can be selected such that it can be selectively patterned relative to the material of the underlying layers (such as the dummy gate 72 and / or the first ILD 88). For example, the hard mask 120 may include any suitable material, such as silicon nitride, silicon oxynitride, silicon carbonitride, amorphous silicon, Al2O3, etc., which is deposited using suitable processes such as PVD, CVD, ALD, combinations thereof, etc.

[0052] For example, the hard mask 120 can be patterned using a combination of photolithography and etching to include an opening 122 that exposes a portion of the dummy gate 72. The pattern of the opening 122 can correspond to the gate cut-off locations of the dummy gate 72 (e.g., regions where adjacent portions of the dummy gate 72 will be physically separated). Due to the etching process used to pattern the hard mask 120, the width of the opening 122 at the top surface of the hard mask 120 can be smaller than the width of the opening 122 at the bottom surface of the hard mask 120. For example, the etching process may leave a slight overhang at the top surface of the hard mask 120, which creates a critical dimension (e.g., width) at the top of the opening 122 that is slightly narrower than at the bottom of the opening 122.

[0053] exist Figure 14A and Figure 14B In this process, opening 122 extends through the dummy gate 72 and fin 52 into the substrate 50. Extending opening 122 may include one or more etching processes, such as dry etching, wet etching, or any combination thereof. For example, extending opening 122 may include a first etching process that removes portions of the dummy gate 72 exposed by the hard mask 120 and portions of the dummy dielectric layer 60 exposed by the hard mask 120. Subsequently, a second etching process may be applied to remove portions of the fin 52 exposed by the mask 120, thereby extending opening 122 through the fin 52 and into the substrate 50. The second etching process may be the same as or different from the first etching process used to remove portions of the dummy gate 72 and dummy dielectric layer 60. The second etching process may be a selective etching process that can selectively etch the fin 52 and substrate 50 at a higher rate than the STI region 56. Therefore, opening 122 may extend in the STI region 56 to a depth different from the substrate 50 (e.g., smaller). Furthermore, the second etching process may laterally etch different amounts of the fin 52 at different depths. For example, the width W2 of the opening 122 at the top surface of fin 52 can be less than Figure 14B The maximum width W1 of the opening 122 in the cross-section shown. In some embodiments, the maximum width W1 can be in the range of 28 nm to 38 nm, and the width W2 can be in the range of 13 nm to 30 nm. Other dimensions are also possible in other embodiments.

[0054] exist Figure 15A and Figure 15BIn this process, a dielectric pad 124 is deposited above the mask 120, on the sidewall of the opening 122, and along the bottom surface of the opening 122. The dielectric pad 124 may subsequently be referred to as spacer 124 or spacer layer 124. The dielectric pad 124 may comprise silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, etc., which are deposited using a non-conformal deposition process. Due to the non-conformal deposition process, the dielectric pad 124 can have a varying thickness as it extends along the sidewall of the dummy gate 72. In some embodiments, the thickness T1 of the dielectric pad 124 at the top surface of the first ILD 88 may differ from the thickness T2 of the dielectric pad 124 at the bottom surface of the first ILD 88 / fin 52. Specifically, the thickness T1 may be less than the thickness T2, and the width W2 at the top of the opening 122 may be greater than the width W3 at the bottom surface of the first ILD 88 / fin 52. Therefore, after the dielectric liner 124 is deposited, the deposition window for the dielectric filler material subsequently deposited into the opening 122 is advantageously widened to an increased width at the top of the opening 122.

[0055] In some embodiments, the non-conformal deposition process is a plasma-enhanced atomic layer deposition (PEALD) process, which applies plasma treatment to achieve the varying width of the dielectric pad 124 described above. The PEALD process may include flowing a precursor process gas comprising nitrogen (N2) plasma into the deposition chamber. When the dielectric pad 124 comprises silicon nitride, the precursor process gas may also comprise thermal SiH2I2 (e.g., heated to a gaseous state), hydrogen (H2) plasma, and / or combinations thereof. A nitrogen plasma process is applied to the surface exposed by the opening 122 by flowing the nitrogen plasma precursor as part of the PEALD process. Due to the nitrogen plasma treatment, the incubation time for depositing the dielectric pad 124 may be worse at the top of the opening 122 compared to the bottom of the opening 122, and the dielectric pad 124 may be deposited thinner at the top of the opening 122 compared to the bottom of the opening 122. In some embodiments, for example, PEALD plasma can be implemented at a temperature ranging from 300°C to 600°C and a pressure ranging from 7.5 Torr to 90 Torr, for a duration ranging from 10 minutes to 60 minutes. Other embodiments may implement the PEALD process using different processing parameters.

[0056] exist Figure 16A and Figure 16BIn this process, a dielectric filler 126 is deposited in an opening 122 above a dielectric pad 124. In some embodiments, the dielectric filler 126 may comprise a material similar to the dielectric pad 124 (e.g., silicon nitride). However, the dielectric filler 126 may be deposited using a different type of process than the dielectric pad 124. For example, the dielectric filler 126 may be deposited using a conformal process, such as an ALD process, instead of the non-conformal, PEALD process used for depositing the dielectric pad 124. In some embodiments, the ALD process for depositing the dielectric filler 126 may be a thermal process that does not use plasma. As part of the ALD process, the dielectric filler 126 may be deposited on the surface of the opening 122 until portions of the dielectric filler 126 merge together, defining a seam 128 and filling the opening 122. Due to the profile of the dielectric pad 124 (e.g., thinner at the top of the opening 122), the deposition window of the dielectric filler 126 may be widened and a relatively small seam 128 may be formed within the dielectric filler. Furthermore, the seam 128 may include a gap 128' in the lower portion of the dielectric filling material 126, and the gap 128' may advantageously reduce the dielectric constant of the resulting gate isolation structure, thereby reducing parasitic capacitance.

[0057] exist Figures 17A to 17C In this process, a planarization process is applied to remove excess portions of the dielectric pad 124 and dielectric fill material 126 (e.g., portions outside the opening 122). The planarization process may further remove the hard mask 120. The planarization process may be a CMP process, an etch-back process, or a combination thereof. Thus, a gate isolation structure 130 is formed, comprising the remaining portions of the dielectric pad 124 and dielectric fill material 126. The gate isolation structure 130 can be used to physically separate portions of the dummy gate 72 and help define the pattern of the subsequently formed replacement gate structure.

[0058] Due to the exemplary deposition process described above, the gate isolation structure 130 can have certain advantageous dimensions. Figure 17C With Figure 17BA similar cross-section (e.g., along the aforementioned cross-section BB) shows a detailed view of the gate isolation structure 130. The dielectric pad 124 may have a lateral dimension D1 at the top surface of the fin 52 (e.g., at the level of the bottom surface of the first ILD 88) and a lateral dimension D2 at the level of the top surface of the first ILD 88. Due to the deposition process used to form the dielectric pad 124 (e.g., PEALD with nitrogen plasma), the lateral dimension D2 may be smaller than the lateral dimension D1. In some embodiments, the lateral dimension D1 may be in the range of 3.8 nm to 22.5 nm, while the lateral dimension D2 may be in the range of 3 nm to 18 nm. For example, the ratio of lateral dimension D1 to lateral dimension D2 may be in the range of 1.1 to 1.5. It has been observed that by forming the dielectric pad 124 with the aforementioned dimensions / profile, advantages such as widening the deposition window for the dielectric filler material 126 can be achieved, thereby reducing the size of the seam 128 and reducing manufacturing defects. For example, the seam 128 in the upper portion of the gate isolation structure 130 may have a lateral dimension D4 in the range of 1.5 nm to 9 nm. It has been observed that manufacturing defects can be advantageously reduced by having a seam with the aforementioned dimensions. Specifically, the seam of the aforementioned dimensions can be small enough to avoid the risk of over-etching the gate isolation structure 130 or metal particles being trapped within the seam during subsequent contact formation processes, leading to electrical short circuits. Furthermore, the seam 128 may include a void 128' in the lower portion of the gate isolation structure 130, and the void 128' may have a lateral dimension D3 in the range of 0.5 nm to 3 nm at its widest point in its cross-section. The lateral dimension D3 of the void 128' may be wider than the lateral dimension D4 of the upper portion of the seam 128. It has been observed that by including a void of the aforementioned dimensions, the dielectric constant of the gate isolation structure 130 can be reduced, thereby reducing parasitic capacitance. Furthermore, the dielectric filler material 126 has a lateral dimension D5 at the same horizontal plane as the top surface of the first ILD 88, a lateral dimension D6 at the top surface of the fin 52 (e.g., at the same horizontal plane as the bottom surface of the first ILD 88), and a lateral dimension D7 at the widest point of the dielectric filler material 126 in a cross-sectional view (e.g., in the fin 52). The lateral dimension D5 may be larger than the lateral dimension D6, and the lateral dimension D7 may be larger than each of the lateral dimensions D5 and D6. In some embodiments, the lateral dimension D5 may be in the range of 3.3 nm to 19.5 nm; the lateral dimension D6 may be in the range of 2.5 nm to 15 nm; and the lateral dimension D7 may be in the range of 5 nm to 15 nm. For example, the ratio of the lateral dimension D6 to the lateral dimension D5 may be in the range of 0.7 to 0.9, and the ratio of the lateral dimension D6 to the lateral dimension D7 may be in the range of 0.4 to 0.6.

[0059] Figures 18A to 22BThe following steps are shown: replacing the dummy gate 72 with a functional gate stack and forming the individual contacts. Figure 18A , Figure 19A , Figure 20A , Figure 21A and Figure 22A A view is shown along section AA (e.g., in a direction parallel to the longitudinal direction of fin 52) and through one of the gate isolation structures 130, and Figure 18B , Figure 19B , Figure 20B , Figure 21B and Figure 22B A view is shown along section BB (e.g., in a direction perpendicular to the longitudinal direction of fin 52) and through one of the gate isolation structures 130. Figures 19C to 19F This shows a change view of the device after the functional gate stack is formed.

[0060] exist Figure 18A and Figure 18B In the etching step, the dummy gate 72 is removed, thereby forming a recess 90. A portion of the dummy dielectric layer 60 located in the recess 90 may also be removed. In some embodiments, only the dummy gate 72 is removed, and the dummy dielectric layer 60 remains and is exposed through the recess 90. In some embodiments, the dummy dielectric layer 60 is removed from the recess 90 in a first region of the die (e.g., a core logic region) and remains in the recess 90 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using reactive gases that selectively etches the dummy gate 72 while etching little or no first ILD 88, gate isolation structure 130, or gate spacer 86. Each recess 90 is exposed and / or located over the channel region 58 of the corresponding fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 82. During removal, the dummy dielectric layer 60 may be used as an etch stop layer while etching the dummy gate 72. The dummy dielectric layer 60 can then be optionally removed after the dummy gate 72 is removed.

[0061] exist Figures 19A to 19F In this process, a gate dielectric layer 92 and a gate electrode 94 are formed to replace the gate. Figure 19F The top view and location of each section are shown. Figure 19A It shows along Figure 19F A cross-sectional view of line AA (e.g., through gate isolation structure 130); Figure 19B It shows along Figure 19F A cross-sectional view of the line BB (e.g., through the gate isolation structure 130); Figure 19C It shows along Figure 19FA cross-sectional view of the line CC (e.g., not extending through the gate isolation structure 130 and parallel to section AA); and Figure 19D It shows along Figure 19F A cross-sectional view of the line DD (e.g., not extending through the gate isolation structure 130 and parallel to the section BB). Figure 19E It shows Figure 19B and Figure 19D Detailed view of area 89.

[0062] The gate dielectric layer 92 includes one or more layers deposited in the recess 90, such as on the top surface and sidewalls of the fin 52 and on the sidewalls of the gate sealing spacer 80 / gate spacer 86. The gate dielectric layer 92 may also be formed on the top surface of the first ILD 88. In some embodiments, the gate dielectric layer 92 includes one or more dielectric layers, such as silicon oxide, silicon nitride, metal oxides, metal silicates, etc. For example, in some embodiments, the gate dielectric layer 92 includes an interface layer of silicon oxide formed by thermal oxidation or chemical oxidation, and a high-k dielectric material thereon, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric layer 92 may include a dielectric layer having a k value greater than about 7.0. Methods for forming the gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments where a portion of the dummy gate dielectric 60 remains in the recess 90, the gate dielectric layer 92 includes the material of the dummy gate dielectric 60 (e.g., SiO2).

[0063] Gate electrodes 94 are deposited over gate dielectric layer 92 and fill the remainder of trench 90. Gate electrodes 94 may comprise metallic materials such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. For example, although... Figure 19B and Figure 19D The diagram shows a single-layer gate electrode 94, but the gate electrode 94 may include any number of pad layers 94A, any number of work function adjustment layers 94B, and filler material 94C, such as... Figure 19EAs shown. In some embodiments, the order of the pad layer 94A and the power function adjustment layer 94B can be reversed. After filling the recess 90, a planarization process such as CMP can be performed to remove excess portions of the material of the gate dielectric layer 92 and the gate electrode 94 located above the top surface of the ILD 88. The remaining material of the gate electrode 94 and the gate dielectric layer 92 thus form the replacement gate of the resulting FinFET. The gate electrode 94 and the gate dielectric layer 92 can be collectively referred to as "gate stacks". The gate and gate stacks can extend along the sidewalls of the channel region 58 of the fin 52. Furthermore, each of the gate isolation structures 130 separates adjacent first gate stacks and second gate stacks (each including a gate dielectric layer 92 and a corresponding gate electrode 94), as shown. Figure 19A and Figure 19F As shown.

[0064] The formation of the gate dielectric layer 92 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 92 in each region is formed of the same material, and the formation of the gate electrode 94 can occur simultaneously, such that the gate electrode 94 in each region is formed of the same material. In some embodiments, the gate dielectric layer 92 in each region can be formed by different processes, such that the gate dielectric layer 92 can be made of different materials, and / or the gate electrode 94 in each region can be formed by different processes, such that the gate electrode 94 can be made of different materials. When using different processes, individual masking steps can be used to mask and expose appropriate regions.

[0065] exist Figure 20A and Figure 20B In this process, a gate mask 96 is formed over a gate stack (including a gate dielectric layer 92 and a corresponding gate electrode 94), and the gate mask may be disposed between opposing portions of the gate spacers 86. In some embodiments, forming the gate mask 96 includes recessing the gate stack to form a recess directly over the gate stack and between opposing portions of the gate spacers 86. The recess may further expose the sidewalls of the gate isolation structure 130. The gate mask 96 may further extend along the sidewalls of the gate isolation structure 130. The gate mask 96, comprising one or more layers of dielectric material (such as silicon nitride, silicon oxynitride, etc.), is filled in the recess, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD 88. The gate mask 96 is optional and may be omitted in some embodiments. In such embodiments, the gate stack may remain flush with the top surface of the first ILD 88.

[0066] Also Figure 20A and Figure 20BAs shown, according to some embodiments, a first-level source / drain contact 112 is formed through a first ILD 88. An opening for the source / drain contact 112 is formed through the first ILD 88. The opening can be formed using acceptable photolithography and etching techniques. A pad (not shown), such as a diffusion barrier layer, an adhesive layer, etc., and a conductive material are formed in the opening. The pad may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the surface of the first ILD 88. The remaining pad and conductive material form the source / drain contact 112 in the opening. An annealing process can be performed to form silicide at the interface between the epitaxial source / drain region 82 and the source / drain contact 112. The source / drain contact 112 is physically and electrically coupled to the epitaxial source / drain region 82. Due to the relatively small size of the seam 128, the source / drain contact 112 can be formed without damaging the gate isolation structure 130 (e.g., over-etching or undesirable trapping of metal particles).

[0067] exist Figure 21A and Figure 21B In this process, a second ILD 108 is deposited over the first ILD 88. In some embodiments, the second ILD 108 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 108 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD and PECVD. The gate contact 110 is subsequently formed. Figure 16A and Figure 16B It penetrates the second ILD 108 and the gate mask 96 (if present) to contact the top surface of the recessed gate electrode 94.

[0068] exist Figure 22A and Figure 22BIn some embodiments, a gate contact 110 and a second-level source / drain contact 114 are formed through the second ILD 108. An opening for the source / drain contact 114 is formed through the second ILD 108 to the first-level source / drain contact 112, and an opening for the gate contact 110 is formed through the second ILD 108 and the gate mask 96 (if present). The openings can be formed using acceptable photolithography and etching techniques. Pads (not shown), such as diffusion barrier layers and adhesive layers, as well as conductive material, are formed in the openings. The pads may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be implemented to remove excess material from the surface of the ILD 108. The remaining pads and conductive material form the source / drain contact 114 and the gate contact 110 in the openings. Source / drain contact 114 is physically and electrically coupled to source / drain contact 112, and gate contact 110 is physically and electrically coupled to gate electrode 106. Source / drain contact 112 and gate contact 110 can be formed in different processes or in the same process. Although shown as formed in the same cross-section, it should be understood that each of source / drain contact 112 and gate contact 110 can be formed in different cross-sections, which avoids short circuits in the contacts. Furthermore, the material selected for source / drain contact 114 can be the same as or different from the material of source / drain contact 112 and / or gate contact 110. Thus, a finFET device is formed in a semiconductor device 100 having a gate isolation structure 130 separating adjacent gate stacks 92 / 94.

[0069] Figures 1 to 22B A specific configuration of the gate isolation structure 130 is shown. Other embodiments may include other configurations of the gate isolation structure 130. For example, Figure 23A and Figure 23B Device 150 according to some embodiments is shown. Figure 23A It shows along Figure 1 The view of the cross section AA and through the gate isolation structure 130, and Figure 23B It shows along Figure 1 The view is a cross-section BB and extends through the gate isolation structure 130. Device 150 may be similar to device 100, wherein the same reference numerals denote the same elements formed by the same process. However, unlike device 100, which includes a gap 128' in the lower portion of seam 128, the gate isolation structure 130 in device 150 does not have a gap 128'. For example, the gap 128' can be omitted by controlling the deposition process for forming the dielectric filler 126 and / or controlling the aspect ratio of the openings of the deposited dielectric filler 126. Seam 128 may have a relatively small lateral dimension to achieve the aforementioned benefits.

[0070] As another example, Figure 24A and Figure 24B Device 200 according to some embodiments is shown. Figure 24A It shows along Figure 1 The view of the cross section AA and through the gate isolation structure 130, and Figure 24B It shows along Figure 1 The view is a cross-section BB and extends through the gate isolation structure 130. Device 200 may be similar to device 100, wherein the same reference numerals denote the same elements formed by the same process. However, unlike device 100 where the dielectric pad 124 remains unmerged, the gate isolation structure 130 in device 200 may include a merged dielectric pad 124 extending continuously from the sidewall of the first gate stack to the sidewall of the second gate stack. Specifically, the lower portion of the dielectric pad 124 (e.g., a portion disposed in the fin 52, substrate 50, and STI region 56) may be merged together at the top surface of the fin 52 / STI region 56. The lower portion of the dielectric pad 124 may also include a void 132 formed due to the merging. A filler material 126 may be disposed above the merged lower portion of the dielectric pad 124, and the filler material 126 may include a seam 128 having a relatively small lateral dimension to achieve the aforementioned benefits.

[0071] As another example, Figure 25A and Figure 25B Device 250 according to some embodiments is shown. Figure 25A It shows along Figure 1 The view of the cross section AA and through the gate isolation structure 130, and Figure 25B It shows along Figure 1The cross-section BB and view through the gate isolation structure 130 are shown. Device 250 may be similar to device 100, wherein the same reference numerals denote the same elements formed by the same process. However, unlike device 100, where the dielectric pad 124 directly contacts the dielectric fill material 126, the gate isolation structure 130 in device 250 may also include an additional dielectric pad 134 between the dielectric pad 124 and the dielectric fill material 126. In some embodiments, the dielectric pad 134 may include an oxide material, such as an oxide of the material of the dielectric pad 124. For example, when the dielectric pad 124 comprises silicon nitride, the dielectric pad 134 may comprise silicon oxynitride. The dielectric pad 134 may be a native oxide formed due to the oxidation of the dielectric pad 124 by exposing the dielectric pad 124 to the atmospheric environment. In some embodiments, the dielectric pad 124 may be exposed to the atmosphere when transferring the device 250 between deposition tools (e.g., a PEALD tool for depositing the dielectric pad 124 and an ALD tool for depositing the dielectric filler material 126). Other pad materials may also be used for the dielectric pad 124.

[0072] The disclosed FinFET embodiments can also be applied to nanostructure devices, such as nanostructured (e.g., nanosheets, nanowires, all-around gates, etc.) field-effect transistors (NSFETs). In NSFET embodiments, the fins are replaced by nanostructures formed by a stack of alternating layers of patterned channel layers and sacrificial layers. The dummy gate stack and source / drain regions are formed in a manner similar to the embodiments described above. A gate isolation structure is also formed to extend through the dummy gate stack, as described above. After removing the dummy gate stack, the sacrificial layer in the channel region can be partially or completely removed. The replacement gate structure is formed in a manner similar to the embodiments described above, and the replacement gate structure can partially or completely fill the opening left by removing the sacrificial layer, and the replacement gate structure can partially or completely surround the channel layer in the channel region of the NSFET device. The ILD and the contacts to the replacement gate structure and source / drain regions can be formed in a manner similar to the embodiments described above.

[0073] Figure 26 A perspective view of an NSFET according to some embodiments is shown. Figure 27A and Figure 27B A cross-sectional view of the gate isolation structure 130 in various embodiments within the context of NSFET is shown. (Reference) Figure 26The NSFET device includes a nanostructure 55 (e.g., nanosheet, nanowire, etc.) above fins 52 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 serves as a channel region for the NSFET device. The nanostructure 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. STI regions 56 are disposed between adjacent fins 52, and the fins 52 may protrude over and from between adjacent STI regions 56. A gate dielectric material 92 is located above the top surface of the fins 52 and along the top, sidewalls, and bottom surface of the nanostructure 55. A gate electrode 94 is located above the gate dielectric material 92. Epitaxial source / drain regions 82 are disposed on the fins 52 on opposite sides of the gate stack 92 / 94.

[0074] Figure 26 Reference cross sections used in the following figures are also shown. Cross section XX is along the longitudinal axis of the gate electrode 94 and in a direction, for example, perpendicular to the current flow direction between the epitaxial source / drain regions 82 of the NSFET device. Cross section YY is perpendicular to cross section XX and parallel to the longitudinal axis of the fin 52 of the NSFET device and in a direction, for example, between the epitaxial source / drain regions 82 of the NSFET device. Figure 27A It shows along Figure 26 The cross-section XX merged gate isolation structure 130 (e.g., as above in Figures 1 to 22B The NSFET device described in the embodiments, and Figure 27B It shows along Figure 26 The YY cross-section of the combined gate isolation structure of the NSFET device is 130. Figures 26 to 27B The various components can be similar to those described above. Figures 1 to 22B Those described herein, wherein the same reference numerals denote the same elements formed by the same process. Figure 27A and Figure 27B A gate isolation structure 130 is shown in the context of an NSFET device. Although Figure 27A and Figure 27B A gate isolation structure 130 according to the above-described device 100 is shown, but other embodiments may include a gate isolation structure 130 according to any one of the above-described devices 150, 200 or 250.

[0075] In various embodiments, the gate isolation structure may include a dielectric pad (sometimes referred to as a spacer) deposited using a non-conformal deposition process to have a tapered profile, and the gate isolation structure may also include a dielectric filler material deposited over the dielectric pad. By maintaining the tapered profile within the dielectric pad, the width at the top of the opening can be kept relatively large, and the deposition window for the dielectric filler material is improved. Therefore, the dielectric filler material can be formed with fewer manufacturing tolerances, such as reduced seams / voids. The reduction in the size / number of seams / voids can further reduce electrical defects (e.g., short circuits) that may result from conductive material being unintentionally trapped in exposed seams during subsequent processing steps (e.g., during the formation of the gate or source / drain contacts).

[0076] In some embodiments, the semiconductor device includes: a first transistor having a first gate stack and a first source / drain region located on opposite sides of the first gate stack; a second transistor having a second gate stack and a second source / drain region located on opposite sides of the second gate stack; a gate isolation structure separating the first gate stack from the second gate stack, wherein the gate isolation structure includes: a dielectric pad having a varying thickness along the sidewalls of the first and second gate stacks; and a dielectric filler material located above the dielectric pad, wherein the dielectric filler material includes a seam. Optionally, in some embodiments, the dielectric pad has a lateral portion along the bottom surface of the dielectric filler material, wherein the varying thickness of the dielectric pad increases in a direction toward the lateral portion of the dielectric pad. Optionally, in some embodiments, a gap is provided in the lower portion of the seam, wherein the gap is wider than the upper portion of the seam. Optionally, in some embodiments, the semiconductor device further includes: a second dielectric pad located between the dielectric pad and the dielectric filler material. Optionally, in some embodiments, the dielectric pad includes a first dielectric material, and the second dielectric pad includes an oxide of the first dielectric material. Optionally, in some embodiments, the dielectric pad extends continuously from the sidewall of the first gate stack to the sidewall of the second gate stack. Optionally, in some embodiments, the semiconductor device further includes a void located in the lower portion of the dielectric pad.

[0077] In some embodiments, the semiconductor device includes: a first gate stack located in an interlayer dielectric; a second gate stack located in the interlayer dielectric; and a gate isolation structure located between the first gate stack and the second gate stack, wherein the gate isolation structure contacts the sidewalls of the first gate stack and the second gate stack, wherein the gate isolation structure includes: a dielectric pad, wherein a first lateral dimension of the dielectric pad is smaller than a second lateral dimension of the dielectric pad, wherein the first lateral dimension of the dielectric pad is measured at a horizontal plane of the top surface of the interlayer dielectric, wherein the second lateral dimension of the dielectric pad is measured at a horizontal plane of the bottom surface of the interlayer dielectric; and a dielectric filler material located above the dielectric pad, wherein the dielectric filler material includes a seam. Optionally, in some embodiments, the first lateral dimension of the dielectric filler material is larger than the second lateral dimension of the dielectric filler material, wherein the first lateral dimension of the dielectric filler material is measured at a horizontal plane of the top surface of the interlayer dielectric, wherein the second lateral dimension of the dielectric filler material is measured at a horizontal plane of the bottom surface of the interlayer dielectric. Optionally, in some embodiments, the ratio of the second lateral dimension of the dielectric filler to the first lateral dimension of the dielectric filler is in the range of 0.7 to 0.9. Optionally, in some embodiments, the third lateral dimension of the dielectric filler is greater than both the first and second lateral dimensions of the dielectric filler, wherein the third lateral dimension is measured at the widest point of the dielectric filler in a cross-sectional view, and wherein the third lateral dimension is measured at a horizontal plane below the bottom surface of the interlayer dielectric. Optionally, in some embodiments, the ratio of the second to the third lateral dimension of the dielectric filler is in the range of 0.4 to 0.6. Optionally, in some embodiments, the seam includes an upper portion and a lower portion, wherein the lower portion has a gap with a lateral dimension greater than that of the upper portion. Optionally, in some embodiments, the ratio of the second to the first lateral dimension of the dielectric liner is in the range of 1.1 to 1.5.

[0078] In some embodiments, the method includes: patterning an extension through an opening in a dummy gate stack; depositing a dielectric pad on the sidewalls and bottom surface of the opening, wherein depositing the dielectric pad includes a non-conformal deposition process; depositing a dielectric fill material in the opening above the dielectric pad, wherein depositing the dielectric fill material includes a deposition process of a different type than that used for depositing the dielectric pad, and wherein depositing the dielectric fill material includes forming seams in the dielectric fill material; removing the dummy gate stack; and forming a first gate stack and a second gate stack on opposite sides of the dielectric pad. Optionally, in some embodiments, the non-conformal deposition process is a plasma-enhanced atomic layer deposition (PEALD) process, wherein the PEALD process deposits a thinner dielectric pad at the top of the opening than at the bottom of the opening. Optionally, in some embodiments, depositing the dielectric fill material includes an atomic layer deposition (ALD) process. Optionally, in some embodiments, the PEALD process includes performing a nitrogen plasma treatment. Optionally, in some embodiments, the non-conformal deposition process includes merging the dielectric pad at the bottom of the opening. Optionally, in some embodiments, the method further includes oxidizing the dielectric liner before depositing the dielectric filler material.

[0079] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, comprising: The first transistor has a first gate stack located in an interlayer dielectric and a first source / drain region located on opposite sides of the first gate stack; The second transistor has a second gate stack located in the interlayer dielectric and a second source / drain region located on opposite sides of the second gate stack; A gate isolation structure separates the first gate stack from the second gate stack, wherein the gate isolation structure includes: A dielectric pad having a varying thickness along the sidewalls of the first gate stack and the second gate stack, wherein a first lateral dimension of the dielectric pad, measured at a horizontal plane of the top surface of the interlayer dielectric, is smaller than a second lateral dimension of the dielectric pad, measured at a horizontal plane of the bottom surface of the interlayer dielectric; and A dielectric filler material is located above the dielectric pad, wherein the dielectric filler material includes a seam, and wherein a first lateral dimension of the dielectric filler material, measured at a horizontal plane of the top surface of the interlayer dielectric, is greater than a second lateral dimension of the dielectric filler material, measured at a horizontal plane of the bottom surface of the interlayer dielectric.

2. The semiconductor device according to claim 1, wherein, The dielectric pad has a transverse portion along the bottom surface of the dielectric filler material, wherein the varying thickness of the dielectric pad increases in the direction toward the transverse portion of the dielectric pad.

3. The semiconductor device according to claim 1, wherein, A gap is provided in the lower part of the joint, wherein the gap is wider than the upper part of the joint.

4. The semiconductor device according to claim 1, further comprising: The second dielectric liner is located between the dielectric liner and the dielectric filler material.

5. The semiconductor device according to claim 4, wherein, The dielectric pad includes a first dielectric material, and the second dielectric pad includes an oxide of the first dielectric material.

6. The semiconductor device according to claim 1, wherein, The dielectric pad extends continuously from the sidewall of the first gate stack to the sidewall of the second gate stack.

7. The semiconductor device according to claim 6, further comprising: The gap is located in the lower part of the dielectric pad.

8. A semiconductor device, comprising: The first gate stack is located in the interlayer dielectric; The second gate stack is located in the interlayer dielectric; as well as A gate isolation structure is located between the first gate stack and the second gate stack, wherein the gate isolation structure contacts the sidewalls of the first gate stack and the sidewalls of the second gate stack, and wherein the gate isolation structure includes: A dielectric pad, wherein a first lateral dimension of the dielectric pad is smaller than a second lateral dimension of the dielectric pad, wherein the first lateral dimension of the dielectric pad is measured at a horizontal plane of the top surface of the interlayer dielectric, and wherein the second lateral dimension of the dielectric pad is measured at a horizontal plane of the bottom surface of the interlayer dielectric; and A dielectric filler material is located above the dielectric pad, wherein the dielectric filler material includes a seam, the first lateral dimension of the dielectric filler material is greater than the second lateral dimension of the dielectric filler material, wherein the first lateral dimension of the dielectric filler material is measured at the horizontal plane of the top surface of the interlayer dielectric, and wherein the second lateral dimension of the dielectric filler material is measured at the horizontal plane of the bottom surface of the interlayer dielectric.

9. The semiconductor device according to claim 8, wherein, The dielectric pad extends continuously from the sidewall of the first gate stack to the sidewall of the second gate stack.

10. The semiconductor device according to claim 8, wherein, The ratio of the second lateral dimension of the dielectric filler to the first lateral dimension of the dielectric filler is in the range of 0.7 to 0.

9.

11. The semiconductor device according to claim 8, wherein, The third lateral dimension of the dielectric filler is greater than the first lateral dimension and the second lateral dimension of the dielectric filler, wherein the third lateral dimension is measured at the widest point of the dielectric filler in the cross-sectional view, and wherein the third lateral dimension is measured at a horizontal plane below the bottom surface of the interlayer dielectric.

12. The semiconductor device according to claim 11, wherein, The ratio of the second lateral dimension of the dielectric filler to the third lateral dimension of the dielectric filler is in the range of 0.4 to 0.

6.

13. The semiconductor device according to claim 8, wherein, The seam includes an upper part and a lower part, wherein the lower part has a gap with a lateral dimension larger than that of the upper part.

14. The semiconductor device according to claim 8, wherein, The ratio of the second lateral dimension of the dielectric pad to the first lateral dimension of the dielectric pad is in the range of 1.1 to 1.

5.

15. A method of forming a semiconductor device, comprising: A dummy gate stack is formed in the interlayer dielectric, and a patterned extension extends through the openings of the dummy gate stack; A dielectric pad is deposited on the sidewalls and bottom surface of the opening, wherein the deposition of the dielectric pad includes a non-conformal deposition process, and a first lateral dimension of the dielectric pad, measured at the horizontal plane of the top surface of the interlayer dielectric, is smaller than a second lateral dimension of the dielectric pad, measured at the horizontal plane of the bottom surface of the interlayer dielectric. Depositing a dielectric filler material in the opening above the dielectric pad, wherein depositing the dielectric filler material includes a deposition process of a different type than depositing the dielectric pad, and wherein depositing the dielectric filler material includes forming a seam in the dielectric filler material, wherein a first lateral dimension of the dielectric filler material measured at the horizontal plane of the top surface of the interlayer dielectric is greater than a second lateral dimension of the dielectric filler material measured at the horizontal plane of the bottom surface of the interlayer dielectric; Remove the dummy gate stack; and A first gate stack and a second gate stack are formed on opposite sides of the dielectric pad.

16. The method according to claim 15, wherein, The non-conformal deposition process is a plasma-enhanced atomic layer deposition (PEALD) process, wherein the plasma-enhanced atomic layer deposition process deposits a thinner dielectric pad at the top of the opening than at the bottom of the opening.

17. The method according to claim 16, wherein, The deposition of the dielectric filling material includes an atomic layer deposition (ALD) process.

18. The method according to claim 16, wherein, The plasma-enhanced atomic layer deposition process includes performing nitrogen plasma treatment.

19. The method according to claim 15, wherein, The non-conformal deposition process includes incorporating the dielectric pad at the lower part of the opening.

20. The method of claim 15, further comprising: The dielectric liner is oxidized before the dielectric filler material is deposited.

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