Storage devices, methods of manufacturing the same, and electronic devices including the storage devices

Abstract

A memory device, a method for manufacturing the same, and an electronic device including the memory device are disclosed. According to an embodiment, the memory device may include: a first interconnect layer, a second interconnect layer, a third interconnect layer, and a fourth interconnect layer sequentially disposed in a vertical direction relative to a substrate. The first interconnect layer includes a plurality of first conductive lines extending parallel to each other along a first direction; one of the second and third interconnect layers includes a plurality of conductive lines extending parallel to each other along a second direction intersecting the first direction; and the fourth interconnect layer includes a plurality of fourth conductive lines extending parallel to each other along a third direction. A memory cell is disposed at the intersection of the conductive lines. Each memory cell includes a first transistor, a second transistor, and a third transistor stacked vertically on top of each other. A fifth interconnect layer is disposed above the memory cell and includes a plurality of fifth conductive lines extending along a fourth direction intersecting the third direction.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more specifically to memory devices, methods of manufacturing the same, and electronic devices including such memory devices. Background Technology

[0002] Dynamic random access memory (DRAM) often uses capacitors as storage elements. For example, in a common 1T1C configuration, there is a transistor (T) as a switching device and a capacitor (C) as a storage element. However, as the size of storage devices continues to shrink, the area used to fabricate capacitors also gradually decreases, making it difficult to ensure that the capacitors have a sufficiently large capacitance to retain data.

[0003] A 3T0C configuration DRAM that does not use capacitors has been proposed. In this configuration, three transistors are used, and the gate capacitance of the transistors can replace the capacitors as storage elements. However, the 3T0C configuration occupies a relatively large area. Summary of the Invention

[0004] In view of this, the purpose of this disclosure is at least in part to provide a space-saving storage device, a method of manufacturing the same, and an electronic device including such a storage device.

[0005] According to one aspect of this disclosure, a memory device is provided, comprising: a first interconnect layer, a second interconnect layer, a third interconnect layer, and a fourth interconnect layer disposed sequentially in a vertical direction relative to a substrate, wherein the first interconnect layer includes a plurality of first conductive lines extending parallel to each other along a first direction, one of the second and third interconnect layers includes a plurality of conductive lines extending parallel to each other along a second direction intersecting the first direction, and the fourth interconnect layer includes a plurality of fourth conductive lines extending parallel to each other along a third direction; a plurality of memory cells, wherein each memory cell extends vertically from a corresponding first conductive line in the first interconnect layer and forms an electrical connection with a corresponding conductive line in the second interconnect layer or therein, a corresponding conductive line in the third interconnect layer or therein, and a corresponding fourth conductive line in the fourth interconnect layer, and includes a first transistor, a second transistor, and a third transistor stacked on top of each other in a vertical direction. The first transistor includes: a first active layer including a first source / drain region, a second source / drain region electrically connected to a corresponding conductive line in a second interconnect layer or therein, and a channel region located vertically between the first source / drain region and the second source / drain region; a first gate dielectric layer on the first active layer; and a first gate conductor layer on the first gate dielectric layer, wherein the first gate conductor layer extends toward a corresponding first conductive line in the first interconnect layer to be electrically connected to the corresponding first conductive line. The second transistor includes: a second active layer including a first source / drain region, a second source / drain region electrically connected to a corresponding conductive line in a third interconnect layer or therein, and a channel region located vertically between the first source / drain region and the second source / drain region, wherein the second source / drain region of the first transistor is close to and electrically connected to the first source / drain region of the second transistor; a second gate dielectric layer on the second active layer; and a second gate conductor layer on the second gate dielectric layer, the second gate conductor layer being electrically isolated from the first gate conductor layer. The third transistor includes: a third active layer comprising a first source / drain region electrically connected to a second gate conductor layer, a second source / drain region electrically connected to a corresponding fourth conductive line in a fourth interconnect layer, and a channel region located vertically between the first source / drain region and the second source / drain region; a third gate dielectric layer on the third active layer; and a third gate conductor layer on the third gate dielectric layer. The memory device further includes: a fifth interconnect layer above the memory cell, comprising a plurality of fifth conductive lines extending along a fourth direction intersecting the third direction, wherein the third gate conductor layer of each memory cell is electrically connected to a corresponding fifth conductive line in the fifth interconnect layer.

[0006] According to another aspect of this disclosure, a method for manufacturing a memory device is provided, comprising: forming a first isolation layer on a substrate; forming a first interconnect layer on the first isolation layer and patterning the first interconnect layer as a plurality of first conductive lines extending parallel to each other along a first direction; sequentially forming a second isolation layer, a second interconnect layer, a third isolation layer, and a third interconnect layer on the first isolation layer and the first interconnect layer, wherein one of the second interconnect layer and the third interconnect layer is patterned as a plurality of conductive lines extending parallel to each other along a second direction intersecting the first direction; forming a fourth isolation layer on the third interconnect layer; forming a fourth interconnect layer on the fourth isolation layer and patterning the fourth interconnect layer as a plurality of fourth conductive lines extending parallel to each other along a third direction; forming a fifth isolation layer on the fourth isolation layer and the fourth interconnect layer; forming a plurality of vertically extending openings at the intersections of corresponding conductive lines in the first to fourth interconnect layers; and forming a first transistor, a second transistor, and a third transistor stacked vertically in each opening to form a memory cell. The first transistor includes: a first active layer including a first source / drain region, a second source / drain region electrically connected to a corresponding conductive line in a second interconnect layer or therein, and a channel region located vertically between the first source / drain region and the second source / drain region; a first gate dielectric layer on the first active layer; and a first gate conductor layer on the first gate dielectric layer, wherein the first gate conductor layer extends toward a corresponding first conductive line in the first interconnect layer to be electrically connected to the corresponding first conductive line. The second transistor includes: a second active layer including a first source / drain region, a second source / drain region electrically connected to a corresponding conductive line in a third interconnect layer or therein, and a channel region located vertically between the first source / drain region and the second source / drain region, wherein the second source / drain region of the first transistor is electrically connected to the first source / drain region of the second transistor; a second gate dielectric layer on the second active layer; and a second gate conductor layer on the second gate dielectric layer, the second gate conductor layer being electrically isolated from the first gate conductor layer. The third transistor includes: a third active layer comprising a first source / drain region electrically connected to a second gate conductor layer, a second source / drain region electrically connected to a corresponding fourth conductive line in a fourth interconnect layer, and a channel region located vertically between the first source / drain region and the second source / drain region; a third gate dielectric layer on the third active layer; and a third gate conductor layer on the third gate dielectric layer. The method further includes: forming a fifth interconnect layer on a fifth isolation layer, the fifth interconnect layer including a plurality of fifth conductive lines extending along a fourth direction intersecting the third third direction, wherein the third gate conductor layer of each memory cell is electrically connected to a corresponding fifth conductive line in the fifth interconnect layer.

[0007] According to another aspect of this disclosure, an electronic device is provided, including the aforementioned storage device.

[0008] According to embodiments of this disclosure, a storage device is provided in which transistors constituting memory cells are stacked on top of each other, thereby saving area. In particular, the transistors stacked on top of each other in each memory cell can be self-aligned in the vertical direction. Attached Figure Description

[0009] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0010] Figures 1(a) to 13(c) A schematic diagram of some stages in the process of manufacturing a storage device according to an embodiment of the present disclosure is shown;

[0011] Figures 14(a) to 16 A schematic diagram of some stages in the process of manufacturing a storage device according to another embodiment of the present disclosure is shown;

[0012] Figure 17(a) and 17(b) An equivalent circuit diagram of a memory cell according to an embodiment of the present disclosure is schematically shown.

[0013] in, Figure 1(a) , 4(a) Figures 7(a), 11(a), and 13(a) are top views. Figure 1(a) shows the positions of lines AA′ and BB′.

[0014] Figure 1(b) , 5 Figures 6(a), 7(b), 11(b), 12(a), 13(b), 14(a), and 15(a) are cross-sectional views along line AA′.

[0015] Figure 2 , 3 4(b), 6(b), 7(c), 8 to 10, 11(c), 12(b), 13(c), 14(b), 15(b), and 16 are cross-sectional views along line BB′.

[0016] Figure 14(c) is a cross-sectional view of the gate length control layer.

[0017] Throughout the accompanying drawings, the same or similar reference numerals denote the same or similar parts. Detailed Implementation

[0018] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0019] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0020] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0021] The memory device according to embodiments of this disclosure is based on a vertical device. The vertical device may include a vertical active region relative to the substrate, including source / drain regions disposed at the top and bottom ends and a channel region located between the source / drain regions. A conductive path can be formed between the source / drain regions through the channel region.

[0022] According to embodiments of this disclosure, the location of source / drain regions in an active region can be defined by electrodes. For example, the active region can be defined by a semiconductor layer extending substantially vertically (generally perpendicular to the substrate surface) (with a laterally extending bottom possible, as described below, considering fabrication processes). Regions in the semiconductor layer that are in contact with the electrodes (e.g., regions at the top and bottom ends of the semiconductor layer) can form source / drain regions, while regions between the source / drain regions can form channel regions. A gate conductor layer can be positioned across the channel regions via a gate dielectric layer to control the channel regions. Electrodes can include bit lines, word lines, ground planes, gate length control pads, etc., of the memory device.

[0023] The memory device according to embodiments of this disclosure can be a dynamic random access memory (DRAM) and can have a capacitor-free configuration, such as a 3TOC configuration. In a 3TOC configuration, each memory cell of the memory device can have three transistors, namely, a first transistor (e.g., a select transistor), a second transistor (e.g., a read transistor), and a third transistor (e.g., a write transistor). As mentioned above, these three transistors can be vertical devices and therefore can be easily stacked on top of each other, thereby saving area. These three transistors can be defined by respective active regions (in conjunction with respective gate stacks) and can be self-aligned as described below. For example, adjacent portions of the active layers of the three transistors (e.g., the vertically extending semiconductor layers described above) can be substantially aligned in the vertical direction. In addition, depending on the interconnection, isolation portions can be provided between the transistors (active regions) to achieve electrical isolation. As described below, such isolation portions can also be self-aligned. The self-aligned configuration can further save area. According to embodiments of this disclosure, a memory cell area of ​​4F can be achieved. 2 DRAM.

[0024] According to embodiments of this disclosure, multiple interconnect layers at different levels can be provided to define source / drain regions at different heights of the active region. For example, a first interconnect layer, a second interconnect layer, a third interconnect layer, and a fourth interconnect layer can be provided, which include conductive material and can be patterned as corresponding conductive lines (the interconnect layer may not be patterned when used as a ground plane). Memory cells can be formed where the conductive lines in the different interconnect layers intersect each other.

[0025] A first interconnect layer may be disposed below the first transistor to define the gate of the first transistor. A second interconnect layer may be disposed at the vertical height of the lower end of the active region of the first transistor to define the lower source / drain region of the first transistor. A third interconnect layer may be disposed at the vertical height of the upper end of the active region of the second transistor to define the upper source / drain region of the second transistor. A fourth interconnect layer may be disposed at the vertical height of the upper end of the active region of the third transistor to define the upper source / drain region of the third transistor.

[0026] In a 3T0C configuration, the upper source / drain regions of the first transistor and the lower source / drain regions of the second transistor can be electrically connected to each other. This can be achieved through an active region extending continuously between the first and second transistors, without the need for additional interconnect layers. Furthermore, the gate of the second transistor can be electrically connected to a source / drain region of the third transistor (e.g., the lower source / drain region). Therefore, for the third transistor, its lower source / drain region can be defined by the gate conductor layer of the second transistor, without the need for additional interconnect layers. Additionally, a fifth interconnect layer including corresponding conductive lines can be provided to achieve electrical connections to the gates of each third transistor. In a 3T0C configuration, the conductive lines in the first interconnect layer can be read word lines (RWL), the conductive lines in the second interconnect layer can be either read bit lines (RBL) or ground plane, the conductive lines in the third interconnect layer can be either read bit lines (RBL) or ground plane, the conductive lines in the fourth interconnect layer can be write bit lines (WBL), and the conductive lines in the fifth interconnect layer can be write word lines (WWL). For ease of addressing, RWL and RBL can extend in intersecting (e.g., perpendicular) directions, and WBL and WWL can also extend in intersecting (e.g., perpendicular) directions. Furthermore, for ease of array fabrication, conductive lines in vertically adjacent interconnect layers can extend in intersecting (e.g., perpendicular) directions.

[0027] Each memory cell can be formed to extend vertically to form an electrical connection with each interconnect layer. For example, each memory cell can extend vertically through the interconnect layers used to define the source / drain regions (the second to fourth interconnect layers mentioned above, but not through the bottom first interconnect layer used to define the gate electrode). That is, each memory cell can be formed within an opening where conductive lines intersect each other. The active regions of the first transistor and the second transistor can be continuous with each other as described above, and therefore can be implemented by the same semiconductor layer (hereinafter referred to as the "first active layer"). The first active layer can be formed along the sidewall of the opening, and thus can be annular. The first gate dielectric layer of the first transistor can extend along the lower inner wall of the first active layer, and the first gate conductor layer can fill the inner space of the first gate dielectric layer. The second gate dielectric layer of the second transistor can extend along the upper inner wall of the first active layer, and the second gate conductor layer can fill the inner space of the second gate dielectric layer. The first gate conductor layer and the second gate conductor layer can be electrically isolated from each other (e.g., through the second gate dielectric layer). The semiconductor layer used as the active region in the third transistor (hereinafter referred to as the "second active layer") can be formed along the sidewall of the opening and, due to the manufacturing process, can also extend along the top of the second transistor. Thus, the second active layer can be cup-shaped. The third gate dielectric layer of the third transistor can extend along the inner wall of the cup-shaped second active layer, and the third gate conductor layer can fill the inner space of the third gate dielectric layer. These three transistors can be formed in an opening based on the same mask and therefore can be self-aligned with each other. For example, adjacent portions of the outer walls of each of these three transistors can be substantially coplanar in the vertical direction (defined by the inner sidewall of the opening).

[0028] The first, second, and third transistors can present substantially the same or similar forms: a ring-shaped (or cup-shaped due to manufacturing process) active layer; a gate stack (including a gate dielectric layer and a gate conductor layer) disposed inside the active layer; and a connecting layer disposed outside the active layer to define the source / drain regions. Their respective active layers and gate stacks can have the same configuration, or they can have different configurations to further optimize device performance. For example, the first active layer may include a semiconductor material with relatively high mobility to reduce read time (or increase read speed) when the second transistor is used as a read transistor; while the second active layer may include a semiconductor material with relatively low leakage current or a relatively large bandgap to increase data retention capability when the third transistor is used as a write transistor.

[0029] To achieve electrical isolation between the first active layer and the second active layer, an isolation portion can be provided between them. This isolation portion can be implemented as a sidewall formed on the sidewall of the opening, and thus can be self-aligned between the first and second active layers. Here, the isolation portion can expose the second gate conductor layer to achieve the electrical connection between the lower source / drain region of the third transistor and the gate of the second transistor, as described above. For example, the second active layer can be in direct physical contact with the second gate conductor layer. On the one hand, due to the presence of the second gate conductor layer, the lower source / drain region is defined at a corresponding location in the second active layer; on the other hand, the direct physical contact between them achieves the electrical connection between the lower source / drain region of the third transistor and the gate of the second transistor. Alternatively, a metal connection portion can be additionally provided between the second active layer and the second gate conductor layer to reduce the contact resistance between them.

[0030] Such a storage device can be manufactured, for example, as follows.

[0031] Multiple isolation layers and multiple interconnect layers can be alternately disposed on a substrate, for example, a first isolation layer, a first interconnect layer, a second isolation layer, a second interconnect layer, a third isolation layer, a third interconnect layer, a fourth isolation layer, a fourth interconnect layer, and a fifth isolation layer. As described above, each interconnect layer (except for the interconnect layer used as a ground plane) can be patterned as a corresponding conductive line. Openings can be formed at the intersections of the conductive lines, so that these openings can pass through each interconnect layer in the vertical direction (ending at the lowermost first interconnect layer). Memory cells can be formed in each opening. As described above, each memory cell can include a first transistor, a second transistor, and a third transistor stacked on top of each other. Transistors can be formed by sequentially forming a corresponding active layer, a gate dielectric layer, and a gate conductor layer into the opening. After forming the second transistor and before forming the third transistor, an isolation portion can be formed on the sidewall of the opening using a sidewall process to shield the top of the first active layer. In addition, after forming the isolation portion and before forming the third transistor, a connection portion (e.g., metal) that physically contacts the second gate conductor layer can be formed on the second transistor within the opening. In addition, a fifth interconnect layer including corresponding conductive lines can be formed on the fifth isolation layer to achieve electrical connection to the gate of each third transistor.

[0032] This disclosure may be presented in various forms, some of which will be described below. In the following description, the selection of various materials is discussed. The selection of materials takes into account not only their function (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation, conductive materials for forming electrodes, interconnect structures, etc.) but also etching selectivity. In the following description, the desired etching selectivity may or may not be indicated. Those skilled in the art will understand that when the following references to etching a material layer, unless it is mentioned that other layers are also etched or not shown in the figures, then such etching may be selective, and the material layer may possess etching selectivity relative to other layers exposed to the same etching formulation.

[0033] Figures 1(a) to 13(c) A schematic diagram of some stages in the process of manufacturing a storage device according to an embodiment of the present disclosure is shown.

[0034] like Figure 1(a) and 1(b) As shown, a substrate 1001 is provided. This substrate 1001 can be of various forms, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, and compound semiconductor substrates such as SiGe substrates. In the following description, for ease of explanation, a bulk Si substrate, such as a Si wafer, will be used as an example.

[0035] On substrate 1001, a first isolation layer 1003 and a first interconnect layer 1005 can be formed, for example, by deposition. The first isolation layer 1003 may include a dielectric material such as an oxide (e.g., silicon oxide) to achieve electrical isolation, and its thickness may be, for example, about 20 nm to 200 nm. The first interconnect layer 1005 may include a conductive material, such as a metal such as molybdenum (Mo), ruthenium (Ru), etc., and its thickness may be, for example, about 5 nm to 100 nm. As described below, the first interconnect layer 1005 may define a bit line (RWL). As a bit line or word line, it may be a plurality of conductive lines extending parallel to each other along a certain direction.

[0036] Therefore, as shown in the figure, photoresist 1007 can be formed on the first interconnect layer 1005 and patterned by photolithography as lines extending along a first direction (the horizontal direction within the plane of the paper in Figure 1(a)). The linewidth of these lines can be from about 20 nm to 500 nm, and the spacing W1 between them can be from about 10 nm to 50 nm.

[0037] like Figure 2As shown, the photoresist 1007, configured as a mask, can be used to selectively etch the first interconnect layer 1005, such as through a vertical reactive ion etching (RIE). The RIE can stop at the underlying first isolation layer 1003. Thus, the first interconnect layer 1005 can be patterned to correspond to the pattern of the photoresist 1007, i.e., first conductive lines extending parallel in a first direction. Afterwards, the photoresist 1007 can be removed.

[0038] A second isolation layer 1009 can be formed on the first interconnect layer 1005, for example, by deposition. The second isolation layer 1009 may include a dielectric material such as an oxide, nitride (e.g., silicon nitride), carbide (e.g., silicon carbide), etc., to achieve electrical isolation. Here, the deposition thickness of the second isolation layer 1009 can be controlled to be greater than W1 / 2 to fill the gaps between the first conductive lines in the first interconnect layer 1005, and a sufficiently flat top surface can be achieved to avoid the use of planarization processes such as chemical mechanical polishing (CMP). Avoiding the use of planarization processes allows for better control of the thickness of the second isolation layer 1009 (particularly the thickness on the first interconnect layer 1005). For example, the thickness of the second isolation layer 1009 (on the first interconnect layer 1005) can be approximately 10 nm to 100 nm.

[0039] like Figure 3 As shown, a second interconnect layer 1011 and a third interconnect layer 1013 can be formed on the second isolation layer 1009 by, for example, deposition. The second interconnect layer 1011 may include a conductive material, such as a metal like Mo or Ru, with a thickness of, for example, about 5 nm to 20 nm. As described below, the second interconnect layer 1011 may define a ground plane. For memory devices, the ground can be common, so the second interconnect layer 1011 does not necessarily need to be patterned as separate portions corresponding to each memory cell, but can extend continuously to become a single conductive plate. Of course, this disclosure is not limited to this. For example, the second interconnect layer 1011 may also be patterned as several separate portions, such as several conductive lines (e.g., conductive lines extending along the first direction or the second direction described below), or several conductive plates (e.g., conductive blocks arranged in an array along the first direction and the second direction described below), which can be connected to the ground together. The third interconnect layer 1013 may include a dielectric material such as oxide, nitride, carbide, etc., to achieve electrical isolation, with a thickness of, for example, about 20 nm to 200 nm. The thickness of the third isolation layer 1013 can at least partially define the gate length (or channel length) of the first transistor and the second transistor.

[0040] like Figure 4(a) and 4(b)As shown, a third interconnect layer 1015 can be formed on the third isolation layer 1013, for example, by deposition. Similarly, the third interconnect layer 1015 may include a conductive material, such as a metal like Mo or Ru, with a thickness of, for example, about 5 nm to 20 nm. As described below, the third interconnect layer 1015 may define an RBL. To facilitate addressing of the array of memory cells, the RBL defined by the third interconnect layer 1015 may be formed as a conductive line extending in a direction that intersects (e.g., is perpendicular to) the RWL defined by the first interconnect layer 1015.

[0041] To this end, as shown in the figure, photoresist 1017 can be formed on the third interconnect layer 1015 and patterned by photolithography as lines extending along a second direction (vertical direction in the plane of the paper in FIG. 4(a)) that intersects (e.g., is perpendicular to) the first direction. The linewidth of these lines can be from about 20 nm to 500 nm, and the spacing W2 between them can be from about 10 nm to 50 nm.

[0042] like Figure 5 As shown, the photoresist 1017 can be used as a mask to selectively etch the third interconnect layer 1015, such as vertically oriented RIEs. The RIEs can stop at the underlying third isolation layer 1013. Thus, the third interconnect layer 1015 can be patterned to correspond to the pattern of the photoresist 1017, i.e., third conductive lines extending parallel in the second direction. Afterwards, the photoresist 1017 can be removed.

[0043] On the third interconnect layer 1015, a fourth isolation layer 1019 can be formed, for example, by deposition. The fourth isolation layer 1019 may include a dielectric material such as an oxide, nitride, or carbide to achieve electrical isolation. Similarly, the deposition thickness of the fourth isolation layer 1019 can be controlled to be greater than W² / 2 to fill the gaps between the third conductive lines in the third interconnect layer 1015 and to achieve a sufficiently flat top surface, thus avoiding the use of a planarization process. Avoiding the use of a planarization process allows for better control of the thickness of the fourth isolation layer 1019 (particularly on the third interconnect layer 1015), since this thickness will subsequently at least partially define the gate length (or channel length) of the third transistor. For example, the thickness of the fourth isolation layer 1019 (on the third interconnect layer 1015) can be from approximately 20 nm to 200 nm.

[0044] like Figure 6(a) and 6(b)As shown, a fourth interconnect layer 1021 and a fifth interconnect layer 1023 can be formed on the fourth isolation layer 1019. The fourth interconnect layer 1021 may include a conductive material, such as a metal like Mo or Ru, with a thickness of approximately 5 nm to 20 nm. As described below, the fourth interconnect layer 1021 may define a WBL. The WBL may be a plurality of conductive lines extending parallel to each other along a certain direction, such as a third direction. The third direction may be the same as the aforementioned first or second direction (for ease of fabrication, for example, the same photomask can be used), or it may be different from the first and second directions.

[0045] In this example, the fourth connection layer 1021 is shown with a substantially the same configuration as the first connection layer 1005, for example, the same mask can be used. Therefore, for the configuration of the fourth connection layer 1021, please refer to the above combination. Figure 1(a) and 1(b) as well as Figure 2 The description is omitted here. However, this disclosure is not limited thereto. As long as the conductive lines in each interconnect layer have overlapping portions in the vertical direction, openings can be formed in these overlapping portions as described below, and memory cells can be formed within these openings.

[0046] The fifth isolation layer 1023 may include dielectric materials such as oxides, nitrides, and carbides to achieve electrical isolation. The fifth isolation layer 1023 can be formed using the same process as the second isolation layer 1009, as described above. Figure 2 The description is omitted here.

[0047] Through the above process, intersecting conductive lines (bit lines or word lines) are formed, and memory cells can be formed at the intersections of these conductive lines. More specifically, the intersecting conductive lines define an array of regions on the substrate, where memory cells can be formed (in a 3T0C configuration, three transistors can be formed).

[0048] These regions can define the space for the active regions of transistors in the memory cells.

[0049] For example, such as Figure 7(a) , 7(b) As shown in 7(c), photoresist 1025 can be formed on the fourth isolation layer 1023. The photoresist 1025 can be patterned by photolithography to have a series of openings to expose the areas where conductive lines intersect each other. Although the openings in this photoresist 1025 are shown as square, the shape of the openings is not limited to this, but can include various other shapes suitable for manufacturing, such as rectangles, circles, etc.

[0050] Using the photoresist 1025 with this configuration as a mask, selective etching is performed on the underlying layers, such as vertically oriented RIEs. The RIEs can stop at the second isolation layer 1009. Afterward, the photoresist 1025 can be removed.

[0051] Thus, each conductive line in the second interconnect layer 1011, the third interconnect layer 1015, and the fourth interconnect layer 1021 has an opening corresponding to the photoresist 1025, and these openings are arranged in an array. In this example, each conductive line still extends continuously along the first or second direction and is not completely interrupted by such an opening. In particular, each conductive line has material that extends continuously around the outer periphery of the opening. However, this disclosure is not limited thereto. For example, at at least some conductive lines, the opening may not be completely surrounded by the corresponding conductive line (e.g., the corresponding conductive line may be offset to one side of the opening, thus only surrounding a portion of the sidewall of the opening).

[0052] In each opening, three vertical transistors can be formed that are stacked on top of each other.

[0053] For example, such as Figure 8 As shown, the first active layer 1027 can be formed in a generally conformal manner by deposition such as direct current (DC) magnetron sputtering, radio frequency (RF) magnetron sputtering, atomic layer deposition (ALD), etc. The first active layer 1027 may include a semiconductor material to define the active region of the first transistor (e.g., a select transistor). For example, the first active layer 1027 may include an oxide semiconductor, such as indium gallium zinc oxide (IGZO), with a thickness of about 5 nm to 100 nm. The portion of the first active layer 1027 located at the bottom of the opening (and the portion located outside the opening) can be removed by selective etching, such as vertical RIE. Thus, the first active layer 1027 can remain on the sidewall of the opening. Since no opening is formed in the second isolation layer 1009 at this time, the formed first active layer 1027 can be electrically isolated from the first interconnect layer 1005 that defines the RWL (which electrically connects to the gate of the select transistor).

[0054] With a first active layer 1027 present on the sidewall, the openings can be further deepened. For example, openings can be formed in the second isolation layer 1009 via a vertically oriented RIE (which may stop at the first interconnect layer 1005). In the deepened openings, a first gate dielectric layer 1029 can be formed by deposition in a generally conformal manner. The portion of the first gate dielectric layer 1029 located at the bottom of the opening (and the portion located outside the opening) can be removed by selective etching, such as a vertically oriented RIE. For example, the first gate dielectric layer 1029 may include an oxide dielectric such as aluminum oxide (Al2O3) with a thickness of approximately 2 nm to 30 nm. Then, a first gate conductor layer 1031 can be formed by deposition. The first gate conductor layer 1031 can fill the remaining space in each opening. The first gate conductor layer 1031 may include a conductor, such as a conductive nitride like titanium nitride (TiN), a metal like tungsten (W), or a conductive oxide such as zinc-doped indium oxide (IZO). The first gate conductor layer 1031 can be etched back using wet etching, RIE, atomic layer etching (ALE), etc., so that its top surface descends to between the top surface of the second interconnect layer 1011 and the bottom surface of the third interconnect layer 1015.

[0055] Thus, a first transistor (e.g., a selection transistor) is formed in each opening. Figure 8 As shown, each first transistor may include a first active layer 1027. The first active layer 1027 may extend along the sidewall of the opening, thus forming a ring. The region of the first active layer 1027 that is in contact with the second interconnect layer 1011 may define the lower source / drain region of the first transistor. The region of the first active layer 1027 above the lower source / drain region and intermediate through the first gate dielectric layer 1029 facing the first gate conductor layer 1031 may define the channel region of the first transistor, while the region of the first active layer 1027 above the channel region may define the upper source / drain region of the first transistor. The channel length or gate length may be defined by the height of the first gate conductor layer 1031 above the top surface of the second interconnect layer 1011.

[0056] A second transistor (e.g., a read transistor) can be formed above the first transistor in the opening. For example, as... Figure 9As shown, the etched-back first gate conductor layer 1031 can be used as a mask to selectively etch the first gate dielectric layer 1029 using methods such as wet etching, dry etching, or ALE. Then, the second gate dielectric layer 1033 and the second gate conductor layer 1035 can be formed similarly to the formation of the first transistor, except that the bottom of the second gate dielectric layer 1033 does not need to be etched to achieve electrical isolation between the gates of the first and second transistors. The material and thickness of the second gate dielectric layer 1033 and the second gate conductor layer 1035 can be the same as or different from the first gate dielectric layer 1029 and the first gate conductor layer 1031. Here, the top surface of the second gate conductor layer 1035 can be etched back to near the top surface of the third interconnect layer 1015.

[0057] In this example, the first gate dielectric layer 1029 is selectively etched first, and then the second gate dielectric layer 1033 is formed. However, this disclosure is not limited thereto. For example, the first gate dielectric layer 1029 may not be etched, and the second gate dielectric layer 1033 may be formed on the first gate dielectric layer 1029 instead.

[0058] In this example, instead of forming a separate active layer for the second transistor, the same first active layer 1027 as the first transistor is used. However, this disclosure is not limited to this. For example, the first gate conductor layer 1031 after etching back can be used as a mask to selectively etch the first active layer 1027 (after selectively etching the first gate dielectric layer 1029 as described above). Then, using the process for forming the annular first active layer 1027, an annular second active layer for the second transistor (whose lower end may contact the upper end of the first active layer 1027) can be formed in each opening. On this separately formed second active upper layer, the second gate dielectric layer 1033 and the second gate conductor layer 1035 can be formed as described above. This can be advantageous when the first transistor and the second transistor need to be optimized differently.

[0059] Thus, a second transistor (e.g., a read transistor) is formed in each opening. Figure 9 As shown, each second transistor may include a first active layer 1027. A region in the first active layer 1027 that is adjacent to the third interconnect layer 1015 may define the upper source / drain region of the second transistor. A region in the first active layer 1027 below the upper source / drain region and intermediate through the second gate dielectric layer 1033 facing the second gate conductor layer 1035 may define the channel region of the second transistor, while a region in the first active layer 1027 below the channel region may define the lower source / drain region of the second transistor. The channel length or gate length may be defined by the height of the second gate conductor layer 1035 below the bottom surface of the third interconnect layer 1015.

[0060] Therefore, the upper source / drain region of the first transistor and the lower source / drain region of the second transistor can share the same region in the first active layer 1027 (e.g., the region between the top surface of the first gate conductor layer 1031 and the bottom surface of the second gate conductor layer 1035 in vertical height).

[0061] In addition, such as Figure 10 As shown, the second gate conductor layer 1035 after etching can be used as a mask to selectively etch the second gate dielectric layer 1033 and the first active layer 1027 by means of, for example, wet etching, dry etching, ALE, etc. The top surface of the first active layer 1027 may not exceed the top surface of the third interconnect layer 1015.

[0062] Above the second transistor in the opening, a third transistor (e.g., a write transistor) can be formed. To achieve isolation between the second and third transistors, particularly between the active regions, an isolation portion 1037 can be formed. Here, considering the first active layer 1027 along the sidewall of the opening, the isolation portion 1037 in the form of a spacer can be formed on the sidewall of the opening. For example, a dielectric layer can be deposited in a generally conformal manner, and then anisotropically etched, such as a vertical RIE, onto the deposited dielectric to remove the lateral extensions of the deposited dielectric, leaving its vertical extensions, thereby forming the spacer. Considering etching selectivity, for example, if the previously formed isolation layers include oxides, the isolation portion 1037 can be considered to include nitrides.

[0063] Here, the isolation section 1037 is arranged along the sidewall of the opening and exposes the second gate conductor layer 1035 in the middle of the opening so that the second gate conductor layer 1035 can be electrically connected to the third transistor thereafter.

[0064] The third transistor can be formed similarly. For example, as... Figure 11(a) , 11(b) As shown in 11(c), a third active layer 1041, a third gate dielectric layer 1043, and a third gate conductor layer 1045 can be sequentially formed above the second transistor in the opening. Their formation methods can be combined as described above. Figure 8The difference with respect to the first active layer 1027, the first gate dielectric layer 1029, and the first gate conductor layer 1031 is that the bottom of the third active layer 1041 and the third gate dielectric layer 1043 does not need to be etched, and planarization such as CMP can be performed after the second gate conductor layer 1045 is deposited, allowing them to remain within the opening. The materials and thicknesses of the third active layer 1041, the third gate dielectric layer 1043, and the third gate conductor layer 1045 can be the same as, or different from, the first active layer 1027, the first gate dielectric layer 1029, and the first gate conductor layer 1031. In particular, the third active layer 1041 may include a semiconductor material with relatively low leakage current or a relatively large bandgap (e.g., relative to silicon) to increase data retention capability, while the first active layer 1027 may include a semiconductor material with relatively high mobility (e.g., relative to silicon) to reduce read time (or increase read speed).

[0065] Thus, a third transistor (e.g., a write transistor) is formed in each opening. As shown, each third transistor may include a third active layer 1041. The third active layer 1041 may extend along the sidewalls of the opening and the top surface of the first transistor (and the isolation portion 1037), thereby forming a cup shape. The portion of the third active layer 1041 that connects to the fourth interconnect layer 1021 may define the upper source / drain region of the third transistor, and the portion of the third active layer 1041 that connects to the second gate conductor layer 1035 may define the lower source / drain region of the second transistor. The portion between the upper and lower source / drain regions is the channel region, controlled by the third gate conductor layer 1045 (intervened by the third gate dielectric layer 1043). The channel length or gate length is primarily defined by the thickness of the fourth isolation layer 1019.

[0066] According to another embodiment of this disclosure, such as Figure 12(a) and 12(b) As shown, before fabricating the third transistor, a connection portion 1041' can be formed in each opening. For example, the connection portion 1041' can be formed by depositing a conductive material such as metal, planarizing the deposited conductive material (e.g., CMP), and then etching back the planarized conductive material. The connection portion 1041' reduces the contact resistance with the second gate conductor layer 1035. Furthermore, the connection portion 1041' allows adjustment of the bottom position of the third gate conductor layer 1045 of the third transistor, which, as described below, can be advantageous for controlling the gate length of the third transistor. Hereinafter, Figure 12(a) and 12(b) The scenario shown is used as an example for description, but these descriptions also apply to other situations. Figure 11(a) , 11(b) The situation shown in 11(c).

[0067] Additionally, a fifth interconnect layer can be formed on the fifth isolation layer 1023. For example, as... Figure 13(a) , 13(b) As shown in 13(c), a sixth isolation layer 1047 can be formed, for example, by deposition. The sixth isolation layer 1047 may include a dielectric material such as oxide, nitride, carbide, etc., to achieve electrical isolation. In the sixth isolation layer 1047, openings corresponding to the third gate conductor layer 1045 of each third transistor and trenches extending along the fourth direction can be formed, for example, using a dual damascene process. Conductive material can be filled into the openings and trenches thus formed in the sixth isolation layer 1047, for example, by deposition followed by planarization. The conductive material filling the openings of the sixth isolation layer 1047 can form contact plugs 1049, while the conductive material filling the trenches of the sixth isolation layer 1047 can form fifth conductive lines 1051. The fifth conductive lines 1051 can define a WWL. For ease of addressing memory cells, the WWL defined by the fifth conductive lines 1051 can intersect with the WBL defined by the fourth conductive lines in the fourth interconnect layer 1021. That is, the fourth direction can intersect (e.g., be perpendicular to) the third direction. In this example, the fourth direction can be substantially the same as the second direction if the third direction is substantially the same as the first direction.

[0068] Thus, the storage unit according to this embodiment is obtained.

[0069] As shown in Figure 17(a), a first transistor, serving as a select transistor TS, can be connected between the second interconnect layer 1011 (ground plane) and a second transistor, serving as a read transistor TR, with its gate electrically connected to a first conductive line (e.g., RWL) in the first interconnect layer 1005. The second transistor can be connected between the first transistor and a third conductive line (e.g., RBL) in the third interconnect layer 1015. A third transistor, serving as a write transistor TW, can be connected between the gate of the second transistor and a fourth conductive line (e.g., WBL) in the fourth interconnect layer 1021, with its gate electrically connected to a fifth conductive line 1051 (e.g., WWL) in the fifth interconnect layer.

[0070] In this type of memory cell, instead of using separate memory elements such as capacitors, the gate capacitance of the read transistor TR can serve as the memory element. The node between the write transistor and the read transistor is the memory node SN. Thus, a 3T0C configuration is obtained.

[0071] According to another embodiment, the positions of the second connection layer 1011 and the third connection layer 1015 can be interchanged, for example, by changing their formation order. In this case, the first transistor, which serves as the selection transistor TS, can be connected between the third conductive line (e.g., RBL) in the third connection layer 1015 and the second transistor, which serves as the read transistor TR, and the second transistor can be connected between the first transistor and the second connection layer 1011 (ground plane). This results in the configuration shown in FIG17(b).

[0072] In the above embodiments, the gate length of each transistor may exhibit relatively large process variations. According to embodiments of this disclosure, the gate length of the transistor can be controlled more precisely.

[0073] Figures 14(a) to 16 A schematic diagram of some stages in the manufacturing process of a storage device according to another embodiment of this disclosure is shown. The differences between this embodiment and the embodiments described above will be described below.

[0074] It can be combined as described above. Figures 1(a) to 3 As described above, a first isolation layer 1003, a first interconnect layer 1005, a second isolation layer 1009, and a second interconnect layer 1011 are sequentially formed on the substrate 1001. Similarly, a third isolation layer 1013' can be formed on the second interconnect layer 1011, the difference being that a gate length control layer 1201 can be inserted into the third isolation layer 1013', such as... Figure 14(a) , 14(b) As shown in 14(c). For example, the lower portion of the third isolation layer 1013' can be formed on the second interconnect layer 1011 in the manner described above. On the lower portion of the third isolation layer 1013', a gate length control layer 1201 can be formed, for example, by deposition. The gate length control layer 1201 may include a conductive material, such as a metal such as Mo, Ru, etc., and a thickness of, for example, about 10 nm to 150 nm. The gate length control layer 1201 can be patterned into gate length control pads corresponding to each memory cell by selective etching such as RIE. For example, the gate length control layer 1201 can be patterned based on the combined pattern of the mask used to pattern the first interconnect layer and the mask used to pattern the third interconnect layer (the pattern shown in FIG. 1(a) + the pattern shown in FIG. 4(a)). The resulting gate length control pad can be located where the first conductive line in the first interconnect layer intersects with the third conductive line in the third interconnect layer, as shown in FIG. 14(c) (a cross-sectional view of the gate length control layer 1201 on a plane parallel to the substrate surface). Then, the upper part of the third isolation layer 1013′ can be formed on the gate length control layer 1201 in the manner described above for forming the isolation layer.

[0075] The same combination can be achieved on the third isolation layer 1013′. Figures 4(a) to 5The third interconnect layer 1015 is formed, and a fourth isolation layer 1019' can be similarly formed on the third interconnect layer 1015. A gate length control layer 1203 can be similarly inserted into the fourth isolation layer 1019', such as... Figure 15(a) and 15(b) As shown. For the formation of the fourth isolation layer 1019′ and the gate length control layer 1203, please refer to the above description of the third isolation layer 1013′ and the gate length control layer 1201.

[0076] Next, the process can be carried out as described in the above embodiments. For example, as... Figure 16 As shown, space can be defined for the active region of transistors in the memory cell, that is, a series of openings arranged in an array can be formed. Similarly, these openings also pass through the corresponding gate length control pads in the gate length control layers 1201 and 1203, respectively. Then, first to third transistors stacked on top of each other can be formed in these openings.

[0077] Here, a connection portion 1041' is provided to better define the lower end of the channel region of the third transistor. More specifically, the top surface of the connection portion 1041' can be located between the top and bottom surfaces of the gate length control layer 1203 (and thus in contact with the gate length control layer 1203), so the lower part of the third active layer 1041 is surrounded by a conductive material such as metal (connection portion 1041', gate length control pad in the gate length control layer 1203), and is thus defined as the lower source / drain region. The top of this lower source / drain region is defined by the top surface of the gate length control layer 1203. On the other hand, the bottom of the upper source / drain region is defined by the bottom surface of the fourth interconnect layer 1021. Therefore, the channel length (or gate length) between the upper and lower source / drain regions can be determined by the gap between the top surface of the gate length control layer 1203 and the bottom surface of the fourth interconnect layer 1021, that is, the thickness of the upper part of the fourth isolation layer 1019′ (the thickness above the gate length control layer 1203). Here, the bottom surface of the third gate conductor layer 1045 is located between the top and bottom surfaces of the gate length control layer 1203 so as to cover the entire vertical range of the gap or the thickness.

[0078] In this example, the top surface of the connector 1041' is shown as substantially flat and is located between the top and bottom surfaces of the gate length control layer 1203. However, this disclosure is not limited thereto. The top surface of the connector 1041' may not be flat, but may have a shape that is lower in the middle of the opening and higher near the sidewalls of the opening, especially when the opening is narrow. Alternatively, the connector 1041' may not be provided. In these cases, the bottom of the third active layer 1041 may also not extend flat in the lower structure, for example, extending over the connector 1041' (low in the middle and high on both sides), or, in the absence of the connector 1041', extending over the gate conductor layer 1031 and the isolation portion 1037 as described in the above embodiment. In this case, the bottom surface of the gate conductor layer 1045 may not be flat, and its lowest point may be lower than the top surface of the gate length control pad in the gate length control layer 1203, so as to cover the entire vertical range of the spacing or the thickness.

[0079] Similarly, the highest point of the top surface of the first gate conductor layer 1031 may be higher than the bottom surface of the gate length control layer 1201 (the top surface of the first gate conductor layer 1031 may be located between the top and bottom surfaces of the gate length control layer 1201 if it is substantially flat), and the lowest point of the bottom surface of the second gate conductor layer 1035 may be lower than the top surface of the gate length control layer 1201 (the bottom surface of the second gate conductor layer 1035 may be located between the top and bottom surfaces of the gate length control layer 1201 if it is substantially flat). Therefore, the gate length of the first transistor can be determined by the gap between the top surface of the second interconnect layer 1011 and the bottom surface of the gate length control layer 1201, that is, the thickness of the lower part of the third isolation layer 1013′ (the thickness below the gate length control layer 1201), while the gate length of the second transistor can be determined by the gap between the top surface of the gate length control layer 1201 and the bottom surface of the third interconnect layer 1015, that is, the thickness of the upper part of the third isolation layer 1013′ (the thickness above the gate length control layer 1201).

[0080] In this example, two gate length control layers 1201 and 1203 are provided. According to other embodiments, only one of them may be provided.

[0081] The storage device according to embodiments of this disclosure can be applied to various electronic devices. For example, the storage device can store various programs, applications, and data required for the operation of the electronic device. The electronic device may also include a processor that cooperates with the storage device. For example, the processor can operate the electronic device by running programs stored in the storage device. Such electronic devices include smartphones, personal computers (PCs), tablet computers, artificial intelligence devices, wearable devices, or power banks.

[0082] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0083] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A storage device, comprising: A first interconnect layer, a second interconnect layer, a third interconnect layer, and a fourth interconnect layer are sequentially arranged in a vertical direction relative to a substrate. The first interconnect layer includes a plurality of first conductive lines extending parallel to each other along a first direction. One of the second interconnect layer and the third interconnect layer includes a plurality of conductive lines extending parallel to each other along a second direction that intersects the first direction. The fourth interconnect layer includes a plurality of fourth conductive lines extending parallel to each other along a third direction. Multiple memory cells, wherein each memory cell extends vertically from a corresponding first conductive line in the first interconnect layer and forms an electrical connection with a corresponding conductive line in the second interconnect layer or therein, a corresponding conductive line in the third interconnect layer or therein, and a corresponding fourth conductive line in the fourth interconnect layer, and includes a first transistor, a second transistor, and a third transistor stacked on top of each other in the vertical direction, wherein... The first transistor includes: The first active layer includes a first source / drain region, a second source / drain region, and a channel region located in the vertical direction between the first source / drain region and the second source / drain region, which are electrically connected to the second interconnection layer or a corresponding conductive line therein. The first gate dielectric layer on the first active layer; and A first gate conductor layer on the first gate dielectric layer, wherein the first gate conductor layer extends toward a corresponding first conductive line in the first interconnect layer to be electrically connected to the corresponding first conductive line. The second transistor includes: The second active layer includes a third source / drain region, a fourth source / drain region electrically connected to the third interconnect layer or a corresponding conductive line therein, and a channel region located in the vertical direction between the third source / drain region and the fourth source / drain region, wherein the second source / drain region of the first transistor and the third source / drain region of the second transistor are close to each other and electrically connected. The second gate dielectric layer on the second active layer; and A second gate conductor layer is located on the second gate dielectric layer, and the second gate conductor layer is electrically isolated from the first gate conductor layer. The third transistor includes: The third active layer includes a fifth source / drain region electrically connected to the second gate conductor layer, a sixth source / drain region electrically connected to a corresponding fourth conductive line in the fourth interconnect layer, and a channel region located in the vertical direction between the fifth source / drain region and the sixth source / drain region; The third gate dielectric layer on the third active layer; and The third gate conductor layer on the third gate dielectric layer; The fifth interconnect layer, above the memory cell, includes a plurality of fifth conductive lines extending along a fourth direction intersecting the third direction, wherein the third gate conductor layer of each memory cell is electrically connected to a corresponding fifth conductive line in the fifth interconnect layer.

2. The storage device according to claim 1, wherein, The adjacent portions of the first active layer, the second active layer, and the third active layer are substantially aligned in the vertical direction.

3. The storage device according to claim 2, wherein, The adjacent portions of the outer sidewalls of the first active layer, the second active layer, and the third active layer are substantially coplanar in the vertical direction.

4. The storage device according to claim 1, wherein, Each memory cell is surrounded by at least one of a corresponding conductive line in the second interconnect layer or therein, a corresponding conductive line in the third interconnect layer or therein, and a corresponding fourth conductive line in the fourth interconnect layer.

5. The storage device according to claim 1, wherein, The second connecting line layer and the third connecting line layer are integral conductive plates.

6. The storage device according to claim 1, wherein, The first active layer and the second active layer are provided by the same semiconductor layer.

7. The storage device according to claim 6, wherein, The second source / drain region of the first transistor and the third source / drain region of the second transistor are regions in the semiconductor layer located vertically between the top surface of the first gate conductor layer and the bottom surface of the second gate conductor layer.

8. The storage device according to claim 6, wherein, The semiconductor layer is in the form of a vertically extending ring, and the outer sidewall of the ring-shaped semiconductor layer is in physical contact with the corresponding conductive line of the second connecting line layer or therein at the bottom and in the third connecting line layer or therein at the top.

9. The storage device according to claim 8, wherein, The first gate dielectric layer extends along the inner sidewall of the annular semiconductor layer, the first gate conductor layer fills the inner space of the first gate dielectric layer, and extends toward and physically contacts the corresponding first conductive line in the first interconnect layer.

10. The storage device according to claim 8, wherein, The second gate dielectric layer has a vertical extension extending along the inner sidewall of the annular semiconductor layer and a bottom, the second gate conductor layer fills the inner space of the second gate dielectric layer, and the first gate conductor layer and the second gate conductor layer are electrically isolated from each other through the bottom of the second gate dielectric layer.

11. The storage device according to claim 8, wherein, The third active layer has a bottom and a vertical extension extending vertically upward from the bottom, wherein the bottom is electrically connected to the second gate conductor layer, and the vertical extension is in physical contact with a corresponding fourth conductive line in the fourth connection layer.

12. The storage device according to claim 11, wherein, The bottom of the third active layer is in physical contact with the second gate conductor layer.

13. The storage device according to claim 11, wherein, The storage unit further includes: A connection portion is provided between the second transistor and the third transistor, wherein the bottom of the third active layer is electrically connected to the second gate conductor layer through the connection portion.

14. The storage device according to claim 11, wherein, The third gate dielectric layer extends along the inner wall of the third active layer, and the third gate conductor layer fills the inner space of the third gate dielectric layer.

15. The storage device according to claim 11, wherein, The annular semiconductor layer and the vertical extension of the third active layer are substantially aligned in the vertical direction.

16. The storage device of claim 11, further comprising: A first gate length control layer between the second interconnect layer and the third interconnect layer, wherein the first gate length control layer includes a first gate length control pad disposed around the memory cell, the highest point of the top surface of the first gate conductor layer is higher than the bottom surface of the first gate length control pad, and the lowest point of the bottom surface of the second gate conductor layer is lower than the top surface of the first gate length control pad; and / or The second gate length control layer between the third interconnect layer and the fourth interconnect layer includes a second gate length control pad disposed around the memory cell, wherein the lowest point of the bottom surface of the third gate conductor layer is lower than the top surface of the second gate length control pad.

17. The storage device according to claim 11, wherein, The storage unit further includes: An isolation section in the form of a sidewall is located between the semiconductor layer and the third active layer.

18. The storage device according to claim 17, wherein, The annular semiconductor layer, the vertical extension of the third active layer, and the outer wall of the isolation portion are substantially coplanar in the vertical direction.

19. The storage device according to claim 1, wherein, At least one of the first active layer, the second active layer, and the third active layer comprises indium gallium zinc oxide.

20. The storage device according to claim 1, wherein, The second active layer comprises a semiconductor material with relatively high mobility, and the third active layer comprises a semiconductor material with relatively low leakage current or relatively large bandgap.

21. The storage device according to claim 1, wherein, The first active layer, the second active layer, and the third active layer are self-aligned in the vertical direction.

22. The storage device according to claim 21, wherein, The storage unit further includes: A sidewall-shaped isolation section is located between the second active layer and the third active layer. The first active layer, the second active layer, the third active layer, and the isolation portion are self-aligned in the vertical direction.

23. The storage device according to claim 1, wherein, The storage device is a dynamic random access memory device. The first conductive line corresponds to a read bit line, the corresponding conductive line of one of the second and third connection layers corresponds to a read word line, the other of the second and third connection layers corresponds to a ground plane, the fourth conductive line corresponds to a write bit line, and the fifth conductive line corresponds to a write word line.

24. A method for manufacturing a storage device, comprising: A first isolation layer is formed on the substrate; A first interconnection layer is formed on the first isolation layer, and the first interconnection layer is patterned as a plurality of first conductive lines extending parallel to each other along a first direction; A second isolation layer, a second connection layer, a third isolation layer, and a third connection layer are sequentially formed on the first isolation layer and the first connection layer, wherein one of the second connection layer and the third connection layer is patterned as multiple conductive lines extending parallel to each other along a second direction that intersects the first direction; A fourth isolation layer is formed on the third interconnect layer; A fourth connection layer is formed on the fourth isolation layer, and the fourth connection layer is patterned as multiple fourth conductive lines extending parallel to each other along a third direction; A fifth isolation layer is formed on the fourth isolation layer and the fourth interconnect layer; At the points where the corresponding conductive lines in the first to the fourth connecting lines intersect each other, a plurality of vertically extending openings are formed; In each of the openings, a first transistor, a second transistor, and a third transistor are formed, stacked vertically to form a memory cell, wherein... The first transistor includes: The first active layer includes a first source / drain region, a second source / drain region, and a channel region located in the vertical direction between the first source / drain region and the second source / drain region, which are electrically connected to the second interconnection layer or a corresponding conductive line therein. The first gate dielectric layer on the first active layer; and A first gate conductor layer on the first gate dielectric layer, wherein the first gate conductor layer extends toward a corresponding first conductive line in the first interconnect layer to be electrically connected to the corresponding first conductive line. The second transistor includes: The second active layer includes a third source / drain region, a fourth source / drain region electrically connected to the third interconnect layer or a corresponding conductive line therein, and a channel region located in the vertical direction between the third source / drain region and the fourth source / drain region, wherein the second source / drain region of the first transistor and the third source / drain region of the second transistor are electrically connected to each other. The second gate dielectric layer on the second active layer; and A second gate conductor layer is located on the second gate dielectric layer, and the second gate conductor layer is electrically isolated from the first gate conductor layer. The third transistor includes: The third active layer includes a fifth source / drain region electrically connected to the second gate conductor layer, a sixth source / drain region electrically connected to a corresponding fourth conductive line in the fourth interconnect layer, and a channel region located in the vertical direction between the fifth source / drain region and the sixth source / drain region; The third gate dielectric layer on the third active layer; and The third gate conductor layer on the third gate dielectric layer; A fifth interconnect layer is formed on the fifth isolation layer. The fifth interconnect layer includes a plurality of fifth conductive lines extending along a fourth direction intersecting the third third direction, wherein the third gate conductor layer of each memory cell is electrically connected to a corresponding fifth conductive line in the fifth interconnect layer.

25. The method according to claim 24, wherein, Forming the opening includes: forming a preliminary opening penetrating the fifth insulating layer, a corresponding fourth conductive line in the fourth connecting line layer, the fourth insulating layer, the third connecting line layer or a corresponding conductive line therein, the third insulating layer, and the second connecting line layer or a corresponding conductive line therein, to expose the second insulating layer. Forming the first transistor includes: A first active layer is formed on the inner wall of the prepared opening; The second isolation layer is selectively etched through the pre-opening on the inner sidewall where the first active layer is formed, to deepen the pre-opening and expose the corresponding first conductive line in the first interconnect layer, wherein the deepened pre-opening forms the opening; A first gate dielectric layer is formed on the inner sidewall of the first active layer and the inner sidewall of the opening; The opening is filled with a first gate conductor layer; and The first gate conductor layer is etched back so that its top surface is vertically positioned between the top surface of the second interconnect layer and the bottom surface of the third interconnect layer.

26. The method of claim 25, wherein, Forming the second transistor includes: A second gate dielectric layer is formed in a generally conformal manner above the first gate conductor layer within the opening; A second gate conductor layer is filled into the opening; The second gate conductor layer is etched back so that its top surface is near the top surface of the third interconnect layer in vertical height; Using the etched second gate conductor layer as a mask, the second gate dielectric layer and the first active layer are selectively etched.

27. The method according to claim 26, wherein, Before forming the second gate dielectric layer, the method further includes: Using the first gate conductor layer after back etching as a mask, the first gate dielectric layer is selectively etched.

28. The method according to claim 26, wherein, Forming the third transistor includes: A third active layer is formed in a generally conformal manner above the second transistor in the opening; A third gate dielectric layer is formed on the third active layer in a generally conformal manner; A third gate conductor layer is filled into the opening; A planarization process is performed so that the third active layer, the third gate dielectric layer, and the third active layer remain within the opening.

29. The method of claim 26, further comprising: An isolation section in the form of a sidewall is formed on the sidewall of the opening, and the isolation section shields the top of the first active layer.

30. The method of claim 28, further comprising: A connection is formed on the second transistor in the opening, and the connection is in physical contact with the second gate conductor layer.

31. The method according to claim 28 or 30, further comprising: A first gate length control layer is formed in the third isolation layer. The first gate length control layer includes a first gate length control pad disposed around the opening. The highest point of the top surface of the first gate conductor layer is higher than the bottom surface of the first gate length control pad, and the lowest point of the bottom surface of the second gate conductor layer is lower than the top surface of the first gate length control pad; and / or A second gate length control layer is formed in the fourth isolation layer. The second gate length control layer includes a second gate length control pad disposed around the opening. The lowest point of the bottom surface of the third gate conductor layer is lower than the top surface of the second gate length control pad.

32. The method according to claim 24, wherein, At least one of the following is true: Forming the second isolation layer includes depositing a dielectric material on the first isolation layer and the first interconnect layer, wherein the deposition thickness of the dielectric material is greater than half the spacing between the first conductive lines in the first interconnect layer, and it is not necessary to planarize the deposited dielectric material. Forming a third isolation layer includes depositing a dielectric material on the second isolation layer and the second interconnect layer, wherein the thickness of the dielectric material is greater than half the spacing between corresponding conductive lines in the second interconnect layer, and planarization of the deposited dielectric material is not required; or, forming a fourth isolation layer includes depositing a dielectric material on the third isolation layer and the third interconnect layer, wherein the thickness of the dielectric material is greater than half the spacing between corresponding conductive lines in the third interconnect layer, and planarization of the deposited dielectric material is not required. Forming the fifth isolation layer involves depositing a dielectric material on the fourth isolation layer and the fourth interconnect layer. The thickness of the deposited dielectric material is greater than half the spacing between the fourth conductive lines in the fourth interconnect layer, and planarization of the deposited dielectric material is not required.

33. An electronic device comprising a storage device according to any one of claims 1 to 23.

34. The electronic device according to claim 33, wherein, The electronic devices include smartphones, personal computers, artificial intelligence devices, wearable devices, or power banks.

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