Semiconductor structure and method of making the same, memory

Abstract

The embodiments of the present disclosure disclose a semiconductor structure, a manufacturing method thereof and a memory, comprising: a substrate, a plurality of first active pillars, a storage structure, a plurality of transistors and a plurality of second active pillars above the substrate; the plurality of first active pillars are arranged in an array along a first direction and a second direction; the first direction and the second direction are both perpendicular to the extension direction of the first active pillars, and the first direction and the second direction intersect; the substrate comprises an isolation structure, and the first active pillars are located on the isolation structure; the storage structure comprises a first electrode layer, a dielectric layer and a second electrode layer, the first electrode layer covers the sidewall of the first active pillar, the dielectric layer covers at least the surface of the first electrode layer, the second electrode layer covers the surface of the dielectric layer, and the bottom of the dielectric layer and the second electrode layer is embedded in the isolation structure; each second active pillar is located above a corresponding first active pillar; the channel structure of each transistor is located in the second active pillar, and the extension direction of the channel structure is the same as the extension direction of the second active pillar.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to a semiconductor structure and its fabrication method, and a memory. Background Technology

[0002] The memory array architecture of Dynamic Random Access Memory (DRAM) consists of an array of memory cells (i.e., 1T1C memory cells) each containing one transistor and one capacitor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.

[0003] As the size of dynamic random access memory (DRAM) continues to shrink, the size of capacitors also shrinks. Ensuring the performance of capacitors in DRAM has become a pressing issue.

[0004] Public content

[0005] In view of this, embodiments of the present disclosure provide a semiconductor structure, a method for fabricating the same, and a memory.

[0006] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:

[0007] A substrate, a plurality of first active pillars, a memory structure, a plurality of transistors, and a plurality of second active pillars located above the substrate; wherein,

[0008] The plurality of first active pillars are arranged in an array along a first direction and a second direction; both the first direction and the second direction are perpendicular to the extension direction of the first active pillars, and the first direction and the second direction intersect; the substrate includes an isolation structure, and the plurality of first active pillars are located on the isolation structure;

[0009] The storage structure includes a first electrode layer, a dielectric layer, and a second electrode layer. The first electrode layer covers the sidewall of the first active post. The dielectric layer covers at least the surface of the first electrode layer. The second electrode layer covers the surface of the dielectric layer. The bottoms of the dielectric layer and the second electrode layer are embedded in the isolation structure.

[0010] Each of the second active pillars is located above a corresponding first active pillar; the channel structure of each transistor is located within the second active pillar, and the extension direction of the channel structure is the same as the extension direction of the second active pillar.

[0011] In the above scheme, the isolation structure includes: a doped semiconductor layer, a second oxide layer, and a plurality of oxide pillars; the second oxide layer is located on the surface of the doped semiconductor layer, the plurality of oxide pillars are located on the doped semiconductor layer, and each of the first active pillars is located on the top surface of a corresponding oxide pillar; the doping type of the doped semiconductor layer is different from the doping type of the first active pillar.

[0012] In the above scheme, the dielectric layer also covers the sidewalls of the oxide pillars and the bottom of the gaps between adjacent oxide pillars; the second electrode layer extends into the gaps between the oxide pillars.

[0013] In the above scheme, the semiconductor structure further includes a plurality of connecting pillars, each of which is located between each of the first active pillars and each of the second active pillars, and the diameter of the connecting pillar is greater than the diameter of the first active pillar and the diameter of the second active pillar.

[0014] In the above scheme, the transistor includes: a gate oxide layer disposed around the second active pillar, a gate disposed around the gate oxide layer, and a source and a drain disposed at two opposite ends of the second active pillar, wherein the side of the gate away from the gate oxide layer is flush with the sidewall of the connecting pillar.

[0015] In the above scheme, the semiconductor structure further includes:

[0016] Multiple bit lines are located on the transistor and are electrically contacted at the top of the second active pillar.

[0017] According to another aspect of this disclosure, a memory is provided, comprising: at least one semiconductor structure as described in any of the above embodiments of this disclosure.

[0018] According to another aspect of this disclosure, a method for fabricating a semiconductor structure is provided, the method comprising:

[0019] A substrate is provided, an isolation structure is formed on the substrate, and a plurality of first active pillars are formed on the isolation structure in an array along a first direction and a second direction; the first direction and the second direction are both perpendicular to the extension direction of the first active pillars, and the first direction and the second direction intersect each other;

[0020] A storage structure is formed around the sidewall of the first active pillar. The storage structure includes a first electrode layer, a dielectric layer, and a second electrode layer. The first electrode layer covers the sidewall of the first active pillar. The dielectric layer covers at least the surface of the first electrode layer. The second electrode layer covers the surface of the dielectric layer. The bottoms of the dielectric layer and the second electrode layer are embedded in the isolation structure.

[0021] Multiple second active pillars are formed, each second active pillar being located above a corresponding first active pillar;

[0022] Multiple transistors are formed, wherein the channel structure of the transistors is located within the second active pillar, and the extension direction of the channel structure is the same as the extension direction of the second active pillar.

[0023] In the above scheme, forming an isolation structure on the substrate includes:

[0024] The bottom of the substrate is doped to form a doped semiconductor layer, and multiple first trenches spaced apart along a first direction and multiple second trenches spaced apart along a second direction are formed in the substrate; the bottoms of the first trenches and the second trenches are both located in the doped semiconductor layer.

[0025] The bottom of each of the first trenches and / or the second trenches is enlarged to form a plurality of first semiconductor pillars; each of the first semiconductor pillars includes a first portion and a second portion located on the first portion, wherein the maximum diameter of the first portion is smaller than the minimum diameter of the second portion;

[0026] The first semiconductor pillar is oxidized so that the first portion is completely oxidized into an oxide pillar, the surface of the exposed second portion is oxidized into a first oxide layer, and the surface of the doped semiconductor layer is oxidized into a second oxide layer; the unoxidized doped semiconductor layer, the oxide pillar, and the second oxide layer together constitute the isolation structure.

[0027] In the above scheme, the doping type of the doped semiconductor layer is different from the doping type of the first semiconductor pillar.

[0028] In the above scheme, the method further includes: forming a top support layer above the substrate, wherein forming the top support layer includes:

[0029] After the first trench is formed, the first insulating layer is filled into the first trench;

[0030] A portion of the first insulating layer is removed to form a first groove; the bottom surface of the first groove is lower than the top surface of the substrate.

[0031] A first support material layer is formed covering the first groove and the top of the substrate;

[0032] The first support material layer and the substrate are etched to form a plurality of second trenches spaced apart along a second direction in the substrate, and the second trenches are filled with a second insulating layer.

[0033] A portion of the second insulating layer is removed to form a plurality of second grooves arranged in an array along the first and second directions; the bottom surface of the second groove is flush with the bottom surface of the first groove.

[0034] The second groove is filled to form a second support material layer, and the first support material layer and the second support material layer form the top support layer.

[0035] In the above scheme, after forming the top support layer, it further includes:

[0036] The remaining first insulating layer and the remaining second insulating layer are removed to form a first filling region; the first filling region exposes a portion of the sidewall of the first semiconductor pillar to form the first oxide layer, the second oxide layer and the oxide pillar through the oxidation process;

[0037] After the oxidation process is completed, the first filling area is filled with sacrificial material, and part of the top support layer and part of the sacrificial material are removed to expose the top surface of the first semiconductor pillar.

[0038] In the above scheme, the storage structure is formed around the sidewall of the first active pillar, including:

[0039] Remove the top support layer to expose portions of the first and second grooves;

[0040] Remove the first oxide layer to form a second filled area;

[0041] A first conductive material is formed in the first groove, the second groove, and the second filling region, and the first conductive material located in the second filling region forms a first electrode layer; all the sacrificial material is removed to form a third filling region, a dielectric layer is formed in the third filling region, and a second conductive material is deposited on the surface of the dielectric layer to form a second electrode layer.

[0042] In the above scheme, multiple second active pillars are formed, including:

[0043] Remove the first conductive material and the second conductive material located around the top sidewall of the first semiconductor pillar;

[0044] A first semiconductor substrate is epitaxially grown on the top of the first semiconductor pillar;

[0045] Multiple third trenches are formed in the first semiconductor substrate at intervals along the first direction;

[0046] A third insulating layer is formed in the third trench;

[0047] A first mask layer is formed on the first semiconductor substrate; through the first mask layer, a plurality of fourth trenches are formed at intervals along a second direction; wherein the third trenches and the fourth trenches divide the first semiconductor substrate into a plurality of second semiconductor pillars;

[0048] A fourth insulating layer is formed in the fourth trench;

[0049] Remove a portion of the third insulating layer and a portion of the fourth insulating layer to expose a portion of the sidewall of the second semiconductor pillar;

[0050] The exposed sidewalls of the second semiconductor pillar are oxidized to form a third oxide layer.

[0051] The third oxide layer is removed, and the exposed second semiconductor pillar forms a second active pillar.

[0052] In the above scheme, forming multiple transistors includes:

[0053] A gate oxide layer is formed on a portion of the sidewall of the second active pillar;

[0054] A third conductive material is filled into the gap of the second active pillar where the gate oxide layer is formed;

[0055] By removing a portion of the third conductive material through the first mask layer, a gate is formed;

[0056] The source and drain are formed at opposite ends of the second active pillar, respectively.

[0057] The method in the above scheme further includes:

[0058] Multiple bit lines are formed on the second active post; the multiple bit lines are in electrical contact with the top of the second active post.

[0059] This disclosure provides a semiconductor structure and its fabrication method, as well as a memory. The semiconductor structure fabrication method includes: providing a substrate; forming an isolation structure on the substrate; forming a plurality of first active pillars arranged in an array along a first direction and a second direction on the isolation structure; the first direction and the second direction are both perpendicular to the extension direction of the first active pillars and intersect each other; forming a memory structure surrounding the sidewalls of the first active pillars, the memory structure including a first electrode layer, a dielectric layer, and a second electrode layer, the first electrode layer covering the sidewalls of the first active pillars, the dielectric layer at least covering the surface of the first electrode layer, the second electrode layer covering the surface of the dielectric layer, and the bottoms of the dielectric layer and the second electrode layer being embedded in the isolation structure; forming a plurality of second active pillars, each second active pillar located above a corresponding first active pillar; forming a plurality of transistors, the channel structure of the transistors located within the second active pillars, the extension direction of the channel structure being the same as the extension direction of the second active pillars. In this embodiment of the present disclosure, on the one hand, by forming an isolation structure on the substrate and embedding the bottom of the formed memory structure into the isolation structure, the leakage problem of the memory structure can be improved. On the other hand, by first forming a first active pillar and forming a memory structure around the first active pillar, then forming a second active pillar on the first active pillar and forming a transistor in the gap between the second active pillar, the problem of easy collapse caused by forming a tall active pillar at once can be improved. Attached Figure Description

[0060] Figure 1 This is a schematic diagram of the circuit connection of a DRAM transistor provided in an embodiment of this disclosure;

[0061] Figure 2 A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure;

[0062] Figures 3-33 This is a cross-sectional schematic diagram of the manufacturing process of a semiconductor structure provided in an embodiment of the present disclosure. Detailed Implementation

[0063] To make the technical solutions and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this disclosure are shown in the accompanying drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the implementation methods set forth herein. Rather, these implementation methods are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0064] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0065] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0066] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0067] In embodiments of this disclosure, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0068] In embodiments of this disclosure, the term "layer" refers to a portion of material including a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0069] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0070] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form the final device structure. Here, the final device may include a memory, including but not limited to dynamic random access memory (DRAM). The following description uses DRAM as an example only.

[0071] However, it should be noted that the following description of dynamic random access memory is only for illustrating this disclosure and is not intended to limit the scope of this disclosure.

[0072] With the development of dynamic random access memory technology, the size of memory cells is getting smaller and smaller, and their array architecture has increased from 8F. 2 Go to 6F 2 Then go to 4F 2 Furthermore, based on the requirements for ions and leakage current in dynamic random access memory, the memory architecture has evolved from planar array transistors to recessed gate array transistors, then from recessed gate array transistors to buried channel array transistors, and finally from buried channel array transistors to vertical channel array transistors.

[0073] In some embodiments of this disclosure, regardless of whether it is a planar transistor, a recessed gate array transistor, a buried transistor, or a vertical gate transistor, the dynamic random access memory is composed of multiple memory cell structures. Each memory cell structure mainly consists of a transistor and a memory cell (storage capacitor) controlled by the transistor. That is, the dynamic random access memory includes an architecture of 1 transistor (T) and 1 capacitor (C) (1T1C). Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0074] Figure 1 This is a circuit connection diagram of a 1T1C architecture provided in an embodiment of this disclosure; as shown... Figure 1 As shown, the drain of transistor T is electrically connected to the bit line (BL), and the source of transistor T is electrically connected to one of the electrode plates of capacitor C. The other electrode plate of capacitor C can be connected to a reference voltage, which can be ground or other voltages. The gate of transistor T is connected to the word line (WL). The transistor T is turned on or off by applying a voltage through the word line WL. The bit line BL is used to perform read or write operations on transistor T when it is turned on.

[0075] However, with the development of memory, the size of dynamic random access memory is constantly shrinking and the storage capacity of memory is constantly increasing, which makes the process of forming capacitors increasingly difficult and causes collapse problems. At the same time, capacitors also have leakage problems during use.

[0076] Based on this, in order to solve one or more of the above problems, this disclosure provides a method for manufacturing a semiconductor structure, which can improve the collapse problem and at the same time improve the leakage problem of capacitors during use. Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Figure 2 As shown, the method for fabricating a semiconductor structure provided in this embodiment includes the following steps:

[0077] S100: Provide a substrate, form an isolation structure on the substrate, and form a plurality of first active pillars arranged in an array along a first direction and a second direction on the isolation structure; the first direction and the second direction are both perpendicular to the extension direction of the first active pillars, and the first direction and the second direction intersect each other;

[0078] S200: Form a storage structure around the sidewall of the first active pillar, the storage structure including a first electrode layer, a dielectric layer and a second electrode layer, the first electrode layer covering the sidewall of the first active pillar, the dielectric layer at least covering the surface of the first electrode layer, the second electrode layer covering the surface of the dielectric layer, and the bottoms of the dielectric layer and the second electrode layer are embedded in the isolation structure;

[0079] S300: Form a plurality of second active pillars, each of the second active pillars being located above a corresponding first active pillar;

[0080] S400: A plurality of transistors are formed, wherein the channel structure of the transistors is located within the second active pillar, and the extension direction of the channel structure is the same as the extension direction of the second active pillar.

[0081] It should be understood that Figure 2 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 2 The steps shown can be adjusted in order according to actual needs. Figures 3 to 33 This is a cross-sectional schematic diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of this disclosure. It should be noted that... Figures 3 to 33 This is a schematic diagram illustrating the complete manufacturing process of a semiconductor structure. Unmarked parts in some of the accompanying drawings can be shared. The following section combines... Figure 2 , Figures 3 to 33The method for fabricating the semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0082] In step S100, the main task is to form an isolation structure and a first active pillar on the substrate.

[0083] In some embodiments, forming an isolation structure on the substrate includes:

[0084] The bottom of the substrate is doped to form a doped semiconductor layer, and multiple first trenches spaced apart along a first direction and multiple second trenches spaced apart along a second direction are formed in the substrate; the bottoms of the first trenches and the second trenches are both located in the doped semiconductor layer.

[0085] The bottom of each of the first trenches and / or the second trenches is enlarged to form a plurality of first semiconductor pillars; each of the first semiconductor pillars includes a first portion and a second portion located on the first portion, wherein the maximum diameter of the first portion is smaller than the minimum diameter of the second portion;

[0086] The first semiconductor pillar is oxidized so that the first portion is completely oxidized into an oxide pillar, the surface of the exposed second portion is oxidized into a first oxide layer, and the surface of the doped semiconductor layer is oxidized into a second oxide layer; the unoxidized doped semiconductor layer, the oxide pillar, and the second oxide layer together constitute the isolation structure.

[0087] In some embodiments, the doping type of the doped semiconductor layer is different from the doping type of the first semiconductor pillar.

[0088] In some embodiments, the method further includes: forming a top support layer over the substrate, wherein forming the top support layer includes:

[0089] After the first trench is formed, the first insulating layer is filled into the first trench;

[0090] A portion of the first insulating layer is removed to form a first groove; the bottom surface of the first groove is lower than the top surface of the substrate.

[0091] A first support material layer is formed covering the first groove and the top of the substrate;

[0092] The first support material layer and the substrate are etched to form a plurality of second trenches spaced apart along a second direction in the substrate, and the second trenches are filled with a second insulating layer.

[0093] A portion of the second insulating layer is removed to form a plurality of second grooves arranged in an array along the first and second directions; the bottom surface of the second groove is flush with the bottom surface of the first groove.

[0094] The second groove is filled to form a second support material layer, and the first support material layer and the second support material layer form the top support layer.

[0095] The following is combined Figures 3-15 The formation process of the isolation structure and the first active column is described in detail.

[0096] like Figure 3 As shown, a doped semiconductor layer 103 is formed by doping the bottom of the substrate 101.

[0097] In some specific examples, the substrate 101 may include a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon (SiGe) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate.

[0098] In some specific examples, the method further includes: doping a portion of the substrate 101 other than the bottom, wherein the doping type of the bottom of the substrate 101 is different from the doping type of the portion of the substrate 101 other than the bottom.

[0099] For example, when the doping type of the bottom of the substrate 101 is N-type, the doping type of the portion outside the bottom of the substrate 101 is P-type; when the doping type of the bottom of the substrate 101 is P-type, the doping type of the portion outside the bottom of the substrate 101 is N-type.

[0100] For example, when the doping type is P-type doping, the P-type impurity source can be boron (B), aluminum (Al), etc., and the P-type impurity source is not limited to these; when the doping type is N-type doping, the N-type impurity source can be phosphorus (P), arsenic (As), etc., and the N-type impurity source is not limited to these.

[0101] In some specific examples, the methods for doping the portion of the substrate 101 other than the bottom and for doping the bottom of the substrate 101 include, but are not limited to, ion implantation and diffusion.

[0102] In some specific examples, the doping concentration at the bottom of the substrate 101 is less than the doping concentration of the portion of the substrate 101 excluding the bottom.

[0103] Understandably, the doping treatment of the bottom of the substrate 101 here makes the formed doped semiconductor layer 103 constitute a depletion region, thereby improving the leakage problem of the memory structure 106 formed in subsequent processes.

[0104] Next, as Figure 4As shown, the surface of the substrate 101 is etched to form a plurality of first trenches 108 spaced apart along a first direction in the substrate 101. The bottom of the first trenches 108 is located in the doped semiconductor layer 103. Here, each of the first trenches 108 extends along a second direction.

[0105] Here, the first direction is parallel to the surface of the substrate 101; the second direction intersects the first direction and is parallel to the surface of the substrate 101. The third direction is the extension direction of the first semiconductor pillar 105, and the third direction is perpendicular to the surface of the substrate 101.

[0106] Here, the first direction intersects with the second direction, which can be understood as the angle between the first direction and the second direction being 0-90 degrees.

[0107] To clearly describe this disclosure, the following embodiments are illustrated using the example of a first direction being perpendicular to a second direction. For example, the first direction is... Figure 3 The X-axis direction shown in the figure; the second direction is Figure 3 The Y-axis direction is shown in the figure; the third direction is Figure 3 The Z-axis direction is shown in the figure. However, it should be noted that the description of the direction in the following embodiments is for illustrative purposes only and is not intended to limit the scope of this disclosure.

[0108] In some specific examples, the first trench 108 includes, but is not limited to, a shallow trench isolation (STI) structure.

[0109] In some specific examples, the method for forming the first trench 108 includes, but is not limited to, dry plasma etching processes.

[0110] like Figure 5 As shown, a first insulating layer 110 is formed in the first trench 108; wherein, the top surface of the first insulating layer 110 is substantially flush with the top surface of the substrate 101; here, the first insulating layer 110 serves as a support.

[0111] It should be noted that the term "basic flush" in this disclosure can be understood as "approximately flush"; it is also understood that misalignment or non-flushness caused by process errors during the manufacturing process of memory is also included within the scope of "basic flush".

[0112] In some specific examples, the constituent materials of the first insulating layer 110 include, but are not limited to, silicon oxide (SiO2).

[0113] In some specific examples, the methods for forming the first insulating layer 110 include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and other processes.

[0114] like Figure 6 As shown, a portion of the first insulating layer 110 is removed to form a first groove 112; the bottom surface of the first groove 112 is lower than the top surface of the substrate 101, that is, the first groove 112 is formed in the substrate 101.

[0115] In some specific examples, the projection of the first groove 112 and the first trench 108 onto a first plane. Here, the first plane is a plane perpendicular to a third direction.

[0116] In some specific examples, the methods for removing part of the first insulating layer 110 include, but are not limited to, dry etching process and wet etching process.

[0117] like Figure 7 As shown, the material of the first support material layer 114 is filled in the first groove 112 and on the substrate 101 to form a first support material layer 114 covering the first groove 112 and the top of the substrate 101.

[0118] In some specific examples, the constituent materials of the first support material layer 114 include, but are not limited to, silicon nitride.

[0119] In some specific examples, the methods for forming the first support material layer 114 include, but are not limited to, PVD, CVD, and ALD.

[0120] In some specific examples, after filling the first support material layer 114 with material, the first support material layer 114 is further planarized to make the surface of the first support material layer 114 flat.

[0121] In some specific examples, the planarization process includes, but is not limited to, chemical mechanical polishing (CMP).

[0122] It is understandable that a first support material layer 114 is also formed on the top surface of the substrate 101 to protect the top surface of the substrate 101 and prevent the top of the substrate 101 from being consumed in subsequent processes.

[0123] like Figure 8As shown, the first support material layer 114 and the substrate 101 are etched to form a plurality of second trenches 109 spaced apart along a second direction in the substrate 101; the bottom of the second trenches 109 is located in the doped semiconductor layer 103. The plurality of second trenches 109 are spaced apart along the second direction, and each second trench 109 extends along a first direction; that is, the first trench 108 and the second trench 109 intersect.

[0124] In some specific examples, when the first direction is perpendicular to the second direction, the first groove 108 and the second groove 109 are perpendicular to each other.

[0125] In some specific examples, a plurality of first grooves 108 are spaced apart along the X-axis direction; and each first groove 108 extends along the Y-axis direction; a plurality of second grooves 109 are spaced apart along the Y-axis direction; and each second groove 109 extends along the X-axis direction.

[0126] In some specific examples, the methods for forming the second trench 109 include, but are not limited to, dry plasma etching processes.

[0127] In some specific examples, the second trench 109 includes, but is not limited to, shallow trench isolation (STI) structures.

[0128] Here, the first trench 108 and the second trench 109 divide the substrate 101 into a plurality of first semiconductor pillars 105 arranged in an array along the first direction and the second direction.

[0129] Next, as Figure 8 As shown, the bottom of each of the first trench 108 and / or the second trench 109 is enlarged; here, the enlargement process can be understood as etching the bottom of the first trench 108 along a first direction; and / or etching the bottom of the second trench 109 along a second direction, such that the diameter of the bottom of the first trench 108 and / or the second trench 109 along the first direction is greater than the diameter of the top of the corresponding trench along the first direction.

[0130] And / or,

[0131] The bottom diameter of the first groove 108 and / or the second groove 109 along the second direction is greater than the top diameter of the corresponding groove along the second direction.

[0132] In some specific examples, the etching process used may include wet etching, dry etching, etc.

[0133] For example, in the wet etching process, an etchant is introduced into the bottom of the first trench 108 and / or the second trench 109, and the diameter of the bottom of the first trench 108 and / or the second trench 109 along the X-axis is increased by the anisotropic etching of the etchant; and / or, the diameter of the bottom of the first trench 108 and / or the second trench 109 along the Y-axis is increased.

[0134] For example, in the dry etching process, lateral etching is performed by controlling plasma to form a trench structure with an enlarged diameter at the bottom of the first trench 108 and / or the second trench 109.

[0135] In this embodiment of the disclosure, after the process of enlarging the bottom of each of the first trench 108 and / or the second trench 109, the etching process causes the bottom regions of the plurality of first semiconductor pillars 105 located on the substrate 101 to be etched, thereby reducing the size of the bottom regions of the first semiconductor pillars 105.

[0136] In other words, the first semiconductor pillar 105 includes a first portion 105-1 and a second portion 105-2 located on the first portion 105-1; here, the second portion 105-2 of the first semiconductor pillar 105 is located on the first portion 105-1 of the first semiconductor pillar 105.

[0137] For example, when only the first trench 108 is enlarged, the maximum diameter of the first portion 105-1 of the first semiconductor pillar 105 along the X-axis is smaller than the minimum diameter of the second portion 105-2 of the first semiconductor pillar 105 along the X-axis.

[0138] For example, when only the second trench 109 is enlarged, the maximum diameter of the first portion 105-1 of the first semiconductor pillar 105 along the Y-axis is smaller than the minimum diameter of the second portion 105-2 of the first semiconductor pillar 105 along the Y-axis.

[0139] For example, when both the first trench 108 and the second trench 109 are enlarged, the maximum diameter of the first portion 105-1 of the first semiconductor pillar 105 along the X-axis is smaller than the minimum diameter of the second portion 105-2 of the first semiconductor pillar 105 along the X-axis; and the maximum diameter of the first portion 105-1 of the first semiconductor pillar 105 along the Y-axis is smaller than the minimum diameter of the second portion 105-2 of the first semiconductor pillar 105 along the Y-axis.

[0140] Preferably, both the first trench 108 and the second trench 109 are enlarged to reduce the size of the first portion 105-1 of the first semiconductor pillar 105.

[0141] For example, the maximum diameter of the first part 105-1 can be understood as Figure 8 The diameter at the contact point between the first portion 105-1 and the second portion 105-2 of the first semiconductor pillar 105; the minimum diameter of the second portion 105-2 can be understood as the smallest region within the second portion 105-2 of the first semiconductor pillar 105; Reference Figure 8 The upper and lower portions of the second part 105-2 of the first semiconductor pillar 105 have the same dimensions, that is, the minimum diameter and the maximum diameter of the second part 105-2 of the first semiconductor pillar 105 are the same.

[0142] Next, as Figure 9 As shown, a second insulating layer 111 is formed in the second trench 109. The second insulating layer 111 serves a supporting function.

[0143] In some specific examples, the constituent materials of the second insulating layer 111 include, but are not limited to, silicon oxide (SiO2).

[0144] In some specific examples, the methods for forming the second insulating layer 111 include, but are not limited to, PVD, CVD, and ALD.

[0145] Next, as Figure 10 As shown, a portion of the second insulating layer 111 is removed to form a plurality of second grooves 113 arranged in an array along the first and second directions; the bottom surface of the second groove 113 is flush with the bottom surface of the first groove 112.

[0146] In some specific examples, the methods for removing part of the second insulating layer 111 include, but are not limited to, dry etching process and wet etching process.

[0147] Next, as Figure 11 As shown, the second groove 113 is filled to form a second support material layer 115 (specifically, it can be as follows). Figure 11 The portion shown in the dashed box in the middle), the first support material layer 114 and the second support material layer 115 form the top support layer 119 (as shown in the dashed box in the middle). Figure 15 (As shown in the image).

[0148] Here, the materials of the first support material layer 114 and the second support material layer 115 may be the same or different.

[0149] In some specific examples, the methods for forming the second support material layer 115 include, but are not limited to, PVD, CVD, and ALD.

[0150] In some specific examples, after filling the second support material layer 115 with material, the second support material layer 115 is further planarized so that the second support material layer 115 is flush with the top surface of the second insulating layer 111.

[0151] In some specific examples, the planarization process includes CMP.

[0152] Understandably, the top support layer 119 formed here can support the first semiconductor pillar 105 and improve the problem of the first semiconductor pillar 105 being prone to collapse in subsequent processes.

[0153] In some embodiments, after forming the top support layer, the method further includes:

[0154] The remaining first insulating layer and the remaining second insulating layer are removed to form a first filling region; the first filling region exposes a portion of the sidewall of the first semiconductor pillar to form the first oxide layer, the second oxide layer and the oxide pillar through the oxidation process;

[0155] After the oxidation process is completed, the first filling area is filled with sacrificial material, and part of the top support layer and part of the sacrificial material are removed to expose the top surface of the first semiconductor pillar.

[0156] like Figure 12 As shown, the remaining first insulating layer 110 and the remaining second insulating layer 111 are removed to form a first filling region 120. The first filling region 120 exposes a portion of the sidewalls of the first semiconductor pillar 105.

[0157] In some specific examples, the methods for removing the remaining first insulating layer 110 and the remaining second insulating layer 111 include, but are not limited to, dry etching processes and wet etching processes.

[0158] Next, as Figure 13 As shown, the exposed surface of the first semiconductor pillar 105 is oxidized through an oxidation process, such as thermal oxidation, so that the entire first portion 105-1 of the first semiconductor pillar 105 is oxidized into an oxide pillar 116, and the surface of the exposed second portion 105-2 of the first semiconductor pillar 105 is oxidized into a first oxide layer 117. Simultaneously, the surface of the substrate 101 is also oxidized to form a second oxide layer 118. The doped semiconductor layer 103, the oxide pillar 116, and the second oxide layer 118 together constitute the isolation structure 102. The top of the first semiconductor pillar 105 is covered by a first support material layer 114 and a second support material layer 115, therefore the top of the first semiconductor pillar 105 is not oxidized. The portion of the first semiconductor pillar 105 covered by the first oxide layer 117 constitutes the first active pillar 104.

[0159] Understandably, the oxide pillars 116 and the second oxide layer 118 formed here enable the capacitors formed in subsequent processes to be isolated from the bottom doped semiconductor layer 103, thereby further improving the leakage problem at the bottom of the capacitor.

[0160] Here, the first oxide layer 117, the second oxide layer 118, and the oxide pillar 116 are made of the same material. For example, the constituent materials of the first oxide layer 117, the second oxide layer 118, and the oxide pillar 116 include, but are not limited to, silicon oxide.

[0161] In some specific examples, the materials of the first oxide layer 117, the second oxide layer 118, and the oxide pillar 116 may be the same as or different from the material of the first insulating layer 110. The materials of the first oxide layer 117, the second oxide layer 118, and the oxide pillar 116 may be the same as or different from the material of the second insulating layer 111.

[0162] It should be noted that, in the foregoing embodiments, after enlarging the first trench 108 and / or the second trench 109, the first portion 105-1 of the first semiconductor pillar 105 is smaller in size and easier to be completely oxidized. Moreover, when the first portion 105-1 of the first semiconductor pillar 105 is oxidized, only the surface of the second portion 105-2 of the first semiconductor pillar 105 is oxidized.

[0163] Next, as Figure 14 As shown, the first filling area 120 is filled with sacrificial material 121.

[0164] In some specific examples, the methods for filling the sacrificial material 121 include, but are not limited to, PVD, CVD, and ALD.

[0165] In some specific examples, the material of the sacrificial material 121 formed includes, but is not limited to, polycrystalline silicon and carbon.

[0166] Regarding the selection of the material of the sacrificial material 121, firstly, it is necessary to consider that the sacrificial material 121 has a certain etching selectivity relative to the first oxide layer 117, so that the sacrificial material 121 can be retained when the first oxide layer 117 is removed in the subsequent process; secondly, it is necessary to consider that the sacrificial material 121 has a certain etching selectivity relative to the material of the first electrode layer 106-1 formed in the subsequent process, so that the impact on the already formed first electrode layer 106-1 is reduced when the sacrificial material 121 is removed to form the sacrificial layer in the subsequent process; thirdly, the sacrificial material 121 needs to be easy to remove in the subsequent process.

[0167] Next, as Figure 15 As shown, a portion of the top support layer 119 and a portion of the sacrificial material 121 are removed, exposing the top surface of the first semiconductor pillar 105.

[0168] In some specific examples, methods for removing portions of the top support layer 119 and the sacrificial material 121 include, but are not limited to, CMP.

[0169] from Figure 15 As can be seen, both the first support material layer 114 and the second support material layer 115 cover a portion of the sidewalls of the first semiconductor pillar 105, and the second support material layer 115 covers a portion of the sidewalls perpendicular to the second direction at the top of the first semiconductor pillar 105, while the first support layer covers all the sidewalls perpendicular to the first direction at the top of the first semiconductor pillar 105. Furthermore, the top support layer 119, composed of the first support material layer 114 and the second support material layer 115, forms a mesh structure that supports the first semiconductor pillar 105, mitigating the problem of the first semiconductor pillar 105 being prone to collapse.

[0170] In step S200, the main task is to form a storage structure 106 surrounding the sidewall of the first active pillar 104.

[0171] In some embodiments, the storage structure is formed around the sidewall of the first active pillar, including:

[0172] Remove the top support layer to expose portions of the first and second grooves;

[0173] Remove the first oxide layer to form a second filled area;

[0174] A first conductive material is formed in the first groove, the second groove, and the second filling region, and the first conductive material located in the second filling region forms a first electrode layer; all the sacrificial material is removed to form a third filling region, a dielectric layer is formed in the third filling region, and a second conductive material is deposited on the surface of the dielectric layer to form a second electrode layer.

[0175] like Figure 15 , 16 As shown, the top support layer 119 is removed, exposing portions of the first groove 112 and the second groove 113.

[0176] In some specific examples, the methods for removing the top support layer 119 include, but are not limited to, dry etching and wet etching processes.

[0177] After the top support layer 119 is removed, since the sacrificial material 121 covers part of the top sidewall of the first semiconductor pillar 105, the sacrificial material 121 between the tops of the first semiconductor pillar 105 can support the first semiconductor pillar 105 when the first oxide layer 117 is removed in the subsequent process, thereby improving the collapse problem of the first semiconductor pillar 105.

[0178] like Figure 16 ,17 As shown, the first oxide layer 117 is removed to form the second filling region 122.

[0179] In some specific examples, the methods for removing the first oxide layer 117 include, but are not limited to, dry etching and wet etching processes.

[0180] like Figure 18 As shown, a first conductive material is formed in the first groove 112, the second groove 113, and the second filling area 122, and the first conductive material located in the second filling area 122 forms a first electrode layer 106-1.

[0181] It is understandable that the first conductive material filled in the first groove 112 and the second groove 113 is connected to the top sidewall of the first semiconductor pillar 105, so that the first conductive material filled in the first groove 112 and the second groove 113 supports the first semiconductor pillar 105, thereby improving the problem that the first semiconductor pillar 105 is prone to collapse when all the sacrificial material 121 is removed in the subsequent process.

[0182] Here, the first electrode layer 106-1 is used as the lower electrode of the capacitor.

[0183] In some specific examples, the constituent materials of the first electrode layer 106-1 may include, but are not limited to, ruthenium (Ru), ruthenium oxide (RuO), and titanium nitride (TiN).

[0184] In some specific examples, the methods for forming the first electrode layer 106-1 include, but are not limited to, PVD, CVD, and ALD.

[0185] It is understood that in this embodiment, after removing the first oxide layer 117, a second filling region 122 is formed. This second filling region 122 surrounds the first active pillar 104. The material used to form the first electrode layer 106-1 is directly filled into the second filling region 122, thereby forming the first electrode layer 106-1. The multiple first electrode layers 106-1 formed are separated from each other. A conventional method involves directly depositing the material of the first electrode layer 106-1 in the first trench 108 and second trench 109 in the gap of the first semiconductor pillar 105 to form multiple first electrode layers 106-1. This makes it impossible for the bottoms of the multiple first electrode layers 106-1 to be separated from each other, resulting in mutual interference between the first electrode layers 106-1. However, the solution in this embodiment allows the first electrode layers 106-1 to be separated from each other, thereby improving the problem of mutual interference between the multiple first electrode layers 106-1.

[0186] Next, as Figure 19 As shown, all of the sacrificial material 121 is removed to form a third filling area 123.

[0187] In some specific examples, the methods for removing the sacrificial material 121 include, but are not limited to, wet etching and dry etching processes.

[0188] Next, as Figure 20 As shown, a dielectric layer 106-2 is formed in the third filling region 123, and a second conductive material is deposited on the surface of the dielectric layer 106-2 to form a second electrode layer 106-3. The dielectric layer 106-2 and the second electrode layer 106-3 formed here are embedded in the isolation structure 102. The dielectric layer 106-2, the first electrode layer 106-1, and the second electrode layer 106-2 together constitute the storage structure 106.

[0189] It should be noted that, Figure 20 The diagram only shows the case where a dielectric layer 106-2 is formed in the gap between the first active pillars 104. In some specific examples, when a dielectric layer 106-2 is formed between the first active pillars 104, a dielectric layer 106-2 is also formed in the gap at the top of the first semiconductor pillar 105.

[0190] Here, dielectric layer 106-2 is used as the dielectric of the capacitor.

[0191] Here, the constituent materials of the dielectric layer 106-2 include high-dielectric-constant (High-K) materials. High-dielectric-constant materials generally refer to materials with a dielectric constant higher than 3.9, and are usually significantly higher than this value. In some specific examples, the materials of the dielectric layer 106-2 may include, but are not limited to, alumina (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), strontium titanate (SrTiO3), etc.

[0192] In some specific embodiments, the constituent materials of the second electrode layer 106-3 may include, but are not limited to, ruthenium, ruthenium oxide, and titanium nitride.

[0193] Here, the methods for forming the second electrode layer 106-3 include, but are not limited to, processes such as PVD and CVD.

[0194] Understandably, the dielectric layer 106-2 and the second electrode layer 106-3 are embedded in the isolation structure 102 to improve the leakage current problem of the capacitor.

[0195] In step S300, as Figures 21 to 29 The main purpose is to form multiple second active columns 107.

[0196] In some embodiments, forming a plurality of the second active pillars includes:

[0197] Remove the first conductive material and the second conductive material located around the top sidewall of the first active column;

[0198] A first semiconductor substrate is epitaxially grown on the top of the first semiconductor pillar;

[0199] Multiple third trenches are formed in the first semiconductor substrate at intervals along the first direction;

[0200] A third insulating layer is formed in the third trench;

[0201] A first mask layer is formed on the first semiconductor substrate; through the first mask layer, a plurality of fourth trenches are formed at intervals along a second direction; wherein the third trenches and the fourth trenches divide the first semiconductor substrate into a plurality of second semiconductor pillars;

[0202] A fourth insulating layer is formed in the fourth trench;

[0203] Remove a portion of the third insulating layer and a portion of the fourth insulating layer to expose a portion of the sidewall of the second semiconductor pillar;

[0204] The exposed sidewalls of the second semiconductor pillar are oxidized to form a third oxide layer.

[0205] The third oxide layer is removed, and the exposed second semiconductor pillar forms a second active pillar.

[0206] The following is combined Figures 21-29 The formation process of the second active column is described in detail. For example... Figure 21 As shown, the first conductive material, the second conductive material, and the dielectric layer 106-2 located around the top sidewall of the first semiconductor pillar 105 are removed.

[0207] In some specific examples, the methods for removing the first conductive material, the second conductive material, and the dielectric layer 106-2 located around the top sidewall of the first semiconductor pillar 105 include, but are not limited to, dry etching processes and wet etching processes.

[0208] Next, as Figure 22 As shown, a first semiconductor substrate 124 is formed on the top of the first semiconductor pillar 105 by epitaxial growth.

[0209] In some specific examples, the methods for forming the first semiconductor substrate 124 include, but are not limited to, epitaxial growth processes.

[0210] It is understood that the purpose of removing the first conductive material, the second conductive material, and the dielectric layer 106-2 around the top sidewall of the first semiconductor pillar 105 in the above embodiment, and exposing part of the top sidewall of the first semiconductor pillar 105, is mainly to make it easier to form the first semiconductor substrate 124 by epitaxial growth.

[0211] In some specific examples, the material of the first semiconductor substrate 124 may include elemental semiconductor materials (e.g., silicon, germanium, etc.), composite semiconductor materials (e.g., germanium-silicon, etc.), etc.

[0212] Next, as Figure 23 As shown, a plurality of third trenches 125 are formed in the first semiconductor substrate 124 at intervals along the first direction.

[0213] In some specific examples, the methods for forming the third groove include, but are not limited to, dry etching and wet etching processes.

[0214] Next, as Figure 24 As shown, a third insulating layer 128 is formed in the third trench 125.

[0215] In some specific examples, the material of the third insulating layer 128 includes, but is not limited to, silicon oxide.

[0216] In some specific examples, the methods for forming the third insulating layer 128 include, but are not limited to, PVD, CVD, and ALD.

[0217] Next, as Figure 25 As shown, a first mask layer 130 is formed on a first semiconductor substrate 124; through the first mask layer 130, a plurality of fourth trenches 126 are formed at intervals along a second direction; wherein, the third trenches 125 and the fourth trenches 126 divide the first semiconductor substrate 124 into a plurality of second semiconductor pillars 127. Here, the formed second semiconductor pillars 127 coincide with the projection of the first semiconductor pillars 105 onto the first plane.

[0218] In some specific examples, the material of the first mask layer 130 includes, but is not limited to, silicon nitride.

[0219] In some specific examples, the methods for forming the first mask layer 130 include, but are not limited to, PVD, CVD, and ALD.

[0220] Next, as Figure 26 As shown, a fourth insulating layer 129 is formed in the fourth trench 126.

[0221] In some specific examples, the material of the fourth insulating layer 129 includes, but is not limited to, silicon oxide.

[0222] In some specific examples, the methods for forming the fourth insulating layer 129 include, but are not limited to, PVD, CVD, and ALD.

[0223] Next, as Figure 27 As shown, a portion of the third insulating layer 128 and a portion of the fourth insulating layer 129 are removed, exposing a portion of the sidewall of the second semiconductor pillar 127.

[0224] In some specific examples, the methods for removing portions of the third insulating layer 128 and the fourth insulating layer 129 include, but are not limited to, dry etching processes and wet etching processes.

[0225] Next, as Figure 28 As shown, the exposed sidewalls of the second semiconductor pillar 127 are oxidized to form a third oxide layer 131.

[0226] In some specific examples, the material of the third oxide layer 131 includes, but is not limited to, silicon oxide.

[0227] Next, as Figure 29 As shown, after removing the third oxide layer 131, the exposed portion of the second semiconductor pillar 127 forms a second active pillar 107. The portion of the semiconductor pillar between the first active pillar 104 and the second active pillar 107 constitutes a connecting pillar 136. The diameter of the connecting pillar 136 is greater than the diameters of both the first active pillar 104 and the second active pillar 107.

[0228] In step S400, the main task is to form multiple transistors.

[0229] In some embodiments, forming a plurality of transistors includes:

[0230] A gate oxide layer is formed on a portion of the sidewall of the second active pillar;

[0231] A third conductive material is filled into the gap of the second active pillar where the gate oxide layer is formed;

[0232] By removing a portion of the third conductive material through the first mask layer, a gate is formed;

[0233] The source and drain are formed at opposite ends of the second active pillar, respectively.

[0234] The following is combined Figures 30-33 The process of transistor formation is explained in detail.

[0235] like Figure 30 As shown, a gate oxide layer 132 is formed on a portion of the sidewall of the second active pillar 107.

[0236] Here, the gate oxide layer is located between the gate 133 and the channel region to electrically isolate the channel region and the gate 133, thereby reducing the hot carrier effect of the transistor.

[0237] In some specific examples, the methods for forming the gate oxide layer 132 include, but are not limited to, thermal oxidation.

[0238] In some specific examples, the gate oxide layer 132 includes, but is not limited to, silicon oxide.

[0239] Next, as Figure 31 As shown, a third conductive material is filled into the gaps of the second active pillar 107 where the gate oxide layer 132 is formed. A portion of the third conductive material is removed through the first mask layer 130 to form the gate 133.

[0240] It is understood that in the aforementioned embodiment, after the fourth trench 126 is formed by the first mask layer 130, the first mask layer 130 is not removed. When removing part of the third conductive material, the first mask layer 130 is still used as a mask, which can simplify the process steps, save process time, and save process materials.

[0241] In some specific examples, the third conductive material may include metals or polycrystalline silicon, etc.

[0242] In some specific examples, the methods for forming the third conductive material include, but are not limited to, PVD, CVD, ALD, etc.

[0243] Here, the shape of the gate 133 varies in different types of transistors; for example, in a pillar gate transistor, the gate 133 is formed in a pillar shape on one side of the channel region; in a semi-around gate transistor, the gate 133 partially surrounds the channel region; in a gate all around (GAA) gate transistor, the gate 133 completely surrounds the channel region.

[0244] The transistor types in this disclosure may include, but are not limited to, the types described above. Preferably, the transistor type is a full-around gate transistor.

[0245] Next, source and drain electrodes are formed at opposite ends of the second active pillar 107. Methods for forming the source and drain electrodes include, but are not limited to, doping and diffusion processes.

[0246] It should be noted that the positions of the source and drain at opposite ends of the second active post 107 can be interchanged; in practice, the selection and setting can be made according to actual needs.

[0247] Next, as Figure 32 As shown, a fifth insulating layer 134 is formed between the second active pillars 107 (e.g. Figure 32 (The part shown in the dashed box).

[0248] In some specific examples, the material of the fifth insulating layer 134 includes, but is not limited to, silicon oxide.

[0249] Next, as Figure 33As shown, the first mask layer 130 is removed, and a portion of the gate 133 is removed. A sixth insulating layer 135 is then filled between the second active pillars 107 (as shown). Figure 33 (The part shown in the dashed box).

[0250] In some specific examples, the material of the sixth insulating layer 135 includes, but is not limited to, silicon oxide.

[0251] In some embodiments, the method further includes:

[0252] Multiple bit lines are formed on the second active post 107; the multiple bit lines are in electrical contact with the top of the second active post 107.

[0253] It is understood that the memory in the above embodiment is a transistor-capacitor (TOC) structure, which further includes multiple bit lines located on the transistor and electrically contacting the top of the second active pillar 107.

[0254] It is understood that the bit line BL is used to perform read or write operations on the transistor when the transistor is turned on.

[0255] Here, placing the bit line BL above the transistor and treating the bit line BL as a metal bit line can reduce resistance and simplify the manufacturing process; it is also more compatible with the circuit design of the memory.

[0256] Understandably, with the increasing demands for memory density, the aspect ratio of semiconductor pillars is constantly increasing. When forming tall semiconductor pillars to create the memory structure 106 and transistors in one go, collapse is likely to occur. In this embodiment, the first semiconductor pillar 105 is formed first, the memory structure 106 is formed between the first semiconductor pillars 105, and then the second semiconductor pillar 127 is formed on the first semiconductor pillar 105, and the transistor is formed between the second semiconductor pillars 127. That is to say, the semiconductor pillars in this embodiment are formed in two stages, and a top support layer 119 is formed on the top of the first semiconductor pillar 105, which can effectively improve the collapse problem.

[0257] This disclosure provides a method for fabricating a semiconductor structure, including: providing a substrate 101; forming an isolation structure 102 on the substrate 101; forming a plurality of first active pillars 104 arranged in an array along a first direction and a second direction on the isolation structure 102; the first direction and the second direction are both perpendicular to the extension direction of the first active pillars 104, and the first direction and the second direction intersect; forming a memory structure 106 surrounding the sidewalls of the first active pillars 104, the memory structure 106 including a first electrode layer 106-1, a dielectric layer 106-2, and a second electrode layer 106-3, wherein the first electrode layer 106-1... The dielectric layer 106-2 covers at least the surface of the first electrode layer 106-1, and the second electrode layer 106-3 covers the surface of the dielectric layer 106-2. The bottoms of the dielectric layer 106-2 and the second electrode layer 106-3 are embedded in the isolation structure 102. A plurality of second active pillars 107 are formed, each second active pillar 107 being located above a corresponding first active pillar 104. A plurality of transistors are formed, the channel structure of the transistors being located within the second active pillars 107, and the extension direction of the channel structure being the same as the extension direction of the second active pillars 107. In this embodiment of the present disclosure, on the one hand, by forming an isolation structure 102 on the substrate 101 and embedding the bottom of the formed memory structure 106 into the isolation structure 102, the leakage problem of the memory structure 106 can be improved. On the other hand, by first forming a first active pillar 104 and forming a memory structure 106 around the first active pillar 104, and then forming a second active pillar 107 on the first active pillar 104 and forming transistors in the gaps of the second active pillar 107, the problem of easy collapse caused by forming a tall active pillar at once can be improved.

[0258] According to another aspect of this disclosure, embodiments of this disclosure further provide a semiconductor structure, including:

[0259] A substrate, a plurality of first active pillars, a memory structure, a plurality of transistors, and a plurality of second active pillars located above the substrate; wherein,

[0260] The plurality of first active pillars are arranged in an array along a first direction and a second direction; both the first direction and the second direction are perpendicular to the extension direction of the first active pillars, and the first direction and the second direction intersect; the substrate includes an isolation structure, and the plurality of first active pillars are located on the isolation structure;

[0261] The storage structure includes a first electrode layer, a dielectric layer, and a second electrode layer. The first electrode layer covers the sidewall of the first active post. The dielectric layer covers at least the surface of the first electrode layer. The second electrode layer covers the surface of the dielectric layer. The bottoms of the dielectric layer and the second electrode layer are embedded in the isolation structure.

[0262] Each of the second active pillars is located above a corresponding first active pillar; the channel structure of each transistor is located within the second active pillar, and the extension direction of the channel structure is the same as the extension direction of the second active pillar.

[0263] In some embodiments, the isolation structure includes: a doped semiconductor layer, a second oxide layer, and a plurality of oxide pillars; the second oxide layer is located on the surface of the doped semiconductor layer, the plurality of oxide pillars are located on the doped semiconductor layer, and each of the first active pillars is located on the top surface of a corresponding oxide pillar; the doping type of the doped semiconductor layer is different from the doping type of the first active pillars.

[0264] In some embodiments, the dielectric layer further covers the sidewalls of the oxide pillars and the bottom of the gaps between adjacent oxide pillars; the second electrode layer extends into the gaps between the oxide pillars.

[0265] In some embodiments, the semiconductor structure further includes a plurality of connection posts, each connection post being located between each of the first active posts and each of the second active posts, wherein the diameter of the connection post is greater than the diameter of the first active post and the diameter of the second active post.

[0266] In some embodiments, the transistor includes: a gate oxide layer disposed around the second active pillar, a gate disposed around the gate oxide layer, and a source and a drain disposed at two opposite ends of the second active pillar, wherein the side of the gate away from the gate oxide layer is flush with the sidewall of the connecting pillar.

[0267] In some embodiments, the semiconductor structure further includes:

[0268] Multiple bit lines are located on the transistor and are electrically contacted at the top of the second active pillar.

[0269] According to another aspect of this disclosure, embodiments of this disclosure also provide a memory comprising: at least one semiconductor structure as described in any of the embodiments described above in this disclosure.

[0270] The semiconductor structure and memory provided in the above embodiments have been described in detail in the method section, and will not be repeated here.

[0271] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the various components shown or discussed may be coupled or directly coupled to each other.

[0272] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0273] This disclosure provides specific embodiments, but its scope of protection is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, a plurality of first active pillars, a memory structure, a plurality of transistors, and a plurality of second active pillars located above the substrate; wherein, The plurality of first active pillars are arranged in an array along a first direction and a second direction; both the first direction and the second direction are perpendicular to the extension direction of the first active pillars, and the first direction and the second direction intersect; the substrate includes an isolation structure, and the plurality of first active pillars are located on the isolation structure; the isolation structure includes: a doped semiconductor layer, a second oxide layer, and a plurality of oxide pillars; the second oxide layer is located on the surface of the doped semiconductor layer, the plurality of oxide pillars are located on the doped semiconductor layer, and each first active pillar is located on the top surface of a corresponding oxide pillar; the doping type of the doped semiconductor layer is different from the doping type of the first active pillars; The storage structure includes a first electrode layer, a dielectric layer, and a second electrode layer. The first electrode layer covers the sidewall of the first active post. The dielectric layer covers at least the surface of the first electrode layer. The second electrode layer covers the surface of the dielectric layer. The bottoms of the dielectric layer and the second electrode layer are embedded in the isolation structure. Each of the second active pillars is located above a corresponding first active pillar; the channel structure of each transistor is located within the second active pillar, and the extension direction of the channel structure is the same as the extension direction of the second active pillar.

2. The semiconductor structure according to claim 1, characterized in that, The dielectric layer also covers the sidewalls of the oxide pillars and the bottom of the gaps between adjacent oxide pillars; the second electrode layer extends into the gaps between the oxide pillars.

3. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a plurality of connecting pillars, each of which is located between each of the first active pillars and each of the second active pillars, and the diameter of the connecting pillar is greater than the diameter of the first active pillar and the diameter of the second active pillar.

4. The semiconductor structure according to claim 3, characterized in that, The transistor includes: a gate oxide layer disposed around the second active pillar, a gate disposed around the gate oxide layer, and a source and a drain disposed at two opposite ends of the second active pillar, wherein the side of the gate away from the gate oxide layer is flush with the sidewall of the connecting pillar.

5. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: Multiple bit lines are located on the transistor and are electrically contacted at the top of the second active pillar.

6. A memory, characterized in that, include: At least one semiconductor structure as described in any one of claims 1 to 5.

7. A method for fabricating a semiconductor structure, characterized in that, The method includes: A substrate is provided, an isolation structure is formed on the substrate, and a plurality of first active pillars are formed on the isolation structure in an array along a first direction and a second direction; the first direction and the second direction are both perpendicular to the extension direction of the first active pillars, and the first direction and the second direction intersect each other; A storage structure is formed around the sidewall of the first active pillar. The storage structure includes a first electrode layer, a dielectric layer, and a second electrode layer. The first electrode layer covers the sidewall of the first active pillar. The dielectric layer covers at least the surface of the first electrode layer. The second electrode layer covers the surface of the dielectric layer. The bottoms of the dielectric layer and the second electrode layer are embedded in the isolation structure. Multiple second active pillars are formed, each second active pillar being located above a corresponding first active pillar; Multiple transistors are formed, wherein the channel structure of the transistors is located within the second active pillar, and the extension direction of the channel structure is the same as the extension direction of the second active pillar. The formation of the isolation structure on the substrate includes: The bottom of the substrate is doped to form a doped semiconductor layer, and multiple first trenches spaced apart along a first direction and multiple second trenches spaced apart along a second direction are formed in the substrate; the bottoms of the first trenches and the second trenches are both located in the doped semiconductor layer. The bottom of each of the first trenches and / or the second trenches is enlarged to form a plurality of first semiconductor pillars; each of the first semiconductor pillars includes a first portion and a second portion located on the first portion, wherein the maximum diameter of the first portion is smaller than the minimum diameter of the second portion; The first semiconductor pillar is oxidized so that the first portion is completely oxidized into an oxide pillar, the surface of the exposed second portion is oxidized into a first oxide layer, and the surface of the doped semiconductor layer is oxidized into a second oxide layer; the unoxidized doped semiconductor layer, the oxide pillar, and the second oxide layer together constitute the isolation structure.

8. The method for fabricating a semiconductor structure according to claim 7, characterized in that, The doping type of the doped semiconductor layer is different from the doping type of the first semiconductor pillar.

9. The method for fabricating a semiconductor structure according to claim 7, characterized in that, The method further includes: forming a top support layer over the substrate, wherein forming the top support layer includes: After the first trench is formed, the first insulating layer is filled into the first trench; A portion of the first insulating layer is removed to form a first groove; the bottom surface of the first groove is lower than the top surface of the substrate. A first support material layer is formed covering the first groove and the top of the substrate; The first support material layer and the substrate are etched to form a plurality of second trenches spaced apart along a second direction in the substrate, and the second trenches are filled with a second insulating layer. A portion of the second insulating layer is removed to form a plurality of second grooves arranged in an array along the first and second directions; the bottom surface of the second groove is flush with the bottom surface of the first groove. The second groove is filled to form a second support material layer, and the first support material layer and the second support material layer form the top support layer.

10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, After forming the top support layer, the following is also included: The remaining first insulating layer and the remaining second insulating layer are removed to form a first filling region; the first filling region exposes a portion of the sidewall of the first semiconductor pillar to form the first oxide layer, the second oxide layer and the oxide pillar through the oxidation process; After the oxidation process is completed, the first filling area is filled with sacrificial material, and part of the top support layer and part of the sacrificial material are removed to expose the top surface of the first semiconductor pillar.

11. The method for fabricating a semiconductor structure according to claim 10, characterized in that, The storage structure is formed around the sidewall of the first active pillar, including: Remove the top support layer to expose portions of the first and second grooves; Remove the first oxide layer to form a second filled area; A first conductive material is formed in the first groove, the second groove, and the second filling region, and the first conductive material located in the second filling region forms a first electrode layer; all the sacrificial material is removed to form a third filling region, a dielectric layer is formed in the third filling region, and a second conductive material is deposited on the surface of the dielectric layer to form a second electrode layer.

12. The method for fabricating a semiconductor structure according to claim 11, characterized in that, Forming multiple second active pillars, including: Remove the first conductive material and the second conductive material located around the top sidewall of the first semiconductor pillar; A first semiconductor substrate is epitaxially grown on the top of the first semiconductor pillar; Multiple third trenches are formed in the first semiconductor substrate at intervals along the first direction; A third insulating layer is formed in the third trench; A first mask layer is formed on the first semiconductor substrate; through the first mask layer, a plurality of fourth trenches are formed at intervals along a second direction; wherein the third trenches and the fourth trenches divide the first semiconductor substrate into a plurality of second semiconductor pillars; A fourth insulating layer is formed in the fourth trench; Remove a portion of the third insulating layer and a portion of the fourth insulating layer to expose a portion of the sidewall of the second semiconductor pillar; The exposed sidewalls of the second semiconductor pillar are oxidized to form a third oxide layer. The third oxide layer is removed, and the exposed second semiconductor pillar forms a second active pillar.

13. The method for fabricating a semiconductor structure according to claim 12, characterized in that, The formation of multiple transistors includes: A gate oxide layer is formed on a portion of the sidewall of the second active pillar; A third conductive material is filled into the gap of the second active pillar where the gate oxide layer is formed; By removing a portion of the third conductive material through the first mask layer, a gate is formed; The source and drain are formed at opposite ends of the second active pillar, respectively.

14. The method for fabricating a semiconductor structure according to claim 7, characterized in that, The method further includes: Multiple bit lines are formed on the second active post; the multiple bit lines are in electrical contact with the top of the second active post.

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